1From 7750e2a29b084ee033acc82abab410035e220d3f Mon Sep 17 00:00:00 2001
2From: Ross Burton <ross.burton@arm.com>
3Date: Tue, 16 Jan 2024 18:21:26 +0000
4Subject: [PATCH 1/2] coredump-mips-register
5
6glibc and musl have different names for the registers, add a
7macro that generates the names appropriately.
8
9Upstream-Status: Pending
10Signed-off-by: Ross Burton <ross.burton@arm.com>
11
12---
13 src/coredump/_UCD_access_reg_linux.c | 69 ++++++++++++++++------------
14 1 file changed, 39 insertions(+), 30 deletions(-)
15
16diff --git a/src/coredump/_UCD_access_reg_linux.c b/src/coredump/_UCD_access_reg_linux.c
17index 27eef123..beefdb47 100644
18--- a/src/coredump/_UCD_access_reg_linux.c
19+++ b/src/coredump/_UCD_access_reg_linux.c
20@@ -67,38 +67,47 @@ _UCD_access_reg (unw_addr_space_t as,
21     goto badreg;
22 #else
23 #if defined(UNW_TARGET_MIPS)
24+
25+/* glibc and musl use different names */
26+#ifdef __GLIBC__
27+#define EF_REG(x) EF_REG ## x
28+#else
29+#include <sys/reg.h>
30+#define EF_REG(x) EF_R ## x
31+#endif
32+
33   static const uint8_t remap_regs[] =
34     {
35-      [UNW_MIPS_R0]  = EF_REG0,
36-      [UNW_MIPS_R1]  = EF_REG1,
37-      [UNW_MIPS_R2]  = EF_REG2,
38-      [UNW_MIPS_R3]  = EF_REG3,
39-      [UNW_MIPS_R4]  = EF_REG4,
40-      [UNW_MIPS_R5]  = EF_REG5,
41-      [UNW_MIPS_R6]  = EF_REG6,
42-      [UNW_MIPS_R7]  = EF_REG7,
43-      [UNW_MIPS_R8]  = EF_REG8,
44-      [UNW_MIPS_R9]  = EF_REG9,
45-      [UNW_MIPS_R10] = EF_REG10,
46-      [UNW_MIPS_R11] = EF_REG11,
47-      [UNW_MIPS_R12] = EF_REG12,
48-      [UNW_MIPS_R13] = EF_REG13,
49-      [UNW_MIPS_R14] = EF_REG14,
50-      [UNW_MIPS_R15] = EF_REG15,
51-      [UNW_MIPS_R16] = EF_REG16,
52-      [UNW_MIPS_R17] = EF_REG17,
53-      [UNW_MIPS_R18] = EF_REG18,
54-      [UNW_MIPS_R19] = EF_REG19,
55-      [UNW_MIPS_R20] = EF_REG20,
56-      [UNW_MIPS_R21] = EF_REG21,
57-      [UNW_MIPS_R22] = EF_REG22,
58-      [UNW_MIPS_R23] = EF_REG23,
59-      [UNW_MIPS_R24] = EF_REG24,
60-      [UNW_MIPS_R25] = EF_REG25,
61-      [UNW_MIPS_R28] = EF_REG28,
62-      [UNW_MIPS_R29] = EF_REG29,
63-      [UNW_MIPS_R30] = EF_REG30,
64-      [UNW_MIPS_R31] = EF_REG31,
65+      [UNW_MIPS_R0]  = EF_REG(0),
66+      [UNW_MIPS_R1]  = EF_REG(1),
67+      [UNW_MIPS_R2]  = EF_REG(2),
68+      [UNW_MIPS_R3]  = EF_REG(3),
69+      [UNW_MIPS_R4]  = EF_REG(4),
70+      [UNW_MIPS_R5]  = EF_REG(5),
71+      [UNW_MIPS_R6]  = EF_REG(6),
72+      [UNW_MIPS_R7]  = EF_REG(7),
73+      [UNW_MIPS_R8]  = EF_REG(8),
74+      [UNW_MIPS_R9]  = EF_REG(9),
75+      [UNW_MIPS_R10] = EF_REG(10),
76+      [UNW_MIPS_R11] = EF_REG(11),
77+      [UNW_MIPS_R12] = EF_REG(12),
78+      [UNW_MIPS_R13] = EF_REG(13),
79+      [UNW_MIPS_R14] = EF_REG(14),
80+      [UNW_MIPS_R15] = EF_REG(15),
81+      [UNW_MIPS_R16] = EF_REG(16),
82+      [UNW_MIPS_R17] = EF_REG(17),
83+      [UNW_MIPS_R18] = EF_REG(18),
84+      [UNW_MIPS_R19] = EF_REG(19),
85+      [UNW_MIPS_R20] = EF_REG(20),
86+      [UNW_MIPS_R21] = EF_REG(21),
87+      [UNW_MIPS_R22] = EF_REG(22),
88+      [UNW_MIPS_R23] = EF_REG(23),
89+      [UNW_MIPS_R24] = EF_REG(24),
90+      [UNW_MIPS_R25] = EF_REG(25),
91+      [UNW_MIPS_R28] = EF_REG(28),
92+      [UNW_MIPS_R29] = EF_REG(29),
93+      [UNW_MIPS_R30] = EF_REG(30),
94+      [UNW_MIPS_R31] = EF_REG(31),
95       [UNW_MIPS_PC]  = EF_CP0_EPC,
96     };
97 #elif defined(UNW_TARGET_X86)
98--
992.34.1
100
101