1From 3cd9aa92ab8ddd230cf6a9a68a27a18705b6f57c Mon Sep 17 00:00:00 2001 2From: Xo Wang <xow@google.com> 3Date: Thu, 20 Oct 2016 16:26:29 -0700 4Subject: [PATCH 1/2] board/aspeed: Add reset_phy() for Zaius 5 6The Broadcom PHY for the Zaius BMC requires a hard reset after RGMII 7clocks are enabled. Add reset_phy() implementation and configure it to 8be called. 9 10Signed-off-by: Xo Wang <xow@google.com> 11--- 12 board/aspeed/ast-g5/ast-g5.c | 19 +++++++++++++++++++ 13 include/configs/ast-common.h | 3 +++ 14 2 files changed, 22 insertions(+) 15 16diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c 17index da79d7b..433ad18 100644 18--- a/board/aspeed/ast-g5/ast-g5.c 19+++ b/board/aspeed/ast-g5/ast-g5.c 20@@ -33,6 +33,25 @@ int dram_init(void) 21 return 0; 22 } 23 24+void reset_phy(void) 25+{ 26+ unsigned long reg; 27+ /* D3 in GPIOA/B/C/D direction and data registers */ 28+ unsigned long phy_reset_mask = BIT(27); 29+ 30+ /* Assert MAC2 PHY hardware reset */ 31+ /* Set pin low */ 32+ reg = readl(AST_GPIO_BASE | 0x00); 33+ writel(reg & ~phy_reset_mask, AST_GPIO_BASE | 0x00); 34+ /* Enable pin for output */ 35+ reg = readl(AST_GPIO_BASE | 0x04); 36+ writel(reg | phy_reset_mask, AST_GPIO_BASE | 0x04); 37+ udelay(3); 38+ /* Set pin high */ 39+ reg = readl(AST_GPIO_BASE | 0x00); 40+ writel(reg | phy_reset_mask, AST_GPIO_BASE | 0x00); 41+} 42+ 43 #ifdef CONFIG_FTGMAC100 44 int board_eth_init(bd_t *bd) 45 { 46diff --git a/include/configs/ast-common.h b/include/configs/ast-common.h 47index b39ea33..3566f73 100644 48--- a/include/configs/ast-common.h 49+++ b/include/configs/ast-common.h 50@@ -104,4 +104,7 @@ 51 "spi_dma=yes\0" \ 52 "" 53 54+/* Call reset_phy() */ 55+#define CONFIG_RESET_PHY_R 1 56+ 57 #endif /* __AST_COMMON_CONFIG_H */ 58-- 592.8.0.rc3.226.g39d4020 60 61