1From 3cd9aa92ab8ddd230cf6a9a68a27a18705b6f57c Mon Sep 17 00:00:00 2001
2From: Xo Wang <xow@google.com>
3Date: Thu, 20 Oct 2016 16:26:29 -0700
4Subject: [PATCH 1/2] board/aspeed: Add reset_phy() for Zaius
5
6The Broadcom PHY for the Zaius BMC requires a hard reset after RGMII
7clocks are enabled. Add reset_phy() implementation and configure it to
8be called.
9
10Upstream-Status: Pending
11
12Signed-off-by: Xo Wang <xow@google.com>
13---
14 board/aspeed/ast-g5/ast-g5.c | 19 +++++++++++++++++++
15 include/configs/ast-common.h |  3 +++
16 2 files changed, 22 insertions(+)
17
18diff --git a/board/aspeed/ast-g5/ast-g5.c b/board/aspeed/ast-g5/ast-g5.c
19index da79d7b..433ad18 100644
20--- a/board/aspeed/ast-g5/ast-g5.c
21+++ b/board/aspeed/ast-g5/ast-g5.c
22@@ -33,6 +33,25 @@ int dram_init(void)
23 	return 0;
24 }
25
26+void reset_phy(void)
27+{
28+	unsigned long reg;
29+	/* D3 in GPIOA/B/C/D direction and data registers */
30+	unsigned long phy_reset_mask = BIT(27);
31+
32+	/* Assert MAC2 PHY hardware reset */
33+	/* Set pin low */
34+	reg = readl(AST_GPIO_BASE | 0x00);
35+	writel(reg & ~phy_reset_mask, AST_GPIO_BASE | 0x00);
36+	/* Enable pin for output */
37+	reg = readl(AST_GPIO_BASE | 0x04);
38+	writel(reg | phy_reset_mask, AST_GPIO_BASE | 0x04);
39+	udelay(3);
40+	/* Set pin high */
41+	reg = readl(AST_GPIO_BASE | 0x00);
42+	writel(reg | phy_reset_mask, AST_GPIO_BASE | 0x00);
43+}
44+
45 #ifdef CONFIG_FTGMAC100
46 int board_eth_init(bd_t *bd)
47 {
48diff --git a/include/configs/ast-common.h b/include/configs/ast-common.h
49index b39ea33..3566f73 100644
50--- a/include/configs/ast-common.h
51+++ b/include/configs/ast-common.h
52@@ -104,4 +104,7 @@
53 	"spi_dma=yes\0" \
54 	""
55
56+/* Call reset_phy() */
57+#define CONFIG_RESET_PHY_R	1
58+
59 #endif	/* __AST_COMMON_CONFIG_H */
60--
612.8.0.rc3.226.g39d4020
62
63