1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * linux/drivers/video/omap2/dss/dispc.c
4 *
5 * Copyright (C) 2009 Nokia Corporation
6 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 *
8 * Some code and ideas taken from drivers/video/omap/ driver
9 * by Imre Deak.
10 */
11
12 #define DSS_SUBSYS_NAME "DISPC"
13
14 #include <linux/kernel.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/vmalloc.h>
17 #include <linux/export.h>
18 #include <linux/clk.h>
19 #include <linux/io.h>
20 #include <linux/jiffies.h>
21 #include <linux/seq_file.h>
22 #include <linux/delay.h>
23 #include <linux/workqueue.h>
24 #include <linux/hardirq.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/sizes.h>
28 #include <linux/mfd/syscon.h>
29 #include <linux/regmap.h>
30 #include <linux/of.h>
31 #include <linux/component.h>
32
33 #include <video/omapfb_dss.h>
34
35 #include "dss.h"
36 #include "dss_features.h"
37 #include "dispc.h"
38
39 /* DISPC */
40 #define DISPC_SZ_REGS SZ_4K
41
42 enum omap_burst_size {
43 BURST_SIZE_X2 = 0,
44 BURST_SIZE_X4 = 1,
45 BURST_SIZE_X8 = 2,
46 };
47
48 #define REG_GET(idx, start, end) \
49 FLD_GET(dispc_read_reg(idx), start, end)
50
51 #define REG_FLD_MOD(idx, val, start, end) \
52 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
53
54 struct dispc_features {
55 u8 sw_start;
56 u8 fp_start;
57 u8 bp_start;
58 u16 sw_max;
59 u16 vp_max;
60 u16 hp_max;
61 u8 mgr_width_start;
62 u8 mgr_height_start;
63 u16 mgr_width_max;
64 u16 mgr_height_max;
65 unsigned long max_lcd_pclk;
66 unsigned long max_tv_pclk;
67 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
68 const struct omap_video_timings *mgr_timings,
69 u16 width, u16 height, u16 out_width, u16 out_height,
70 enum omap_color_mode color_mode, bool *five_taps,
71 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
72 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
73 unsigned long (*calc_core_clk) (unsigned long pclk,
74 u16 width, u16 height, u16 out_width, u16 out_height,
75 bool mem_to_mem);
76 u8 num_fifos;
77
78 /* swap GFX & WB fifos */
79 bool gfx_fifo_workaround:1;
80
81 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
82 bool no_framedone_tv:1;
83
84 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
85 bool mstandby_workaround:1;
86
87 bool set_max_preload:1;
88
89 /* PIXEL_INC is not added to the last pixel of a line */
90 bool last_pixel_inc_missing:1;
91
92 /* POL_FREQ has ALIGN bit */
93 bool supports_sync_align:1;
94
95 bool has_writeback:1;
96 };
97
98 #define DISPC_MAX_NR_FIFOS 5
99
100 static struct {
101 struct platform_device *pdev;
102 void __iomem *base;
103
104 int irq;
105 irq_handler_t user_handler;
106 void *user_data;
107
108 unsigned long core_clk_rate;
109 unsigned long tv_pclk_rate;
110
111 u32 fifo_size[DISPC_MAX_NR_FIFOS];
112 /* maps which plane is using a fifo. fifo-id -> plane-id */
113 int fifo_assignment[DISPC_MAX_NR_FIFOS];
114
115 bool ctx_valid;
116 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
117
118 const struct dispc_features *feat;
119
120 bool is_enabled;
121
122 struct regmap *syscon_pol;
123 u32 syscon_pol_offset;
124
125 /* DISPC_CONTROL & DISPC_CONFIG lock*/
126 spinlock_t control_lock;
127 } dispc;
128
129 enum omap_color_component {
130 /* used for all color formats for OMAP3 and earlier
131 * and for RGB and Y color component on OMAP4
132 */
133 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
134 /* used for UV component for
135 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
136 * color formats on OMAP4
137 */
138 DISPC_COLOR_COMPONENT_UV = 1 << 1,
139 };
140
141 enum mgr_reg_fields {
142 DISPC_MGR_FLD_ENABLE,
143 DISPC_MGR_FLD_STNTFT,
144 DISPC_MGR_FLD_GO,
145 DISPC_MGR_FLD_TFTDATALINES,
146 DISPC_MGR_FLD_STALLMODE,
147 DISPC_MGR_FLD_TCKENABLE,
148 DISPC_MGR_FLD_TCKSELECTION,
149 DISPC_MGR_FLD_CPR,
150 DISPC_MGR_FLD_FIFOHANDCHECK,
151 /* used to maintain a count of the above fields */
152 DISPC_MGR_FLD_NUM,
153 };
154
155 struct dispc_reg_field {
156 u16 reg;
157 u8 high;
158 u8 low;
159 };
160
161 static const struct {
162 const char *name;
163 u32 vsync_irq;
164 u32 framedone_irq;
165 u32 sync_lost_irq;
166 struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
167 } mgr_desc[] = {
168 [OMAP_DSS_CHANNEL_LCD] = {
169 .name = "LCD",
170 .vsync_irq = DISPC_IRQ_VSYNC,
171 .framedone_irq = DISPC_IRQ_FRAMEDONE,
172 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
173 .reg_desc = {
174 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
175 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
176 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
177 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
178 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
179 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
180 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
181 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
182 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
183 },
184 },
185 [OMAP_DSS_CHANNEL_DIGIT] = {
186 .name = "DIGIT",
187 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
188 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
189 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
190 .reg_desc = {
191 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
192 [DISPC_MGR_FLD_STNTFT] = { },
193 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
194 [DISPC_MGR_FLD_TFTDATALINES] = { },
195 [DISPC_MGR_FLD_STALLMODE] = { },
196 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
197 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
198 [DISPC_MGR_FLD_CPR] = { },
199 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
200 },
201 },
202 [OMAP_DSS_CHANNEL_LCD2] = {
203 .name = "LCD2",
204 .vsync_irq = DISPC_IRQ_VSYNC2,
205 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
206 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
207 .reg_desc = {
208 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
209 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
210 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
211 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
212 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
213 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
214 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
215 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
216 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
217 },
218 },
219 [OMAP_DSS_CHANNEL_LCD3] = {
220 .name = "LCD3",
221 .vsync_irq = DISPC_IRQ_VSYNC3,
222 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
223 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
224 .reg_desc = {
225 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
226 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
227 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
228 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
229 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
230 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
231 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
232 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
233 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
234 },
235 },
236 };
237
238 struct color_conv_coef {
239 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
240 int full_range;
241 };
242
243 static unsigned long dispc_fclk_rate(void);
244 static unsigned long dispc_core_clk_rate(void);
245 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
246 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
247
248 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
249 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
250
dispc_write_reg(const u16 idx,u32 val)251 static inline void dispc_write_reg(const u16 idx, u32 val)
252 {
253 __raw_writel(val, dispc.base + idx);
254 }
255
dispc_read_reg(const u16 idx)256 static inline u32 dispc_read_reg(const u16 idx)
257 {
258 return __raw_readl(dispc.base + idx);
259 }
260
mgr_fld_read(enum omap_channel channel,enum mgr_reg_fields regfld)261 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
262 {
263 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
264 return REG_GET(rfld.reg, rfld.high, rfld.low);
265 }
266
mgr_fld_write(enum omap_channel channel,enum mgr_reg_fields regfld,int val)267 static void mgr_fld_write(enum omap_channel channel,
268 enum mgr_reg_fields regfld, int val) {
269 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
270 const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
271 unsigned long flags;
272
273 if (need_lock)
274 spin_lock_irqsave(&dispc.control_lock, flags);
275
276 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
277
278 if (need_lock)
279 spin_unlock_irqrestore(&dispc.control_lock, flags);
280 }
281
282 #define SR(reg) \
283 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
284 #define RR(reg) \
285 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
286
dispc_save_context(void)287 static void dispc_save_context(void)
288 {
289 int i, j;
290
291 DSSDBG("dispc_save_context\n");
292
293 SR(IRQENABLE);
294 SR(CONTROL);
295 SR(CONFIG);
296 SR(LINE_NUMBER);
297 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
298 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
299 SR(GLOBAL_ALPHA);
300 if (dss_has_feature(FEAT_MGR_LCD2)) {
301 SR(CONTROL2);
302 SR(CONFIG2);
303 }
304 if (dss_has_feature(FEAT_MGR_LCD3)) {
305 SR(CONTROL3);
306 SR(CONFIG3);
307 }
308
309 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
310 SR(DEFAULT_COLOR(i));
311 SR(TRANS_COLOR(i));
312 SR(SIZE_MGR(i));
313 if (i == OMAP_DSS_CHANNEL_DIGIT)
314 continue;
315 SR(TIMING_H(i));
316 SR(TIMING_V(i));
317 SR(POL_FREQ(i));
318 SR(DIVISORo(i));
319
320 SR(DATA_CYCLE1(i));
321 SR(DATA_CYCLE2(i));
322 SR(DATA_CYCLE3(i));
323
324 if (dss_has_feature(FEAT_CPR)) {
325 SR(CPR_COEF_R(i));
326 SR(CPR_COEF_G(i));
327 SR(CPR_COEF_B(i));
328 }
329 }
330
331 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
332 SR(OVL_BA0(i));
333 SR(OVL_BA1(i));
334 SR(OVL_POSITION(i));
335 SR(OVL_SIZE(i));
336 SR(OVL_ATTRIBUTES(i));
337 SR(OVL_FIFO_THRESHOLD(i));
338 SR(OVL_ROW_INC(i));
339 SR(OVL_PIXEL_INC(i));
340 if (dss_has_feature(FEAT_PRELOAD))
341 SR(OVL_PRELOAD(i));
342 if (i == OMAP_DSS_GFX) {
343 SR(OVL_WINDOW_SKIP(i));
344 SR(OVL_TABLE_BA(i));
345 continue;
346 }
347 SR(OVL_FIR(i));
348 SR(OVL_PICTURE_SIZE(i));
349 SR(OVL_ACCU0(i));
350 SR(OVL_ACCU1(i));
351
352 for (j = 0; j < 8; j++)
353 SR(OVL_FIR_COEF_H(i, j));
354
355 for (j = 0; j < 8; j++)
356 SR(OVL_FIR_COEF_HV(i, j));
357
358 for (j = 0; j < 5; j++)
359 SR(OVL_CONV_COEF(i, j));
360
361 if (dss_has_feature(FEAT_FIR_COEF_V)) {
362 for (j = 0; j < 8; j++)
363 SR(OVL_FIR_COEF_V(i, j));
364 }
365
366 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
367 SR(OVL_BA0_UV(i));
368 SR(OVL_BA1_UV(i));
369 SR(OVL_FIR2(i));
370 SR(OVL_ACCU2_0(i));
371 SR(OVL_ACCU2_1(i));
372
373 for (j = 0; j < 8; j++)
374 SR(OVL_FIR_COEF_H2(i, j));
375
376 for (j = 0; j < 8; j++)
377 SR(OVL_FIR_COEF_HV2(i, j));
378
379 for (j = 0; j < 8; j++)
380 SR(OVL_FIR_COEF_V2(i, j));
381 }
382 if (dss_has_feature(FEAT_ATTR2))
383 SR(OVL_ATTRIBUTES2(i));
384 }
385
386 if (dss_has_feature(FEAT_CORE_CLK_DIV))
387 SR(DIVISOR);
388
389 dispc.ctx_valid = true;
390
391 DSSDBG("context saved\n");
392 }
393
dispc_restore_context(void)394 static void dispc_restore_context(void)
395 {
396 int i, j;
397
398 DSSDBG("dispc_restore_context\n");
399
400 if (!dispc.ctx_valid)
401 return;
402
403 /*RR(IRQENABLE);*/
404 /*RR(CONTROL);*/
405 RR(CONFIG);
406 RR(LINE_NUMBER);
407 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
408 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
409 RR(GLOBAL_ALPHA);
410 if (dss_has_feature(FEAT_MGR_LCD2))
411 RR(CONFIG2);
412 if (dss_has_feature(FEAT_MGR_LCD3))
413 RR(CONFIG3);
414
415 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
416 RR(DEFAULT_COLOR(i));
417 RR(TRANS_COLOR(i));
418 RR(SIZE_MGR(i));
419 if (i == OMAP_DSS_CHANNEL_DIGIT)
420 continue;
421 RR(TIMING_H(i));
422 RR(TIMING_V(i));
423 RR(POL_FREQ(i));
424 RR(DIVISORo(i));
425
426 RR(DATA_CYCLE1(i));
427 RR(DATA_CYCLE2(i));
428 RR(DATA_CYCLE3(i));
429
430 if (dss_has_feature(FEAT_CPR)) {
431 RR(CPR_COEF_R(i));
432 RR(CPR_COEF_G(i));
433 RR(CPR_COEF_B(i));
434 }
435 }
436
437 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
438 RR(OVL_BA0(i));
439 RR(OVL_BA1(i));
440 RR(OVL_POSITION(i));
441 RR(OVL_SIZE(i));
442 RR(OVL_ATTRIBUTES(i));
443 RR(OVL_FIFO_THRESHOLD(i));
444 RR(OVL_ROW_INC(i));
445 RR(OVL_PIXEL_INC(i));
446 if (dss_has_feature(FEAT_PRELOAD))
447 RR(OVL_PRELOAD(i));
448 if (i == OMAP_DSS_GFX) {
449 RR(OVL_WINDOW_SKIP(i));
450 RR(OVL_TABLE_BA(i));
451 continue;
452 }
453 RR(OVL_FIR(i));
454 RR(OVL_PICTURE_SIZE(i));
455 RR(OVL_ACCU0(i));
456 RR(OVL_ACCU1(i));
457
458 for (j = 0; j < 8; j++)
459 RR(OVL_FIR_COEF_H(i, j));
460
461 for (j = 0; j < 8; j++)
462 RR(OVL_FIR_COEF_HV(i, j));
463
464 for (j = 0; j < 5; j++)
465 RR(OVL_CONV_COEF(i, j));
466
467 if (dss_has_feature(FEAT_FIR_COEF_V)) {
468 for (j = 0; j < 8; j++)
469 RR(OVL_FIR_COEF_V(i, j));
470 }
471
472 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
473 RR(OVL_BA0_UV(i));
474 RR(OVL_BA1_UV(i));
475 RR(OVL_FIR2(i));
476 RR(OVL_ACCU2_0(i));
477 RR(OVL_ACCU2_1(i));
478
479 for (j = 0; j < 8; j++)
480 RR(OVL_FIR_COEF_H2(i, j));
481
482 for (j = 0; j < 8; j++)
483 RR(OVL_FIR_COEF_HV2(i, j));
484
485 for (j = 0; j < 8; j++)
486 RR(OVL_FIR_COEF_V2(i, j));
487 }
488 if (dss_has_feature(FEAT_ATTR2))
489 RR(OVL_ATTRIBUTES2(i));
490 }
491
492 if (dss_has_feature(FEAT_CORE_CLK_DIV))
493 RR(DIVISOR);
494
495 /* enable last, because LCD & DIGIT enable are here */
496 RR(CONTROL);
497 if (dss_has_feature(FEAT_MGR_LCD2))
498 RR(CONTROL2);
499 if (dss_has_feature(FEAT_MGR_LCD3))
500 RR(CONTROL3);
501 /* clear spurious SYNC_LOST_DIGIT interrupts */
502 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
503
504 /*
505 * enable last so IRQs won't trigger before
506 * the context is fully restored
507 */
508 RR(IRQENABLE);
509
510 DSSDBG("context restored\n");
511 }
512
513 #undef SR
514 #undef RR
515
dispc_runtime_get(void)516 int dispc_runtime_get(void)
517 {
518 int r;
519
520 DSSDBG("dispc_runtime_get\n");
521
522 r = pm_runtime_resume_and_get(&dispc.pdev->dev);
523 if (WARN_ON(r < 0))
524 return r;
525 return 0;
526 }
527 EXPORT_SYMBOL(dispc_runtime_get);
528
dispc_runtime_put(void)529 void dispc_runtime_put(void)
530 {
531 int r;
532
533 DSSDBG("dispc_runtime_put\n");
534
535 r = pm_runtime_put_sync(&dispc.pdev->dev);
536 WARN_ON(r < 0 && r != -ENOSYS);
537 }
538 EXPORT_SYMBOL(dispc_runtime_put);
539
dispc_mgr_get_vsync_irq(enum omap_channel channel)540 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
541 {
542 return mgr_desc[channel].vsync_irq;
543 }
544 EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
545
dispc_mgr_get_framedone_irq(enum omap_channel channel)546 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
547 {
548 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
549 return 0;
550
551 return mgr_desc[channel].framedone_irq;
552 }
553 EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
554
dispc_mgr_get_sync_lost_irq(enum omap_channel channel)555 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
556 {
557 return mgr_desc[channel].sync_lost_irq;
558 }
559 EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
560
dispc_mgr_go_busy(enum omap_channel channel)561 bool dispc_mgr_go_busy(enum omap_channel channel)
562 {
563 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
564 }
565 EXPORT_SYMBOL(dispc_mgr_go_busy);
566
dispc_mgr_go(enum omap_channel channel)567 void dispc_mgr_go(enum omap_channel channel)
568 {
569 WARN_ON(!dispc_mgr_is_enabled(channel));
570 WARN_ON(dispc_mgr_go_busy(channel));
571
572 DSSDBG("GO %s\n", mgr_desc[channel].name);
573
574 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
575 }
576 EXPORT_SYMBOL(dispc_mgr_go);
577
dispc_ovl_write_firh_reg(enum omap_plane plane,int reg,u32 value)578 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
579 {
580 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
581 }
582
dispc_ovl_write_firhv_reg(enum omap_plane plane,int reg,u32 value)583 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
584 {
585 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
586 }
587
dispc_ovl_write_firv_reg(enum omap_plane plane,int reg,u32 value)588 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
589 {
590 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
591 }
592
dispc_ovl_write_firh2_reg(enum omap_plane plane,int reg,u32 value)593 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
594 {
595 BUG_ON(plane == OMAP_DSS_GFX);
596
597 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
598 }
599
dispc_ovl_write_firhv2_reg(enum omap_plane plane,int reg,u32 value)600 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
601 u32 value)
602 {
603 BUG_ON(plane == OMAP_DSS_GFX);
604
605 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
606 }
607
dispc_ovl_write_firv2_reg(enum omap_plane plane,int reg,u32 value)608 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
609 {
610 BUG_ON(plane == OMAP_DSS_GFX);
611
612 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
613 }
614
dispc_ovl_set_scale_coef(enum omap_plane plane,int fir_hinc,int fir_vinc,int five_taps,enum omap_color_component color_comp)615 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
616 int fir_vinc, int five_taps,
617 enum omap_color_component color_comp)
618 {
619 const struct dispc_coef *h_coef, *v_coef;
620 int i;
621
622 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
623 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
624
625 for (i = 0; i < 8; i++) {
626 u32 h, hv;
627
628 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
629 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
630 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
631 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
632 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
633 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
634 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
635 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
636
637 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
638 dispc_ovl_write_firh_reg(plane, i, h);
639 dispc_ovl_write_firhv_reg(plane, i, hv);
640 } else {
641 dispc_ovl_write_firh2_reg(plane, i, h);
642 dispc_ovl_write_firhv2_reg(plane, i, hv);
643 }
644
645 }
646
647 if (five_taps) {
648 for (i = 0; i < 8; i++) {
649 u32 v;
650 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
651 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
652 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
653 dispc_ovl_write_firv_reg(plane, i, v);
654 else
655 dispc_ovl_write_firv2_reg(plane, i, v);
656 }
657 }
658 }
659
660
dispc_ovl_write_color_conv_coef(enum omap_plane plane,const struct color_conv_coef * ct)661 static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
662 const struct color_conv_coef *ct)
663 {
664 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
665
666 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
667 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
668 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
669 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
670 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
671
672 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
673
674 #undef CVAL
675 }
676
dispc_setup_color_conv_coef(void)677 static void dispc_setup_color_conv_coef(void)
678 {
679 int i;
680 int num_ovl = dss_feat_get_num_ovls();
681 const struct color_conv_coef ctbl_bt601_5_ovl = {
682 /* YUV -> RGB */
683 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
684 };
685 const struct color_conv_coef ctbl_bt601_5_wb = {
686 /* RGB -> YUV */
687 66, 129, 25, 112, -94, -18, -38, -74, 112, 0,
688 };
689
690 for (i = 1; i < num_ovl; i++)
691 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
692
693 if (dispc.feat->has_writeback)
694 dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb);
695 }
696
dispc_ovl_set_ba0(enum omap_plane plane,u32 paddr)697 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
698 {
699 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
700 }
701
dispc_ovl_set_ba1(enum omap_plane plane,u32 paddr)702 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
703 {
704 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
705 }
706
dispc_ovl_set_ba0_uv(enum omap_plane plane,u32 paddr)707 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
708 {
709 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
710 }
711
dispc_ovl_set_ba1_uv(enum omap_plane plane,u32 paddr)712 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
713 {
714 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
715 }
716
dispc_ovl_set_pos(enum omap_plane plane,enum omap_overlay_caps caps,int x,int y)717 static void dispc_ovl_set_pos(enum omap_plane plane,
718 enum omap_overlay_caps caps, int x, int y)
719 {
720 u32 val;
721
722 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
723 return;
724
725 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
726
727 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
728 }
729
dispc_ovl_set_input_size(enum omap_plane plane,int width,int height)730 static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
731 int height)
732 {
733 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
734
735 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
736 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
737 else
738 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
739 }
740
dispc_ovl_set_output_size(enum omap_plane plane,int width,int height)741 static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
742 int height)
743 {
744 u32 val;
745
746 BUG_ON(plane == OMAP_DSS_GFX);
747
748 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
749
750 if (plane == OMAP_DSS_WB)
751 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
752 else
753 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
754 }
755
dispc_ovl_set_zorder(enum omap_plane plane,enum omap_overlay_caps caps,u8 zorder)756 static void dispc_ovl_set_zorder(enum omap_plane plane,
757 enum omap_overlay_caps caps, u8 zorder)
758 {
759 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
760 return;
761
762 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
763 }
764
dispc_ovl_enable_zorder_planes(void)765 static void dispc_ovl_enable_zorder_planes(void)
766 {
767 int i;
768
769 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
770 return;
771
772 for (i = 0; i < dss_feat_get_num_ovls(); i++)
773 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
774 }
775
dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,enum omap_overlay_caps caps,bool enable)776 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
777 enum omap_overlay_caps caps, bool enable)
778 {
779 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
780 return;
781
782 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
783 }
784
dispc_ovl_setup_global_alpha(enum omap_plane plane,enum omap_overlay_caps caps,u8 global_alpha)785 static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
786 enum omap_overlay_caps caps, u8 global_alpha)
787 {
788 static const unsigned shifts[] = { 0, 8, 16, 24, };
789 int shift;
790
791 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
792 return;
793
794 shift = shifts[plane];
795 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
796 }
797
dispc_ovl_set_pix_inc(enum omap_plane plane,s32 inc)798 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
799 {
800 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
801 }
802
dispc_ovl_set_row_inc(enum omap_plane plane,s32 inc)803 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
804 {
805 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
806 }
807
dispc_ovl_set_color_mode(enum omap_plane plane,enum omap_color_mode color_mode)808 static void dispc_ovl_set_color_mode(enum omap_plane plane,
809 enum omap_color_mode color_mode)
810 {
811 u32 m = 0;
812 if (plane != OMAP_DSS_GFX) {
813 switch (color_mode) {
814 case OMAP_DSS_COLOR_NV12:
815 m = 0x0; break;
816 case OMAP_DSS_COLOR_RGBX16:
817 m = 0x1; break;
818 case OMAP_DSS_COLOR_RGBA16:
819 m = 0x2; break;
820 case OMAP_DSS_COLOR_RGB12U:
821 m = 0x4; break;
822 case OMAP_DSS_COLOR_ARGB16:
823 m = 0x5; break;
824 case OMAP_DSS_COLOR_RGB16:
825 m = 0x6; break;
826 case OMAP_DSS_COLOR_ARGB16_1555:
827 m = 0x7; break;
828 case OMAP_DSS_COLOR_RGB24U:
829 m = 0x8; break;
830 case OMAP_DSS_COLOR_RGB24P:
831 m = 0x9; break;
832 case OMAP_DSS_COLOR_YUV2:
833 m = 0xa; break;
834 case OMAP_DSS_COLOR_UYVY:
835 m = 0xb; break;
836 case OMAP_DSS_COLOR_ARGB32:
837 m = 0xc; break;
838 case OMAP_DSS_COLOR_RGBA32:
839 m = 0xd; break;
840 case OMAP_DSS_COLOR_RGBX32:
841 m = 0xe; break;
842 case OMAP_DSS_COLOR_XRGB16_1555:
843 m = 0xf; break;
844 default:
845 BUG(); return;
846 }
847 } else {
848 switch (color_mode) {
849 case OMAP_DSS_COLOR_CLUT1:
850 m = 0x0; break;
851 case OMAP_DSS_COLOR_CLUT2:
852 m = 0x1; break;
853 case OMAP_DSS_COLOR_CLUT4:
854 m = 0x2; break;
855 case OMAP_DSS_COLOR_CLUT8:
856 m = 0x3; break;
857 case OMAP_DSS_COLOR_RGB12U:
858 m = 0x4; break;
859 case OMAP_DSS_COLOR_ARGB16:
860 m = 0x5; break;
861 case OMAP_DSS_COLOR_RGB16:
862 m = 0x6; break;
863 case OMAP_DSS_COLOR_ARGB16_1555:
864 m = 0x7; break;
865 case OMAP_DSS_COLOR_RGB24U:
866 m = 0x8; break;
867 case OMAP_DSS_COLOR_RGB24P:
868 m = 0x9; break;
869 case OMAP_DSS_COLOR_RGBX16:
870 m = 0xa; break;
871 case OMAP_DSS_COLOR_RGBA16:
872 m = 0xb; break;
873 case OMAP_DSS_COLOR_ARGB32:
874 m = 0xc; break;
875 case OMAP_DSS_COLOR_RGBA32:
876 m = 0xd; break;
877 case OMAP_DSS_COLOR_RGBX32:
878 m = 0xe; break;
879 case OMAP_DSS_COLOR_XRGB16_1555:
880 m = 0xf; break;
881 default:
882 BUG(); return;
883 }
884 }
885
886 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
887 }
888
dispc_ovl_configure_burst_type(enum omap_plane plane,enum omap_dss_rotation_type rotation_type)889 static void dispc_ovl_configure_burst_type(enum omap_plane plane,
890 enum omap_dss_rotation_type rotation_type)
891 {
892 if (!dss_has_feature(FEAT_BURST_2D))
893 return;
894
895 if (rotation_type == OMAP_DSS_ROT_TILER)
896 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
897 else
898 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
899 }
900
dispc_ovl_set_channel_out(enum omap_plane plane,enum omap_channel channel)901 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
902 {
903 int shift;
904 u32 val;
905 int chan = 0, chan2 = 0;
906
907 switch (plane) {
908 case OMAP_DSS_GFX:
909 shift = 8;
910 break;
911 case OMAP_DSS_VIDEO1:
912 case OMAP_DSS_VIDEO2:
913 case OMAP_DSS_VIDEO3:
914 shift = 16;
915 break;
916 default:
917 BUG();
918 return;
919 }
920
921 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
922 if (dss_has_feature(FEAT_MGR_LCD2)) {
923 switch (channel) {
924 case OMAP_DSS_CHANNEL_LCD:
925 chan = 0;
926 chan2 = 0;
927 break;
928 case OMAP_DSS_CHANNEL_DIGIT:
929 chan = 1;
930 chan2 = 0;
931 break;
932 case OMAP_DSS_CHANNEL_LCD2:
933 chan = 0;
934 chan2 = 1;
935 break;
936 case OMAP_DSS_CHANNEL_LCD3:
937 if (dss_has_feature(FEAT_MGR_LCD3)) {
938 chan = 0;
939 chan2 = 2;
940 } else {
941 BUG();
942 return;
943 }
944 break;
945 case OMAP_DSS_CHANNEL_WB:
946 chan = 0;
947 chan2 = 3;
948 break;
949 default:
950 BUG();
951 return;
952 }
953
954 val = FLD_MOD(val, chan, shift, shift);
955 val = FLD_MOD(val, chan2, 31, 30);
956 } else {
957 val = FLD_MOD(val, channel, shift, shift);
958 }
959 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
960 }
961 EXPORT_SYMBOL(dispc_ovl_set_channel_out);
962
dispc_ovl_get_channel_out(enum omap_plane plane)963 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
964 {
965 int shift;
966 u32 val;
967
968 switch (plane) {
969 case OMAP_DSS_GFX:
970 shift = 8;
971 break;
972 case OMAP_DSS_VIDEO1:
973 case OMAP_DSS_VIDEO2:
974 case OMAP_DSS_VIDEO3:
975 shift = 16;
976 break;
977 default:
978 BUG();
979 return 0;
980 }
981
982 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
983
984 if (FLD_GET(val, shift, shift) == 1)
985 return OMAP_DSS_CHANNEL_DIGIT;
986
987 if (!dss_has_feature(FEAT_MGR_LCD2))
988 return OMAP_DSS_CHANNEL_LCD;
989
990 switch (FLD_GET(val, 31, 30)) {
991 case 0:
992 default:
993 return OMAP_DSS_CHANNEL_LCD;
994 case 1:
995 return OMAP_DSS_CHANNEL_LCD2;
996 case 2:
997 return OMAP_DSS_CHANNEL_LCD3;
998 case 3:
999 return OMAP_DSS_CHANNEL_WB;
1000 }
1001 }
1002
dispc_ovl_set_burst_size(enum omap_plane plane,enum omap_burst_size burst_size)1003 static void dispc_ovl_set_burst_size(enum omap_plane plane,
1004 enum omap_burst_size burst_size)
1005 {
1006 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
1007 int shift;
1008
1009 shift = shifts[plane];
1010 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1011 }
1012
dispc_configure_burst_sizes(void)1013 static void dispc_configure_burst_sizes(void)
1014 {
1015 int i;
1016 const int burst_size = BURST_SIZE_X8;
1017
1018 /* Configure burst size always to maximum size */
1019 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1020 dispc_ovl_set_burst_size(i, burst_size);
1021 if (dispc.feat->has_writeback)
1022 dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size);
1023 }
1024
dispc_ovl_get_burst_size(enum omap_plane plane)1025 static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1026 {
1027 unsigned unit = dss_feat_get_burst_size_unit();
1028 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1029 return unit * 8;
1030 }
1031
dispc_enable_gamma_table(bool enable)1032 void dispc_enable_gamma_table(bool enable)
1033 {
1034 /*
1035 * This is partially implemented to support only disabling of
1036 * the gamma table.
1037 */
1038 if (enable) {
1039 DSSWARN("Gamma table enabling for TV not yet supported");
1040 return;
1041 }
1042
1043 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1044 }
1045
dispc_mgr_enable_cpr(enum omap_channel channel,bool enable)1046 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1047 {
1048 if (channel == OMAP_DSS_CHANNEL_DIGIT)
1049 return;
1050
1051 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
1052 }
1053
dispc_mgr_set_cpr_coef(enum omap_channel channel,const struct omap_dss_cpr_coefs * coefs)1054 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1055 const struct omap_dss_cpr_coefs *coefs)
1056 {
1057 u32 coef_r, coef_g, coef_b;
1058
1059 if (!dss_mgr_is_lcd(channel))
1060 return;
1061
1062 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1063 FLD_VAL(coefs->rb, 9, 0);
1064 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1065 FLD_VAL(coefs->gb, 9, 0);
1066 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1067 FLD_VAL(coefs->bb, 9, 0);
1068
1069 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1070 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1071 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1072 }
1073
dispc_ovl_set_vid_color_conv(enum omap_plane plane,bool enable)1074 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1075 {
1076 u32 val;
1077
1078 BUG_ON(plane == OMAP_DSS_GFX);
1079
1080 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1081 val = FLD_MOD(val, enable, 9, 9);
1082 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1083 }
1084
dispc_ovl_enable_replication(enum omap_plane plane,enum omap_overlay_caps caps,bool enable)1085 static void dispc_ovl_enable_replication(enum omap_plane plane,
1086 enum omap_overlay_caps caps, bool enable)
1087 {
1088 static const unsigned shifts[] = { 5, 10, 10, 10 };
1089 int shift;
1090
1091 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1092 return;
1093
1094 shift = shifts[plane];
1095 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1096 }
1097
dispc_mgr_set_size(enum omap_channel channel,u16 width,u16 height)1098 static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
1099 u16 height)
1100 {
1101 u32 val;
1102
1103 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1104 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1105
1106 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1107 }
1108
dispc_init_fifos(void)1109 static void dispc_init_fifos(void)
1110 {
1111 u32 size;
1112 int fifo;
1113 u8 start, end;
1114 u32 unit;
1115 int i;
1116
1117 unit = dss_feat_get_buffer_size_unit();
1118
1119 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1120
1121 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1122 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
1123 size *= unit;
1124 dispc.fifo_size[fifo] = size;
1125
1126 /*
1127 * By default fifos are mapped directly to overlays, fifo 0 to
1128 * ovl 0, fifo 1 to ovl 1, etc.
1129 */
1130 dispc.fifo_assignment[fifo] = fifo;
1131 }
1132
1133 /*
1134 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1135 * causes problems with certain use cases, like using the tiler in 2D
1136 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1137 * giving GFX plane a larger fifo. WB but should work fine with a
1138 * smaller fifo.
1139 */
1140 if (dispc.feat->gfx_fifo_workaround) {
1141 u32 v;
1142
1143 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1144
1145 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1146 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1147 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1148 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1149
1150 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1151
1152 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1153 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1154 }
1155
1156 /*
1157 * Setup default fifo thresholds.
1158 */
1159 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1160 u32 low, high;
1161 const bool use_fifomerge = false;
1162 const bool manual_update = false;
1163
1164 dispc_ovl_compute_fifo_thresholds(i, &low, &high,
1165 use_fifomerge, manual_update);
1166
1167 dispc_ovl_set_fifo_threshold(i, low, high);
1168 }
1169
1170 if (dispc.feat->has_writeback) {
1171 u32 low, high;
1172 const bool use_fifomerge = false;
1173 const bool manual_update = false;
1174
1175 dispc_ovl_compute_fifo_thresholds(OMAP_DSS_WB, &low, &high,
1176 use_fifomerge, manual_update);
1177
1178 dispc_ovl_set_fifo_threshold(OMAP_DSS_WB, low, high);
1179 }
1180 }
1181
dispc_ovl_get_fifo_size(enum omap_plane plane)1182 static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1183 {
1184 int fifo;
1185 u32 size = 0;
1186
1187 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1188 if (dispc.fifo_assignment[fifo] == plane)
1189 size += dispc.fifo_size[fifo];
1190 }
1191
1192 return size;
1193 }
1194
dispc_ovl_set_fifo_threshold(enum omap_plane plane,u32 low,u32 high)1195 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1196 {
1197 u8 hi_start, hi_end, lo_start, lo_end;
1198 u32 unit;
1199
1200 unit = dss_feat_get_buffer_size_unit();
1201
1202 WARN_ON(low % unit != 0);
1203 WARN_ON(high % unit != 0);
1204
1205 low /= unit;
1206 high /= unit;
1207
1208 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1209 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1210
1211 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1212 plane,
1213 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1214 lo_start, lo_end) * unit,
1215 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1216 hi_start, hi_end) * unit,
1217 low * unit, high * unit);
1218
1219 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1220 FLD_VAL(high, hi_start, hi_end) |
1221 FLD_VAL(low, lo_start, lo_end));
1222
1223 /*
1224 * configure the preload to the pipeline's high threhold, if HT it's too
1225 * large for the preload field, set the threshold to the maximum value
1226 * that can be held by the preload register
1227 */
1228 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1229 plane != OMAP_DSS_WB)
1230 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
1231 }
1232
dispc_enable_fifomerge(bool enable)1233 void dispc_enable_fifomerge(bool enable)
1234 {
1235 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1236 WARN_ON(enable);
1237 return;
1238 }
1239
1240 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1241 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1242 }
1243
dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,u32 * fifo_low,u32 * fifo_high,bool use_fifomerge,bool manual_update)1244 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1245 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1246 bool manual_update)
1247 {
1248 /*
1249 * All sizes are in bytes. Both the buffer and burst are made of
1250 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1251 */
1252
1253 unsigned buf_unit = dss_feat_get_buffer_size_unit();
1254 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1255 int i;
1256
1257 burst_size = dispc_ovl_get_burst_size(plane);
1258 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1259
1260 if (use_fifomerge) {
1261 total_fifo_size = 0;
1262 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1263 total_fifo_size += dispc_ovl_get_fifo_size(i);
1264 } else {
1265 total_fifo_size = ovl_fifo_size;
1266 }
1267
1268 /*
1269 * We use the same low threshold for both fifomerge and non-fifomerge
1270 * cases, but for fifomerge we calculate the high threshold using the
1271 * combined fifo size
1272 */
1273
1274 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1275 *fifo_low = ovl_fifo_size - burst_size * 2;
1276 *fifo_high = total_fifo_size - burst_size;
1277 } else if (plane == OMAP_DSS_WB) {
1278 /*
1279 * Most optimal configuration for writeback is to push out data
1280 * to the interconnect the moment writeback pushes enough pixels
1281 * in the FIFO to form a burst
1282 */
1283 *fifo_low = 0;
1284 *fifo_high = burst_size;
1285 } else {
1286 *fifo_low = ovl_fifo_size - burst_size;
1287 *fifo_high = total_fifo_size - buf_unit;
1288 }
1289 }
1290
dispc_ovl_set_mflag(enum omap_plane plane,bool enable)1291 static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
1292 {
1293 int bit;
1294
1295 if (plane == OMAP_DSS_GFX)
1296 bit = 14;
1297 else
1298 bit = 23;
1299
1300 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1301 }
1302
dispc_ovl_set_mflag_threshold(enum omap_plane plane,int low,int high)1303 static void dispc_ovl_set_mflag_threshold(enum omap_plane plane,
1304 int low, int high)
1305 {
1306 dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
1307 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
1308 }
1309
dispc_init_mflag(void)1310 static void dispc_init_mflag(void)
1311 {
1312 int i;
1313
1314 /*
1315 * HACK: NV12 color format and MFLAG seem to have problems working
1316 * together: using two displays, and having an NV12 overlay on one of
1317 * the displays will cause underflows/synclosts when MFLAG_CTRL=2.
1318 * Changing MFLAG thresholds and PRELOAD to certain values seem to
1319 * remove the errors, but there doesn't seem to be a clear logic on
1320 * which values work and which not.
1321 *
1322 * As a work-around, set force MFLAG to always on.
1323 */
1324 dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,
1325 (1 << 0) | /* MFLAG_CTRL = force always on */
1326 (0 << 2)); /* MFLAG_START = disable */
1327
1328 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1329 u32 size = dispc_ovl_get_fifo_size(i);
1330 u32 unit = dss_feat_get_buffer_size_unit();
1331 u32 low, high;
1332
1333 dispc_ovl_set_mflag(i, true);
1334
1335 /*
1336 * Simulation team suggests below thesholds:
1337 * HT = fifosize * 5 / 8;
1338 * LT = fifosize * 4 / 8;
1339 */
1340
1341 low = size * 4 / 8 / unit;
1342 high = size * 5 / 8 / unit;
1343
1344 dispc_ovl_set_mflag_threshold(i, low, high);
1345 }
1346
1347 if (dispc.feat->has_writeback) {
1348 u32 size = dispc_ovl_get_fifo_size(OMAP_DSS_WB);
1349 u32 unit = dss_feat_get_buffer_size_unit();
1350 u32 low, high;
1351
1352 dispc_ovl_set_mflag(OMAP_DSS_WB, true);
1353
1354 /*
1355 * Simulation team suggests below thesholds:
1356 * HT = fifosize * 5 / 8;
1357 * LT = fifosize * 4 / 8;
1358 */
1359
1360 low = size * 4 / 8 / unit;
1361 high = size * 5 / 8 / unit;
1362
1363 dispc_ovl_set_mflag_threshold(OMAP_DSS_WB, low, high);
1364 }
1365 }
1366
dispc_ovl_set_fir(enum omap_plane plane,int hinc,int vinc,enum omap_color_component color_comp)1367 static void dispc_ovl_set_fir(enum omap_plane plane,
1368 int hinc, int vinc,
1369 enum omap_color_component color_comp)
1370 {
1371 u32 val;
1372
1373 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1374 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1375
1376 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1377 &hinc_start, &hinc_end);
1378 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1379 &vinc_start, &vinc_end);
1380 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1381 FLD_VAL(hinc, hinc_start, hinc_end);
1382
1383 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1384 } else {
1385 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1386 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1387 }
1388 }
1389
dispc_ovl_set_vid_accu0(enum omap_plane plane,int haccu,int vaccu)1390 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1391 {
1392 u32 val;
1393 u8 hor_start, hor_end, vert_start, vert_end;
1394
1395 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1396 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1397
1398 val = FLD_VAL(vaccu, vert_start, vert_end) |
1399 FLD_VAL(haccu, hor_start, hor_end);
1400
1401 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1402 }
1403
dispc_ovl_set_vid_accu1(enum omap_plane plane,int haccu,int vaccu)1404 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1405 {
1406 u32 val;
1407 u8 hor_start, hor_end, vert_start, vert_end;
1408
1409 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1410 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1411
1412 val = FLD_VAL(vaccu, vert_start, vert_end) |
1413 FLD_VAL(haccu, hor_start, hor_end);
1414
1415 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1416 }
1417
dispc_ovl_set_vid_accu2_0(enum omap_plane plane,int haccu,int vaccu)1418 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1419 int vaccu)
1420 {
1421 u32 val;
1422
1423 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1424 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1425 }
1426
dispc_ovl_set_vid_accu2_1(enum omap_plane plane,int haccu,int vaccu)1427 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1428 int vaccu)
1429 {
1430 u32 val;
1431
1432 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1433 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1434 }
1435
dispc_ovl_set_scale_param(enum omap_plane plane,u16 orig_width,u16 orig_height,u16 out_width,u16 out_height,bool five_taps,u8 rotation,enum omap_color_component color_comp)1436 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1437 u16 orig_width, u16 orig_height,
1438 u16 out_width, u16 out_height,
1439 bool five_taps, u8 rotation,
1440 enum omap_color_component color_comp)
1441 {
1442 int fir_hinc, fir_vinc;
1443
1444 fir_hinc = 1024 * orig_width / out_width;
1445 fir_vinc = 1024 * orig_height / out_height;
1446
1447 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1448 color_comp);
1449 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1450 }
1451
dispc_ovl_set_accu_uv(enum omap_plane plane,u16 orig_width,u16 orig_height,u16 out_width,u16 out_height,bool ilace,enum omap_color_mode color_mode,u8 rotation)1452 static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1453 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1454 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1455 {
1456 int h_accu2_0, h_accu2_1;
1457 int v_accu2_0, v_accu2_1;
1458 int chroma_hinc, chroma_vinc;
1459 int idx;
1460
1461 struct accu {
1462 s8 h0_m, h0_n;
1463 s8 h1_m, h1_n;
1464 s8 v0_m, v0_n;
1465 s8 v1_m, v1_n;
1466 };
1467
1468 const struct accu *accu_table;
1469 const struct accu *accu_val;
1470
1471 static const struct accu accu_nv12[4] = {
1472 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1473 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1474 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1475 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1476 };
1477
1478 static const struct accu accu_nv12_ilace[4] = {
1479 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1480 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1481 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1482 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1483 };
1484
1485 static const struct accu accu_yuv[4] = {
1486 { 0, 1, 0, 1, 0, 1, 0, 1 },
1487 { 0, 1, 0, 1, 0, 1, 0, 1 },
1488 { -1, 1, 0, 1, 0, 1, 0, 1 },
1489 { 0, 1, 0, 1, -1, 1, 0, 1 },
1490 };
1491
1492 switch (rotation) {
1493 case OMAP_DSS_ROT_0:
1494 idx = 0;
1495 break;
1496 case OMAP_DSS_ROT_90:
1497 idx = 1;
1498 break;
1499 case OMAP_DSS_ROT_180:
1500 idx = 2;
1501 break;
1502 case OMAP_DSS_ROT_270:
1503 idx = 3;
1504 break;
1505 default:
1506 BUG();
1507 return;
1508 }
1509
1510 switch (color_mode) {
1511 case OMAP_DSS_COLOR_NV12:
1512 if (ilace)
1513 accu_table = accu_nv12_ilace;
1514 else
1515 accu_table = accu_nv12;
1516 break;
1517 case OMAP_DSS_COLOR_YUV2:
1518 case OMAP_DSS_COLOR_UYVY:
1519 accu_table = accu_yuv;
1520 break;
1521 default:
1522 BUG();
1523 return;
1524 }
1525
1526 accu_val = &accu_table[idx];
1527
1528 chroma_hinc = 1024 * orig_width / out_width;
1529 chroma_vinc = 1024 * orig_height / out_height;
1530
1531 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1532 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1533 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1534 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1535
1536 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1537 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1538 }
1539
dispc_ovl_set_scaling_common(enum omap_plane plane,u16 orig_width,u16 orig_height,u16 out_width,u16 out_height,bool ilace,bool five_taps,bool fieldmode,enum omap_color_mode color_mode,u8 rotation)1540 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1541 u16 orig_width, u16 orig_height,
1542 u16 out_width, u16 out_height,
1543 bool ilace, bool five_taps,
1544 bool fieldmode, enum omap_color_mode color_mode,
1545 u8 rotation)
1546 {
1547 int accu0 = 0;
1548 int accu1 = 0;
1549 u32 l;
1550
1551 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1552 out_width, out_height, five_taps,
1553 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1554 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1555
1556 /* RESIZEENABLE and VERTICALTAPS */
1557 l &= ~((0x3 << 5) | (0x1 << 21));
1558 l |= (orig_width != out_width) ? (1 << 5) : 0;
1559 l |= (orig_height != out_height) ? (1 << 6) : 0;
1560 l |= five_taps ? (1 << 21) : 0;
1561
1562 /* VRESIZECONF and HRESIZECONF */
1563 if (dss_has_feature(FEAT_RESIZECONF)) {
1564 l &= ~(0x3 << 7);
1565 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1566 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1567 }
1568
1569 /* LINEBUFFERSPLIT */
1570 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1571 l &= ~(0x1 << 22);
1572 l |= five_taps ? (1 << 22) : 0;
1573 }
1574
1575 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1576
1577 /*
1578 * field 0 = even field = bottom field
1579 * field 1 = odd field = top field
1580 */
1581 if (ilace && !fieldmode) {
1582 accu1 = 0;
1583 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1584 if (accu0 >= 1024/2) {
1585 accu1 = 1024/2;
1586 accu0 -= accu1;
1587 }
1588 }
1589
1590 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1591 dispc_ovl_set_vid_accu1(plane, 0, accu1);
1592 }
1593
dispc_ovl_set_scaling_uv(enum omap_plane plane,u16 orig_width,u16 orig_height,u16 out_width,u16 out_height,bool ilace,bool five_taps,bool fieldmode,enum omap_color_mode color_mode,u8 rotation)1594 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1595 u16 orig_width, u16 orig_height,
1596 u16 out_width, u16 out_height,
1597 bool ilace, bool five_taps,
1598 bool fieldmode, enum omap_color_mode color_mode,
1599 u8 rotation)
1600 {
1601 int scale_x = out_width != orig_width;
1602 int scale_y = out_height != orig_height;
1603 bool chroma_upscale = plane != OMAP_DSS_WB;
1604
1605 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1606 return;
1607 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1608 color_mode != OMAP_DSS_COLOR_UYVY &&
1609 color_mode != OMAP_DSS_COLOR_NV12)) {
1610 /* reset chroma resampling for RGB formats */
1611 if (plane != OMAP_DSS_WB)
1612 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1613 return;
1614 }
1615
1616 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1617 out_height, ilace, color_mode, rotation);
1618
1619 switch (color_mode) {
1620 case OMAP_DSS_COLOR_NV12:
1621 if (chroma_upscale) {
1622 /* UV is subsampled by 2 horizontally and vertically */
1623 orig_height >>= 1;
1624 orig_width >>= 1;
1625 } else {
1626 /* UV is downsampled by 2 horizontally and vertically */
1627 orig_height <<= 1;
1628 orig_width <<= 1;
1629 }
1630
1631 break;
1632 case OMAP_DSS_COLOR_YUV2:
1633 case OMAP_DSS_COLOR_UYVY:
1634 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1635 if (rotation == OMAP_DSS_ROT_0 ||
1636 rotation == OMAP_DSS_ROT_180) {
1637 if (chroma_upscale)
1638 /* UV is subsampled by 2 horizontally */
1639 orig_width >>= 1;
1640 else
1641 /* UV is downsampled by 2 horizontally */
1642 orig_width <<= 1;
1643 }
1644
1645 /* must use FIR for YUV422 if rotated */
1646 if (rotation != OMAP_DSS_ROT_0)
1647 scale_x = scale_y = true;
1648
1649 break;
1650 default:
1651 BUG();
1652 return;
1653 }
1654
1655 if (out_width != orig_width)
1656 scale_x = true;
1657 if (out_height != orig_height)
1658 scale_y = true;
1659
1660 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1661 out_width, out_height, five_taps,
1662 rotation, DISPC_COLOR_COMPONENT_UV);
1663
1664 if (plane != OMAP_DSS_WB)
1665 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1666 (scale_x || scale_y) ? 1 : 0, 8, 8);
1667
1668 /* set H scaling */
1669 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1670 /* set V scaling */
1671 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1672 }
1673
dispc_ovl_set_scaling(enum omap_plane plane,u16 orig_width,u16 orig_height,u16 out_width,u16 out_height,bool ilace,bool five_taps,bool fieldmode,enum omap_color_mode color_mode,u8 rotation)1674 static void dispc_ovl_set_scaling(enum omap_plane plane,
1675 u16 orig_width, u16 orig_height,
1676 u16 out_width, u16 out_height,
1677 bool ilace, bool five_taps,
1678 bool fieldmode, enum omap_color_mode color_mode,
1679 u8 rotation)
1680 {
1681 BUG_ON(plane == OMAP_DSS_GFX);
1682
1683 dispc_ovl_set_scaling_common(plane,
1684 orig_width, orig_height,
1685 out_width, out_height,
1686 ilace, five_taps,
1687 fieldmode, color_mode,
1688 rotation);
1689
1690 dispc_ovl_set_scaling_uv(plane,
1691 orig_width, orig_height,
1692 out_width, out_height,
1693 ilace, five_taps,
1694 fieldmode, color_mode,
1695 rotation);
1696 }
1697
dispc_ovl_set_rotation_attrs(enum omap_plane plane,u8 rotation,enum omap_dss_rotation_type rotation_type,bool mirroring,enum omap_color_mode color_mode)1698 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1699 enum omap_dss_rotation_type rotation_type,
1700 bool mirroring, enum omap_color_mode color_mode)
1701 {
1702 bool row_repeat = false;
1703 int vidrot = 0;
1704
1705 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1706 color_mode == OMAP_DSS_COLOR_UYVY) {
1707
1708 if (mirroring) {
1709 switch (rotation) {
1710 case OMAP_DSS_ROT_0:
1711 vidrot = 2;
1712 break;
1713 case OMAP_DSS_ROT_90:
1714 vidrot = 1;
1715 break;
1716 case OMAP_DSS_ROT_180:
1717 vidrot = 0;
1718 break;
1719 case OMAP_DSS_ROT_270:
1720 vidrot = 3;
1721 break;
1722 }
1723 } else {
1724 switch (rotation) {
1725 case OMAP_DSS_ROT_0:
1726 vidrot = 0;
1727 break;
1728 case OMAP_DSS_ROT_90:
1729 vidrot = 1;
1730 break;
1731 case OMAP_DSS_ROT_180:
1732 vidrot = 2;
1733 break;
1734 case OMAP_DSS_ROT_270:
1735 vidrot = 3;
1736 break;
1737 }
1738 }
1739
1740 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1741 row_repeat = true;
1742 else
1743 row_repeat = false;
1744 }
1745
1746 /*
1747 * OMAP4/5 Errata i631:
1748 * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
1749 * rows beyond the framebuffer, which may cause OCP error.
1750 */
1751 if (color_mode == OMAP_DSS_COLOR_NV12 &&
1752 rotation_type != OMAP_DSS_ROT_TILER)
1753 vidrot = 1;
1754
1755 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1756 if (dss_has_feature(FEAT_ROWREPEATENABLE))
1757 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1758 row_repeat ? 1 : 0, 18, 18);
1759
1760 if (color_mode == OMAP_DSS_COLOR_NV12) {
1761 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1762 (rotation == OMAP_DSS_ROT_0 ||
1763 rotation == OMAP_DSS_ROT_180);
1764 /* DOUBLESTRIDE */
1765 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1766 }
1767
1768 }
1769
color_mode_to_bpp(enum omap_color_mode color_mode)1770 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1771 {
1772 switch (color_mode) {
1773 case OMAP_DSS_COLOR_CLUT1:
1774 return 1;
1775 case OMAP_DSS_COLOR_CLUT2:
1776 return 2;
1777 case OMAP_DSS_COLOR_CLUT4:
1778 return 4;
1779 case OMAP_DSS_COLOR_CLUT8:
1780 case OMAP_DSS_COLOR_NV12:
1781 return 8;
1782 case OMAP_DSS_COLOR_RGB12U:
1783 case OMAP_DSS_COLOR_RGB16:
1784 case OMAP_DSS_COLOR_ARGB16:
1785 case OMAP_DSS_COLOR_YUV2:
1786 case OMAP_DSS_COLOR_UYVY:
1787 case OMAP_DSS_COLOR_RGBA16:
1788 case OMAP_DSS_COLOR_RGBX16:
1789 case OMAP_DSS_COLOR_ARGB16_1555:
1790 case OMAP_DSS_COLOR_XRGB16_1555:
1791 return 16;
1792 case OMAP_DSS_COLOR_RGB24P:
1793 return 24;
1794 case OMAP_DSS_COLOR_RGB24U:
1795 case OMAP_DSS_COLOR_ARGB32:
1796 case OMAP_DSS_COLOR_RGBA32:
1797 case OMAP_DSS_COLOR_RGBX32:
1798 return 32;
1799 default:
1800 BUG();
1801 return 0;
1802 }
1803 }
1804
pixinc(int pixels,u8 ps)1805 static s32 pixinc(int pixels, u8 ps)
1806 {
1807 if (pixels == 1)
1808 return 1;
1809 else if (pixels > 1)
1810 return 1 + (pixels - 1) * ps;
1811 else if (pixels < 0)
1812 return 1 - (-pixels + 1) * ps;
1813 else
1814 BUG();
1815 return 0;
1816 }
1817
calc_vrfb_rotation_offset(u8 rotation,bool mirror,u16 screen_width,u16 width,u16 height,enum omap_color_mode color_mode,bool fieldmode,unsigned int field_offset,unsigned * offset0,unsigned * offset1,s32 * row_inc,s32 * pix_inc,int x_predecim,int y_predecim)1818 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1819 u16 screen_width,
1820 u16 width, u16 height,
1821 enum omap_color_mode color_mode, bool fieldmode,
1822 unsigned int field_offset,
1823 unsigned *offset0, unsigned *offset1,
1824 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1825 {
1826 u8 ps;
1827
1828 /* FIXME CLUT formats */
1829 switch (color_mode) {
1830 case OMAP_DSS_COLOR_CLUT1:
1831 case OMAP_DSS_COLOR_CLUT2:
1832 case OMAP_DSS_COLOR_CLUT4:
1833 case OMAP_DSS_COLOR_CLUT8:
1834 BUG();
1835 return;
1836 case OMAP_DSS_COLOR_YUV2:
1837 case OMAP_DSS_COLOR_UYVY:
1838 ps = 4;
1839 break;
1840 default:
1841 ps = color_mode_to_bpp(color_mode) / 8;
1842 break;
1843 }
1844
1845 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1846 width, height);
1847
1848 /*
1849 * field 0 = even field = bottom field
1850 * field 1 = odd field = top field
1851 */
1852 switch (rotation + mirror * 4) {
1853 case OMAP_DSS_ROT_0:
1854 case OMAP_DSS_ROT_180:
1855 /*
1856 * If the pixel format is YUV or UYVY divide the width
1857 * of the image by 2 for 0 and 180 degree rotation.
1858 */
1859 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1860 color_mode == OMAP_DSS_COLOR_UYVY)
1861 width = width >> 1;
1862 fallthrough;
1863 case OMAP_DSS_ROT_90:
1864 case OMAP_DSS_ROT_270:
1865 *offset1 = 0;
1866 if (field_offset)
1867 *offset0 = field_offset * screen_width * ps;
1868 else
1869 *offset0 = 0;
1870
1871 *row_inc = pixinc(1 +
1872 (y_predecim * screen_width - x_predecim * width) +
1873 (fieldmode ? screen_width : 0), ps);
1874 *pix_inc = pixinc(x_predecim, ps);
1875 break;
1876
1877 case OMAP_DSS_ROT_0 + 4:
1878 case OMAP_DSS_ROT_180 + 4:
1879 /* If the pixel format is YUV or UYVY divide the width
1880 * of the image by 2 for 0 degree and 180 degree
1881 */
1882 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1883 color_mode == OMAP_DSS_COLOR_UYVY)
1884 width = width >> 1;
1885 fallthrough;
1886 case OMAP_DSS_ROT_90 + 4:
1887 case OMAP_DSS_ROT_270 + 4:
1888 *offset1 = 0;
1889 if (field_offset)
1890 *offset0 = field_offset * screen_width * ps;
1891 else
1892 *offset0 = 0;
1893 *row_inc = pixinc(1 -
1894 (y_predecim * screen_width + x_predecim * width) -
1895 (fieldmode ? screen_width : 0), ps);
1896 *pix_inc = pixinc(x_predecim, ps);
1897 break;
1898
1899 default:
1900 BUG();
1901 return;
1902 }
1903 }
1904
calc_dma_rotation_offset(u8 rotation,bool mirror,u16 screen_width,u16 width,u16 height,enum omap_color_mode color_mode,bool fieldmode,unsigned int field_offset,unsigned * offset0,unsigned * offset1,s32 * row_inc,s32 * pix_inc,int x_predecim,int y_predecim)1905 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1906 u16 screen_width,
1907 u16 width, u16 height,
1908 enum omap_color_mode color_mode, bool fieldmode,
1909 unsigned int field_offset,
1910 unsigned *offset0, unsigned *offset1,
1911 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1912 {
1913 u8 ps;
1914 u16 fbw, fbh;
1915
1916 /* FIXME CLUT formats */
1917 switch (color_mode) {
1918 case OMAP_DSS_COLOR_CLUT1:
1919 case OMAP_DSS_COLOR_CLUT2:
1920 case OMAP_DSS_COLOR_CLUT4:
1921 case OMAP_DSS_COLOR_CLUT8:
1922 BUG();
1923 return;
1924 default:
1925 ps = color_mode_to_bpp(color_mode) / 8;
1926 break;
1927 }
1928
1929 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1930 width, height);
1931
1932 /* width & height are overlay sizes, convert to fb sizes */
1933
1934 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1935 fbw = width;
1936 fbh = height;
1937 } else {
1938 fbw = height;
1939 fbh = width;
1940 }
1941
1942 /*
1943 * field 0 = even field = bottom field
1944 * field 1 = odd field = top field
1945 */
1946 switch (rotation + mirror * 4) {
1947 case OMAP_DSS_ROT_0:
1948 *offset1 = 0;
1949 if (field_offset)
1950 *offset0 = *offset1 + field_offset * screen_width * ps;
1951 else
1952 *offset0 = *offset1;
1953 *row_inc = pixinc(1 +
1954 (y_predecim * screen_width - fbw * x_predecim) +
1955 (fieldmode ? screen_width : 0), ps);
1956 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1957 color_mode == OMAP_DSS_COLOR_UYVY)
1958 *pix_inc = pixinc(x_predecim, 2 * ps);
1959 else
1960 *pix_inc = pixinc(x_predecim, ps);
1961 break;
1962 case OMAP_DSS_ROT_90:
1963 *offset1 = screen_width * (fbh - 1) * ps;
1964 if (field_offset)
1965 *offset0 = *offset1 + field_offset * ps;
1966 else
1967 *offset0 = *offset1;
1968 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1969 y_predecim + (fieldmode ? 1 : 0), ps);
1970 *pix_inc = pixinc(-x_predecim * screen_width, ps);
1971 break;
1972 case OMAP_DSS_ROT_180:
1973 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1974 if (field_offset)
1975 *offset0 = *offset1 - field_offset * screen_width * ps;
1976 else
1977 *offset0 = *offset1;
1978 *row_inc = pixinc(-1 -
1979 (y_predecim * screen_width - fbw * x_predecim) -
1980 (fieldmode ? screen_width : 0), ps);
1981 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1982 color_mode == OMAP_DSS_COLOR_UYVY)
1983 *pix_inc = pixinc(-x_predecim, 2 * ps);
1984 else
1985 *pix_inc = pixinc(-x_predecim, ps);
1986 break;
1987 case OMAP_DSS_ROT_270:
1988 *offset1 = (fbw - 1) * ps;
1989 if (field_offset)
1990 *offset0 = *offset1 - field_offset * ps;
1991 else
1992 *offset0 = *offset1;
1993 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1994 y_predecim - (fieldmode ? 1 : 0), ps);
1995 *pix_inc = pixinc(x_predecim * screen_width, ps);
1996 break;
1997
1998 /* mirroring */
1999 case OMAP_DSS_ROT_0 + 4:
2000 *offset1 = (fbw - 1) * ps;
2001 if (field_offset)
2002 *offset0 = *offset1 + field_offset * screen_width * ps;
2003 else
2004 *offset0 = *offset1;
2005 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
2006 (fieldmode ? screen_width : 0),
2007 ps);
2008 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2009 color_mode == OMAP_DSS_COLOR_UYVY)
2010 *pix_inc = pixinc(-x_predecim, 2 * ps);
2011 else
2012 *pix_inc = pixinc(-x_predecim, ps);
2013 break;
2014
2015 case OMAP_DSS_ROT_90 + 4:
2016 *offset1 = 0;
2017 if (field_offset)
2018 *offset0 = *offset1 + field_offset * ps;
2019 else
2020 *offset0 = *offset1;
2021 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
2022 y_predecim + (fieldmode ? 1 : 0),
2023 ps);
2024 *pix_inc = pixinc(x_predecim * screen_width, ps);
2025 break;
2026
2027 case OMAP_DSS_ROT_180 + 4:
2028 *offset1 = screen_width * (fbh - 1) * ps;
2029 if (field_offset)
2030 *offset0 = *offset1 - field_offset * screen_width * ps;
2031 else
2032 *offset0 = *offset1;
2033 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
2034 (fieldmode ? screen_width : 0),
2035 ps);
2036 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2037 color_mode == OMAP_DSS_COLOR_UYVY)
2038 *pix_inc = pixinc(x_predecim, 2 * ps);
2039 else
2040 *pix_inc = pixinc(x_predecim, ps);
2041 break;
2042
2043 case OMAP_DSS_ROT_270 + 4:
2044 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2045 if (field_offset)
2046 *offset0 = *offset1 - field_offset * ps;
2047 else
2048 *offset0 = *offset1;
2049 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
2050 y_predecim - (fieldmode ? 1 : 0),
2051 ps);
2052 *pix_inc = pixinc(-x_predecim * screen_width, ps);
2053 break;
2054
2055 default:
2056 BUG();
2057 return;
2058 }
2059 }
2060
calc_tiler_rotation_offset(u16 screen_width,u16 width,enum omap_color_mode color_mode,bool fieldmode,unsigned int field_offset,unsigned * offset0,unsigned * offset1,s32 * row_inc,s32 * pix_inc,int x_predecim,int y_predecim)2061 static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
2062 enum omap_color_mode color_mode, bool fieldmode,
2063 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
2064 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
2065 {
2066 u8 ps;
2067
2068 switch (color_mode) {
2069 case OMAP_DSS_COLOR_CLUT1:
2070 case OMAP_DSS_COLOR_CLUT2:
2071 case OMAP_DSS_COLOR_CLUT4:
2072 case OMAP_DSS_COLOR_CLUT8:
2073 BUG();
2074 return;
2075 default:
2076 ps = color_mode_to_bpp(color_mode) / 8;
2077 break;
2078 }
2079
2080 DSSDBG("scrw %d, width %d\n", screen_width, width);
2081
2082 /*
2083 * field 0 = even field = bottom field
2084 * field 1 = odd field = top field
2085 */
2086 *offset1 = 0;
2087 if (field_offset)
2088 *offset0 = *offset1 + field_offset * screen_width * ps;
2089 else
2090 *offset0 = *offset1;
2091 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
2092 (fieldmode ? screen_width : 0), ps);
2093 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2094 color_mode == OMAP_DSS_COLOR_UYVY)
2095 *pix_inc = pixinc(x_predecim, 2 * ps);
2096 else
2097 *pix_inc = pixinc(x_predecim, ps);
2098 }
2099
2100 /*
2101 * This function is used to avoid synclosts in OMAP3, because of some
2102 * undocumented horizontal position and timing related limitations.
2103 */
check_horiz_timing_omap3(unsigned long pclk,unsigned long lclk,const struct omap_video_timings * t,u16 pos_x,u16 width,u16 height,u16 out_width,u16 out_height,bool five_taps)2104 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
2105 const struct omap_video_timings *t, u16 pos_x,
2106 u16 width, u16 height, u16 out_width, u16 out_height,
2107 bool five_taps)
2108 {
2109 const int ds = DIV_ROUND_UP(height, out_height);
2110 unsigned long nonactive;
2111 static const u8 limits[3] = { 8, 10, 20 };
2112 u64 val, blank;
2113 int i;
2114
2115 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
2116
2117 i = 0;
2118 if (out_height < height)
2119 i++;
2120 if (out_width < width)
2121 i++;
2122 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
2123 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2124 if (blank <= limits[i])
2125 return -EINVAL;
2126
2127 /* FIXME add checks for 3-tap filter once the limitations are known */
2128 if (!five_taps)
2129 return 0;
2130
2131 /*
2132 * Pixel data should be prepared before visible display point starts.
2133 * So, atleast DS-2 lines must have already been fetched by DISPC
2134 * during nonactive - pos_x period.
2135 */
2136 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2137 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2138 val, max(0, ds - 2) * width);
2139 if (val < max(0, ds - 2) * width)
2140 return -EINVAL;
2141
2142 /*
2143 * All lines need to be refilled during the nonactive period of which
2144 * only one line can be loaded during the active period. So, atleast
2145 * DS - 1 lines should be loaded during nonactive period.
2146 */
2147 val = div_u64((u64)nonactive * lclk, pclk);
2148 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
2149 val, max(0, ds - 1) * width);
2150 if (val < max(0, ds - 1) * width)
2151 return -EINVAL;
2152
2153 return 0;
2154 }
2155
calc_core_clk_five_taps(unsigned long pclk,const struct omap_video_timings * mgr_timings,u16 width,u16 height,u16 out_width,u16 out_height,enum omap_color_mode color_mode)2156 static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2157 const struct omap_video_timings *mgr_timings, u16 width,
2158 u16 height, u16 out_width, u16 out_height,
2159 enum omap_color_mode color_mode)
2160 {
2161 u32 core_clk = 0;
2162 u64 tmp;
2163
2164 if (height <= out_height && width <= out_width)
2165 return (unsigned long) pclk;
2166
2167 if (height > out_height) {
2168 unsigned int ppl = mgr_timings->x_res;
2169
2170 tmp = (u64)pclk * height * out_width;
2171 do_div(tmp, 2 * out_height * ppl);
2172 core_clk = tmp;
2173
2174 if (height > 2 * out_height) {
2175 if (ppl == out_width)
2176 return 0;
2177
2178 tmp = (u64)pclk * (height - 2 * out_height) * out_width;
2179 do_div(tmp, 2 * out_height * (ppl - out_width));
2180 core_clk = max_t(u32, core_clk, tmp);
2181 }
2182 }
2183
2184 if (width > out_width) {
2185 tmp = (u64)pclk * width;
2186 do_div(tmp, out_width);
2187 core_clk = max_t(u32, core_clk, tmp);
2188
2189 if (color_mode == OMAP_DSS_COLOR_RGB24U)
2190 core_clk <<= 1;
2191 }
2192
2193 return core_clk;
2194 }
2195
calc_core_clk_24xx(unsigned long pclk,u16 width,u16 height,u16 out_width,u16 out_height,bool mem_to_mem)2196 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
2197 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2198 {
2199 if (height > out_height && width > out_width)
2200 return pclk * 4;
2201 else
2202 return pclk * 2;
2203 }
2204
calc_core_clk_34xx(unsigned long pclk,u16 width,u16 height,u16 out_width,u16 out_height,bool mem_to_mem)2205 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
2206 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2207 {
2208 unsigned int hf, vf;
2209
2210 /*
2211 * FIXME how to determine the 'A' factor
2212 * for the no downscaling case ?
2213 */
2214
2215 if (width > 3 * out_width)
2216 hf = 4;
2217 else if (width > 2 * out_width)
2218 hf = 3;
2219 else if (width > out_width)
2220 hf = 2;
2221 else
2222 hf = 1;
2223 if (height > out_height)
2224 vf = 2;
2225 else
2226 vf = 1;
2227
2228 return pclk * vf * hf;
2229 }
2230
calc_core_clk_44xx(unsigned long pclk,u16 width,u16 height,u16 out_width,u16 out_height,bool mem_to_mem)2231 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2232 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2233 {
2234 /*
2235 * If the overlay/writeback is in mem to mem mode, there are no
2236 * downscaling limitations with respect to pixel clock, return 1 as
2237 * required core clock to represent that we have sufficient enough
2238 * core clock to do maximum downscaling
2239 */
2240 if (mem_to_mem)
2241 return 1;
2242
2243 if (width > out_width)
2244 return DIV_ROUND_UP(pclk, out_width) * width;
2245 else
2246 return pclk;
2247 }
2248
dispc_ovl_calc_scaling_24xx(unsigned long pclk,unsigned long lclk,const struct omap_video_timings * mgr_timings,u16 width,u16 height,u16 out_width,u16 out_height,enum omap_color_mode color_mode,bool * five_taps,int * x_predecim,int * y_predecim,int * decim_x,int * decim_y,u16 pos_x,unsigned long * core_clk,bool mem_to_mem)2249 static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2250 const struct omap_video_timings *mgr_timings,
2251 u16 width, u16 height, u16 out_width, u16 out_height,
2252 enum omap_color_mode color_mode, bool *five_taps,
2253 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2254 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2255 {
2256 int error;
2257 u16 in_width, in_height;
2258 int min_factor = min(*decim_x, *decim_y);
2259 const int maxsinglelinewidth =
2260 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2261
2262 *five_taps = false;
2263
2264 do {
2265 in_height = height / *decim_y;
2266 in_width = width / *decim_x;
2267 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2268 in_height, out_width, out_height, mem_to_mem);
2269 error = (in_width > maxsinglelinewidth || !*core_clk ||
2270 *core_clk > dispc_core_clk_rate());
2271 if (error) {
2272 if (*decim_x == *decim_y) {
2273 *decim_x = min_factor;
2274 ++*decim_y;
2275 } else {
2276 swap(*decim_x, *decim_y);
2277 if (*decim_x < *decim_y)
2278 ++*decim_x;
2279 }
2280 }
2281 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2282
2283 if (error) {
2284 DSSERR("failed to find scaling settings\n");
2285 return -EINVAL;
2286 }
2287
2288 if (in_width > maxsinglelinewidth) {
2289 DSSERR("Cannot scale max input width exceeded");
2290 return -EINVAL;
2291 }
2292 return 0;
2293 }
2294
dispc_ovl_calc_scaling_34xx(unsigned long pclk,unsigned long lclk,const struct omap_video_timings * mgr_timings,u16 width,u16 height,u16 out_width,u16 out_height,enum omap_color_mode color_mode,bool * five_taps,int * x_predecim,int * y_predecim,int * decim_x,int * decim_y,u16 pos_x,unsigned long * core_clk,bool mem_to_mem)2295 static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
2296 const struct omap_video_timings *mgr_timings,
2297 u16 width, u16 height, u16 out_width, u16 out_height,
2298 enum omap_color_mode color_mode, bool *five_taps,
2299 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2300 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2301 {
2302 int error;
2303 u16 in_width, in_height;
2304 const int maxsinglelinewidth =
2305 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2306
2307 do {
2308 in_height = height / *decim_y;
2309 in_width = width / *decim_x;
2310 *five_taps = in_height > out_height;
2311
2312 if (in_width > maxsinglelinewidth)
2313 if (in_height > out_height &&
2314 in_height < out_height * 2)
2315 *five_taps = false;
2316 again:
2317 if (*five_taps)
2318 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2319 in_width, in_height, out_width,
2320 out_height, color_mode);
2321 else
2322 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2323 in_height, out_width, out_height,
2324 mem_to_mem);
2325
2326 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2327 pos_x, in_width, in_height, out_width,
2328 out_height, *five_taps);
2329 if (error && *five_taps) {
2330 *five_taps = false;
2331 goto again;
2332 }
2333
2334 error = (error || in_width > maxsinglelinewidth * 2 ||
2335 (in_width > maxsinglelinewidth && *five_taps) ||
2336 !*core_clk || *core_clk > dispc_core_clk_rate());
2337
2338 if (!error) {
2339 /* verify that we're inside the limits of scaler */
2340 if (in_width / 4 > out_width)
2341 error = 1;
2342
2343 if (*five_taps) {
2344 if (in_height / 4 > out_height)
2345 error = 1;
2346 } else {
2347 if (in_height / 2 > out_height)
2348 error = 1;
2349 }
2350 }
2351
2352 if (error)
2353 ++*decim_y;
2354 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2355
2356 if (error) {
2357 DSSERR("failed to find scaling settings\n");
2358 return -EINVAL;
2359 }
2360
2361 if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width,
2362 in_height, out_width, out_height, *five_taps)) {
2363 DSSERR("horizontal timing too tight\n");
2364 return -EINVAL;
2365 }
2366
2367 if (in_width > (maxsinglelinewidth * 2)) {
2368 DSSERR("Cannot setup scaling");
2369 DSSERR("width exceeds maximum width possible");
2370 return -EINVAL;
2371 }
2372
2373 if (in_width > maxsinglelinewidth && *five_taps) {
2374 DSSERR("cannot setup scaling with five taps");
2375 return -EINVAL;
2376 }
2377 return 0;
2378 }
2379
dispc_ovl_calc_scaling_44xx(unsigned long pclk,unsigned long lclk,const struct omap_video_timings * mgr_timings,u16 width,u16 height,u16 out_width,u16 out_height,enum omap_color_mode color_mode,bool * five_taps,int * x_predecim,int * y_predecim,int * decim_x,int * decim_y,u16 pos_x,unsigned long * core_clk,bool mem_to_mem)2380 static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2381 const struct omap_video_timings *mgr_timings,
2382 u16 width, u16 height, u16 out_width, u16 out_height,
2383 enum omap_color_mode color_mode, bool *five_taps,
2384 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2385 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2386 {
2387 u16 in_width, in_width_max;
2388 int decim_x_min = *decim_x;
2389 u16 in_height = height / *decim_y;
2390 const int maxsinglelinewidth =
2391 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2392 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2393
2394 if (mem_to_mem) {
2395 in_width_max = out_width * maxdownscale;
2396 } else {
2397 in_width_max = dispc_core_clk_rate() /
2398 DIV_ROUND_UP(pclk, out_width);
2399 }
2400
2401 *decim_x = DIV_ROUND_UP(width, in_width_max);
2402
2403 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2404 if (*decim_x > *x_predecim)
2405 return -EINVAL;
2406
2407 do {
2408 in_width = width / *decim_x;
2409 } while (*decim_x <= *x_predecim &&
2410 in_width > maxsinglelinewidth && ++*decim_x);
2411
2412 if (in_width > maxsinglelinewidth) {
2413 DSSERR("Cannot scale width exceeds max line width");
2414 return -EINVAL;
2415 }
2416
2417 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
2418 out_width, out_height, mem_to_mem);
2419 return 0;
2420 }
2421
2422 #define DIV_FRAC(dividend, divisor) \
2423 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2424
dispc_ovl_calc_scaling(unsigned long pclk,unsigned long lclk,enum omap_overlay_caps caps,const struct omap_video_timings * mgr_timings,u16 width,u16 height,u16 out_width,u16 out_height,enum omap_color_mode color_mode,bool * five_taps,int * x_predecim,int * y_predecim,u16 pos_x,enum omap_dss_rotation_type rotation_type,bool mem_to_mem)2425 static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2426 enum omap_overlay_caps caps,
2427 const struct omap_video_timings *mgr_timings,
2428 u16 width, u16 height, u16 out_width, u16 out_height,
2429 enum omap_color_mode color_mode, bool *five_taps,
2430 int *x_predecim, int *y_predecim, u16 pos_x,
2431 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
2432 {
2433 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2434 const int max_decim_limit = 16;
2435 unsigned long core_clk = 0;
2436 int decim_x, decim_y, ret;
2437
2438 if (width == out_width && height == out_height)
2439 return 0;
2440
2441 if (!mem_to_mem && (pclk == 0 || mgr_timings->pixelclock == 0)) {
2442 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2443 return -EINVAL;
2444 }
2445
2446 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2447 return -EINVAL;
2448
2449 if (mem_to_mem) {
2450 *x_predecim = *y_predecim = 1;
2451 } else {
2452 *x_predecim = max_decim_limit;
2453 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2454 dss_has_feature(FEAT_BURST_2D)) ?
2455 2 : max_decim_limit;
2456 }
2457
2458 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2459 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2460 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2461 color_mode == OMAP_DSS_COLOR_CLUT8) {
2462 *x_predecim = 1;
2463 *y_predecim = 1;
2464 *five_taps = false;
2465 return 0;
2466 }
2467
2468 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2469 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2470
2471 if (decim_x > *x_predecim || out_width > width * 8)
2472 return -EINVAL;
2473
2474 if (decim_y > *y_predecim || out_height > height * 8)
2475 return -EINVAL;
2476
2477 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
2478 out_width, out_height, color_mode, five_taps,
2479 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2480 mem_to_mem);
2481 if (ret)
2482 return ret;
2483
2484 DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n",
2485 width, height,
2486 out_width, out_height,
2487 out_width / width, DIV_FRAC(out_width, width),
2488 out_height / height, DIV_FRAC(out_height, height),
2489
2490 decim_x, decim_y,
2491 width / decim_x, height / decim_y,
2492 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x),
2493 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y),
2494
2495 *five_taps ? 5 : 3,
2496 core_clk, dispc_core_clk_rate());
2497
2498 if (!core_clk || core_clk > dispc_core_clk_rate()) {
2499 DSSERR("failed to set up scaling, "
2500 "required core clk rate = %lu Hz, "
2501 "current core clk rate = %lu Hz\n",
2502 core_clk, dispc_core_clk_rate());
2503 return -EINVAL;
2504 }
2505
2506 *x_predecim = decim_x;
2507 *y_predecim = decim_y;
2508 return 0;
2509 }
2510
dispc_ovl_check(enum omap_plane plane,enum omap_channel channel,const struct omap_overlay_info * oi,const struct omap_video_timings * timings,int * x_predecim,int * y_predecim)2511 int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
2512 const struct omap_overlay_info *oi,
2513 const struct omap_video_timings *timings,
2514 int *x_predecim, int *y_predecim)
2515 {
2516 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2517 bool five_taps = true;
2518 bool fieldmode = false;
2519 u16 in_height = oi->height;
2520 u16 in_width = oi->width;
2521 bool ilace = timings->interlace;
2522 u16 out_width, out_height;
2523 int pos_x = oi->pos_x;
2524 unsigned long pclk = dispc_mgr_pclk_rate(channel);
2525 unsigned long lclk = dispc_mgr_lclk_rate(channel);
2526
2527 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2528 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
2529
2530 if (ilace && oi->height == out_height)
2531 fieldmode = true;
2532
2533 if (ilace) {
2534 if (fieldmode)
2535 in_height /= 2;
2536 out_height /= 2;
2537
2538 DSSDBG("adjusting for ilace: height %d, out_height %d\n",
2539 in_height, out_height);
2540 }
2541
2542 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
2543 return -EINVAL;
2544
2545 return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width,
2546 in_height, out_width, out_height, oi->color_mode,
2547 &five_taps, x_predecim, y_predecim, pos_x,
2548 oi->rotation_type, false);
2549 }
2550 EXPORT_SYMBOL(dispc_ovl_check);
2551
dispc_ovl_setup_common(enum omap_plane plane,enum omap_overlay_caps caps,u32 paddr,u32 p_uv_addr,u16 screen_width,int pos_x,int pos_y,u16 width,u16 height,u16 out_width,u16 out_height,enum omap_color_mode color_mode,u8 rotation,bool mirror,u8 zorder,u8 pre_mult_alpha,u8 global_alpha,enum omap_dss_rotation_type rotation_type,bool replication,const struct omap_video_timings * mgr_timings,bool mem_to_mem)2552 static int dispc_ovl_setup_common(enum omap_plane plane,
2553 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2554 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2555 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2556 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2557 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
2558 bool replication, const struct omap_video_timings *mgr_timings,
2559 bool mem_to_mem)
2560 {
2561 bool five_taps = true;
2562 bool fieldmode = false;
2563 int r, cconv = 0;
2564 unsigned offset0, offset1;
2565 s32 row_inc;
2566 s32 pix_inc;
2567 u16 frame_width, frame_height;
2568 unsigned int field_offset = 0;
2569 u16 in_height = height;
2570 u16 in_width = width;
2571 int x_predecim = 1, y_predecim = 1;
2572 bool ilace = mgr_timings->interlace;
2573 unsigned long pclk = dispc_plane_pclk_rate(plane);
2574 unsigned long lclk = dispc_plane_lclk_rate(plane);
2575
2576 if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
2577 return -EINVAL;
2578
2579 switch (color_mode) {
2580 case OMAP_DSS_COLOR_YUV2:
2581 case OMAP_DSS_COLOR_UYVY:
2582 case OMAP_DSS_COLOR_NV12:
2583 if (in_width & 1) {
2584 DSSERR("input width %d is not even for YUV format\n",
2585 in_width);
2586 return -EINVAL;
2587 }
2588 break;
2589
2590 default:
2591 break;
2592 }
2593
2594 out_width = out_width == 0 ? width : out_width;
2595 out_height = out_height == 0 ? height : out_height;
2596
2597 if (ilace && height == out_height)
2598 fieldmode = true;
2599
2600 if (ilace) {
2601 if (fieldmode)
2602 in_height /= 2;
2603 pos_y /= 2;
2604 out_height /= 2;
2605
2606 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2607 "out_height %d\n", in_height, pos_y,
2608 out_height);
2609 }
2610
2611 if (!dss_feat_color_mode_supported(plane, color_mode))
2612 return -EINVAL;
2613
2614 r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
2615 in_height, out_width, out_height, color_mode,
2616 &five_taps, &x_predecim, &y_predecim, pos_x,
2617 rotation_type, mem_to_mem);
2618 if (r)
2619 return r;
2620
2621 in_width = in_width / x_predecim;
2622 in_height = in_height / y_predecim;
2623
2624 if (x_predecim > 1 || y_predecim > 1)
2625 DSSDBG("predecimation %d x %x, new input size %d x %d\n",
2626 x_predecim, y_predecim, in_width, in_height);
2627
2628 switch (color_mode) {
2629 case OMAP_DSS_COLOR_YUV2:
2630 case OMAP_DSS_COLOR_UYVY:
2631 case OMAP_DSS_COLOR_NV12:
2632 if (in_width & 1) {
2633 DSSDBG("predecimated input width is not even for YUV format\n");
2634 DSSDBG("adjusting input width %d -> %d\n",
2635 in_width, in_width & ~1);
2636
2637 in_width &= ~1;
2638 }
2639 break;
2640
2641 default:
2642 break;
2643 }
2644
2645 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2646 color_mode == OMAP_DSS_COLOR_UYVY ||
2647 color_mode == OMAP_DSS_COLOR_NV12)
2648 cconv = 1;
2649
2650 if (ilace && !fieldmode) {
2651 /*
2652 * when downscaling the bottom field may have to start several
2653 * source lines below the top field. Unfortunately ACCUI
2654 * registers will only hold the fractional part of the offset
2655 * so the integer part must be added to the base address of the
2656 * bottom field.
2657 */
2658 if (!in_height || in_height == out_height)
2659 field_offset = 0;
2660 else
2661 field_offset = in_height / out_height / 2;
2662 }
2663
2664 /* Fields are independent but interleaved in memory. */
2665 if (fieldmode)
2666 field_offset = 1;
2667
2668 offset0 = 0;
2669 offset1 = 0;
2670 row_inc = 0;
2671 pix_inc = 0;
2672
2673 if (plane == OMAP_DSS_WB) {
2674 frame_width = out_width;
2675 frame_height = out_height;
2676 } else {
2677 frame_width = in_width;
2678 frame_height = height;
2679 }
2680
2681 if (rotation_type == OMAP_DSS_ROT_TILER)
2682 calc_tiler_rotation_offset(screen_width, frame_width,
2683 color_mode, fieldmode, field_offset,
2684 &offset0, &offset1, &row_inc, &pix_inc,
2685 x_predecim, y_predecim);
2686 else if (rotation_type == OMAP_DSS_ROT_DMA)
2687 calc_dma_rotation_offset(rotation, mirror, screen_width,
2688 frame_width, frame_height,
2689 color_mode, fieldmode, field_offset,
2690 &offset0, &offset1, &row_inc, &pix_inc,
2691 x_predecim, y_predecim);
2692 else
2693 calc_vrfb_rotation_offset(rotation, mirror,
2694 screen_width, frame_width, frame_height,
2695 color_mode, fieldmode, field_offset,
2696 &offset0, &offset1, &row_inc, &pix_inc,
2697 x_predecim, y_predecim);
2698
2699 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2700 offset0, offset1, row_inc, pix_inc);
2701
2702 dispc_ovl_set_color_mode(plane, color_mode);
2703
2704 dispc_ovl_configure_burst_type(plane, rotation_type);
2705
2706 dispc_ovl_set_ba0(plane, paddr + offset0);
2707 dispc_ovl_set_ba1(plane, paddr + offset1);
2708
2709 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2710 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2711 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
2712 }
2713
2714 if (dispc.feat->last_pixel_inc_missing)
2715 row_inc += pix_inc - 1;
2716
2717 dispc_ovl_set_row_inc(plane, row_inc);
2718 dispc_ovl_set_pix_inc(plane, pix_inc);
2719
2720 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2721 in_height, out_width, out_height);
2722
2723 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
2724
2725 dispc_ovl_set_input_size(plane, in_width, in_height);
2726
2727 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2728 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2729 out_height, ilace, five_taps, fieldmode,
2730 color_mode, rotation);
2731 dispc_ovl_set_output_size(plane, out_width, out_height);
2732 dispc_ovl_set_vid_color_conv(plane, cconv);
2733 }
2734
2735 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2736 color_mode);
2737
2738 dispc_ovl_set_zorder(plane, caps, zorder);
2739 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2740 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
2741
2742 dispc_ovl_enable_replication(plane, caps, replication);
2743
2744 return 0;
2745 }
2746
dispc_ovl_setup(enum omap_plane plane,const struct omap_overlay_info * oi,bool replication,const struct omap_video_timings * mgr_timings,bool mem_to_mem)2747 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2748 bool replication, const struct omap_video_timings *mgr_timings,
2749 bool mem_to_mem)
2750 {
2751 int r;
2752 enum omap_overlay_caps caps;
2753 enum omap_channel channel;
2754
2755 if (plane == OMAP_DSS_WB)
2756 return -EINVAL;
2757
2758 caps = dss_feat_get_overlay_caps(plane);
2759 channel = dispc_ovl_get_channel_out(plane);
2760
2761 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2762 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2763 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
2764 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2765 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2766
2767 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
2768 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2769 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2770 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2771 oi->rotation_type, replication, mgr_timings, mem_to_mem);
2772
2773 return r;
2774 }
2775 EXPORT_SYMBOL(dispc_ovl_setup);
2776
dispc_ovl_enable(enum omap_plane plane,bool enable)2777 int dispc_ovl_enable(enum omap_plane plane, bool enable)
2778 {
2779 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2780
2781 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2782
2783 return 0;
2784 }
2785 EXPORT_SYMBOL(dispc_ovl_enable);
2786
dispc_ovl_enabled(enum omap_plane plane)2787 bool dispc_ovl_enabled(enum omap_plane plane)
2788 {
2789 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2790 }
2791 EXPORT_SYMBOL(dispc_ovl_enabled);
2792
dispc_mgr_enable(enum omap_channel channel,bool enable)2793 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2794 {
2795 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2796 /* flush posted write */
2797 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2798 }
2799 EXPORT_SYMBOL(dispc_mgr_enable);
2800
dispc_mgr_is_enabled(enum omap_channel channel)2801 bool dispc_mgr_is_enabled(enum omap_channel channel)
2802 {
2803 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2804 }
2805 EXPORT_SYMBOL(dispc_mgr_is_enabled);
2806
dispc_lcd_enable_signal_polarity(bool act_high)2807 static void dispc_lcd_enable_signal_polarity(bool act_high)
2808 {
2809 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2810 return;
2811
2812 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2813 }
2814
dispc_lcd_enable_signal(bool enable)2815 void dispc_lcd_enable_signal(bool enable)
2816 {
2817 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2818 return;
2819
2820 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2821 }
2822
dispc_pck_free_enable(bool enable)2823 void dispc_pck_free_enable(bool enable)
2824 {
2825 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2826 return;
2827
2828 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2829 }
2830
dispc_mgr_enable_fifohandcheck(enum omap_channel channel,bool enable)2831 static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2832 {
2833 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2834 }
2835
2836
dispc_mgr_set_lcd_type_tft(enum omap_channel channel)2837 static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2838 {
2839 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2840 }
2841
dispc_set_loadmode(enum omap_dss_load_mode mode)2842 static void dispc_set_loadmode(enum omap_dss_load_mode mode)
2843 {
2844 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2845 }
2846
2847
dispc_mgr_set_default_color(enum omap_channel channel,u32 color)2848 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2849 {
2850 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2851 }
2852
dispc_mgr_set_trans_key(enum omap_channel ch,enum omap_dss_trans_key_type type,u32 trans_key)2853 static void dispc_mgr_set_trans_key(enum omap_channel ch,
2854 enum omap_dss_trans_key_type type,
2855 u32 trans_key)
2856 {
2857 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
2858
2859 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2860 }
2861
dispc_mgr_enable_trans_key(enum omap_channel ch,bool enable)2862 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2863 {
2864 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
2865 }
2866
dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,bool enable)2867 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2868 bool enable)
2869 {
2870 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2871 return;
2872
2873 if (ch == OMAP_DSS_CHANNEL_LCD)
2874 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2875 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2876 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2877 }
2878
dispc_mgr_setup(enum omap_channel channel,const struct omap_overlay_manager_info * info)2879 void dispc_mgr_setup(enum omap_channel channel,
2880 const struct omap_overlay_manager_info *info)
2881 {
2882 dispc_mgr_set_default_color(channel, info->default_color);
2883 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2884 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2885 dispc_mgr_enable_alpha_fixed_zorder(channel,
2886 info->partial_alpha_enabled);
2887 if (dss_has_feature(FEAT_CPR)) {
2888 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2889 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2890 }
2891 }
2892 EXPORT_SYMBOL(dispc_mgr_setup);
2893
dispc_mgr_set_tft_data_lines(enum omap_channel channel,u8 data_lines)2894 static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2895 {
2896 int code;
2897
2898 switch (data_lines) {
2899 case 12:
2900 code = 0;
2901 break;
2902 case 16:
2903 code = 1;
2904 break;
2905 case 18:
2906 code = 2;
2907 break;
2908 case 24:
2909 code = 3;
2910 break;
2911 default:
2912 BUG();
2913 return;
2914 }
2915
2916 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
2917 }
2918
dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)2919 static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2920 {
2921 u32 l;
2922 int gpout0, gpout1;
2923
2924 switch (mode) {
2925 case DSS_IO_PAD_MODE_RESET:
2926 gpout0 = 0;
2927 gpout1 = 0;
2928 break;
2929 case DSS_IO_PAD_MODE_RFBI:
2930 gpout0 = 1;
2931 gpout1 = 0;
2932 break;
2933 case DSS_IO_PAD_MODE_BYPASS:
2934 gpout0 = 1;
2935 gpout1 = 1;
2936 break;
2937 default:
2938 BUG();
2939 return;
2940 }
2941
2942 l = dispc_read_reg(DISPC_CONTROL);
2943 l = FLD_MOD(l, gpout0, 15, 15);
2944 l = FLD_MOD(l, gpout1, 16, 16);
2945 dispc_write_reg(DISPC_CONTROL, l);
2946 }
2947
dispc_mgr_enable_stallmode(enum omap_channel channel,bool enable)2948 static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2949 {
2950 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
2951 }
2952
dispc_mgr_set_lcd_config(enum omap_channel channel,const struct dss_lcd_mgr_config * config)2953 void dispc_mgr_set_lcd_config(enum omap_channel channel,
2954 const struct dss_lcd_mgr_config *config)
2955 {
2956 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
2957
2958 dispc_mgr_enable_stallmode(channel, config->stallmode);
2959 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
2960
2961 dispc_mgr_set_clock_div(channel, &config->clock_info);
2962
2963 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
2964
2965 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
2966
2967 dispc_mgr_set_lcd_type_tft(channel);
2968 }
2969 EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
2970
_dispc_mgr_size_ok(u16 width,u16 height)2971 static bool _dispc_mgr_size_ok(u16 width, u16 height)
2972 {
2973 return width <= dispc.feat->mgr_width_max &&
2974 height <= dispc.feat->mgr_height_max;
2975 }
2976
_dispc_lcd_timings_ok(int hsw,int hfp,int hbp,int vsw,int vfp,int vbp)2977 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2978 int vsw, int vfp, int vbp)
2979 {
2980 if (hsw < 1 || hsw > dispc.feat->sw_max ||
2981 hfp < 1 || hfp > dispc.feat->hp_max ||
2982 hbp < 1 || hbp > dispc.feat->hp_max ||
2983 vsw < 1 || vsw > dispc.feat->sw_max ||
2984 vfp < 0 || vfp > dispc.feat->vp_max ||
2985 vbp < 0 || vbp > dispc.feat->vp_max)
2986 return false;
2987 return true;
2988 }
2989
_dispc_mgr_pclk_ok(enum omap_channel channel,unsigned long pclk)2990 static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
2991 unsigned long pclk)
2992 {
2993 if (dss_mgr_is_lcd(channel))
2994 return pclk <= dispc.feat->max_lcd_pclk;
2995 else
2996 return pclk <= dispc.feat->max_tv_pclk;
2997 }
2998
dispc_mgr_timings_ok(enum omap_channel channel,const struct omap_video_timings * timings)2999 bool dispc_mgr_timings_ok(enum omap_channel channel,
3000 const struct omap_video_timings *timings)
3001 {
3002 if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res))
3003 return false;
3004
3005 if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock))
3006 return false;
3007
3008 if (dss_mgr_is_lcd(channel)) {
3009 /* TODO: OMAP4+ supports interlace for LCD outputs */
3010 if (timings->interlace)
3011 return false;
3012
3013 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
3014 timings->hbp, timings->vsw, timings->vfp,
3015 timings->vbp))
3016 return false;
3017 }
3018
3019 return true;
3020 }
3021
_dispc_mgr_set_lcd_timings(enum omap_channel channel,int hsw,int hfp,int hbp,int vsw,int vfp,int vbp,enum omap_dss_signal_level vsync_level,enum omap_dss_signal_level hsync_level,enum omap_dss_signal_edge data_pclk_edge,enum omap_dss_signal_level de_level,enum omap_dss_signal_edge sync_pclk_edge)3022 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
3023 int hfp, int hbp, int vsw, int vfp, int vbp,
3024 enum omap_dss_signal_level vsync_level,
3025 enum omap_dss_signal_level hsync_level,
3026 enum omap_dss_signal_edge data_pclk_edge,
3027 enum omap_dss_signal_level de_level,
3028 enum omap_dss_signal_edge sync_pclk_edge)
3029
3030 {
3031 u32 timing_h, timing_v, l;
3032 bool onoff, rf, ipc, vs, hs, de;
3033
3034 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
3035 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
3036 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
3037 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
3038 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
3039 FLD_VAL(vbp, dispc.feat->bp_start, 20);
3040
3041 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
3042 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
3043
3044 switch (vsync_level) {
3045 case OMAPDSS_SIG_ACTIVE_LOW:
3046 vs = true;
3047 break;
3048 case OMAPDSS_SIG_ACTIVE_HIGH:
3049 vs = false;
3050 break;
3051 default:
3052 BUG();
3053 }
3054
3055 switch (hsync_level) {
3056 case OMAPDSS_SIG_ACTIVE_LOW:
3057 hs = true;
3058 break;
3059 case OMAPDSS_SIG_ACTIVE_HIGH:
3060 hs = false;
3061 break;
3062 default:
3063 BUG();
3064 }
3065
3066 switch (de_level) {
3067 case OMAPDSS_SIG_ACTIVE_LOW:
3068 de = true;
3069 break;
3070 case OMAPDSS_SIG_ACTIVE_HIGH:
3071 de = false;
3072 break;
3073 default:
3074 BUG();
3075 }
3076
3077 switch (data_pclk_edge) {
3078 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3079 ipc = false;
3080 break;
3081 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3082 ipc = true;
3083 break;
3084 default:
3085 BUG();
3086 }
3087
3088 /* always use the 'rf' setting */
3089 onoff = true;
3090
3091 switch (sync_pclk_edge) {
3092 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3093 rf = false;
3094 break;
3095 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3096 rf = true;
3097 break;
3098 default:
3099 BUG();
3100 }
3101
3102 l = FLD_VAL(onoff, 17, 17) |
3103 FLD_VAL(rf, 16, 16) |
3104 FLD_VAL(de, 15, 15) |
3105 FLD_VAL(ipc, 14, 14) |
3106 FLD_VAL(hs, 13, 13) |
3107 FLD_VAL(vs, 12, 12);
3108
3109 /* always set ALIGN bit when available */
3110 if (dispc.feat->supports_sync_align)
3111 l |= (1 << 18);
3112
3113 dispc_write_reg(DISPC_POL_FREQ(channel), l);
3114
3115 if (dispc.syscon_pol) {
3116 const int shifts[] = {
3117 [OMAP_DSS_CHANNEL_LCD] = 0,
3118 [OMAP_DSS_CHANNEL_LCD2] = 1,
3119 [OMAP_DSS_CHANNEL_LCD3] = 2,
3120 };
3121
3122 u32 mask, val;
3123
3124 mask = (1 << 0) | (1 << 3) | (1 << 6);
3125 val = (rf << 0) | (ipc << 3) | (onoff << 6);
3126
3127 mask <<= 16 + shifts[channel];
3128 val <<= 16 + shifts[channel];
3129
3130 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset,
3131 mask, val);
3132 }
3133 }
3134
3135 /* change name to mode? */
dispc_mgr_set_timings(enum omap_channel channel,const struct omap_video_timings * timings)3136 void dispc_mgr_set_timings(enum omap_channel channel,
3137 const struct omap_video_timings *timings)
3138 {
3139 unsigned xtot, ytot;
3140 unsigned long ht, vt;
3141 struct omap_video_timings t = *timings;
3142
3143 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
3144
3145 if (!dispc_mgr_timings_ok(channel, &t)) {
3146 BUG();
3147 return;
3148 }
3149
3150 if (dss_mgr_is_lcd(channel)) {
3151 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
3152 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
3153 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
3154
3155 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
3156 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
3157
3158 ht = timings->pixelclock / xtot;
3159 vt = timings->pixelclock / xtot / ytot;
3160
3161 DSSDBG("pck %u\n", timings->pixelclock);
3162 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
3163 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
3164 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3165 t.vsync_level, t.hsync_level, t.data_pclk_edge,
3166 t.de_level, t.sync_pclk_edge);
3167
3168 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
3169 } else {
3170 if (t.interlace)
3171 t.y_res /= 2;
3172 }
3173
3174 dispc_mgr_set_size(channel, t.x_res, t.y_res);
3175 }
3176 EXPORT_SYMBOL(dispc_mgr_set_timings);
3177
dispc_mgr_set_lcd_divisor(enum omap_channel channel,u16 lck_div,u16 pck_div)3178 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
3179 u16 pck_div)
3180 {
3181 BUG_ON(lck_div < 1);
3182 BUG_ON(pck_div < 1);
3183
3184 dispc_write_reg(DISPC_DIVISORo(channel),
3185 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
3186
3187 if (!dss_has_feature(FEAT_CORE_CLK_DIV) &&
3188 channel == OMAP_DSS_CHANNEL_LCD)
3189 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
3190 }
3191
dispc_mgr_get_lcd_divisor(enum omap_channel channel,int * lck_div,int * pck_div)3192 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
3193 int *pck_div)
3194 {
3195 u32 l;
3196 l = dispc_read_reg(DISPC_DIVISORo(channel));
3197 *lck_div = FLD_GET(l, 23, 16);
3198 *pck_div = FLD_GET(l, 7, 0);
3199 }
3200
dispc_fclk_rate(void)3201 static unsigned long dispc_fclk_rate(void)
3202 {
3203 struct dss_pll *pll;
3204 unsigned long r = 0;
3205
3206 switch (dss_get_dispc_clk_source()) {
3207 case OMAP_DSS_CLK_SRC_FCK:
3208 r = dss_get_dispc_clk_rate();
3209 break;
3210 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3211 pll = dss_pll_find("dsi0");
3212 if (!pll)
3213 pll = dss_pll_find("video0");
3214
3215 r = pll->cinfo.clkout[0];
3216 break;
3217 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3218 pll = dss_pll_find("dsi1");
3219 if (!pll)
3220 pll = dss_pll_find("video1");
3221
3222 r = pll->cinfo.clkout[0];
3223 break;
3224 default:
3225 BUG();
3226 return 0;
3227 }
3228
3229 return r;
3230 }
3231
dispc_mgr_lclk_rate(enum omap_channel channel)3232 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
3233 {
3234 struct dss_pll *pll;
3235 int lcd;
3236 unsigned long r;
3237 u32 l;
3238
3239 if (dss_mgr_is_lcd(channel)) {
3240 l = dispc_read_reg(DISPC_DIVISORo(channel));
3241
3242 lcd = FLD_GET(l, 23, 16);
3243
3244 switch (dss_get_lcd_clk_source(channel)) {
3245 case OMAP_DSS_CLK_SRC_FCK:
3246 r = dss_get_dispc_clk_rate();
3247 break;
3248 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3249 pll = dss_pll_find("dsi0");
3250 if (!pll)
3251 pll = dss_pll_find("video0");
3252
3253 r = pll->cinfo.clkout[0];
3254 break;
3255 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3256 pll = dss_pll_find("dsi1");
3257 if (!pll)
3258 pll = dss_pll_find("video1");
3259
3260 r = pll->cinfo.clkout[0];
3261 break;
3262 default:
3263 BUG();
3264 return 0;
3265 }
3266
3267 return r / lcd;
3268 } else {
3269 return dispc_fclk_rate();
3270 }
3271 }
3272
dispc_mgr_pclk_rate(enum omap_channel channel)3273 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
3274 {
3275 unsigned long r;
3276
3277 if (dss_mgr_is_lcd(channel)) {
3278 int pcd;
3279 u32 l;
3280
3281 l = dispc_read_reg(DISPC_DIVISORo(channel));
3282
3283 pcd = FLD_GET(l, 7, 0);
3284
3285 r = dispc_mgr_lclk_rate(channel);
3286
3287 return r / pcd;
3288 } else {
3289 return dispc.tv_pclk_rate;
3290 }
3291 }
3292
dispc_set_tv_pclk(unsigned long pclk)3293 void dispc_set_tv_pclk(unsigned long pclk)
3294 {
3295 dispc.tv_pclk_rate = pclk;
3296 }
3297
dispc_core_clk_rate(void)3298 static unsigned long dispc_core_clk_rate(void)
3299 {
3300 return dispc.core_clk_rate;
3301 }
3302
dispc_plane_pclk_rate(enum omap_plane plane)3303 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3304 {
3305 enum omap_channel channel;
3306
3307 if (plane == OMAP_DSS_WB)
3308 return 0;
3309
3310 channel = dispc_ovl_get_channel_out(plane);
3311
3312 return dispc_mgr_pclk_rate(channel);
3313 }
3314
dispc_plane_lclk_rate(enum omap_plane plane)3315 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3316 {
3317 enum omap_channel channel;
3318
3319 if (plane == OMAP_DSS_WB)
3320 return 0;
3321
3322 channel = dispc_ovl_get_channel_out(plane);
3323
3324 return dispc_mgr_lclk_rate(channel);
3325 }
3326
dispc_dump_clocks_channel(struct seq_file * s,enum omap_channel channel)3327 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
3328 {
3329 int lcd, pcd;
3330 enum omap_dss_clk_source lcd_clk_src;
3331
3332 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3333
3334 lcd_clk_src = dss_get_lcd_clk_source(channel);
3335
3336 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3337 dss_get_generic_clk_source_name(lcd_clk_src),
3338 dss_feat_get_clk_source_name(lcd_clk_src));
3339
3340 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3341
3342 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3343 dispc_mgr_lclk_rate(channel), lcd);
3344 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3345 dispc_mgr_pclk_rate(channel), pcd);
3346 }
3347
dispc_dump_clocks(struct seq_file * s)3348 void dispc_dump_clocks(struct seq_file *s)
3349 {
3350 int lcd;
3351 u32 l;
3352 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
3353
3354 if (dispc_runtime_get())
3355 return;
3356
3357 seq_printf(s, "- DISPC -\n");
3358
3359 seq_printf(s, "dispc fclk source = %s (%s)\n",
3360 dss_get_generic_clk_source_name(dispc_clk_src),
3361 dss_feat_get_clk_source_name(dispc_clk_src));
3362
3363 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
3364
3365 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3366 seq_printf(s, "- DISPC-CORE-CLK -\n");
3367 l = dispc_read_reg(DISPC_DIVISOR);
3368 lcd = FLD_GET(l, 23, 16);
3369
3370 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3371 (dispc_fclk_rate()/lcd), lcd);
3372 }
3373
3374 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
3375
3376 if (dss_has_feature(FEAT_MGR_LCD2))
3377 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3378 if (dss_has_feature(FEAT_MGR_LCD3))
3379 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
3380
3381 dispc_runtime_put();
3382 }
3383
dispc_dump_regs(struct seq_file * s)3384 static void dispc_dump_regs(struct seq_file *s)
3385 {
3386 int i, j;
3387 const char *mgr_names[] = {
3388 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3389 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3390 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
3391 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
3392 };
3393 const char *ovl_names[] = {
3394 [OMAP_DSS_GFX] = "GFX",
3395 [OMAP_DSS_VIDEO1] = "VID1",
3396 [OMAP_DSS_VIDEO2] = "VID2",
3397 [OMAP_DSS_VIDEO3] = "VID3",
3398 [OMAP_DSS_WB] = "WB",
3399 };
3400 const char **p_names;
3401
3402 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
3403
3404 if (dispc_runtime_get())
3405 return;
3406
3407 /* DISPC common registers */
3408 DUMPREG(DISPC_REVISION);
3409 DUMPREG(DISPC_SYSCONFIG);
3410 DUMPREG(DISPC_SYSSTATUS);
3411 DUMPREG(DISPC_IRQSTATUS);
3412 DUMPREG(DISPC_IRQENABLE);
3413 DUMPREG(DISPC_CONTROL);
3414 DUMPREG(DISPC_CONFIG);
3415 DUMPREG(DISPC_CAPABLE);
3416 DUMPREG(DISPC_LINE_STATUS);
3417 DUMPREG(DISPC_LINE_NUMBER);
3418 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3419 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
3420 DUMPREG(DISPC_GLOBAL_ALPHA);
3421 if (dss_has_feature(FEAT_MGR_LCD2)) {
3422 DUMPREG(DISPC_CONTROL2);
3423 DUMPREG(DISPC_CONFIG2);
3424 }
3425 if (dss_has_feature(FEAT_MGR_LCD3)) {
3426 DUMPREG(DISPC_CONTROL3);
3427 DUMPREG(DISPC_CONFIG3);
3428 }
3429 if (dss_has_feature(FEAT_MFLAG))
3430 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
3431
3432 #undef DUMPREG
3433
3434 #define DISPC_REG(i, name) name(i)
3435 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3436 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
3437 dispc_read_reg(DISPC_REG(i, r)))
3438
3439 p_names = mgr_names;
3440
3441 /* DISPC channel specific registers */
3442 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3443 DUMPREG(i, DISPC_DEFAULT_COLOR);
3444 DUMPREG(i, DISPC_TRANS_COLOR);
3445 DUMPREG(i, DISPC_SIZE_MGR);
3446
3447 if (i == OMAP_DSS_CHANNEL_DIGIT)
3448 continue;
3449
3450 DUMPREG(i, DISPC_TIMING_H);
3451 DUMPREG(i, DISPC_TIMING_V);
3452 DUMPREG(i, DISPC_POL_FREQ);
3453 DUMPREG(i, DISPC_DIVISORo);
3454
3455 DUMPREG(i, DISPC_DATA_CYCLE1);
3456 DUMPREG(i, DISPC_DATA_CYCLE2);
3457 DUMPREG(i, DISPC_DATA_CYCLE3);
3458
3459 if (dss_has_feature(FEAT_CPR)) {
3460 DUMPREG(i, DISPC_CPR_COEF_R);
3461 DUMPREG(i, DISPC_CPR_COEF_G);
3462 DUMPREG(i, DISPC_CPR_COEF_B);
3463 }
3464 }
3465
3466 p_names = ovl_names;
3467
3468 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3469 DUMPREG(i, DISPC_OVL_BA0);
3470 DUMPREG(i, DISPC_OVL_BA1);
3471 DUMPREG(i, DISPC_OVL_POSITION);
3472 DUMPREG(i, DISPC_OVL_SIZE);
3473 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3474 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3475 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3476 DUMPREG(i, DISPC_OVL_ROW_INC);
3477 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3478
3479 if (dss_has_feature(FEAT_PRELOAD))
3480 DUMPREG(i, DISPC_OVL_PRELOAD);
3481 if (dss_has_feature(FEAT_MFLAG))
3482 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3483
3484 if (i == OMAP_DSS_GFX) {
3485 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3486 DUMPREG(i, DISPC_OVL_TABLE_BA);
3487 continue;
3488 }
3489
3490 DUMPREG(i, DISPC_OVL_FIR);
3491 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3492 DUMPREG(i, DISPC_OVL_ACCU0);
3493 DUMPREG(i, DISPC_OVL_ACCU1);
3494 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3495 DUMPREG(i, DISPC_OVL_BA0_UV);
3496 DUMPREG(i, DISPC_OVL_BA1_UV);
3497 DUMPREG(i, DISPC_OVL_FIR2);
3498 DUMPREG(i, DISPC_OVL_ACCU2_0);
3499 DUMPREG(i, DISPC_OVL_ACCU2_1);
3500 }
3501 if (dss_has_feature(FEAT_ATTR2))
3502 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3503 }
3504
3505 if (dispc.feat->has_writeback) {
3506 i = OMAP_DSS_WB;
3507 DUMPREG(i, DISPC_OVL_BA0);
3508 DUMPREG(i, DISPC_OVL_BA1);
3509 DUMPREG(i, DISPC_OVL_SIZE);
3510 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3511 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3512 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3513 DUMPREG(i, DISPC_OVL_ROW_INC);
3514 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3515
3516 if (dss_has_feature(FEAT_MFLAG))
3517 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3518
3519 DUMPREG(i, DISPC_OVL_FIR);
3520 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3521 DUMPREG(i, DISPC_OVL_ACCU0);
3522 DUMPREG(i, DISPC_OVL_ACCU1);
3523 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3524 DUMPREG(i, DISPC_OVL_BA0_UV);
3525 DUMPREG(i, DISPC_OVL_BA1_UV);
3526 DUMPREG(i, DISPC_OVL_FIR2);
3527 DUMPREG(i, DISPC_OVL_ACCU2_0);
3528 DUMPREG(i, DISPC_OVL_ACCU2_1);
3529 }
3530 if (dss_has_feature(FEAT_ATTR2))
3531 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3532 }
3533
3534 #undef DISPC_REG
3535 #undef DUMPREG
3536
3537 #define DISPC_REG(plane, name, i) name(plane, i)
3538 #define DUMPREG(plane, name, i) \
3539 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3540 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3541 dispc_read_reg(DISPC_REG(plane, name, i)))
3542
3543 /* Video pipeline coefficient registers */
3544
3545 /* start from OMAP_DSS_VIDEO1 */
3546 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3547 for (j = 0; j < 8; j++)
3548 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
3549
3550 for (j = 0; j < 8; j++)
3551 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
3552
3553 for (j = 0; j < 5; j++)
3554 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
3555
3556 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3557 for (j = 0; j < 8; j++)
3558 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3559 }
3560
3561 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3562 for (j = 0; j < 8; j++)
3563 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3564
3565 for (j = 0; j < 8; j++)
3566 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3567
3568 for (j = 0; j < 8; j++)
3569 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3570 }
3571 }
3572
3573 dispc_runtime_put();
3574
3575 #undef DISPC_REG
3576 #undef DUMPREG
3577 }
3578
3579 /* calculate clock rates using dividers in cinfo */
dispc_calc_clock_rates(unsigned long dispc_fclk_rate,struct dispc_clock_info * cinfo)3580 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3581 struct dispc_clock_info *cinfo)
3582 {
3583 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3584 return -EINVAL;
3585 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3586 return -EINVAL;
3587
3588 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3589 cinfo->pck = cinfo->lck / cinfo->pck_div;
3590
3591 return 0;
3592 }
3593
dispc_div_calc(unsigned long dispc,unsigned long pck_min,unsigned long pck_max,dispc_div_calc_func func,void * data)3594 bool dispc_div_calc(unsigned long dispc,
3595 unsigned long pck_min, unsigned long pck_max,
3596 dispc_div_calc_func func, void *data)
3597 {
3598 int lckd, lckd_start, lckd_stop;
3599 int pckd, pckd_start, pckd_stop;
3600 unsigned long pck, lck;
3601 unsigned long lck_max;
3602 unsigned long pckd_hw_min, pckd_hw_max;
3603 unsigned min_fck_per_pck;
3604 unsigned long fck;
3605
3606 #ifdef CONFIG_FB_OMAP2_DSS_MIN_FCK_PER_PCK
3607 min_fck_per_pck = CONFIG_FB_OMAP2_DSS_MIN_FCK_PER_PCK;
3608 #else
3609 min_fck_per_pck = 0;
3610 #endif
3611
3612 pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3613 pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3614
3615 lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
3616
3617 pck_min = pck_min ? pck_min : 1;
3618 pck_max = pck_max ? pck_max : ULONG_MAX;
3619
3620 lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3621 lckd_stop = min(dispc / pck_min, 255ul);
3622
3623 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3624 lck = dispc / lckd;
3625
3626 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3627 pckd_stop = min(lck / pck_min, pckd_hw_max);
3628
3629 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3630 pck = lck / pckd;
3631
3632 /*
3633 * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3634 * clock, which means we're configuring DISPC fclk here
3635 * also. Thus we need to use the calculated lck. For
3636 * OMAP4+ the DISPC fclk is a separate clock.
3637 */
3638 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3639 fck = dispc_core_clk_rate();
3640 else
3641 fck = lck;
3642
3643 if (fck < pck * min_fck_per_pck)
3644 continue;
3645
3646 if (func(lckd, pckd, lck, pck, data))
3647 return true;
3648 }
3649 }
3650
3651 return false;
3652 }
3653
dispc_mgr_set_clock_div(enum omap_channel channel,const struct dispc_clock_info * cinfo)3654 void dispc_mgr_set_clock_div(enum omap_channel channel,
3655 const struct dispc_clock_info *cinfo)
3656 {
3657 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3658 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3659
3660 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
3661 }
3662
dispc_mgr_get_clock_div(enum omap_channel channel,struct dispc_clock_info * cinfo)3663 int dispc_mgr_get_clock_div(enum omap_channel channel,
3664 struct dispc_clock_info *cinfo)
3665 {
3666 unsigned long fck;
3667
3668 fck = dispc_fclk_rate();
3669
3670 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3671 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
3672
3673 cinfo->lck = fck / cinfo->lck_div;
3674 cinfo->pck = cinfo->lck / cinfo->pck_div;
3675
3676 return 0;
3677 }
3678
dispc_read_irqstatus(void)3679 u32 dispc_read_irqstatus(void)
3680 {
3681 return dispc_read_reg(DISPC_IRQSTATUS);
3682 }
3683 EXPORT_SYMBOL(dispc_read_irqstatus);
3684
dispc_clear_irqstatus(u32 mask)3685 void dispc_clear_irqstatus(u32 mask)
3686 {
3687 dispc_write_reg(DISPC_IRQSTATUS, mask);
3688 }
3689 EXPORT_SYMBOL(dispc_clear_irqstatus);
3690
dispc_read_irqenable(void)3691 u32 dispc_read_irqenable(void)
3692 {
3693 return dispc_read_reg(DISPC_IRQENABLE);
3694 }
3695 EXPORT_SYMBOL(dispc_read_irqenable);
3696
dispc_write_irqenable(u32 mask)3697 void dispc_write_irqenable(u32 mask)
3698 {
3699 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3700
3701 /* clear the irqstatus for newly enabled irqs */
3702 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3703
3704 dispc_write_reg(DISPC_IRQENABLE, mask);
3705 }
3706 EXPORT_SYMBOL(dispc_write_irqenable);
3707
dispc_enable_sidle(void)3708 void dispc_enable_sidle(void)
3709 {
3710 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3711 }
3712
dispc_disable_sidle(void)3713 void dispc_disable_sidle(void)
3714 {
3715 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3716 }
3717
_omap_dispc_initial_config(void)3718 static void _omap_dispc_initial_config(void)
3719 {
3720 u32 l;
3721
3722 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3723 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3724 l = dispc_read_reg(DISPC_DIVISOR);
3725 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3726 l = FLD_MOD(l, 1, 0, 0);
3727 l = FLD_MOD(l, 1, 23, 16);
3728 dispc_write_reg(DISPC_DIVISOR, l);
3729
3730 dispc.core_clk_rate = dispc_fclk_rate();
3731 }
3732
3733 /* FUNCGATED */
3734 if (dss_has_feature(FEAT_FUNCGATED))
3735 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3736
3737 dispc_setup_color_conv_coef();
3738
3739 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3740
3741 dispc_init_fifos();
3742
3743 dispc_configure_burst_sizes();
3744
3745 dispc_ovl_enable_zorder_planes();
3746
3747 if (dispc.feat->mstandby_workaround)
3748 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
3749
3750 if (dss_has_feature(FEAT_MFLAG))
3751 dispc_init_mflag();
3752 }
3753
3754 static const struct dispc_features omap24xx_dispc_feats = {
3755 .sw_start = 5,
3756 .fp_start = 15,
3757 .bp_start = 27,
3758 .sw_max = 64,
3759 .vp_max = 255,
3760 .hp_max = 256,
3761 .mgr_width_start = 10,
3762 .mgr_height_start = 26,
3763 .mgr_width_max = 2048,
3764 .mgr_height_max = 2048,
3765 .max_lcd_pclk = 66500000,
3766 .calc_scaling = dispc_ovl_calc_scaling_24xx,
3767 .calc_core_clk = calc_core_clk_24xx,
3768 .num_fifos = 3,
3769 .no_framedone_tv = true,
3770 .set_max_preload = false,
3771 .last_pixel_inc_missing = true,
3772 };
3773
3774 static const struct dispc_features omap34xx_rev1_0_dispc_feats = {
3775 .sw_start = 5,
3776 .fp_start = 15,
3777 .bp_start = 27,
3778 .sw_max = 64,
3779 .vp_max = 255,
3780 .hp_max = 256,
3781 .mgr_width_start = 10,
3782 .mgr_height_start = 26,
3783 .mgr_width_max = 2048,
3784 .mgr_height_max = 2048,
3785 .max_lcd_pclk = 173000000,
3786 .max_tv_pclk = 59000000,
3787 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3788 .calc_core_clk = calc_core_clk_34xx,
3789 .num_fifos = 3,
3790 .no_framedone_tv = true,
3791 .set_max_preload = false,
3792 .last_pixel_inc_missing = true,
3793 };
3794
3795 static const struct dispc_features omap34xx_rev3_0_dispc_feats = {
3796 .sw_start = 7,
3797 .fp_start = 19,
3798 .bp_start = 31,
3799 .sw_max = 256,
3800 .vp_max = 4095,
3801 .hp_max = 4096,
3802 .mgr_width_start = 10,
3803 .mgr_height_start = 26,
3804 .mgr_width_max = 2048,
3805 .mgr_height_max = 2048,
3806 .max_lcd_pclk = 173000000,
3807 .max_tv_pclk = 59000000,
3808 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3809 .calc_core_clk = calc_core_clk_34xx,
3810 .num_fifos = 3,
3811 .no_framedone_tv = true,
3812 .set_max_preload = false,
3813 .last_pixel_inc_missing = true,
3814 };
3815
3816 static const struct dispc_features omap44xx_dispc_feats = {
3817 .sw_start = 7,
3818 .fp_start = 19,
3819 .bp_start = 31,
3820 .sw_max = 256,
3821 .vp_max = 4095,
3822 .hp_max = 4096,
3823 .mgr_width_start = 10,
3824 .mgr_height_start = 26,
3825 .mgr_width_max = 2048,
3826 .mgr_height_max = 2048,
3827 .max_lcd_pclk = 170000000,
3828 .max_tv_pclk = 185625000,
3829 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3830 .calc_core_clk = calc_core_clk_44xx,
3831 .num_fifos = 5,
3832 .gfx_fifo_workaround = true,
3833 .set_max_preload = true,
3834 .supports_sync_align = true,
3835 .has_writeback = true,
3836 };
3837
3838 static const struct dispc_features omap54xx_dispc_feats = {
3839 .sw_start = 7,
3840 .fp_start = 19,
3841 .bp_start = 31,
3842 .sw_max = 256,
3843 .vp_max = 4095,
3844 .hp_max = 4096,
3845 .mgr_width_start = 11,
3846 .mgr_height_start = 27,
3847 .mgr_width_max = 4096,
3848 .mgr_height_max = 4096,
3849 .max_lcd_pclk = 170000000,
3850 .max_tv_pclk = 186000000,
3851 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3852 .calc_core_clk = calc_core_clk_44xx,
3853 .num_fifos = 5,
3854 .gfx_fifo_workaround = true,
3855 .mstandby_workaround = true,
3856 .set_max_preload = true,
3857 .supports_sync_align = true,
3858 .has_writeback = true,
3859 };
3860
dispc_get_features(void)3861 static const struct dispc_features *dispc_get_features(void)
3862 {
3863 switch (omapdss_get_version()) {
3864 case OMAPDSS_VER_OMAP24xx:
3865 return &omap24xx_dispc_feats;
3866
3867 case OMAPDSS_VER_OMAP34xx_ES1:
3868 return &omap34xx_rev1_0_dispc_feats;
3869
3870 case OMAPDSS_VER_OMAP34xx_ES3:
3871 case OMAPDSS_VER_OMAP3630:
3872 case OMAPDSS_VER_AM35xx:
3873 case OMAPDSS_VER_AM43xx:
3874 return &omap34xx_rev3_0_dispc_feats;
3875
3876 case OMAPDSS_VER_OMAP4430_ES1:
3877 case OMAPDSS_VER_OMAP4430_ES2:
3878 case OMAPDSS_VER_OMAP4:
3879 return &omap44xx_dispc_feats;
3880
3881 case OMAPDSS_VER_OMAP5:
3882 case OMAPDSS_VER_DRA7xx:
3883 return &omap54xx_dispc_feats;
3884
3885 default:
3886 return NULL;
3887 }
3888 }
3889
dispc_irq_handler(int irq,void * arg)3890 static irqreturn_t dispc_irq_handler(int irq, void *arg)
3891 {
3892 if (!dispc.is_enabled)
3893 return IRQ_NONE;
3894
3895 return dispc.user_handler(irq, dispc.user_data);
3896 }
3897
dispc_request_irq(irq_handler_t handler,void * dev_id)3898 int dispc_request_irq(irq_handler_t handler, void *dev_id)
3899 {
3900 int r;
3901
3902 if (dispc.user_handler != NULL)
3903 return -EBUSY;
3904
3905 dispc.user_handler = handler;
3906 dispc.user_data = dev_id;
3907
3908 /* ensure the dispc_irq_handler sees the values above */
3909 smp_wmb();
3910
3911 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
3912 IRQF_SHARED, "OMAP DISPC", &dispc);
3913 if (r) {
3914 dispc.user_handler = NULL;
3915 dispc.user_data = NULL;
3916 }
3917
3918 return r;
3919 }
3920 EXPORT_SYMBOL(dispc_request_irq);
3921
dispc_free_irq(void * dev_id)3922 void dispc_free_irq(void *dev_id)
3923 {
3924 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
3925
3926 dispc.user_handler = NULL;
3927 dispc.user_data = NULL;
3928 }
3929 EXPORT_SYMBOL(dispc_free_irq);
3930
3931 /* DISPC HW IP initialisation */
dispc_bind(struct device * dev,struct device * master,void * data)3932 static int dispc_bind(struct device *dev, struct device *master, void *data)
3933 {
3934 struct platform_device *pdev = to_platform_device(dev);
3935 u32 rev;
3936 int r = 0;
3937 struct resource *dispc_mem;
3938 struct device_node *np = pdev->dev.of_node;
3939
3940 dispc.pdev = pdev;
3941
3942 spin_lock_init(&dispc.control_lock);
3943
3944 dispc.feat = dispc_get_features();
3945 if (!dispc.feat)
3946 return -ENODEV;
3947
3948 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3949 if (!dispc_mem) {
3950 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3951 return -EINVAL;
3952 }
3953
3954 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3955 resource_size(dispc_mem));
3956 if (!dispc.base) {
3957 DSSERR("can't ioremap DISPC\n");
3958 return -ENOMEM;
3959 }
3960
3961 dispc.irq = platform_get_irq(dispc.pdev, 0);
3962 if (dispc.irq < 0) {
3963 DSSERR("platform_get_irq failed\n");
3964 return -ENODEV;
3965 }
3966
3967 if (np && of_property_read_bool(np, "syscon-pol")) {
3968 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
3969 if (IS_ERR(dispc.syscon_pol)) {
3970 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
3971 return PTR_ERR(dispc.syscon_pol);
3972 }
3973
3974 if (of_property_read_u32_index(np, "syscon-pol", 1,
3975 &dispc.syscon_pol_offset)) {
3976 dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
3977 return -EINVAL;
3978 }
3979 }
3980
3981 pm_runtime_enable(&pdev->dev);
3982
3983 r = dispc_runtime_get();
3984 if (r)
3985 goto err_runtime_get;
3986
3987 _omap_dispc_initial_config();
3988
3989 rev = dispc_read_reg(DISPC_REVISION);
3990 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
3991 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3992
3993 dispc_runtime_put();
3994
3995 dss_init_overlay_managers();
3996
3997 dss_debugfs_create_file("dispc", dispc_dump_regs);
3998
3999 return 0;
4000
4001 err_runtime_get:
4002 pm_runtime_disable(&pdev->dev);
4003 return r;
4004 }
4005
dispc_unbind(struct device * dev,struct device * master,void * data)4006 static void dispc_unbind(struct device *dev, struct device *master,
4007 void *data)
4008 {
4009 pm_runtime_disable(dev);
4010
4011 dss_uninit_overlay_managers();
4012 }
4013
4014 static const struct component_ops dispc_component_ops = {
4015 .bind = dispc_bind,
4016 .unbind = dispc_unbind,
4017 };
4018
dispc_probe(struct platform_device * pdev)4019 static int dispc_probe(struct platform_device *pdev)
4020 {
4021 return component_add(&pdev->dev, &dispc_component_ops);
4022 }
4023
dispc_remove(struct platform_device * pdev)4024 static void dispc_remove(struct platform_device *pdev)
4025 {
4026 component_del(&pdev->dev, &dispc_component_ops);
4027 }
4028
dispc_runtime_suspend(struct device * dev)4029 static int dispc_runtime_suspend(struct device *dev)
4030 {
4031 dispc.is_enabled = false;
4032 /* ensure the dispc_irq_handler sees the is_enabled value */
4033 smp_wmb();
4034 /* wait for current handler to finish before turning the DISPC off */
4035 synchronize_irq(dispc.irq);
4036
4037 dispc_save_context();
4038
4039 return 0;
4040 }
4041
dispc_runtime_resume(struct device * dev)4042 static int dispc_runtime_resume(struct device *dev)
4043 {
4044 /*
4045 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
4046 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
4047 * _omap_dispc_initial_config(). We can thus use it to detect if
4048 * we have lost register context.
4049 */
4050 if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
4051 _omap_dispc_initial_config();
4052
4053 dispc_restore_context();
4054 }
4055
4056 dispc.is_enabled = true;
4057 /* ensure the dispc_irq_handler sees the is_enabled value */
4058 smp_wmb();
4059
4060 return 0;
4061 }
4062
4063 static const struct dev_pm_ops dispc_pm_ops = {
4064 .runtime_suspend = dispc_runtime_suspend,
4065 .runtime_resume = dispc_runtime_resume,
4066 };
4067
4068 static const struct of_device_id dispc_of_match[] = {
4069 { .compatible = "ti,omap2-dispc", },
4070 { .compatible = "ti,omap3-dispc", },
4071 { .compatible = "ti,omap4-dispc", },
4072 { .compatible = "ti,omap5-dispc", },
4073 { .compatible = "ti,dra7-dispc", },
4074 {},
4075 };
4076
4077 static struct platform_driver omap_dispchw_driver = {
4078 .probe = dispc_probe,
4079 .remove_new = dispc_remove,
4080 .driver = {
4081 .name = "omapdss_dispc",
4082 .pm = &dispc_pm_ops,
4083 .of_match_table = dispc_of_match,
4084 .suppress_bind_attrs = true,
4085 },
4086 };
4087
dispc_init_platform_driver(void)4088 int __init dispc_init_platform_driver(void)
4089 {
4090 return platform_driver_register(&omap_dispchw_driver);
4091 }
4092
dispc_uninit_platform_driver(void)4093 void dispc_uninit_platform_driver(void)
4094 {
4095 platform_driver_unregister(&omap_dispchw_driver);
4096 }
4097