1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * IPQ5332 device tree source 4 * 5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,apss-ipq.h> 9#include <dt-bindings/clock/qcom,ipq5332-gcc.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11 12/ { 13 interrupt-parent = <&intc>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 clocks { 18 sleep_clk: sleep-clk { 19 compatible = "fixed-clock"; 20 #clock-cells = <0>; 21 }; 22 23 xo_board: xo-board-clk { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 }; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 CPU0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a53"; 36 reg = <0x0>; 37 enable-method = "psci"; 38 next-level-cache = <&L2_0>; 39 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 40 operating-points-v2 = <&cpu_opp_table>; 41 }; 42 43 CPU1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a53"; 46 reg = <0x1>; 47 enable-method = "psci"; 48 next-level-cache = <&L2_0>; 49 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 50 operating-points-v2 = <&cpu_opp_table>; 51 }; 52 53 CPU2: cpu@2 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a53"; 56 reg = <0x2>; 57 enable-method = "psci"; 58 next-level-cache = <&L2_0>; 59 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 60 operating-points-v2 = <&cpu_opp_table>; 61 }; 62 63 CPU3: cpu@3 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a53"; 66 reg = <0x3>; 67 enable-method = "psci"; 68 next-level-cache = <&L2_0>; 69 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 70 operating-points-v2 = <&cpu_opp_table>; 71 }; 72 73 L2_0: l2-cache { 74 compatible = "cache"; 75 cache-level = <2>; 76 cache-unified; 77 }; 78 }; 79 80 firmware { 81 scm { 82 compatible = "qcom,scm-ipq5332", "qcom,scm"; 83 qcom,dload-mode = <&tcsr 0x6100>; 84 }; 85 }; 86 87 memory@40000000 { 88 device_type = "memory"; 89 /* We expect the bootloader to fill in the size */ 90 reg = <0x0 0x40000000 0x0 0x0>; 91 }; 92 93 cpu_opp_table: opp-table-cpu { 94 compatible = "operating-points-v2"; 95 opp-shared; 96 97 opp-1488000000 { 98 opp-hz = /bits/ 64 <1488000000>; 99 clock-latency-ns = <200000>; 100 }; 101 }; 102 103 pmu { 104 compatible = "arm,cortex-a53-pmu"; 105 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 106 }; 107 108 psci { 109 compatible = "arm,psci-1.0"; 110 method = "smc"; 111 }; 112 113 reserved-memory { 114 #address-cells = <2>; 115 #size-cells = <2>; 116 ranges; 117 118 bootloader@4a100000 { 119 reg = <0x0 0x4a100000 0x0 0x400000>; 120 no-map; 121 }; 122 123 sbl@4a500000 { 124 reg = <0x0 0x4a500000 0x0 0x100000>; 125 no-map; 126 }; 127 128 tz_mem: tz@4a600000 { 129 reg = <0x0 0x4a600000 0x0 0x200000>; 130 no-map; 131 }; 132 133 smem@4a800000 { 134 compatible = "qcom,smem"; 135 reg = <0x0 0x4a800000 0x0 0x100000>; 136 no-map; 137 138 hwlocks = <&tcsr_mutex 3>; 139 }; 140 }; 141 142 soc@0 { 143 compatible = "simple-bus"; 144 #address-cells = <1>; 145 #size-cells = <1>; 146 ranges = <0 0 0 0xffffffff>; 147 148 qfprom: efuse@a4000 { 149 compatible = "qcom,ipq5332-qfprom", "qcom,qfprom"; 150 reg = <0x000a4000 0x721>; 151 #address-cells = <1>; 152 #size-cells = <1>; 153 }; 154 155 rng: rng@e3000 { 156 compatible = "qcom,prng-ee"; 157 reg = <0x000e3000 0x1000>; 158 clocks = <&gcc GCC_PRNG_AHB_CLK>; 159 clock-names = "core"; 160 }; 161 162 tlmm: pinctrl@1000000 { 163 compatible = "qcom,ipq5332-tlmm"; 164 reg = <0x01000000 0x300000>; 165 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 166 gpio-controller; 167 #gpio-cells = <2>; 168 gpio-ranges = <&tlmm 0 0 53>; 169 interrupt-controller; 170 #interrupt-cells = <2>; 171 172 serial_0_pins: serial0-state { 173 pins = "gpio18", "gpio19"; 174 function = "blsp0_uart0"; 175 drive-strength = <8>; 176 bias-pull-up; 177 }; 178 }; 179 180 gcc: clock-controller@1800000 { 181 compatible = "qcom,ipq5332-gcc"; 182 reg = <0x01800000 0x80000>; 183 #clock-cells = <1>; 184 #reset-cells = <1>; 185 #power-domain-cells = <1>; 186 clocks = <&xo_board>, 187 <&sleep_clk>, 188 <0>, 189 <0>, 190 <0>; 191 }; 192 193 tcsr_mutex: hwlock@1905000 { 194 compatible = "qcom,tcsr-mutex"; 195 reg = <0x01905000 0x20000>; 196 #hwlock-cells = <1>; 197 }; 198 199 tcsr: syscon@1937000 { 200 compatible = "qcom,tcsr-ipq5332", "syscon"; 201 reg = <0x01937000 0x21000>; 202 }; 203 204 sdhc: mmc@7804000 { 205 compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5"; 206 reg = <0x07804000 0x1000>, <0x07805000 0x1000>; 207 208 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 210 interrupt-names = "hc_irq", "pwr_irq"; 211 212 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 213 <&gcc GCC_SDCC1_APPS_CLK>, 214 <&xo_board>; 215 clock-names = "iface", "core", "xo"; 216 status = "disabled"; 217 }; 218 219 blsp_dma: dma-controller@7884000 { 220 compatible = "qcom,bam-v1.7.0"; 221 reg = <0x07884000 0x1d000>; 222 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>; 223 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 224 clock-names = "bam_clk"; 225 #dma-cells = <1>; 226 qcom,ee = <0>; 227 }; 228 229 blsp1_uart0: serial@78af000 { 230 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 231 reg = <0x078af000 0x200>; 232 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 233 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 234 <&gcc GCC_BLSP1_AHB_CLK>; 235 clock-names = "core", "iface"; 236 status = "disabled"; 237 }; 238 239 blsp1_uart1: serial@78b0000 { 240 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 241 reg = <0x078b0000 0x200>; 242 interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 244 <&gcc GCC_BLSP1_AHB_CLK>; 245 clock-names = "core", "iface"; 246 dmas = <&blsp_dma 2>, <&blsp_dma 3>; 247 dma-names = "tx", "rx"; 248 status = "disabled"; 249 }; 250 251 blsp1_spi0: spi@78b5000 { 252 compatible = "qcom,spi-qup-v2.2.1"; 253 reg = <0x078b5000 0x600>; 254 #address-cells = <1>; 255 #size-cells = <0>; 256 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 258 <&gcc GCC_BLSP1_AHB_CLK>; 259 clock-names = "core", "iface"; 260 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 261 dma-names = "tx", "rx"; 262 status = "disabled"; 263 }; 264 265 blsp1_i2c1: i2c@78b6000 { 266 compatible = "qcom,i2c-qup-v2.2.1"; 267 reg = <0x078b6000 0x600>; 268 #address-cells = <1>; 269 #size-cells = <0>; 270 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>; 271 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 272 <&gcc GCC_BLSP1_AHB_CLK>; 273 clock-names = "core", "iface"; 274 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 275 dma-names = "tx", "rx"; 276 status = "disabled"; 277 }; 278 279 blsp1_spi2: spi@78b7000 { 280 compatible = "qcom,spi-qup-v2.2.1"; 281 reg = <0x078b7000 0x600>; 282 #address-cells = <1>; 283 #size-cells = <0>; 284 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 286 <&gcc GCC_BLSP1_AHB_CLK>; 287 clock-names = "core", "iface"; 288 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 289 dma-names = "tx", "rx"; 290 status = "disabled"; 291 }; 292 293 intc: interrupt-controller@b000000 { 294 compatible = "qcom,msm-qgic2"; 295 reg = <0x0b000000 0x1000>, /* GICD */ 296 <0x0b002000 0x1000>, /* GICC */ 297 <0x0b001000 0x1000>, /* GICH */ 298 <0x0b004000 0x1000>; /* GICV */ 299 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 300 interrupt-controller; 301 #interrupt-cells = <3>; 302 #address-cells = <1>; 303 #size-cells = <1>; 304 ranges = <0 0x0b00c000 0x3000>; 305 306 v2m0: v2m@0 { 307 compatible = "arm,gic-v2m-frame"; 308 reg = <0x00000000 0xffd>; 309 msi-controller; 310 }; 311 312 v2m1: v2m@1000 { 313 compatible = "arm,gic-v2m-frame"; 314 reg = <0x00001000 0xffd>; 315 msi-controller; 316 }; 317 318 v2m2: v2m@2000 { 319 compatible = "arm,gic-v2m-frame"; 320 reg = <0x00002000 0xffd>; 321 msi-controller; 322 }; 323 }; 324 325 watchdog: watchdog@b017000 { 326 compatible = "qcom,apss-wdt-ipq5332", "qcom,kpss-wdt"; 327 reg = <0x0b017000 0x1000>; 328 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 329 clocks = <&sleep_clk>; 330 timeout-sec = <30>; 331 }; 332 333 apcs_glb: mailbox@b111000 { 334 compatible = "qcom,ipq5332-apcs-apps-global", 335 "qcom,ipq6018-apcs-apps-global"; 336 reg = <0x0b111000 0x1000>; 337 #clock-cells = <1>; 338 clocks = <&a53pll>, <&xo_board>; 339 clock-names = "pll", "xo"; 340 #mbox-cells = <1>; 341 }; 342 343 a53pll: clock@b116000 { 344 compatible = "qcom,ipq5332-a53pll"; 345 reg = <0x0b116000 0x40>; 346 #clock-cells = <0>; 347 clocks = <&xo_board>; 348 clock-names = "xo"; 349 }; 350 351 timer@b120000 { 352 compatible = "arm,armv7-timer-mem"; 353 reg = <0x0b120000 0x1000>; 354 #address-cells = <1>; 355 #size-cells = <1>; 356 ranges; 357 358 frame@b120000 { 359 reg = <0x0b121000 0x1000>, 360 <0x0b122000 0x1000>; 361 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 363 frame-number = <0>; 364 }; 365 366 frame@b123000 { 367 reg = <0x0b123000 0x1000>; 368 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 369 frame-number = <1>; 370 status = "disabled"; 371 }; 372 373 frame@b124000 { 374 reg = <0x0b124000 0x1000>; 375 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 376 frame-number = <2>; 377 status = "disabled"; 378 }; 379 380 frame@b125000 { 381 reg = <0x0b125000 0x1000>; 382 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 383 frame-number = <3>; 384 status = "disabled"; 385 }; 386 387 frame@b126000 { 388 reg = <0x0b126000 0x1000>; 389 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 390 frame-number = <4>; 391 status = "disabled"; 392 }; 393 394 frame@b127000 { 395 reg = <0x0b127000 0x1000>; 396 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 397 frame-number = <5>; 398 status = "disabled"; 399 }; 400 401 frame@b128000 { 402 reg = <0x0b128000 0x1000>; 403 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 404 frame-number = <6>; 405 status = "disabled"; 406 }; 407 }; 408 }; 409 410 timer { 411 compatible = "arm,armv8-timer"; 412 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 413 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 414 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 415 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 416 }; 417}; 418