1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
4 //
5 // Authors: Cezary Rojewski <cezary.rojewski@intel.com>
6 // Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
7 //
8
9 #include <linux/devcoredump.h>
10 #include <linux/slab.h>
11 #include <sound/hdaudio_ext.h>
12 #include "avs.h"
13 #include "messages.h"
14
15 static int __maybe_unused
avs_skl_enable_logs(struct avs_dev * adev,enum avs_log_enable enable,u32 aging_period,u32 fifo_full_period,unsigned long resource_mask,u32 * priorities)16 avs_skl_enable_logs(struct avs_dev *adev, enum avs_log_enable enable, u32 aging_period,
17 u32 fifo_full_period, unsigned long resource_mask, u32 *priorities)
18 {
19 struct avs_skl_log_state_info *info;
20 u32 size, num_cores = adev->hw_cfg.dsp_cores;
21 int ret, i;
22
23 if (fls_long(resource_mask) > num_cores)
24 return -EINVAL;
25 size = struct_size(info, logs_core, num_cores);
26 info = kzalloc(size, GFP_KERNEL);
27 if (!info)
28 return -ENOMEM;
29
30 info->core_mask = resource_mask;
31 if (enable)
32 for_each_set_bit(i, &resource_mask, num_cores) {
33 info->logs_core[i].enable = enable;
34 info->logs_core[i].min_priority = *priorities++;
35 }
36 else
37 for_each_set_bit(i, &resource_mask, num_cores)
38 info->logs_core[i].enable = enable;
39
40 ret = avs_ipc_set_enable_logs(adev, (u8 *)info, size);
41 kfree(info);
42 if (ret)
43 return AVS_IPC_RET(ret);
44
45 return 0;
46 }
47
avs_skl_log_buffer_offset(struct avs_dev * adev,u32 core)48 int avs_skl_log_buffer_offset(struct avs_dev *adev, u32 core)
49 {
50 return core * avs_log_buffer_size(adev);
51 }
52
53 /* fw DbgLogWp registers */
54 #define FW_REGS_DBG_LOG_WP(core) (0x30 + 0x4 * core)
55
avs_skl_log_buffer_status(struct avs_dev * adev,union avs_notify_msg * msg)56 static int avs_skl_log_buffer_status(struct avs_dev *adev, union avs_notify_msg *msg)
57 {
58 void __iomem *buf;
59 u16 size, write, offset;
60
61 if (!avs_logging_fw(adev))
62 return 0;
63
64 size = avs_log_buffer_size(adev) / 2;
65 write = readl(avs_sram_addr(adev, AVS_FW_REGS_WINDOW) + FW_REGS_DBG_LOG_WP(msg->log.core));
66 /* determine buffer half */
67 offset = (write < size) ? size : 0;
68
69 /* Address is guaranteed to exist in SRAM2. */
70 buf = avs_log_buffer_addr(adev, msg->log.core) + offset;
71 avs_dump_fw_log_wakeup(adev, buf, size);
72
73 return 0;
74 }
75
avs_skl_coredump(struct avs_dev * adev,union avs_notify_msg * msg)76 static int avs_skl_coredump(struct avs_dev *adev, union avs_notify_msg *msg)
77 {
78 u8 *dump;
79
80 dump = vzalloc(AVS_FW_REGS_SIZE);
81 if (!dump)
82 return -ENOMEM;
83
84 memcpy_fromio(dump, avs_sram_addr(adev, AVS_FW_REGS_WINDOW), AVS_FW_REGS_SIZE);
85 dev_coredumpv(adev->dev, dump, AVS_FW_REGS_SIZE, GFP_KERNEL);
86
87 return 0;
88 }
89
avs_skl_d0ix_toggle(struct avs_dev * adev,struct avs_ipc_msg * tx,bool wake)90 static bool avs_skl_d0ix_toggle(struct avs_dev *adev, struct avs_ipc_msg *tx, bool wake)
91 {
92 /* unsupported on cAVS 1.5 hw */
93 return false;
94 }
95
avs_skl_set_d0ix(struct avs_dev * adev,bool enable)96 static int avs_skl_set_d0ix(struct avs_dev *adev, bool enable)
97 {
98 /* unsupported on cAVS 1.5 hw */
99 return 0;
100 }
101
102 const struct avs_dsp_ops avs_skl_dsp_ops = {
103 .power = avs_dsp_core_power,
104 .reset = avs_dsp_core_reset,
105 .stall = avs_dsp_core_stall,
106 .irq_handler = avs_dsp_irq_handler,
107 .irq_thread = avs_dsp_irq_thread,
108 .int_control = avs_dsp_interrupt_control,
109 .load_basefw = avs_cldma_load_basefw,
110 .load_lib = avs_cldma_load_library,
111 .transfer_mods = avs_cldma_transfer_modules,
112 .log_buffer_offset = avs_skl_log_buffer_offset,
113 .log_buffer_status = avs_skl_log_buffer_status,
114 .coredump = avs_skl_coredump,
115 .d0ix_toggle = avs_skl_d0ix_toggle,
116 .set_d0ix = avs_skl_set_d0ix,
117 AVS_SET_ENABLE_LOGS_OP(skl)
118 };
119