1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2004, 2011 Freescale Semiconductor. 4 */ 5 6 /* 7 * mpc8555cds board configuration file 8 * 9 * Please refer to doc/README.mpc85xxcds for more info. 10 * 11 */ 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* High Level Configuration Options */ 16 #define CONFIG_CPM2 1 /* has CPM2 */ 17 18 #define CONFIG_PCI_INDIRECT_BRIDGE 19 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 20 #define CONFIG_ENV_OVERWRITE 21 22 #define CONFIG_FSL_VIA 23 24 #ifndef __ASSEMBLY__ 25 extern unsigned long get_clock_freq(void); 26 #endif 27 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 28 29 /* 30 * These can be toggled for performance analysis, otherwise use default. 31 */ 32 #define CONFIG_L2_CACHE /* toggle L2 cache */ 33 #define CONFIG_BTB /* toggle branch predition */ 34 35 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 36 #define CONFIG_SYS_MEMTEST_END 0x00400000 37 38 #define CONFIG_SYS_CCSRBAR 0xe0000000 39 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 40 41 /* DDR Setup */ 42 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 43 #define CONFIG_DDR_SPD 44 45 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 46 47 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 48 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 49 50 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 51 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 52 53 /* I2C addresses of SPD EEPROMs */ 54 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 55 56 /* Make sure required options are set */ 57 #ifndef CONFIG_SPD_EEPROM 58 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") 59 #endif 60 61 #undef CONFIG_CLOCKS_IN_MHZ 62 63 /* 64 * Local Bus Definitions 65 */ 66 67 /* 68 * FLASH on the Local Bus 69 * Two banks, 8M each, using the CFI driver. 70 * Boot from BR0/OR0 bank at 0xff00_0000 71 * Alternate BR1/OR1 bank at 0xff80_0000 72 * 73 * BR0, BR1: 74 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 75 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 76 * Port Size = 16 bits = BRx[19:20] = 10 77 * Use GPCM = BRx[24:26] = 000 78 * Valid = BRx[31] = 1 79 * 80 * 0 4 8 12 16 20 24 28 81 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 82 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 83 * 84 * OR0, OR1: 85 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 86 * Reserved ORx[17:18] = 11, confusion here? 87 * CSNT = ORx[20] = 1 88 * ACS = half cycle delay = ORx[21:22] = 11 89 * SCY = 6 = ORx[24:27] = 0110 90 * TRLX = use relaxed timing = ORx[29] = 1 91 * EAD = use external address latch delay = OR[31] = 1 92 * 93 * 0 4 8 12 16 20 24 28 94 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 95 */ 96 97 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */ 98 99 #define CONFIG_SYS_BR0_PRELIM 0xff801001 100 #define CONFIG_SYS_BR1_PRELIM 0xff001001 101 102 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 103 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 104 105 #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} 106 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 107 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 108 #undef CONFIG_SYS_FLASH_CHECKSUM 109 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 110 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 111 112 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 113 114 #define CONFIG_SYS_FLASH_EMPTY_INFO 115 116 /* 117 * SDRAM on the Local Bus 118 */ 119 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 120 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 121 122 /* 123 * Base Register 2 and Option Register 2 configure SDRAM. 124 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 125 * 126 * For BR2, need: 127 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 128 * port-size = 32-bits = BR2[19:20] = 11 129 * no parity checking = BR2[21:22] = 00 130 * SDRAM for MSEL = BR2[24:26] = 011 131 * Valid = BR[31] = 1 132 * 133 * 0 4 8 12 16 20 24 28 134 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 135 * 136 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 137 * FIXME: the top 17 bits of BR2. 138 */ 139 140 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 141 142 /* 143 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 144 * 145 * For OR2, need: 146 * 64MB mask for AM, OR2[0:7] = 1111 1100 147 * XAM, OR2[17:18] = 11 148 * 9 columns OR2[19-21] = 010 149 * 13 rows OR2[23-25] = 100 150 * EAD set for extra time OR[31] = 1 151 * 152 * 0 4 8 12 16 20 24 28 153 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 154 */ 155 156 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 157 158 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 159 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 160 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 161 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 162 163 /* 164 * Common settings for all Local Bus SDRAM commands. 165 * At run time, either BSMA1516 (for CPU 1.1) 166 * or BSMA1617 (for CPU 1.0) (old) 167 * is OR'ed in too. 168 */ 169 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 170 | LSDMR_PRETOACT7 \ 171 | LSDMR_ACTTORW7 \ 172 | LSDMR_BL8 \ 173 | LSDMR_WRC4 \ 174 | LSDMR_CL3 \ 175 | LSDMR_RFEN \ 176 ) 177 178 /* 179 * The CADMUS registers are connected to CS3 on CDS. 180 * The new memory map places CADMUS at 0xf8000000. 181 * 182 * For BR3, need: 183 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 184 * port-size = 8-bits = BR[19:20] = 01 185 * no parity checking = BR[21:22] = 00 186 * GPMC for MSEL = BR[24:26] = 000 187 * Valid = BR[31] = 1 188 * 189 * 0 4 8 12 16 20 24 28 190 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 191 * 192 * For OR3, need: 193 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 194 * disable buffer ctrl OR[19] = 0 195 * CSNT OR[20] = 1 196 * ACS OR[21:22] = 11 197 * XACS OR[23] = 1 198 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 199 * SETA OR[28] = 0 200 * TRLX OR[29] = 1 201 * EHTR OR[30] = 1 202 * EAD extra time OR[31] = 1 203 * 204 * 0 4 8 12 16 20 24 28 205 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 206 */ 207 208 #define CONFIG_FSL_CADMUS 209 210 #define CADMUS_BASE_ADDR 0xf8000000 211 #define CONFIG_SYS_BR3_PRELIM 0xf8000801 212 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 213 214 #define CONFIG_SYS_INIT_RAM_LOCK 1 215 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 216 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 217 218 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 219 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 220 221 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 222 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 223 224 /* Serial Port */ 225 #define CONFIG_SYS_NS16550_SERIAL 226 #define CONFIG_SYS_NS16550_REG_SIZE 1 227 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 228 229 #define CONFIG_SYS_BAUDRATE_TABLE \ 230 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 231 232 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 233 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 234 235 /* 236 * I2C 237 */ 238 #define CONFIG_SYS_I2C 239 #define CONFIG_SYS_I2C_FSL 240 #define CONFIG_SYS_FSL_I2C_SPEED 400000 241 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 242 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 243 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 244 245 /* EEPROM */ 246 #define CONFIG_ID_EEPROM 247 #define CONFIG_SYS_I2C_EEPROM_CCID 248 #define CONFIG_SYS_ID_EEPROM 249 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 250 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 251 252 /* 253 * General PCI 254 * Addresses are mapped 1-1. 255 */ 256 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 257 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 258 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 259 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 260 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 261 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 262 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 263 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 264 265 #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 266 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 267 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 268 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 269 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 270 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 271 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 272 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 273 274 #ifdef CONFIG_LEGACY 275 #define BRIDGE_ID 17 276 #define VIA_ID 2 277 #else 278 #define BRIDGE_ID 28 279 #define VIA_ID 4 280 #endif 281 282 #if defined(CONFIG_PCI) 283 284 #define CONFIG_MPC85XX_PCI2 285 286 #undef CONFIG_EEPRO100 287 #undef CONFIG_TULIP 288 289 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 290 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 291 292 #endif /* CONFIG_PCI */ 293 294 #if defined(CONFIG_TSEC_ENET) 295 296 #define CONFIG_TSEC1 1 297 #define CONFIG_TSEC1_NAME "TSEC0" 298 #define CONFIG_TSEC2 1 299 #define CONFIG_TSEC2_NAME "TSEC1" 300 #define TSEC1_PHY_ADDR 0 301 #define TSEC2_PHY_ADDR 1 302 #define TSEC1_PHYIDX 0 303 #define TSEC2_PHYIDX 0 304 #define TSEC1_FLAGS TSEC_GIGABIT 305 #define TSEC2_FLAGS TSEC_GIGABIT 306 307 /* Options are: TSEC[0-1] */ 308 #define CONFIG_ETHPRIME "TSEC0" 309 310 #endif /* CONFIG_TSEC_ENET */ 311 312 /* 313 * Environment 314 */ 315 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 316 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 317 #define CONFIG_ENV_SIZE 0x2000 318 319 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 320 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 321 322 /* 323 * BOOTP options 324 */ 325 #define CONFIG_BOOTP_BOOTFILESIZE 326 327 #undef CONFIG_WATCHDOG /* watchdog disabled */ 328 329 /* 330 * Miscellaneous configurable options 331 */ 332 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 333 334 /* 335 * For booting Linux, the board info and command line data 336 * have to be in the first 64 MB of memory, since this is 337 * the maximum mapped by the Linux kernel during initialization. 338 */ 339 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 340 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 341 342 #if defined(CONFIG_CMD_KGDB) 343 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 344 #endif 345 346 /* 347 * Environment Configuration 348 */ 349 #if defined(CONFIG_TSEC_ENET) 350 #define CONFIG_HAS_ETH0 351 #define CONFIG_HAS_ETH1 352 #define CONFIG_HAS_ETH2 353 #endif 354 355 #define CONFIG_IPADDR 192.168.1.253 356 357 #define CONFIG_HOSTNAME "unknown" 358 #define CONFIG_ROOTPATH "/nfsroot" 359 #define CONFIG_BOOTFILE "your.uImage" 360 361 #define CONFIG_SERVERIP 192.168.1.1 362 #define CONFIG_GATEWAYIP 192.168.1.1 363 #define CONFIG_NETMASK 255.255.255.0 364 365 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 366 367 #define CONFIG_EXTRA_ENV_SETTINGS \ 368 "netdev=eth0\0" \ 369 "consoledev=ttyS1\0" \ 370 "ramdiskaddr=600000\0" \ 371 "ramdiskfile=your.ramdisk.u-boot\0" \ 372 "fdtaddr=400000\0" \ 373 "fdtfile=your.fdt.dtb\0" 374 375 #define CONFIG_NFSBOOTCOMMAND \ 376 "setenv bootargs root=/dev/nfs rw " \ 377 "nfsroot=$serverip:$rootpath " \ 378 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 379 "console=$consoledev,$baudrate $othbootargs;" \ 380 "tftp $loadaddr $bootfile;" \ 381 "tftp $fdtaddr $fdtfile;" \ 382 "bootm $loadaddr - $fdtaddr" 383 384 #define CONFIG_RAMBOOTCOMMAND \ 385 "setenv bootargs root=/dev/ram rw " \ 386 "console=$consoledev,$baudrate $othbootargs;" \ 387 "tftp $ramdiskaddr $ramdiskfile;" \ 388 "tftp $loadaddr $bootfile;" \ 389 "bootm $loadaddr $ramdiskaddr" 390 391 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 392 393 #endif /* __CONFIG_H */ 394