1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org> 5 */ 6 7#include "imx8mm.dtsi" 8 9/ { 10 model = "Variscite VAR-SOM-MX8MM module"; 11 compatible = "variscite,var-som-mx8mm", "fsl,imx8mm"; 12 13 chosen { 14 stdout-path = &uart4; 15 }; 16 17 memory@40000000 { 18 device_type = "memory"; 19 reg = <0x0 0x40000000 0 0x80000000>; 20 }; 21 22 reg_eth_phy: regulator-eth-phy { 23 compatible = "regulator-fixed"; 24 pinctrl-names = "default"; 25 pinctrl-0 = <&pinctrl_reg_eth_phy>; 26 regulator-name = "eth_phy_pwr"; 27 regulator-min-microvolt = <3300000>; 28 regulator-max-microvolt = <3300000>; 29 gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; 30 enable-active-high; 31 }; 32}; 33 34&A53_0 { 35 cpu-supply = <&buck2_reg>; 36}; 37 38&A53_1 { 39 cpu-supply = <&buck2_reg>; 40}; 41 42&A53_2 { 43 cpu-supply = <&buck2_reg>; 44}; 45 46&A53_3 { 47 cpu-supply = <&buck2_reg>; 48}; 49 50&ddrc { 51 operating-points-v2 = <&ddrc_opp_table>; 52 53 ddrc_opp_table: opp-table { 54 compatible = "operating-points-v2"; 55 56 opp-25000000 { 57 opp-hz = /bits/ 64 <25000000>; 58 }; 59 60 opp-100000000 { 61 opp-hz = /bits/ 64 <100000000>; 62 }; 63 64 opp-750000000 { 65 opp-hz = /bits/ 64 <750000000>; 66 }; 67 }; 68}; 69 70&ecspi1 { 71 pinctrl-names = "default"; 72 pinctrl-0 = <&pinctrl_ecspi1>; 73 cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>, 74 <&gpio1 0 GPIO_ACTIVE_LOW>; 75 /delete-property/ dmas; 76 /delete-property/ dma-names; 77 status = "okay"; 78 79 /* Resistive touch controller */ 80 touchscreen@0 { 81 reg = <0>; 82 compatible = "ti,ads7846"; 83 pinctrl-names = "default"; 84 pinctrl-0 = <&pinctrl_restouch>; 85 interrupt-parent = <&gpio1>; 86 interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 87 88 spi-max-frequency = <1500000>; 89 pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; 90 91 ti,x-min = /bits/ 16 <125>; 92 touchscreen-size-x = <4008>; 93 ti,y-min = /bits/ 16 <282>; 94 touchscreen-size-y = <3864>; 95 ti,x-plate-ohms = /bits/ 16 <180>; 96 touchscreen-max-pressure = <255>; 97 touchscreen-average-samples = <10>; 98 ti,debounce-tol = /bits/ 16 <3>; 99 ti,debounce-rep = /bits/ 16 <1>; 100 ti,settle-delay-usec = /bits/ 16 <150>; 101 ti,keep-vref-on; 102 wakeup-source; 103 }; 104}; 105 106&fec1 { 107 pinctrl-names = "default"; 108 pinctrl-0 = <&pinctrl_fec1>; 109 phy-mode = "rgmii"; 110 phy-handle = <ðphy>; 111 phy-supply = <®_eth_phy>; 112 fsl,magic-packet; 113 status = "okay"; 114 115 mdio { 116 #address-cells = <1>; 117 #size-cells = <0>; 118 119 ethphy: ethernet-phy@4 { 120 compatible = "ethernet-phy-ieee802.3-c22"; 121 reg = <4>; 122 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 123 reset-assert-us = <10000>; 124 reset-deassert-us = <10000>; 125 }; 126 }; 127}; 128 129&i2c1 { 130 clock-frequency = <400000>; 131 pinctrl-names = "default"; 132 pinctrl-0 = <&pinctrl_i2c1>; 133 status = "okay"; 134 135 pmic@4b { 136 compatible = "rohm,bd71847"; 137 reg = <0x4b>; 138 pinctrl-names = "default"; 139 pinctrl-0 = <&pinctrl_pmic>; 140 interrupt-parent = <&gpio2>; 141 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 142 rohm,reset-snvs-powered; 143 144 #clock-cells = <0>; 145 clocks = <&osc_32k>; 146 clock-output-names = "clk-32k-out"; 147 148 regulators { 149 buck1_reg: BUCK1 { 150 regulator-name = "buck1"; 151 regulator-min-microvolt = <700000>; 152 regulator-max-microvolt = <1300000>; 153 regulator-boot-on; 154 regulator-always-on; 155 regulator-ramp-delay = <1250>; 156 }; 157 158 buck2_reg: BUCK2 { 159 regulator-name = "buck2"; 160 regulator-min-microvolt = <700000>; 161 regulator-max-microvolt = <1300000>; 162 regulator-boot-on; 163 regulator-always-on; 164 regulator-ramp-delay = <1250>; 165 rohm,dvs-run-voltage = <1000000>; 166 rohm,dvs-idle-voltage = <900000>; 167 }; 168 169 buck3_reg: BUCK3 { 170 regulator-name = "buck3"; 171 regulator-min-microvolt = <700000>; 172 regulator-max-microvolt = <1350000>; 173 regulator-boot-on; 174 regulator-always-on; 175 }; 176 177 buck4_reg: BUCK4 { 178 regulator-name = "buck4"; 179 regulator-min-microvolt = <3000000>; 180 regulator-max-microvolt = <3300000>; 181 regulator-boot-on; 182 regulator-always-on; 183 }; 184 185 buck5_reg: BUCK5 { 186 regulator-name = "buck5"; 187 regulator-min-microvolt = <1605000>; 188 regulator-max-microvolt = <1995000>; 189 regulator-boot-on; 190 regulator-always-on; 191 }; 192 193 buck6_reg: BUCK6 { 194 regulator-name = "buck6"; 195 regulator-min-microvolt = <800000>; 196 regulator-max-microvolt = <1400000>; 197 regulator-boot-on; 198 regulator-always-on; 199 }; 200 201 ldo1_reg: LDO1 { 202 regulator-name = "ldo1"; 203 regulator-min-microvolt = <1600000>; 204 regulator-max-microvolt = <1900000>; 205 regulator-boot-on; 206 regulator-always-on; 207 }; 208 209 ldo2_reg: LDO2 { 210 regulator-name = "ldo2"; 211 regulator-min-microvolt = <800000>; 212 regulator-max-microvolt = <900000>; 213 regulator-boot-on; 214 regulator-always-on; 215 }; 216 217 ldo3_reg: LDO3 { 218 regulator-name = "ldo3"; 219 regulator-min-microvolt = <1800000>; 220 regulator-max-microvolt = <3300000>; 221 regulator-boot-on; 222 regulator-always-on; 223 }; 224 225 ldo4_reg: LDO4 { 226 regulator-name = "ldo4"; 227 regulator-min-microvolt = <900000>; 228 regulator-max-microvolt = <1800000>; 229 regulator-boot-on; 230 regulator-always-on; 231 }; 232 233 ldo5_reg: LDO5 { 234 regulator-min-microvolt = <1800000>; 235 regulator-max-microvolt = <1800000>; 236 regulator-always-on; 237 }; 238 239 ldo6_reg: LDO6 { 240 regulator-name = "ldo6"; 241 regulator-min-microvolt = <900000>; 242 regulator-max-microvolt = <1800000>; 243 regulator-boot-on; 244 regulator-always-on; 245 }; 246 }; 247 }; 248}; 249 250&i2c3 { 251 clock-frequency = <400000>; 252 pinctrl-names = "default"; 253 pinctrl-0 = <&pinctrl_i2c3>; 254 status = "okay"; 255 256 /* TODO: configure audio, as of now just put a placeholder */ 257 wm8904: codec@1a { 258 compatible = "wlf,wm8904"; 259 reg = <0x1a>; 260 status = "disabled"; 261 }; 262}; 263 264&snvs_pwrkey { 265 status = "okay"; 266}; 267 268/* Bluetooth */ 269&uart2 { 270 pinctrl-names = "default"; 271 pinctrl-0 = <&pinctrl_uart2>; 272 assigned-clocks = <&clk IMX8MM_CLK_UART2>; 273 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 274 uart-has-rtscts; 275 status = "okay"; 276}; 277 278/* Console */ 279&uart4 { 280 pinctrl-names = "default"; 281 pinctrl-0 = <&pinctrl_uart4>; 282 status = "okay"; 283}; 284 285&usbotg1 { 286 dr_mode = "otg"; 287 usb-role-switch; 288 status = "okay"; 289}; 290 291&usbotg2 { 292 dr_mode = "otg"; 293 usb-role-switch; 294 status = "okay"; 295}; 296 297/* WIFI */ 298&usdhc1 { 299 #address-cells = <1>; 300 #size-cells = <0>; 301 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 302 pinctrl-0 = <&pinctrl_usdhc1>; 303 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 304 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 305 bus-width = <4>; 306 non-removable; 307 keep-power-in-suspend; 308 status = "okay"; 309 310 brcmf: bcrmf@1 { 311 reg = <1>; 312 compatible = "brcm,bcm4329-fmac"; 313 }; 314}; 315 316/* SD */ 317&usdhc2 { 318 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; 319 assigned-clock-rates = <200000000>; 320 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 321 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 322 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 323 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 324 cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; 325 bus-width = <4>; 326 vmmc-supply = <®_usdhc2_vmmc>; 327 status = "okay"; 328}; 329 330/* eMMC */ 331&usdhc3 { 332 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; 333 assigned-clock-rates = <400000000>; 334 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 335 pinctrl-0 = <&pinctrl_usdhc3>; 336 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 337 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 338 bus-width = <8>; 339 non-removable; 340 status = "okay"; 341}; 342 343&wdog1 { 344 pinctrl-names = "default"; 345 pinctrl-0 = <&pinctrl_wdog>; 346 fsl,ext-reset-output; 347 status = "okay"; 348}; 349 350&iomuxc { 351 pinctrl_ecspi1: ecspi1grp { 352 fsl,pins = < 353 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13 354 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13 355 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13 356 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x13 357 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x13 358 >; 359 }; 360 361 pinctrl_fec1: fec1grp { 362 fsl,pins = < 363 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 364 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 365 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 366 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 367 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 368 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 369 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 370 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 371 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 372 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 373 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 374 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 375 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 376 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 377 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 378 >; 379 }; 380 381 pinctrl_i2c1: i2c1grp { 382 fsl,pins = < 383 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 384 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 385 >; 386 }; 387 388 pinctrl_i2c3: i2c3grp { 389 fsl,pins = < 390 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 391 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 392 >; 393 }; 394 395 pinctrl_pmic: pmicirqgrp { 396 fsl,pins = < 397 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141 398 >; 399 }; 400 401 pinctrl_reg_eth_phy: regethphygrp { 402 fsl,pins = < 403 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 404 >; 405 }; 406 407 pinctrl_restouch: restouchgrp { 408 fsl,pins = < 409 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 410 >; 411 }; 412 413 pinctrl_uart2: uart2grp { 414 fsl,pins = < 415 MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 416 MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 417 MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 418 MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 419 >; 420 }; 421 422 pinctrl_uart4: uart4grp { 423 fsl,pins = < 424 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 425 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 426 >; 427 }; 428 429 pinctrl_usdhc1: usdhc1grp { 430 fsl,pins = < 431 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 432 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 433 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 434 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 435 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 436 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 437 >; 438 }; 439 440 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 441 fsl,pins = < 442 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 443 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 444 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 445 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 446 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 447 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 448 >; 449 }; 450 451 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 452 fsl,pins = < 453 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 454 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 455 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 456 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 457 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 458 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 459 >; 460 }; 461 462 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 463 fsl,pins = < 464 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xc1 465 >; 466 }; 467 468 pinctrl_usdhc2: usdhc2grp { 469 fsl,pins = < 470 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 471 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 472 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 473 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 474 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 475 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 476 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 477 >; 478 }; 479 480 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 481 fsl,pins = < 482 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 483 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 484 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 485 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 486 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 487 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 488 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 489 >; 490 }; 491 492 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 493 fsl,pins = < 494 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 495 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 496 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 497 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 498 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 499 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 500 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 501 >; 502 }; 503 504 pinctrl_usdhc3: usdhc3grp { 505 fsl,pins = < 506 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 507 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 508 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 509 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 510 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 511 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 512 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 513 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 514 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 515 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 516 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 517 >; 518 }; 519 520 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 521 fsl,pins = < 522 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 523 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 524 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 525 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 526 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 527 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 528 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 529 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 530 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 531 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 532 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 533 >; 534 }; 535 536 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 537 fsl,pins = < 538 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 539 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 540 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 541 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 542 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 543 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 544 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 545 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 546 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 547 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 548 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 549 >; 550 }; 551 552 pinctrl_wdog: wdoggrp { 553 fsl,pins = < 554 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 555 >; 556 }; 557}; 558