1// SPDX-License-Identifier: GPL-2.0 OR X11
2/*
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
5 *
6 */
7
8#include <dt-bindings/clock/imx6qdl-clock.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/input/input.h>
11
12/ {
13	chosen {
14		stdout-path = &uart2;
15	};
16
17	aliases {
18		mmc0 = &usdhc3;
19		mmc1 = &usdhc4;
20	};
21
22	memory@10000000 {
23		device_type = "memory";
24		reg = <0x10000000 0x40000000>;
25	};
26
27	reg_2p5v: regulator-2p5v {
28		compatible = "regulator-fixed";
29		regulator-name = "2P5V";
30		regulator-min-microvolt = <2500000>;
31		regulator-max-microvolt = <2500000>;
32		regulator-always-on;
33	};
34
35	reg_3p3v: regulator-3p3v {
36		compatible = "regulator-fixed";
37		regulator-name = "3P3V";
38		regulator-min-microvolt = <3300000>;
39		regulator-max-microvolt = <3300000>;
40		regulator-always-on;
41	};
42
43	reg_usb_otg_vbus: regulator-usb-otg-vbus {
44		compatible = "regulator-fixed";
45		regulator-name = "usb_otg_vbus";
46		regulator-min-microvolt = <5000000>;
47		regulator-max-microvolt = <5000000>;
48		gpio = <&gpio3 22 0>;
49		enable-active-high;
50	};
51
52	reg_can_xcvr: regulator-can-xcvr {
53		compatible = "regulator-fixed";
54		regulator-name = "CAN XCVR";
55		regulator-min-microvolt = <3300000>;
56		regulator-max-microvolt = <3300000>;
57		pinctrl-names = "default";
58		pinctrl-0 = <&pinctrl_can_xcvr>;
59		gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
60	};
61
62	reg_1p5v: regulator-1p5v {
63		compatible = "regulator-fixed";
64		regulator-name = "1P5V";
65		regulator-min-microvolt = <1500000>;
66		regulator-max-microvolt = <1500000>;
67		regulator-always-on;
68	};
69
70	reg_1p8v: regulator-1p8v {
71		compatible = "regulator-fixed";
72		regulator-name = "1P8V";
73		regulator-min-microvolt = <1800000>;
74		regulator-max-microvolt = <1800000>;
75		regulator-always-on;
76	};
77
78	reg_2p8v: regulator-2p8v {
79		compatible = "regulator-fixed";
80		regulator-name = "2P8V";
81		regulator-min-microvolt = <2800000>;
82		regulator-max-microvolt = <2800000>;
83		regulator-always-on;
84	};
85
86	reg_usb_h1_vbus: regulator-usb-h1-vbus {
87		compatible = "regulator-fixed";
88		pinctrl-names = "default";
89		pinctrl-0 = <&pinctrl_usbh1>;
90		regulator-name = "usb_h1_vbus";
91		regulator-min-microvolt = <3300000>;
92		regulator-max-microvolt = <3300000>;
93		gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
94		enable-active-high;
95	};
96
97	mipi_xclk: mipi_xclk {
98		compatible = "pwm-clock";
99		#clock-cells = <0>;
100		clock-frequency = <22000000>;
101		clock-output-names = "mipi_pwm3";
102		pwms = <&pwm3 0 45>; /* 1 / 45 ns = 22 MHz */
103		status = "okay";
104	};
105
106	gpio-keys {
107		compatible = "gpio-keys";
108		pinctrl-names = "default";
109		pinctrl-0 = <&pinctrl_gpio_keys>;
110
111		power {
112			label = "Power Button";
113			gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
114			linux,code = <KEY_POWER>;
115			wakeup-source;
116		};
117
118		menu {
119			label = "Menu";
120			gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
121			linux,code = <KEY_MENU>;
122		};
123
124		home {
125			label = "Home";
126			gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
127			linux,code = <KEY_HOME>;
128		};
129
130		back {
131			label = "Back";
132			gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
133			linux,code = <KEY_BACK>;
134		};
135
136		volume-up {
137			label = "Volume Up";
138			gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
139			linux,code = <KEY_VOLUMEUP>;
140		};
141
142		volume-down {
143			label = "Volume Down";
144			gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
145			linux,code = <KEY_VOLUMEDOWN>;
146		};
147	};
148
149	sound {
150		compatible = "fsl,imx6q-sabrelite-sgtl5000",
151			     "fsl,imx-audio-sgtl5000";
152		model = "imx6q-sabrelite-sgtl5000";
153		ssi-controller = <&ssi1>;
154		audio-codec = <&codec>;
155		audio-routing =
156			"MIC_IN", "Mic Jack",
157			"Mic Jack", "Mic Bias",
158			"Headphone Jack", "HP_OUT";
159		mux-int-port = <1>;
160		mux-ext-port = <4>;
161	};
162
163	backlight_lcd: backlight-lcd {
164		compatible = "pwm-backlight";
165		pwms = <&pwm1 0 5000000>;
166		brightness-levels = <0 4 8 16 32 64 128 255>;
167		default-brightness-level = <7>;
168		power-supply = <&reg_3p3v>;
169		status = "okay";
170	};
171
172	backlight_lvds: backlight-lvds {
173		compatible = "pwm-backlight";
174		pwms = <&pwm4 0 5000000>;
175		brightness-levels = <0 4 8 16 32 64 128 255>;
176		default-brightness-level = <7>;
177		power-supply = <&reg_3p3v>;
178		status = "okay";
179	};
180
181	lcd_display: disp0 {
182		compatible = "fsl,imx-parallel-display";
183		#address-cells = <1>;
184		#size-cells = <0>;
185		interface-pix-fmt = "bgr666";
186		pinctrl-names = "default";
187		pinctrl-0 = <&pinctrl_j15>;
188		status = "okay";
189
190		port@0 {
191			reg = <0>;
192
193			lcd_display_in: endpoint {
194				remote-endpoint = <&ipu1_di0_disp0>;
195			};
196		};
197
198		port@1 {
199			reg = <1>;
200
201			lcd_display_out: endpoint {
202				remote-endpoint = <&lcd_panel_in>;
203			};
204		};
205	};
206
207	panel-lcd {
208		compatible = "okaya,rs800480t-7x0gp";
209		backlight = <&backlight_lcd>;
210
211		port {
212			lcd_panel_in: endpoint {
213				remote-endpoint = <&lcd_display_out>;
214			};
215		};
216	};
217
218	panel-lvds0 {
219		compatible = "hannstar,hsd100pxn1";
220		backlight = <&backlight_lvds>;
221
222		port {
223			panel_in: endpoint {
224				remote-endpoint = <&lvds0_out>;
225			};
226		};
227	};
228};
229
230&ipu1_csi0_from_ipu1_csi0_mux {
231	bus-width = <8>;
232	data-shift = <12>; /* Lines 19:12 used */
233	hsync-active = <1>;
234	vync-active = <1>;
235};
236
237&ipu1_csi0_mux_from_parallel_sensor {
238	remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
239};
240
241&ipu1_csi0 {
242	pinctrl-names = "default";
243	pinctrl-0 = <&pinctrl_ipu1_csi0>;
244};
245
246&audmux {
247	pinctrl-names = "default";
248	pinctrl-0 = <&pinctrl_audmux>;
249	status = "okay";
250};
251
252&can1 {
253	pinctrl-names = "default";
254	pinctrl-0 = <&pinctrl_can1>;
255	xceiver-supply = <&reg_can_xcvr>;
256	status = "okay";
257};
258
259&clks {
260	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
261			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
262	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
263				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
264};
265
266&ecspi1 {
267	cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
268	pinctrl-names = "default";
269	pinctrl-0 = <&pinctrl_ecspi1>;
270	status = "okay";
271
272	flash: flash@0 {
273		compatible = "sst,sst25vf016b", "jedec,spi-nor";
274		spi-max-frequency = <20000000>;
275		reg = <0>;
276	};
277};
278
279&fec {
280	pinctrl-names = "default";
281	pinctrl-0 = <&pinctrl_enet>;
282	phy-mode = "rgmii";
283	phy-handle = <&ethphy>;
284	phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
285	status = "okay";
286
287	mdio {
288		#address-cells = <1>;
289		#size-cells = <0>;
290
291		ethphy: ethernet-phy {
292			compatible = "ethernet-phy-ieee802.3-c22";
293			txen-skew-ps = <0>;
294			txc-skew-ps = <3000>;
295			rxdv-skew-ps = <0>;
296			rxc-skew-ps = <3000>;
297			rxd0-skew-ps = <0>;
298			rxd1-skew-ps = <0>;
299			rxd2-skew-ps = <0>;
300			rxd3-skew-ps = <0>;
301			txd0-skew-ps = <0>;
302			txd1-skew-ps = <0>;
303			txd2-skew-ps = <0>;
304			txd3-skew-ps = <0>;
305		};
306	};
307};
308
309&hdmi {
310	ddc-i2c-bus = <&i2c2>;
311	status = "okay";
312};
313
314&i2c1 {
315	clock-frequency = <100000>;
316	pinctrl-names = "default";
317	pinctrl-0 = <&pinctrl_i2c1>;
318	status = "okay";
319
320	codec: sgtl5000@a {
321		compatible = "fsl,sgtl5000";
322		reg = <0x0a>;
323		#sound-dai-cells = <0>;
324		clocks = <&clks IMX6QDL_CLK_CKO>;
325		VDDA-supply = <&reg_2p5v>;
326		VDDIO-supply = <&reg_3p3v>;
327	};
328};
329
330&i2c2 {
331	clock-frequency = <100000>;
332	pinctrl-names = "default";
333	pinctrl-0 = <&pinctrl_i2c2>;
334	status = "okay";
335
336	ov5640: camera@40 {
337		compatible = "ovti,ov5640";
338		pinctrl-names = "default";
339		pinctrl-0 = <&pinctrl_ov5640>;
340		reg = <0x40>;
341		clocks = <&mipi_xclk>;
342		clock-names = "xclk";
343		DOVDD-supply = <&reg_1p8v>;
344		AVDD-supply = <&reg_2p8v>;
345		DVDD-supply = <&reg_1p5v>;
346		reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* NANDF_D5 */
347		powerdown-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* NANDF_WP_B */
348
349		port {
350			ov5640_to_mipi_csi2: endpoint {
351				remote-endpoint = <&mipi_csi2_in>;
352				clock-lanes = <0>;
353				data-lanes = <1 2>;
354			};
355		};
356	};
357
358	ov5642: camera@42 {
359		compatible = "ovti,ov5642";
360		pinctrl-names = "default";
361		pinctrl-0 = <&pinctrl_ov5642>;
362		clocks = <&clks IMX6QDL_CLK_CKO2>;
363		clock-names = "xclk";
364		reg = <0x42>;
365		reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
366		powerdown-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
367		gp-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
368		status = "disabled";
369
370		port {
371			ov5642_to_ipu1_csi0_mux: endpoint {
372				remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
373				bus-width = <8>;
374				hsync-active = <1>;
375				vsync-active = <1>;
376			};
377		};
378	};
379};
380
381&i2c3 {
382	clock-frequency = <100000>;
383	pinctrl-names = "default";
384	pinctrl-0 = <&pinctrl_i2c3>;
385	status = "okay";
386};
387
388&iomuxc {
389	pinctrl-names = "default";
390	pinctrl-0 = <&pinctrl_hog>;
391
392	imx6q-sabrelite {
393		pinctrl_hog: hoggrp {
394			fsl,pins = <
395				/* SGTL5000 sys_mclk */
396				MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x030b0
397			>;
398		};
399
400		pinctrl_audmux: audmuxgrp {
401			fsl,pins = <
402				MX6QDL_PAD_SD2_DAT0__AUD4_RXD		0x130b0
403				MX6QDL_PAD_SD2_DAT3__AUD4_TXC		0x130b0
404				MX6QDL_PAD_SD2_DAT2__AUD4_TXD		0x110b0
405				MX6QDL_PAD_SD2_DAT1__AUD4_TXFS		0x130b0
406			>;
407		};
408
409		pinctrl_can1: can1grp {
410			fsl,pins = <
411				MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX	0x1b0b0
412				MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX	0x1b0b0
413			>;
414		};
415
416		pinctrl_can_xcvr: can-xcvrgrp {
417			fsl,pins = <
418				/* Flexcan XCVR enable */
419				MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x1b0b0
420			>;
421		};
422
423		pinctrl_ecspi1: ecspi1grp {
424			fsl,pins = <
425				MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
426				MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
427				MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
428				MX6QDL_PAD_EIM_D19__GPIO3_IO19  0x000b1	/* CS */
429			>;
430		};
431
432		pinctrl_enet: enetgrp {
433			fsl,pins = <
434				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x100b0
435				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x100b0
436				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x10030
437				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x10030
438				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x10030
439				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x10030
440				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x10030
441				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x10030
442				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x100b0
443				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
444				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
445				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
446				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
447				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
448				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
449				/* Phy reset */
450				MX6QDL_PAD_EIM_D23__GPIO3_IO23		0x000b0
451			>;
452		};
453
454		pinctrl_gpio_keys: gpio-keysgrp {
455			fsl,pins = <
456				/* Power Button */
457				MX6QDL_PAD_NANDF_D3__GPIO2_IO03		0x1b0b0
458				/* Menu Button */
459				MX6QDL_PAD_NANDF_D1__GPIO2_IO01		0x1b0b0
460				/* Home Button */
461				MX6QDL_PAD_NANDF_D4__GPIO2_IO04		0x1b0b0
462				/* Back Button */
463				MX6QDL_PAD_NANDF_D2__GPIO2_IO02		0x1b0b0
464				/* Volume Up Button */
465				MX6QDL_PAD_GPIO_18__GPIO7_IO13		0x1b0b0
466				/* Volume Down Button */
467				MX6QDL_PAD_GPIO_19__GPIO4_IO05		0x1b0b0
468			>;
469		};
470
471		pinctrl_i2c1: i2c1grp {
472			fsl,pins = <
473				MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
474				MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
475			>;
476		};
477
478		pinctrl_i2c2: i2c2grp {
479			fsl,pins = <
480				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
481				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
482			>;
483		};
484
485		pinctrl_i2c3: i2c3grp {
486			fsl,pins = <
487				MX6QDL_PAD_GPIO_5__I2C3_SCL		0x4001b8b1
488				MX6QDL_PAD_GPIO_16__I2C3_SDA		0x4001b8b1
489			>;
490		};
491
492		pinctrl_ipu1_csi0: ipu1csi0grp {
493			fsl,pins = <
494				MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x1b0b0
495				MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x1b0b0
496				MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x1b0b0
497				MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x1b0b0
498				MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x1b0b0
499				MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x1b0b0
500				MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x1b0b0
501				MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x1b0b0
502				MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x1b0b0
503				MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x1b0b0
504				MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x1b0b0
505				MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x1b0b0
506			>;
507		};
508
509		pinctrl_j15: j15grp {
510			fsl,pins = <
511				MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
512				MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
513				MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
514				MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
515				MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
516				MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
517				MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
518				MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
519				MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
520				MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
521				MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
522				MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
523				MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
524				MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
525				MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
526				MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
527				MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
528				MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
529				MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
530				MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
531				MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
532				MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
533				MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
534				MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
535				MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
536				MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
537				MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
538				MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
539			>;
540		};
541
542		pinctrl_ov5640: ov5640grp {
543			fsl,pins = <
544				MX6QDL_PAD_NANDF_D5__GPIO2_IO05   0x000b0
545				MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0
546			>;
547		};
548
549		pinctrl_ov5642: ov5642grp {
550			fsl,pins = <
551				MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
552				MX6QDL_PAD_GPIO_6__GPIO1_IO06   0x1b0b0
553				MX6QDL_PAD_GPIO_8__GPIO1_IO08   0x130b0
554				MX6QDL_PAD_GPIO_3__CCM_CLKO2    0x000b0
555			>;
556		};
557
558		pinctrl_pwm1: pwm1grp {
559			fsl,pins = <
560				MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
561			>;
562		};
563
564		pinctrl_pwm3: pwm3grp {
565			fsl,pins = <
566				MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
567			>;
568		};
569
570		pinctrl_pwm4: pwm4grp {
571			fsl,pins = <
572				MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
573			>;
574		};
575
576		pinctrl_uart1: uart1grp {
577			fsl,pins = <
578				MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
579				MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
580			>;
581		};
582
583		pinctrl_uart2: uart2grp {
584			fsl,pins = <
585				MX6QDL_PAD_EIM_D26__UART2_TX_DATA	0x1b0b1
586				MX6QDL_PAD_EIM_D27__UART2_RX_DATA	0x1b0b1
587			>;
588		};
589
590		pinctrl_usbh1: usbh1grp {
591			fsl,pins = <
592				MX6QDL_PAD_GPIO_17__GPIO7_IO12		0x030b0
593			>;
594		};
595
596		pinctrl_usbotg: usbotggrp {
597			fsl,pins = <
598				MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
599				MX6QDL_PAD_KEY_COL4__USB_OTG_OC	0x1b0b0
600				/* power enable, high active */
601				MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x000b0
602			>;
603		};
604
605		pinctrl_usdhc3: usdhc3grp {
606			fsl,pins = <
607				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
608				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
609				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
610				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
611				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
612				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
613				MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0	/* CD */
614				MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0	/* WP */
615			>;
616		};
617
618		pinctrl_usdhc4: usdhc4grp {
619			fsl,pins = <
620				MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
621				MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059
622				MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059
623				MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059
624				MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059
625				MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059
626				MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0	/* CD */
627			>;
628		};
629	};
630};
631
632&ipu1_di0_disp0 {
633	remote-endpoint = <&lcd_display_in>;
634};
635
636&ldb {
637	status = "okay";
638
639	lvds-channel@0 {
640		status = "okay";
641
642		port@4 {
643			reg = <4>;
644
645			lvds0_out: endpoint {
646				remote-endpoint = <&panel_in>;
647			};
648		};
649	};
650};
651
652&pcie {
653	status = "okay";
654};
655
656&pwm1 {
657	#pwm-cells = <2>;
658	pinctrl-names = "default";
659	pinctrl-0 = <&pinctrl_pwm1>;
660	status = "okay";
661};
662
663&pwm3 {
664	#pwm-cells = <2>;
665	pinctrl-names = "default";
666	pinctrl-0 = <&pinctrl_pwm3>;
667	status = "okay";
668};
669
670&pwm4 {
671	#pwm-cells = <2>;
672	pinctrl-names = "default";
673	pinctrl-0 = <&pinctrl_pwm4>;
674	status = "okay";
675};
676
677&ssi1 {
678	status = "okay";
679};
680
681&uart1 {
682	pinctrl-names = "default";
683	pinctrl-0 = <&pinctrl_uart1>;
684	status = "okay";
685};
686
687&uart2 {
688	pinctrl-names = "default";
689	pinctrl-0 = <&pinctrl_uart2>;
690	status = "okay";
691};
692
693&usbh1 {
694	vbus-supply = <&reg_usb_h1_vbus>;
695	status = "okay";
696};
697
698&usbotg {
699	vbus-supply = <&reg_usb_otg_vbus>;
700	pinctrl-names = "default";
701	pinctrl-0 = <&pinctrl_usbotg>;
702	disable-over-current;
703	status = "okay";
704};
705
706&usdhc3 {
707	pinctrl-names = "default";
708	pinctrl-0 = <&pinctrl_usdhc3>;
709	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
710	wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
711	vmmc-supply = <&reg_3p3v>;
712	status = "okay";
713};
714
715&usdhc4 {
716	pinctrl-names = "default";
717	pinctrl-0 = <&pinctrl_usdhc4>;
718	cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
719	vmmc-supply = <&reg_3p3v>;
720	status = "okay";
721};
722
723&mipi_csi {
724	status = "okay";
725
726	port@0 {
727		reg = <0>;
728
729		mipi_csi2_in: endpoint {
730			remote-endpoint = <&ov5640_to_mipi_csi2>;
731			clock-lanes = <0>;
732			data-lanes = <1 2>;
733		};
734	};
735};
736