1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7
8/ {
9	model = "Phytec phyFLEX-i.MX6 Quad";
10	compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
11
12	memory@10000000 {
13		device_type = "memory";
14		reg = <0x10000000 0x80000000>;
15	};
16
17	reg_usb_otg_vbus: regulator-usb-otg-vbus {
18		compatible = "regulator-fixed";
19		regulator-name = "usb_otg_vbus";
20		regulator-min-microvolt = <5000000>;
21		regulator-max-microvolt = <5000000>;
22		gpio = <&gpio4 15 0>;
23		enable-active-high;
24	};
25
26	reg_usb_h1_vbus: regulator-usb-h1-vbus {
27		compatible = "regulator-fixed";
28		pinctrl-names = "default";
29		pinctrl-0 = <&pinctrl_usbh1_vbus>;
30		regulator-name = "usb_h1_vbus";
31		regulator-min-microvolt = <5000000>;
32		regulator-max-microvolt = <5000000>;
33		gpio = <&gpio1 0 0>;
34		enable-active-high;
35	};
36
37	gpio_leds: leds {
38		pinctrl-names = "default";
39		pinctrl-0 = <&pinctrl_leds>;
40		compatible = "gpio-leds";
41
42		led_green: led-green {
43			label = "phyflex:green";
44			gpios = <&gpio1 30 0>;
45		};
46
47		led_red: led-red {
48			label = "phyflex:red";
49			gpios = <&gpio2 31 0>;
50		};
51	};
52};
53
54&audmux {
55	pinctrl-names = "default";
56	pinctrl-0 = <&pinctrl_audmux>;
57	status = "disabled";
58};
59
60&can1 {
61	pinctrl-names = "default";
62	pinctrl-0 = <&pinctrl_flexcan1>;
63	status = "disabled";
64};
65
66&ecspi3 {
67	pinctrl-names = "default";
68	pinctrl-0 = <&pinctrl_ecspi3>;
69	status = "okay";
70	cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
71
72	som_flash: flash@0 {
73		compatible = "m25p80", "jedec,spi-nor";
74		spi-max-frequency = <20000000>;
75		reg = <0>;
76	};
77};
78
79&fec {
80	pinctrl-names = "default";
81	pinctrl-0 = <&pinctrl_enet>;
82	phy-handle = <&ethphy>;
83	phy-mode = "rgmii";
84	phy-reset-duration = <10>; /* in msecs */
85	phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
86	phy-supply = <&vdd_eth_io_reg>;
87	status = "disabled";
88
89	fec_mdio: mdio {
90		#address-cells = <1>;
91		#size-cells = <0>;
92
93		ethphy: ethernet-phy@0 {
94			compatible = "ethernet-phy-ieee802.3-c22";
95			reg = <0>;
96			txc-skew-ps = <1680>;
97			rxc-skew-ps = <1860>;
98		};
99	};
100};
101
102&gpmi {
103	pinctrl-names = "default";
104	pinctrl-0 = <&pinctrl_gpmi_nand>;
105	nand-on-flash-bbt;
106	status = "okay";
107};
108
109&i2c1 {
110	pinctrl-names = "default";
111	pinctrl-0 = <&pinctrl_i2c1>;
112	status = "okay";
113
114	som_eeprom: eeprom@50 {
115		compatible = "catalyst,24c32", "atmel,24c32";
116		pagesize = <32>;
117		reg = <0x50>;
118	};
119
120	pmic@58 {
121		pinctrl-names = "default";
122		pinctrl-0 = <&pinctrl_pmic>;
123		compatible = "dlg,da9063";
124		reg = <0x58>;
125		interrupt-parent = <&gpio2>;
126		interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */
127		#interrupt-cells = <2>;
128		interrupt-controller;
129
130		regulators {
131			vddcore_reg: bcore1 {
132				regulator-min-microvolt = <730000>;
133				regulator-max-microvolt = <1380000>;
134				regulator-always-on;
135			};
136
137			vddsoc_reg: bcore2 {
138				regulator-min-microvolt = <730000>;
139				regulator-max-microvolt = <1380000>;
140				regulator-always-on;
141			};
142
143			vdd_ddr3_reg: bpro {
144				regulator-min-microvolt = <1500000>;
145				regulator-max-microvolt = <1500000>;
146				regulator-always-on;
147			};
148
149			vdd_3v3_reg: bperi {
150				regulator-min-microvolt = <3300000>;
151				regulator-max-microvolt = <3300000>;
152				regulator-always-on;
153			};
154
155			vdd_buckmem_reg: bmem {
156				regulator-min-microvolt = <3300000>;
157				regulator-max-microvolt = <3300000>;
158				regulator-always-on;
159			};
160
161			vdd_eth_reg: bio {
162				regulator-min-microvolt = <1200000>;
163				regulator-max-microvolt = <1200000>;
164				regulator-always-on;
165			};
166
167			vdd_eth_io_reg: ldo4 {
168				regulator-min-microvolt = <2500000>;
169				regulator-max-microvolt = <2500000>;
170				regulator-always-on;
171			};
172
173			vdd_mx6_snvs_reg: ldo5 {
174				regulator-min-microvolt = <3000000>;
175				regulator-max-microvolt = <3000000>;
176				regulator-always-on;
177			};
178
179			vdd_3v3_pmic_io_reg: ldo6 {
180				regulator-min-microvolt = <3300000>;
181				regulator-max-microvolt = <3300000>;
182				regulator-always-on;
183			};
184
185			vdd_sd0_reg: ldo9 {
186				regulator-min-microvolt = <3300000>;
187				regulator-max-microvolt = <3300000>;
188			};
189
190			vdd_sd1_reg: ldo10 {
191				regulator-min-microvolt = <3300000>;
192				regulator-max-microvolt = <3300000>;
193			};
194
195			vdd_mx6_high_reg: ldo11 {
196				regulator-min-microvolt = <3000000>;
197				regulator-max-microvolt = <3000000>;
198				regulator-always-on;
199			};
200		};
201
202		da9063_rtc: rtc {
203			compatible = "dlg,da9063-rtc";
204		};
205
206		da9063_wdog: watchdog {
207			compatible = "dlg,da9063-watchdog";
208		};
209
210		onkey {
211			compatible = "dlg,da9063-onkey";
212			status = "disabled";
213		};
214	};
215};
216
217&i2c2 {
218	pinctrl-names = "default";
219	pinctrl-0 = <&pinctrl_i2c2>;
220	clock-frequency = <100000>;
221};
222
223&i2c3 {
224	pinctrl-names = "default";
225	pinctrl-0 = <&pinctrl_i2c3>;
226	clock-frequency = <100000>;
227};
228
229&iomuxc {
230	imx6q-phytec-pfla02 {
231		pinctrl_ecspi3: ecspi3grp {
232			fsl,pins = <
233				MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO	0x100b1
234				MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI	0x100b1
235				MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK	0x100b1
236				MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24	0x80000000 /* CS0 */
237			>;
238		};
239
240		pinctrl_enet: enetgrp {
241			fsl,pins = <
242				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
243				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
244				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
245				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
246				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
247				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
248				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
249				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
250				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
251				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
252				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
253				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
254				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
255				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
256				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
257				MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0
258				MX6QDL_PAD_EIM_D23__GPIO3_IO23		0x80000000 /* Reset GPIO */
259			>;
260		};
261
262		pinctrl_flexcan1: flexcan1grp {
263			fsl,pins = <
264				MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX	0x1b0b0
265				MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX	0x1b0b0
266			>;
267		};
268
269		pinctrl_gpmi_nand: gpminandgrp {
270			fsl,pins = <
271				MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
272				MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
273				MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
274				MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
275				MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
276				MX6QDL_PAD_NANDF_CS1__NAND_CE1_B	0xb0b1
277				MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
278				MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
279				MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
280				MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
281				MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
282				MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
283				MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
284				MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
285				MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
286				MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
287				MX6QDL_PAD_SD4_DAT0__NAND_DQS		0x00b1
288			>;
289		};
290
291		pinctrl_i2c1: i2c1grp {
292			fsl,pins = <
293				MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
294				MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
295			>;
296		};
297
298		pinctrl_i2c2: i2c2grp {
299			fsl,pins = <
300				MX6QDL_PAD_EIM_EB2__I2C2_SCL		0x4001b8b1
301				MX6QDL_PAD_EIM_D16__I2C2_SDA		0x4001b8b1
302			>;
303		};
304
305		pinctrl_i2c3: i2c3grp {
306			fsl,pins = <
307				MX6QDL_PAD_EIM_D17__I2C3_SCL		0x4001b8b1
308				MX6QDL_PAD_EIM_D18__I2C3_SDA		0x4001b8b1
309			>;
310		};
311
312		pinctrl_leds: ledsgrp {
313			fsl,pins = <
314				MX6QDL_PAD_ENET_TXD0__GPIO1_IO30	0x80000000 /* Green LED */
315				MX6QDL_PAD_EIM_EB3__GPIO2_IO31		0x80000000 /* Red LED */
316			>;
317		};
318
319		pinctrl_pcie: pciegrp {
320			fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17  0x80000000>;
321		};
322
323		pinctrl_pmic: pmicgrp {
324			fsl,pins = <MX6QDL_PAD_SD4_DAT1__GPIO2_IO09	0x80000000>; /* PMIC interrupt */
325		};
326
327		pinctrl_uart3: uart3grp {
328			fsl,pins = <
329				MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
330				MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
331				MX6QDL_PAD_EIM_D31__UART3_RTS_B		0x1b0b1
332				MX6QDL_PAD_EIM_D30__UART3_CTS_B		0x1b0b1
333			>;
334		};
335
336		pinctrl_uart4: uart4grp {
337			fsl,pins = <
338				MX6QDL_PAD_KEY_COL0__UART4_TX_DATA	0x1b0b1
339				MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA	0x1b0b1
340			>;
341		};
342
343		pinctrl_usbh1_vbus: usbh1vbusgrp {
344			fsl,pins = <
345				MX6QDL_PAD_GPIO_0__GPIO1_IO00		0x1b0b0
346			>;
347		};
348
349		pinctrl_usbotg: usbotggrp {
350			fsl,pins = <
351				MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
352				MX6QDL_PAD_KEY_COL4__USB_OTG_OC		0x1b0b0
353				MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0x80000000
354			>;
355		};
356
357		pinctrl_usdhc2: usdhc2grp {
358			fsl,pins = <
359				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
360				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
361				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
362				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
363				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
364				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
365			>;
366		};
367
368		pinctrl_usdhc3: usdhc3grp {
369			fsl,pins = <
370				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
371				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
372				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
373				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
374				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
375				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
376			>;
377		};
378
379		pinctrl_usdhc3_cdwp: usdhc3cdwp {
380			fsl,pins = <
381				MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
382				MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
383			>;
384		};
385
386		pinctrl_audmux: audmuxgrp {
387			fsl,pins = <
388				MX6QDL_PAD_DISP0_DAT16__AUD5_TXC	0x130b0
389				MX6QDL_PAD_DISP0_DAT17__AUD5_TXD	0x110b0
390				MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS	0x130b0
391				MX6QDL_PAD_DISP0_DAT19__AUD5_RXD	0x130b0
392			>;
393		};
394	};
395};
396
397&pcie {
398	pinctrl-names = "default";
399	pinctrl-0 = <&pinctrl_pcie>;
400	reset-gpio = <&gpio4 17 GPIO_ACTIVE_LOW>;
401	status = "disabled";
402};
403
404&reg_arm {
405	vin-supply = <&vddcore_reg>;
406};
407
408&reg_pu {
409	vin-supply = <&vddsoc_reg>;
410};
411
412&reg_soc {
413	vin-supply = <&vddsoc_reg>;
414};
415
416&uart3 {
417	pinctrl-names = "default";
418	pinctrl-0 = <&pinctrl_uart3>;
419	uart-has-rtscts;
420	status = "disabled";
421};
422
423&uart4 {
424	pinctrl-names = "default";
425	pinctrl-0 = <&pinctrl_uart4>;
426	status = "disabled";
427};
428
429&usbh1 {
430	vbus-supply = <&reg_usb_h1_vbus>;
431	status = "disabled";
432};
433
434&usbotg {
435	vbus-supply = <&reg_usb_otg_vbus>;
436	pinctrl-names = "default";
437	pinctrl-0 = <&pinctrl_usbotg>;
438	disable-over-current;
439	status = "disabled";
440};
441
442&usdhc2 {
443	pinctrl-names = "default";
444	pinctrl-0 = <&pinctrl_usdhc2>;
445	cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
446	wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
447	vmmc-supply = <&vdd_sd1_reg>;
448	status = "disabled";
449};
450
451&usdhc3 {
452	pinctrl-names = "default";
453	pinctrl-0 = <&pinctrl_usdhc3
454		     &pinctrl_usdhc3_cdwp>;
455	cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
456	wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
457	vmmc-supply = <&vdd_sd0_reg>;
458	status = "disabled";
459};
460
461&wdog1 {
462	/*
463	 * Rely on PMIC reboot handler. Internal i.MX6 watchdog, that is also
464	 * used for reboot, does not reset all external PMIC voltages on reset.
465	 */
466	status = "disabled";
467};
468