1// SPDX-License-Identifier: GPL-2.0 OR X11 2/* 3 * Copyright 2017 (C) Priit Laes <plaes@plaes.org> 4 * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr@pengutronix.de> 5 * Copyright 2019 (C) Pengutronix, Marco Felsch <kernel@pengutronix.de> 6 * 7 * Based on initial work by Nikita Yushchenko <nyushchenko at dev.rtsoft.ru> 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/sound/fsl-imx-audmux.h> 12 13/ { 14 reg_1p0v_s0: regulator-1p0v-s0 { 15 compatible = "regulator-fixed"; 16 regulator-name = "V_1V0_S0"; 17 regulator-min-microvolt = <1000000>; 18 regulator-max-microvolt = <1000000>; 19 regulator-always-on; 20 regulator-boot-on; 21 vin-supply = <®_smarc_suppy>; 22 }; 23 24 reg_1p35v_vcoredig_s5: regulator-1p35v-vcoredig-s5 { 25 compatible = "regulator-fixed"; 26 regulator-name = "V_1V35_VCOREDIG_S5"; 27 regulator-min-microvolt = <1350000>; 28 regulator-max-microvolt = <1350000>; 29 regulator-always-on; 30 regulator-boot-on; 31 vin-supply = <®_3p3v_s5>; 32 }; 33 34 reg_1p8v_s5: regulator-1p8v-s5 { 35 compatible = "regulator-fixed"; 36 regulator-name = "V_1V8_S5"; 37 regulator-min-microvolt = <1800000>; 38 regulator-max-microvolt = <1800000>; 39 regulator-always-on; 40 regulator-boot-on; 41 vin-supply = <®_3p3v_s5>; 42 }; 43 44 reg_3p3v_s0: regulator-3p3v-s0 { 45 compatible = "regulator-fixed"; 46 regulator-name = "V_3V3_S0"; 47 regulator-min-microvolt = <3300000>; 48 regulator-max-microvolt = <3300000>; 49 regulator-always-on; 50 regulator-boot-on; 51 vin-supply = <®_3p3v_s5>; 52 }; 53 54 reg_3p3v_s5: regulator-3p3v-s5 { 55 compatible = "regulator-fixed"; 56 regulator-name = "V_3V3_S5"; 57 regulator-min-microvolt = <3300000>; 58 regulator-max-microvolt = <3300000>; 59 regulator-always-on; 60 regulator-boot-on; 61 vin-supply = <®_smarc_suppy>; 62 }; 63 64 reg_smarc_lcdbklt: regulator-smarc-lcdbklt { 65 compatible = "regulator-fixed"; 66 pinctrl-names = "default"; 67 pinctrl-0 = <&pinctrl_lcdbklt_en>; 68 regulator-name = "LCD_BKLT_EN"; 69 regulator-min-microvolt = <1800000>; 70 regulator-max-microvolt = <1800000>; 71 gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>; 72 enable-active-high; 73 }; 74 75 reg_smarc_lcdvdd: regulator-smarc-lcdvdd { 76 compatible = "regulator-fixed"; 77 pinctrl-names = "default"; 78 pinctrl-0 = <&pinctrl_lcdvdd_en>; 79 regulator-name = "LCD_VDD_EN"; 80 regulator-min-microvolt = <1800000>; 81 regulator-max-microvolt = <1800000>; 82 gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; 83 enable-active-high; 84 }; 85 86 reg_smarc_rtc: regulator-smarc-rtc { 87 compatible = "regulator-fixed"; 88 regulator-name = "V_IN_RTC_BATT"; 89 regulator-min-microvolt = <3300000>; 90 regulator-max-microvolt = <3300000>; 91 regulator-always-on; 92 regulator-boot-on; 93 }; 94 95 /* Module supply range can be 3.00V ... 5.25V */ 96 reg_smarc_suppy: regulator-smarc-supply { 97 compatible = "regulator-fixed"; 98 regulator-name = "V_IN_WIDE"; 99 regulator-min-microvolt = <5000000>; 100 regulator-max-microvolt = <5000000>; 101 regulator-always-on; 102 regulator-boot-on; 103 }; 104 105 lcd: lcd { 106 #address-cells = <1>; 107 #size-cells = <0>; 108 compatible = "fsl,imx-parallel-display"; 109 pinctrl-names = "default"; 110 pinctrl-0 = <&pinctrl_lcd>; 111 status = "disabled"; 112 113 port@0 { 114 reg = <0>; 115 116 lcd_in: endpoint { 117 }; 118 }; 119 120 port@1 { 121 reg = <1>; 122 123 lcd_out: endpoint { 124 }; 125 }; 126 }; 127 128 lcd_backlight: lcd-backlight { 129 compatible = "pwm-backlight"; 130 pwms = <&pwm4 0 5000000 0>; 131 pwm-names = "LCD_BKLT_PWM"; 132 133 brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; 134 default-brightness-level = <4>; 135 136 power-supply = <®_smarc_lcdbklt>; 137 status = "disabled"; 138 }; 139 140 i2c_intern: i2c-gpio-intern { 141 compatible = "i2c-gpio"; 142 pinctrl-names = "default"; 143 pinctrl-0 = <&pinctrl_i2c_gpio_intern>; 144 sda-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 145 scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 146 i2c-gpio,delay-us = <2>; /* ~100 kHz */ 147 #address-cells = <1>; 148 #size-cells = <0>; 149 }; 150 151 i2c_lcd: i2c-gpio-lcd { 152 compatible = "i2c-gpio"; 153 pinctrl-names = "default"; 154 pinctrl-0 = <&pinctrl_i2c_gpio_lcd>; 155 sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 156 scl-gpios = <&gpio1 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 157 i2c-gpio,delay-us = <2>; /* ~100 kHz */ 158 #address-cells = <1>; 159 #size-cells = <0>; 160 status = "disabled"; 161 }; 162 163 i2c_cam: i2c-gpio-cam { 164 compatible = "i2c-gpio"; 165 pinctrl-names = "default"; 166 pinctrl-0 = <&pinctrl_i2c_gpio_cam>; 167 sda-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 168 scl-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 169 i2c-gpio,delay-us = <2>; /* ~100 kHz */ 170 #address-cells = <1>; 171 #size-cells = <0>; 172 status = "disabled"; 173 }; 174}; 175 176/* I2S0, I2S1 */ 177&audmux { 178 pinctrl-names = "default"; 179 pinctrl-0 = <&pinctrl_audmux>; 180 181 audmux_ssi1 { 182 fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>; 183 fsl,port-config = < 184 (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT3) | 185 IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT3) | 186 IMX_AUDMUX_V2_PTCR_SYN | 187 IMX_AUDMUX_V2_PTCR_TFSDIR | 188 IMX_AUDMUX_V2_PTCR_TCLKDIR) 189 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT3) 190 >; 191 }; 192 193 audmux_adu3 { 194 fsl,audmux-port = <MX51_AUDMUX_PORT3>; 195 fsl,port-config = < 196 IMX_AUDMUX_V2_PTCR_SYN 197 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) 198 >; 199 }; 200 201 audmux_ssi2 { 202 fsl,audmux-port = <MX51_AUDMUX_PORT2_SSI1>; 203 fsl,port-config = < 204 (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) | 205 IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) | 206 IMX_AUDMUX_V2_PTCR_SYN | 207 IMX_AUDMUX_V2_PTCR_TFSDIR | 208 IMX_AUDMUX_V2_PTCR_TCLKDIR) 209 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4) 210 >; 211 }; 212 213 audmux_adu4 { 214 fsl,audmux-port = <MX51_AUDMUX_PORT4>; 215 fsl,port-config = < 216 IMX_AUDMUX_V2_PTCR_SYN 217 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT2_SSI1) 218 >; 219 }; 220}; 221 222/* CAN0 */ 223&can1 { 224 pinctrl-names = "default"; 225 pinctrl-0 = <&pinctrl_flexcan1>; 226}; 227 228/* CAN1 */ 229&can2 { 230 pinctrl-names = "default"; 231 pinctrl-0 = <&pinctrl_flexcan2>; 232}; 233 234/* SPI1 */ 235&ecspi2 { 236 pinctrl-names = "default"; 237 pinctrl-0 = <&pinctrl_ecspi2>; 238 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, 239 <&gpio2 27 GPIO_ACTIVE_LOW>; 240}; 241 242/* SPI0 */ 243&ecspi4 { 244 pinctrl-names = "default"; 245 pinctrl-0 = <&pinctrl_ecspi4>; 246 cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>, 247 <&gpio3 29 GPIO_ACTIVE_LOW>, 248 <&gpio3 25 GPIO_ACTIVE_LOW>; 249 status = "okay"; 250 251 /* default boot source: workaround #1 for errata ERR006282 */ 252 smarc_flash: flash@0 { 253 compatible = "jedec,spi-nor"; 254 reg = <0>; 255 spi-max-frequency = <20000000>; 256 }; 257}; 258 259/* GBE */ 260&fec { 261 pinctrl-names = "default"; 262 pinctrl-0 = <&pinctrl_enet>; 263 phy-connection-type = "rgmii-id"; 264 phy-handle = <ðphy>; 265 266 mdio { 267 #address-cells = <1>; 268 #size-cells = <0>; 269 270 ethphy: ethernet-phy@1 { 271 compatible = "ethernet-phy-ieee802.3-c22"; 272 reg = <1>; 273 reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 274 reset-assert-us = <1000>; 275 }; 276 }; 277}; 278 279&hdmi { 280 ddc-i2c-bus = <&i2c2>; 281}; 282 283&i2c_intern { 284 pmic@8 { 285 compatible = "fsl,pfuze100"; 286 reg = <0x08>; 287 288 regulators { 289 reg_v_core_s0: sw1ab { 290 regulator-name = "V_CORE_S0"; 291 regulator-min-microvolt = <300000>; 292 regulator-max-microvolt = <1875000>; 293 regulator-boot-on; 294 regulator-always-on; 295 }; 296 297 reg_vddsoc_s0: sw1c { 298 regulator-name = "V_VDDSOC_S0"; 299 regulator-min-microvolt = <300000>; 300 regulator-max-microvolt = <1875000>; 301 regulator-boot-on; 302 regulator-always-on; 303 }; 304 305 reg_3p15v_s0: sw2 { 306 regulator-name = "V_3V15_S0"; 307 regulator-min-microvolt = <800000>; 308 regulator-max-microvolt = <3300000>; 309 regulator-boot-on; 310 regulator-always-on; 311 }; 312 313 /* sw3a/b is used in dual mode, but driver does not 314 * support it. Although, there's no need to control 315 * DDR power - so just leaving dummy entries for sw3a 316 * and sw3b for now. 317 */ 318 sw3a { 319 regulator-min-microvolt = <400000>; 320 regulator-max-microvolt = <1975000>; 321 regulator-boot-on; 322 regulator-always-on; 323 }; 324 325 sw3b { 326 regulator-min-microvolt = <400000>; 327 regulator-max-microvolt = <1975000>; 328 regulator-boot-on; 329 regulator-always-on; 330 }; 331 332 reg_1p8v_s0: sw4 { 333 regulator-name = "V_1V8_S0"; 334 regulator-min-microvolt = <800000>; 335 regulator-max-microvolt = <3300000>; 336 regulator-boot-on; 337 regulator-always-on; 338 }; 339 340 /* Regulator for USB */ 341 reg_5p0v_s0: swbst { 342 regulator-name = "V_5V0_S0"; 343 regulator-min-microvolt = <5000000>; 344 regulator-max-microvolt = <5150000>; 345 regulator-boot-on; 346 }; 347 348 reg_vsnvs: vsnvs { 349 regulator-min-microvolt = <1000000>; 350 regulator-max-microvolt = <3000000>; 351 regulator-boot-on; 352 regulator-always-on; 353 }; 354 355 reg_vrefddr: vrefddr { 356 regulator-boot-on; 357 regulator-always-on; 358 }; 359 360 /* 361 * Per schematics, of all VGEN's, only VGEN5 has some 362 * usage ... but even that - over DNI resistor 363 */ 364 vgen1 { 365 regulator-min-microvolt = <800000>; 366 regulator-max-microvolt = <1550000>; 367 }; 368 369 vgen2 { 370 regulator-min-microvolt = <800000>; 371 regulator-max-microvolt = <1550000>; 372 }; 373 374 vgen3 { 375 regulator-min-microvolt = <1800000>; 376 regulator-max-microvolt = <3300000>; 377 }; 378 379 vgen4 { 380 regulator-min-microvolt = <1800000>; 381 regulator-max-microvolt = <3300000>; 382 }; 383 384 reg_2p5v_s0: vgen5 { 385 regulator-name = "V_2V5_S0"; 386 regulator-min-microvolt = <1800000>; 387 regulator-max-microvolt = <3300000>; 388 }; 389 390 vgen6 { 391 regulator-min-microvolt = <1800000>; 392 regulator-max-microvolt = <3300000>; 393 }; 394 }; 395 }; 396}; 397 398/* I2C_GP */ 399&i2c1 { 400 clock-frequency = <375000>; 401 pinctrl-names = "default"; 402 pinctrl-0 = <&pinctrl_i2c1>; 403}; 404 405/* HDMI_CTRL */ 406&i2c2 { 407 clock-frequency = <100000>; 408 pinctrl-names = "default"; 409 pinctrl-0 = <&pinctrl_i2c2>; 410}; 411 412/* I2C_PM */ 413&i2c3 { 414 clock-frequency = <375000>; 415 pinctrl-names = "default"; 416 pinctrl-0 = <&pinctrl_i2c3>; 417 status = "okay"; 418 419 smarc_eeprom: eeprom@50 { 420 compatible = "atmel,24c32"; 421 reg = <0x50>; 422 pagesize = <32>; 423 }; 424}; 425 426&iomuxc { 427 pinctrl-names = "default"; 428 pinctrl-0 = <&pinctrl_mgmt_gpios &pinctrl_gpio>; 429 430 pinctrl_audmux: audmuxgrp { 431 fsl,pins = < 432 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 433 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130b0 434 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 435 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 436 437 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 438 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 439 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 440 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 441 442 /* AUDIO MCLK */ 443 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x000b0 444 >; 445 }; 446 447 pinctrl_ecspi2: ecspi2grp { 448 fsl,pins = < 449 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 450 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 451 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 452 453 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 /* CS0 */ 454 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 /* CS1 */ 455 >; 456 }; 457 458 pinctrl_ecspi4: ecspi4grp { 459 fsl,pins = < 460 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 461 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 462 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 463 464 /* SPI_IMX_CS2# - connected to internal flash */ 465 MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0 466 /* SPI_IMX_CS0# - connected to SMARC SPI0_CS0# */ 467 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 468 /* SPI4_CS3# - connected to SMARC SPI0_CS1# */ 469 MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x1b0b0 470 >; 471 }; 472 473 pinctrl_flexcan1: flexcan1grp { 474 fsl,pins = < 475 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 476 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 477 >; 478 }; 479 480 pinctrl_flexcan2: flexcan2grp { 481 fsl,pins = < 482 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 483 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 484 >; 485 }; 486 487 pinctrl_gpio: gpiogrp { 488 fsl,pins = < 489 MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b0 /* GPIO0 / CAM0_PWR# */ 490 MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b0 /* GPIO1 / CAM1_PWR# */ 491 MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b0 /* GPIO2 / CAM0_RST# */ 492 MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b0 /* GPIO3 / CAM1_RST# */ 493 MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b0 /* GPIO4 / HDA_RST# */ 494 MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b0 /* GPIO5 / PWM_OUT */ 495 MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b0 /* GPIO6 / TACHIN */ 496 MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b0 /* GPIO7 / PCAM_FLD */ 497 MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b0 /* GPIO8 / CAN0_ERR# */ 498 MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b0 /* GPIO9 / CAN1_ERR# */ 499 MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b0 /* GPIO10 */ 500 MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b0 /* GPIO11 */ 501 >; 502 }; 503 504 pinctrl_enet: enetgrp { 505 fsl,pins = < 506 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 507 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 508 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 509 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 510 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 511 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 512 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 513 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 514 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 515 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 516 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 517 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 518 519 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 520 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 521 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 522 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 /* RST_GBE0_PHY# */ 523 >; 524 }; 525 526 pinctrl_i2c_gpio_cam: i2c-gpiocamgrp { 527 fsl,pins = < 528 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* SCL */ 529 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* SDA */ 530 >; 531 }; 532 533 pinctrl_i2c_gpio_intern: i2c-gpiointerngrp { 534 fsl,pins = < 535 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* SCL */ 536 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* SDA */ 537 >; 538 }; 539 540 pinctrl_i2c_gpio_lcd: i2c-gpiolcdgrp { 541 fsl,pins = < 542 MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 /* SCL */ 543 MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b0 /* SDA */ 544 >; 545 }; 546 547 pinctrl_i2c1: i2c1grp { 548 fsl,pins = < 549 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 550 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 551 >; 552 }; 553 554 pinctrl_i2c2: i2c2grp { 555 fsl,pins = < 556 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 557 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 558 >; 559 }; 560 561 pinctrl_i2c3: i2c3grp { 562 fsl,pins = < 563 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 564 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 565 >; 566 }; 567 568 pinctrl_lcd: lcdgrp { 569 fsl,pins = < 570 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100f1 571 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100f1 572 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100f1 573 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100f1 574 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100f1 575 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100f1 576 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100f1 577 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100f1 578 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100f1 579 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100f1 580 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100f1 581 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100f1 582 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100f1 583 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100f1 584 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100f1 585 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100f1 586 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100f1 587 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100f1 588 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x100f1 589 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x100f1 590 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x100f1 591 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x100f1 592 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x100f1 593 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x100f1 594 595 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f1 596 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100f1 /* DE */ 597 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100f1 /* HSYNC */ 598 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100f1 /* VSYNC */ 599 >; 600 }; 601 602 pinctrl_lcdbklt_en: lcdbkltengrp { 603 fsl,pins = < 604 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b1 605 >; 606 }; 607 608 pinctrl_lcdvdd_en: lcdvddengrp { 609 fsl,pins = < 610 MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 611 >; 612 }; 613 614 pinctrl_mipi_csi: mipi-csigrp { 615 fsl,pins = < 616 MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x000b0 /* CSI0/1 MCLK */ 617 >; 618 }; 619 620 pinctrl_mgmt_gpios: mgmt-gpiosgrp { 621 fsl,pins = < 622 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 /* LID# */ 623 MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x1b0b0 /* SLEEP# */ 624 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* CHARGING# */ 625 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* CHARGER_PRSNT# */ 626 MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0 /* CARRIER_STBY# */ 627 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* BATLOW# */ 628 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0 /* TEST# */ 629 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 /* VDD_IO_SEL_D# */ 630 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 /* POWER_BTN# */ 631 >; 632 }; 633 634 pinctrl_pcie: pciegrp { 635 fsl,pins = < 636 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 /* PCI_A_PRSNT# */ 637 MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 /* RST_PCIE_A# */ 638 MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 /* PCIE_WAKE# */ 639 >; 640 }; 641 642 pinctrl_pwm4: pwm4grp { 643 fsl,pins = < 644 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 645 >; 646 }; 647 648 pinctrl_uart1: uart1grp { 649 fsl,pins = < 650 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 651 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 652 MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 653 MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1 654 >; 655 }; 656 657 pinctrl_uart2: uart2grp { 658 fsl,pins = < 659 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 660 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 661 >; 662 }; 663 664 pinctrl_uart4: uart4grp { 665 fsl,pins = < 666 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 667 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 668 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 669 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 670 >; 671 }; 672 673 pinctrl_uart5: uart5grp { 674 fsl,pins = < 675 MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 676 MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 677 >; 678 }; 679 680 pinctrl_usbotg: usbotggrp { 681 fsl,pins = < 682 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1f8b0 683 /* power, oc muxed but not used by the driver */ 684 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 /* USB power */ 685 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 /* USB OC */ 686 >; 687 }; 688 689 pinctrl_usdhc3: usdhc3grp { 690 fsl,pins = < 691 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x17059 692 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 693 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 694 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 695 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 696 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 697 698 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 /* CD */ 699 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 /* WP */ 700 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PWR_EN */ 701 >; 702 }; 703 704 pinctrl_usdhc4: usdhc4grp { 705 fsl,pins = < 706 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 707 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 708 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 709 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 710 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 711 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 712 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 713 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 714 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 715 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 716 >; 717 }; 718 719 pinctrl_wdog1: wdog1rp { 720 fsl,pins = < 721 MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 722 >; 723 }; 724}; 725 726&mipi_csi { 727 pinctrl-names = "default"; 728 pinctrl-0 = <&pinctrl_mipi_csi>; 729}; 730 731&pcie { 732 pinctrl-names = "default"; 733 pinctrl-0 = <&pinctrl_pcie>; 734 wake-up-gpio = <&gpio6 18 GPIO_ACTIVE_HIGH>; 735 reset-gpio = <&gpio3 13 GPIO_ACTIVE_LOW>; 736}; 737 738/* LCD_BKLT_PWM */ 739&pwm4 { 740 pinctrl-names = "default"; 741 pinctrl-0 = <&pinctrl_pwm4>; 742}; 743 744®_arm { 745 vin-supply = <®_v_core_s0>; 746}; 747 748®_pu { 749 vin-supply = <®_vddsoc_s0>; 750}; 751 752®_soc { 753 vin-supply = <®_vddsoc_s0>; 754}; 755 756/* SER0 */ 757&uart1 { 758 pinctrl-names = "default"; 759 pinctrl-0 = <&pinctrl_uart1>; 760 uart-has-rtscts; 761}; 762 763/* SER1 */ 764&uart2 { 765 pinctrl-names = "default"; 766 pinctrl-0 = <&pinctrl_uart2>; 767}; 768 769/* SER2 */ 770&uart4 { 771 pinctrl-names = "default"; 772 pinctrl-0 = <&pinctrl_uart4>; 773 uart-has-rtscts; 774}; 775 776/* SER3 */ 777&uart5 { 778 pinctrl-names = "default"; 779 pinctrl-0 = <&pinctrl_uart5>; 780}; 781 782/* USB0 */ 783&usbotg { 784 /* 785 * no 'imx6-usb-charger-detection' 786 * since USB_OTG_CHD_B pin is not wired 787 */ 788 pinctrl-names = "default"; 789 pinctrl-0 = <&pinctrl_usbotg>; 790}; 791 792/* USB1/2 via hub */ 793&usbh1 { 794 vbus-supply = <®_5p0v_s0>; 795}; 796 797/* SDIO */ 798&usdhc3 { 799 pinctrl-names = "default"; 800 pinctrl-0 = <&pinctrl_usdhc3>; 801 cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; 802 wp-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 803 no-1-8-v; 804}; 805 806/* SDMMC */ 807&usdhc4 { 808 /* Internal eMMC, optional on some boards */ 809 pinctrl-names = "default"; 810 pinctrl-0 = <&pinctrl_usdhc4>; 811 bus-width = <8>; 812 no-sdio; 813 no-sd; 814 non-removable; 815 vmmc-supply = <®_3p3v_s0>; 816 vqmmc-supply = <®_1p8v_s0>; 817}; 818 819&wdog1 { 820 /* CPLD is feeded by watchdog (hardwired) */ 821 pinctrl-names = "default"; 822 pinctrl-0 = <&pinctrl_wdog1>; 823 fsl,ext-reset-output; 824 status = "okay"; 825}; 826