xref: /openbmc/linux/arch/arm/boot/dts/nxp/imx/imx50.dtsi (revision 38633443)
1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2013 Greg Ungerer <gerg@uclinux.org>
4// Copyright 2011 Freescale Semiconductor, Inc.
5// Copyright 2011 Linaro Ltd.
6
7#include "imx50-pinfunc.h"
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/clock/imx5-clock.h>
10
11/ {
12	#address-cells = <1>;
13	#size-cells = <1>;
14	/*
15	 * The decompressor and also some bootloaders rely on a
16	 * pre-existing /chosen node to be available to insert the
17	 * command line and merge other ATAGS info.
18	 */
19	chosen {};
20
21	aliases {
22		ethernet0 = &fec;
23		gpio0 = &gpio1;
24		gpio1 = &gpio2;
25		gpio2 = &gpio3;
26		gpio3 = &gpio4;
27		gpio4 = &gpio5;
28		gpio5 = &gpio6;
29		i2c0 = &i2c1;
30		i2c1 = &i2c2;
31		i2c2 = &i2c3;
32		mmc0 = &esdhc1;
33		mmc1 = &esdhc2;
34		mmc2 = &esdhc3;
35		mmc3 = &esdhc4;
36		serial0 = &uart1;
37		serial1 = &uart2;
38		serial2 = &uart3;
39		serial3 = &uart4;
40		serial4 = &uart5;
41		spi0 = &ecspi1;
42		spi1 = &ecspi2;
43		spi2 = &cspi;
44	};
45
46	cpus {
47		#address-cells = <1>;
48		#size-cells = <0>;
49		cpu@0 {
50			device_type = "cpu";
51			compatible = "arm,cortex-a8";
52			reg = <0x0>;
53		};
54	};
55
56	tzic: tz-interrupt-controller@fffc000 {
57		compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
58		interrupt-controller;
59		#interrupt-cells = <1>;
60		reg = <0x0fffc000 0x4000>;
61	};
62
63	clocks {
64		ckil {
65			compatible = "fixed-clock";
66			#clock-cells = <0>;
67			clock-frequency = <32768>;
68		};
69
70		ckih1 {
71			compatible = "fixed-clock";
72			#clock-cells = <0>;
73			clock-frequency = <22579200>;
74		};
75
76		ckih2 {
77			compatible = "fixed-clock";
78			#clock-cells = <0>;
79			clock-frequency = <0>;
80		};
81
82		osc {
83			compatible = "fixed-clock";
84			#clock-cells = <0>;
85			clock-frequency = <24000000>;
86		};
87	};
88
89	usbphy0: usbphy-0 {
90		compatible = "usb-nop-xceiv";
91		clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
92		clock-names = "main_clk";
93		#phy-cells = <0>;
94		status = "okay";
95	};
96
97	soc: soc {
98		#address-cells = <1>;
99		#size-cells = <1>;
100		compatible = "simple-bus";
101		interrupt-parent = <&tzic>;
102		ranges;
103
104		aips1: bus@50000000 { /* AIPS1 */
105			compatible = "fsl,aips-bus", "simple-bus";
106			#address-cells = <1>;
107			#size-cells = <1>;
108			reg = <0x50000000 0x10000000>;
109			ranges;
110
111			spba-bus@50000000 {
112				compatible = "fsl,spba-bus", "simple-bus";
113				#address-cells = <1>;
114				#size-cells = <1>;
115				reg = <0x50000000 0x40000>;
116				ranges;
117
118				esdhc1: mmc@50004000 {
119					compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
120					reg = <0x50004000 0x4000>;
121					interrupts = <1>;
122					clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
123						 <&clks IMX5_CLK_DUMMY>,
124						 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
125					clock-names = "ipg", "ahb", "per";
126					bus-width = <4>;
127					status = "disabled";
128				};
129
130				esdhc2: mmc@50008000 {
131					compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
132					reg = <0x50008000 0x4000>;
133					interrupts = <2>;
134					clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
135						 <&clks IMX5_CLK_DUMMY>,
136						 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
137					clock-names = "ipg", "ahb", "per";
138					bus-width = <4>;
139					status = "disabled";
140				};
141
142				uart3: serial@5000c000 {
143					compatible = "fsl,imx50-uart", "fsl,imx21-uart";
144					reg = <0x5000c000 0x4000>;
145					interrupts = <33>;
146					clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
147						 <&clks IMX5_CLK_UART3_PER_GATE>;
148					clock-names = "ipg", "per";
149					status = "disabled";
150				};
151
152				ecspi1: spi@50010000 {
153					#address-cells = <1>;
154					#size-cells = <0>;
155					compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
156					reg = <0x50010000 0x4000>;
157					interrupts = <36>;
158					clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
159						 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
160					clock-names = "ipg", "per";
161					status = "disabled";
162				};
163
164				ssi2: ssi@50014000 {
165					#sound-dai-cells = <0>;
166					compatible = "fsl,imx50-ssi",
167							"fsl,imx51-ssi",
168							"fsl,imx21-ssi";
169					reg = <0x50014000 0x4000>;
170					interrupts = <30>;
171					clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
172					dmas = <&sdma 24 1 0>,
173					       <&sdma 25 1 0>;
174					dma-names = "rx", "tx";
175					fsl,fifo-depth = <15>;
176					status = "disabled";
177				};
178
179				esdhc3: mmc@50020000 {
180					compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
181					reg = <0x50020000 0x4000>;
182					interrupts = <3>;
183					clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
184						 <&clks IMX5_CLK_DUMMY>,
185						 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
186					clock-names = "ipg", "ahb", "per";
187					bus-width = <4>;
188					status = "disabled";
189				};
190
191				esdhc4: mmc@50024000 {
192					compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
193					reg = <0x50024000 0x4000>;
194					interrupts = <4>;
195					clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
196						 <&clks IMX5_CLK_DUMMY>,
197						 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
198					clock-names = "ipg", "ahb", "per";
199					bus-width = <4>;
200					status = "disabled";
201				};
202			};
203
204			usbotg: usb@53f80000 {
205				compatible = "fsl,imx50-usb", "fsl,imx27-usb";
206				reg = <0x53f80000 0x0200>;
207				interrupts = <18>;
208				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
209				fsl,usbphy = <&usbphy0>;
210				status = "disabled";
211			};
212
213			usbh1: usb@53f80200 {
214				compatible = "fsl,imx50-usb", "fsl,imx27-usb";
215				reg = <0x53f80200 0x0200>;
216				interrupts = <14>;
217				clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
218				dr_mode = "host";
219				status = "disabled";
220			};
221
222			gpio1: gpio@53f84000 {
223				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
224				reg = <0x53f84000 0x4000>;
225				interrupts = <50 51>;
226				gpio-controller;
227				#gpio-cells = <2>;
228				interrupt-controller;
229				#interrupt-cells = <2>;
230				gpio-ranges = <&iomuxc 0 151 28>;
231			};
232
233			gpio2: gpio@53f88000 {
234				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
235				reg = <0x53f88000 0x4000>;
236				interrupts = <52 53>;
237				gpio-controller;
238				#gpio-cells = <2>;
239				interrupt-controller;
240				#interrupt-cells = <2>;
241				gpio-ranges = <&iomuxc  0 75 8>, <&iomuxc 8 100 8>,
242					      <&iomuxc 16 83 1>, <&iomuxc 17 85 1>,
243					      <&iomuxc 18 87 1>, <&iomuxc 19 84 1>,
244					      <&iomuxc 20 88 1>, <&iomuxc 21 86 1>;
245			};
246
247			gpio3: gpio@53f8c000 {
248				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
249				reg = <0x53f8c000 0x4000>;
250				interrupts = <54 55>;
251				gpio-controller;
252				#gpio-cells = <2>;
253				interrupt-controller;
254				#interrupt-cells = <2>;
255				gpio-ranges = <&iomuxc 0 108 32>;
256			};
257
258			gpio4: gpio@53f90000 {
259				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
260				reg = <0x53f90000 0x4000>;
261				interrupts = <56 57>;
262				gpio-controller;
263				#gpio-cells = <2>;
264				interrupt-controller;
265				#interrupt-cells = <2>;
266				gpio-ranges = <&iomuxc  0   8  8>, <&iomuxc 8 45 12>,
267					      <&iomuxc 20 140 11>;
268			};
269
270			wdog1: watchdog@53f98000 {
271				compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
272				reg = <0x53f98000 0x4000>;
273				interrupts = <58>;
274				clocks = <&clks IMX5_CLK_DUMMY>;
275			};
276
277			gpt: timer@53fa0000 {
278				compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
279				reg = <0x53fa0000 0x4000>;
280				interrupts = <39>;
281				clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
282					 <&clks IMX5_CLK_GPT_HF_GATE>;
283				clock-names = "ipg", "per";
284			};
285
286			iomuxc: iomuxc@53fa8000 {
287				compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
288				reg = <0x53fa8000 0x4000>;
289			};
290
291			pwm1: pwm@53fb4000 {
292				#pwm-cells = <3>;
293				compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
294				reg = <0x53fb4000 0x4000>;
295				clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
296					 <&clks IMX5_CLK_PWM1_HF_GATE>;
297				clock-names = "ipg", "per";
298				interrupts = <61>;
299			};
300
301			pwm2: pwm@53fb8000 {
302				#pwm-cells = <3>;
303				compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
304				reg = <0x53fb8000 0x4000>;
305				clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
306					 <&clks IMX5_CLK_PWM2_HF_GATE>;
307				clock-names = "ipg", "per";
308				interrupts = <94>;
309			};
310
311			uart1: serial@53fbc000 {
312				compatible = "fsl,imx50-uart", "fsl,imx21-uart";
313				reg = <0x53fbc000 0x4000>;
314				interrupts = <31>;
315				clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
316					 <&clks IMX5_CLK_UART1_PER_GATE>;
317				clock-names = "ipg", "per";
318				status = "disabled";
319			};
320
321			uart2: serial@53fc0000 {
322				compatible = "fsl,imx50-uart", "fsl,imx21-uart";
323				reg = <0x53fc0000 0x4000>;
324				interrupts = <32>;
325				clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
326					 <&clks IMX5_CLK_UART2_PER_GATE>;
327				clock-names = "ipg", "per";
328				status = "disabled";
329			};
330
331			src: reset-controller@53fd0000 {
332				compatible = "fsl,imx50-src", "fsl,imx51-src";
333				reg = <0x53fd0000 0x4000>;
334				interrupts = <75>;
335				#reset-cells = <1>;
336			};
337
338			clks: ccm@53fd4000 {
339				compatible = "fsl,imx50-ccm";
340				reg = <0x53fd4000 0x4000>;
341				interrupts = <0 71 0x04 0 72 0x04>;
342				#clock-cells = <1>;
343			};
344
345			gpio5: gpio@53fdc000 {
346				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
347				reg = <0x53fdc000 0x4000>;
348				interrupts = <103 104>;
349				gpio-controller;
350				#gpio-cells = <2>;
351				interrupt-controller;
352				#interrupt-cells = <2>;
353				gpio-ranges = <&iomuxc 0 57 18>, <&iomuxc 18 89 11>;
354			};
355
356			gpio6: gpio@53fe0000 {
357				compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
358				reg = <0x53fe0000 0x4000>;
359				interrupts = <105 106>;
360				gpio-controller;
361				#gpio-cells = <2>;
362				interrupt-controller;
363				#interrupt-cells = <2>;
364				gpio-ranges = <&iomuxc 0 27 18>, <&iomuxc 18 16 11>;
365			};
366
367			i2c3: i2c@53fec000 {
368				#address-cells = <1>;
369				#size-cells = <0>;
370				compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
371				reg = <0x53fec000 0x4000>;
372				interrupts = <64>;
373				clocks = <&clks IMX5_CLK_I2C3_GATE>;
374				status = "disabled";
375			};
376
377			uart4: serial@53ff0000 {
378				compatible = "fsl,imx50-uart", "fsl,imx21-uart";
379				reg = <0x53ff0000 0x4000>;
380				interrupts = <13>;
381				clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
382					 <&clks IMX5_CLK_UART4_PER_GATE>;
383				clock-names = "ipg", "per";
384				status = "disabled";
385			};
386		};
387
388		aips2: bus@60000000 {	/* AIPS2 */
389			compatible = "fsl,aips-bus", "simple-bus";
390			#address-cells = <1>;
391			#size-cells = <1>;
392			reg = <0x60000000 0x10000000>;
393			ranges;
394
395			uart5: serial@63f90000 {
396				compatible = "fsl,imx50-uart", "fsl,imx21-uart";
397				reg = <0x63f90000 0x4000>;
398				interrupts = <86>;
399				clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
400					 <&clks IMX5_CLK_UART5_PER_GATE>;
401				clock-names = "ipg", "per";
402				status = "disabled";
403			};
404
405			owire: owire@63fa4000 {
406				compatible = "fsl,imx50-owire", "fsl,imx21-owire";
407				reg = <0x63fa4000 0x4000>;
408				clocks = <&clks IMX5_CLK_OWIRE_GATE>;
409				status = "disabled";
410			};
411
412			ecspi2: spi@63fac000 {
413				#address-cells = <1>;
414				#size-cells = <0>;
415				compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
416				reg = <0x63fac000 0x4000>;
417				interrupts = <37>;
418				clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
419					 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
420				clock-names = "ipg", "per";
421				status = "disabled";
422			};
423
424			sdma: dma-controller@63fb0000 {
425				compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
426				reg = <0x63fb0000 0x4000>;
427				interrupts = <6>;
428				clocks = <&clks IMX5_CLK_SDMA_GATE>,
429					 <&clks IMX5_CLK_AHB>;
430				clock-names = "ipg", "ahb";
431				#dma-cells = <3>;
432				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
433			};
434
435			cspi: spi@63fc0000 {
436				#address-cells = <1>;
437				#size-cells = <0>;
438				compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
439				reg = <0x63fc0000 0x4000>;
440				interrupts = <38>;
441				clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
442					 <&clks IMX5_CLK_CSPI_IPG_GATE>;
443				clock-names = "ipg", "per";
444				status = "disabled";
445			};
446
447			i2c2: i2c@63fc4000 {
448				#address-cells = <1>;
449				#size-cells = <0>;
450				compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
451				reg = <0x63fc4000 0x4000>;
452				interrupts = <63>;
453				clocks = <&clks IMX5_CLK_I2C2_GATE>;
454				status = "disabled";
455			};
456
457			i2c1: i2c@63fc8000 {
458				#address-cells = <1>;
459				#size-cells = <0>;
460				compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
461				reg = <0x63fc8000 0x4000>;
462				interrupts = <62>;
463				clocks = <&clks IMX5_CLK_I2C1_GATE>;
464				status = "disabled";
465			};
466
467			ssi1: ssi@63fcc000 {
468				#sound-dai-cells = <0>;
469				compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
470							"fsl,imx21-ssi";
471				reg = <0x63fcc000 0x4000>;
472				interrupts = <29>;
473				clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
474				dmas = <&sdma 28 0 0>,
475				       <&sdma 29 0 0>;
476				dma-names = "rx", "tx";
477				fsl,fifo-depth = <15>;
478				status = "disabled";
479			};
480
481			audmux: audmux@63fd0000 {
482				compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
483				reg = <0x63fd0000 0x4000>;
484				status = "disabled";
485			};
486
487			fec: ethernet@63fec000 {
488				compatible = "fsl,imx53-fec", "fsl,imx25-fec";
489				reg = <0x63fec000 0x4000>;
490				interrupts = <87>;
491				clocks = <&clks IMX5_CLK_FEC_GATE>,
492					 <&clks IMX5_CLK_FEC_GATE>,
493					 <&clks IMX5_CLK_FEC_GATE>;
494				clock-names = "ipg", "ahb", "ptp";
495				status = "disabled";
496			};
497		};
498	};
499};
500