1 /*
2 * IGD device quirks
3 *
4 * Copyright Red Hat, Inc. 2016
5 *
6 * Authors:
7 * Alex Williamson <alex.williamson@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 */
12
13 #include "qemu/osdep.h"
14 #include "qemu/units.h"
15 #include "qemu/error-report.h"
16 #include "qapi/error.h"
17 #include "qapi/qmp/qerror.h"
18 #include "hw/boards.h"
19 #include "hw/hw.h"
20 #include "hw/nvram/fw_cfg.h"
21 #include "pci.h"
22 #include "pci-quirks.h"
23 #include "trace.h"
24
25 /*
26 * Intel IGD support
27 *
28 * Obviously IGD is not a discrete device, this is evidenced not only by it
29 * being integrated into the CPU, but by the various chipset and BIOS
30 * dependencies that it brings along with it. Intel is trying to move away
31 * from this and Broadwell and newer devices can run in what Intel calls
32 * "Universal Pass-Through" mode, or UPT. Theoretically in UPT mode, nothing
33 * more is required beyond assigning the IGD device to a VM. There are
34 * however support limitations to this mode. It only supports IGD as a
35 * secondary graphics device in the VM and it doesn't officially support any
36 * physical outputs.
37 *
38 * The code here attempts to enable what we'll call legacy mode assignment,
39 * IGD retains most of the capabilities we expect for it to have on bare
40 * metal. To enable this mode, the IGD device must be assigned to the VM
41 * at PCI address 00:02.0, it must have a ROM, it very likely needs VGA
42 * support, we must have VM BIOS support for reserving and populating some
43 * of the required tables, and we need to tweak the chipset with revisions
44 * and IDs and an LPC/ISA bridge device. The intention is to make all of
45 * this happen automatically by installing the device at the correct VM PCI
46 * bus address. If any of the conditions are not met, we cross our fingers
47 * and hope the user knows better.
48 *
49 * NB - It is possible to enable physical outputs in UPT mode by supplying
50 * an OpRegion table. We don't do this by default because the guest driver
51 * behaves differently if an OpRegion is provided and no monitor is attached
52 * vs no OpRegion and a monitor being attached or not. Effectively, if a
53 * headless setup is desired, the OpRegion gets in the way of that.
54 */
55
56 /*
57 * This presumes the device is already known to be an Intel VGA device, so we
58 * take liberties in which device ID bits match which generation. This should
59 * not be taken as an indication that all the devices are supported, or even
60 * supportable, some of them don't even support VT-d.
61 * See linux:include/drm/i915_pciids.h for IDs.
62 */
igd_gen(VFIOPCIDevice * vdev)63 static int igd_gen(VFIOPCIDevice *vdev)
64 {
65 /*
66 * Device IDs for Broxton/Apollo Lake are 0x0a84, 0x1a84, 0x1a85, 0x5a84
67 * and 0x5a85, match bit 11:1 here
68 * Prefix 0x0a is taken by Haswell, this rule should be matched first.
69 */
70 if ((vdev->device_id & 0xffe) == 0xa84) {
71 return 9;
72 }
73
74 switch (vdev->device_id & 0xff00) {
75 case 0x0100: /* SandyBridge, IvyBridge */
76 return 6;
77 case 0x0400: /* Haswell */
78 case 0x0a00: /* Haswell */
79 case 0x0c00: /* Haswell */
80 case 0x0d00: /* Haswell */
81 case 0x0f00: /* Valleyview/Bay Trail */
82 return 7;
83 case 0x1600: /* Broadwell */
84 case 0x2200: /* Cherryview */
85 return 8;
86 case 0x1900: /* Skylake */
87 case 0x3100: /* Gemini Lake */
88 case 0x5900: /* Kaby Lake */
89 case 0x3e00: /* Coffee Lake */
90 case 0x9B00: /* Comet Lake */
91 return 9;
92 case 0x8A00: /* Ice Lake */
93 case 0x4500: /* Elkhart Lake */
94 case 0x4E00: /* Jasper Lake */
95 return 11;
96 case 0x9A00: /* Tiger Lake */
97 case 0x4C00: /* Rocket Lake */
98 case 0x4600: /* Alder Lake */
99 case 0xA700: /* Raptor Lake */
100 return 12;
101 }
102
103 /*
104 * Unfortunately, Intel changes it's specification quite often. This makes
105 * it impossible to use a suitable default value for unknown devices.
106 * Return -1 for not applying any generation-specific quirks.
107 */
108 return -1;
109 }
110
111 #define IGD_ASLS 0xfc /* ASL Storage Register */
112 #define IGD_GMCH 0x50 /* Graphics Control Register */
113 #define IGD_BDSM 0x5c /* Base Data of Stolen Memory */
114 #define IGD_BDSM_GEN11 0xc0 /* Base Data of Stolen Memory of gen 11 and later */
115
116 #define IGD_GMCH_VGA_DISABLE BIT(1)
117 #define IGD_GMCH_GEN6_GMS_SHIFT 3 /* SNB_GMCH in i915 */
118 #define IGD_GMCH_GEN6_GMS_MASK 0x1f
119 #define IGD_GMCH_GEN8_GMS_SHIFT 8 /* BDW_GMCH in i915 */
120 #define IGD_GMCH_GEN8_GMS_MASK 0xff
121
igd_stolen_memory_size(int gen,uint32_t gmch)122 static uint64_t igd_stolen_memory_size(int gen, uint32_t gmch)
123 {
124 uint64_t gms;
125
126 if (gen < 8) {
127 gms = (gmch >> IGD_GMCH_GEN6_GMS_SHIFT) & IGD_GMCH_GEN6_GMS_MASK;
128 } else {
129 gms = (gmch >> IGD_GMCH_GEN8_GMS_SHIFT) & IGD_GMCH_GEN8_GMS_MASK;
130 }
131
132 if (gen < 9) {
133 return gms * 32 * MiB;
134 } else {
135 if (gms < 0xf0) {
136 return gms * 32 * MiB;
137 } else {
138 return (gms - 0xf0 + 1) * 4 * MiB;
139 }
140 }
141
142 return 0;
143 }
144
145 /*
146 * The OpRegion includes the Video BIOS Table, which seems important for
147 * telling the driver what sort of outputs it has. Without this, the device
148 * may work in the guest, but we may not get output. This also requires BIOS
149 * support to reserve and populate a section of guest memory sufficient for
150 * the table and to write the base address of that memory to the ASLS register
151 * of the IGD device.
152 */
vfio_pci_igd_opregion_init(VFIOPCIDevice * vdev,struct vfio_region_info * info,Error ** errp)153 static bool vfio_pci_igd_opregion_init(VFIOPCIDevice *vdev,
154 struct vfio_region_info *info,
155 Error **errp)
156 {
157 int ret;
158
159 vdev->igd_opregion = g_malloc0(info->size);
160 ret = pread(vdev->vbasedev.fd, vdev->igd_opregion,
161 info->size, info->offset);
162 if (ret != info->size) {
163 error_setg(errp, "failed to read IGD OpRegion");
164 g_free(vdev->igd_opregion);
165 vdev->igd_opregion = NULL;
166 return false;
167 }
168
169 /*
170 * Provide fw_cfg with a copy of the OpRegion which the VM firmware is to
171 * allocate 32bit reserved memory for, copy these contents into, and write
172 * the reserved memory base address to the device ASLS register at 0xFC.
173 * Alignment of this reserved region seems flexible, but using a 4k page
174 * alignment seems to work well. This interface assumes a single IGD
175 * device, which may be at VM address 00:02.0 in legacy mode or another
176 * address in UPT mode.
177 *
178 * NB, there may be future use cases discovered where the VM should have
179 * direct interaction with the host OpRegion, in which case the write to
180 * the ASLS register would trigger MemoryRegion setup to enable that.
181 */
182 fw_cfg_add_file(fw_cfg_find(), "etc/igd-opregion",
183 vdev->igd_opregion, info->size);
184
185 trace_vfio_pci_igd_opregion_enabled(vdev->vbasedev.name);
186
187 return true;
188 }
189
vfio_pci_igd_opregion_detect(VFIOPCIDevice * vdev,struct vfio_region_info ** opregion)190 static bool vfio_pci_igd_opregion_detect(VFIOPCIDevice *vdev,
191 struct vfio_region_info **opregion)
192 {
193 int ret;
194
195 ret = vfio_device_get_region_info_type(&vdev->vbasedev,
196 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL,
197 VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION, opregion);
198 if (ret) {
199 return false;
200 }
201
202 /* Hotplugging is not supported for opregion access */
203 if (vdev->pdev.qdev.hotplugged) {
204 warn_report("IGD device detected, but OpRegion is not supported "
205 "on hotplugged device.");
206 return false;
207 }
208
209 return true;
210 }
211
212 /*
213 * The rather short list of registers that we copy from the host devices.
214 * The LPC/ISA bridge values are definitely needed to support the vBIOS, the
215 * host bridge values may or may not be needed depending on the guest OS.
216 * Since we're only munging revision and subsystem values on the host bridge,
217 * we don't require our own device. The LPC/ISA bridge needs to be our very
218 * own though.
219 */
220 typedef struct {
221 uint8_t offset;
222 uint8_t len;
223 } IGDHostInfo;
224
225 static const IGDHostInfo igd_host_bridge_infos[] = {
226 {PCI_REVISION_ID, 2},
227 {PCI_SUBSYSTEM_VENDOR_ID, 2},
228 {PCI_SUBSYSTEM_ID, 2},
229 };
230
231 static const IGDHostInfo igd_lpc_bridge_infos[] = {
232 {PCI_VENDOR_ID, 2},
233 {PCI_DEVICE_ID, 2},
234 {PCI_REVISION_ID, 2},
235 {PCI_SUBSYSTEM_VENDOR_ID, 2},
236 {PCI_SUBSYSTEM_ID, 2},
237 };
238
vfio_pci_igd_copy(VFIOPCIDevice * vdev,PCIDevice * pdev,struct vfio_region_info * info,const IGDHostInfo * list,int len)239 static int vfio_pci_igd_copy(VFIOPCIDevice *vdev, PCIDevice *pdev,
240 struct vfio_region_info *info,
241 const IGDHostInfo *list, int len)
242 {
243 int i, ret;
244
245 for (i = 0; i < len; i++) {
246 ret = pread(vdev->vbasedev.fd, pdev->config + list[i].offset,
247 list[i].len, info->offset + list[i].offset);
248 if (ret != list[i].len) {
249 error_report("IGD copy failed: %m");
250 return -errno;
251 }
252 }
253
254 return 0;
255 }
256
257 /*
258 * Stuff a few values into the host bridge.
259 */
vfio_pci_igd_host_init(VFIOPCIDevice * vdev,struct vfio_region_info * info)260 static int vfio_pci_igd_host_init(VFIOPCIDevice *vdev,
261 struct vfio_region_info *info)
262 {
263 PCIBus *bus;
264 PCIDevice *host_bridge;
265 int ret;
266
267 bus = pci_device_root_bus(&vdev->pdev);
268 host_bridge = pci_find_device(bus, 0, PCI_DEVFN(0, 0));
269
270 if (!host_bridge) {
271 error_report("Can't find host bridge");
272 return -ENODEV;
273 }
274
275 ret = vfio_pci_igd_copy(vdev, host_bridge, info, igd_host_bridge_infos,
276 ARRAY_SIZE(igd_host_bridge_infos));
277 if (!ret) {
278 trace_vfio_pci_igd_host_bridge_enabled(vdev->vbasedev.name);
279 }
280
281 return ret;
282 }
283
284 /*
285 * IGD LPC/ISA bridge support code. The vBIOS needs this, but we can't write
286 * arbitrary values into just any bridge, so we must create our own. We try
287 * to handle if the user has created it for us, which they might want to do
288 * to enable multifunction so we don't occupy the whole PCI slot.
289 */
vfio_pci_igd_lpc_bridge_realize(PCIDevice * pdev,Error ** errp)290 static void vfio_pci_igd_lpc_bridge_realize(PCIDevice *pdev, Error **errp)
291 {
292 if (pdev->devfn != PCI_DEVFN(0x1f, 0)) {
293 error_setg(errp, "VFIO dummy ISA/LPC bridge must have address 1f.0");
294 }
295 }
296
vfio_pci_igd_lpc_bridge_class_init(ObjectClass * klass,const void * data)297 static void vfio_pci_igd_lpc_bridge_class_init(ObjectClass *klass,
298 const void *data)
299 {
300 DeviceClass *dc = DEVICE_CLASS(klass);
301 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
302
303 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
304 dc->desc = "VFIO dummy ISA/LPC bridge for IGD assignment";
305 dc->hotpluggable = false;
306 k->realize = vfio_pci_igd_lpc_bridge_realize;
307 k->class_id = PCI_CLASS_BRIDGE_ISA;
308 }
309
310 static const TypeInfo vfio_pci_igd_lpc_bridge_info = {
311 .name = "vfio-pci-igd-lpc-bridge",
312 .parent = TYPE_PCI_DEVICE,
313 .class_init = vfio_pci_igd_lpc_bridge_class_init,
314 .interfaces = (const InterfaceInfo[]) {
315 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
316 { },
317 },
318 };
319
vfio_pci_igd_register_types(void)320 static void vfio_pci_igd_register_types(void)
321 {
322 type_register_static(&vfio_pci_igd_lpc_bridge_info);
323 }
324
type_init(vfio_pci_igd_register_types)325 type_init(vfio_pci_igd_register_types)
326
327 static int vfio_pci_igd_lpc_init(VFIOPCIDevice *vdev,
328 struct vfio_region_info *info)
329 {
330 PCIDevice *lpc_bridge;
331 int ret;
332
333 lpc_bridge = pci_find_device(pci_device_root_bus(&vdev->pdev),
334 0, PCI_DEVFN(0x1f, 0));
335 if (!lpc_bridge) {
336 lpc_bridge = pci_create_simple(pci_device_root_bus(&vdev->pdev),
337 PCI_DEVFN(0x1f, 0), "vfio-pci-igd-lpc-bridge");
338 }
339
340 ret = vfio_pci_igd_copy(vdev, lpc_bridge, info, igd_lpc_bridge_infos,
341 ARRAY_SIZE(igd_lpc_bridge_infos));
342 if (!ret) {
343 trace_vfio_pci_igd_lpc_bridge_enabled(vdev->vbasedev.name);
344 }
345
346 return ret;
347 }
348
vfio_pci_igd_setup_lpc_bridge(VFIOPCIDevice * vdev,Error ** errp)349 static bool vfio_pci_igd_setup_lpc_bridge(VFIOPCIDevice *vdev, Error **errp)
350 {
351 struct vfio_region_info *host = NULL;
352 struct vfio_region_info *lpc = NULL;
353 PCIDevice *lpc_bridge;
354 int ret;
355
356 /*
357 * Copying IDs or creating new devices are not supported on hotplug
358 */
359 if (vdev->pdev.qdev.hotplugged) {
360 error_setg(errp, "IGD LPC is not supported on hotplugged device");
361 return false;
362 }
363
364 /*
365 * We need to create an LPC/ISA bridge at PCI bus address 00:1f.0 that we
366 * can stuff host values into, so if there's already one there and it's not
367 * one we can hack on, this quirk is no-go. Sorry Q35.
368 */
369 lpc_bridge = pci_find_device(pci_device_root_bus(&vdev->pdev),
370 0, PCI_DEVFN(0x1f, 0));
371 if (lpc_bridge && !object_dynamic_cast(OBJECT(lpc_bridge),
372 "vfio-pci-igd-lpc-bridge")) {
373 error_setg(errp,
374 "Cannot create LPC bridge due to existing device at 1f.0");
375 return false;
376 }
377
378 /*
379 * Check whether we have all the vfio device specific regions to
380 * support LPC quirk (added in Linux v4.6).
381 */
382 ret = vfio_device_get_region_info_type(&vdev->vbasedev,
383 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL,
384 VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG, &lpc);
385 if (ret) {
386 error_setg(errp, "IGD LPC bridge access is not supported by kernel");
387 return false;
388 }
389
390 ret = vfio_device_get_region_info_type(&vdev->vbasedev,
391 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL,
392 VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG, &host);
393 if (ret) {
394 error_setg(errp, "IGD host bridge access is not supported by kernel");
395 return false;
396 }
397
398 /* Create/modify LPC bridge */
399 ret = vfio_pci_igd_lpc_init(vdev, lpc);
400 if (ret) {
401 error_setg(errp, "Failed to create/modify LPC bridge for IGD");
402 return false;
403 }
404
405 /* Stuff some host values into the VM PCI host bridge */
406 ret = vfio_pci_igd_host_init(vdev, host);
407 if (ret) {
408 error_setg(errp, "Failed to modify host bridge for IGD");
409 return false;
410 }
411
412 return true;
413 }
414
vfio_pci_igd_override_gms(int gen,uint32_t gms,uint32_t * gmch)415 static bool vfio_pci_igd_override_gms(int gen, uint32_t gms, uint32_t *gmch)
416 {
417 bool ret = false;
418
419 if (gen == -1) {
420 error_report("x-igd-gms is not supported on this device");
421 } else if (gen < 8) {
422 if (gms <= 0x10) {
423 *gmch &= ~(IGD_GMCH_GEN6_GMS_MASK << IGD_GMCH_GEN6_GMS_SHIFT);
424 *gmch |= gms << IGD_GMCH_GEN6_GMS_SHIFT;
425 ret = true;
426 } else {
427 error_report(QERR_INVALID_PARAMETER_VALUE, "x-igd-gms", "0~0x10");
428 }
429 } else if (gen == 8) {
430 if (gms <= 0x40) {
431 *gmch &= ~(IGD_GMCH_GEN8_GMS_MASK << IGD_GMCH_GEN8_GMS_SHIFT);
432 *gmch |= gms << IGD_GMCH_GEN8_GMS_SHIFT;
433 ret = true;
434 } else {
435 error_report(QERR_INVALID_PARAMETER_VALUE, "x-igd-gms", "0~0x40");
436 }
437 } else {
438 /* 0x0 to 0x40: 32MB increments starting at 0MB */
439 /* 0xf0 to 0xfe: 4MB increments starting at 4MB */
440 if ((gms <= 0x40) || (gms >= 0xf0 && gms <= 0xfe)) {
441 *gmch &= ~(IGD_GMCH_GEN8_GMS_MASK << IGD_GMCH_GEN8_GMS_SHIFT);
442 *gmch |= gms << IGD_GMCH_GEN8_GMS_SHIFT;
443 ret = true;
444 } else {
445 error_report(QERR_INVALID_PARAMETER_VALUE,
446 "x-igd-gms", "0~0x40 or 0xf0~0xfe");
447 }
448 }
449
450 return ret;
451 }
452
453 #define IGD_GGC_MMIO_OFFSET 0x108040
454 #define IGD_BDSM_MMIO_OFFSET 0x1080C0
455
vfio_probe_igd_bar0_quirk(VFIOPCIDevice * vdev,int nr)456 void vfio_probe_igd_bar0_quirk(VFIOPCIDevice *vdev, int nr)
457 {
458 VFIOQuirk *ggc_quirk, *bdsm_quirk;
459 VFIOConfigMirrorQuirk *ggc_mirror, *bdsm_mirror;
460 int gen;
461
462 if (!vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, PCI_ANY_ID) ||
463 !vfio_is_vga(vdev) || nr != 0) {
464 return;
465 }
466
467 /* Only on IGD Gen6-12 device needs quirks in BAR 0 */
468 gen = igd_gen(vdev);
469 if (gen < 6) {
470 return;
471 }
472
473 if (vdev->igd_gms) {
474 ggc_quirk = vfio_quirk_alloc(1);
475 ggc_mirror = ggc_quirk->data = g_malloc0(sizeof(*ggc_mirror));
476 ggc_mirror->mem = ggc_quirk->mem;
477 ggc_mirror->vdev = vdev;
478 ggc_mirror->bar = nr;
479 ggc_mirror->offset = IGD_GGC_MMIO_OFFSET;
480 ggc_mirror->config_offset = IGD_GMCH;
481
482 memory_region_init_io(ggc_mirror->mem, OBJECT(vdev),
483 &vfio_generic_mirror_quirk, ggc_mirror,
484 "vfio-igd-ggc-quirk", 2);
485 memory_region_add_subregion_overlap(vdev->bars[nr].region.mem,
486 ggc_mirror->offset, ggc_mirror->mem,
487 1);
488
489 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, ggc_quirk, next);
490 }
491
492 bdsm_quirk = vfio_quirk_alloc(1);
493 bdsm_mirror = bdsm_quirk->data = g_malloc0(sizeof(*bdsm_mirror));
494 bdsm_mirror->mem = bdsm_quirk->mem;
495 bdsm_mirror->vdev = vdev;
496 bdsm_mirror->bar = nr;
497 bdsm_mirror->offset = IGD_BDSM_MMIO_OFFSET;
498 bdsm_mirror->config_offset = (gen < 11) ? IGD_BDSM : IGD_BDSM_GEN11;
499
500 memory_region_init_io(bdsm_mirror->mem, OBJECT(vdev),
501 &vfio_generic_mirror_quirk, bdsm_mirror,
502 "vfio-igd-bdsm-quirk", (gen < 11) ? 4 : 8);
503 memory_region_add_subregion_overlap(vdev->bars[nr].region.mem,
504 bdsm_mirror->offset, bdsm_mirror->mem,
505 1);
506
507 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, bdsm_quirk, next);
508 }
509
vfio_pci_igd_config_quirk(VFIOPCIDevice * vdev,Error ** errp)510 static bool vfio_pci_igd_config_quirk(VFIOPCIDevice *vdev, Error **errp)
511 {
512 struct vfio_region_info *opregion = NULL;
513 int ret, gen;
514 uint64_t gms_size = 0;
515 uint64_t *bdsm_size;
516 uint32_t gmch;
517 bool legacy_mode_enabled = false;
518 Error *err = NULL;
519
520 if (!vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, PCI_ANY_ID) ||
521 !vfio_is_vga(vdev)) {
522 return true;
523 }
524
525 /* IGD device always comes with OpRegion */
526 if (!vfio_pci_igd_opregion_detect(vdev, &opregion)) {
527 return true;
528 }
529 info_report("OpRegion detected on Intel display %x.", vdev->device_id);
530
531 gen = igd_gen(vdev);
532 gmch = vfio_pci_read_config(&vdev->pdev, IGD_GMCH, 4);
533
534 /*
535 * For backward compatibility, enable legacy mode when
536 * - Device geneation is 6 to 9 (including both)
537 * - IGD claims VGA cycles on host
538 * - Machine type is i440fx (pc_piix)
539 * - IGD device is at guest BDF 00:02.0
540 * - Not manually disabled by x-igd-legacy-mode=off
541 */
542 if ((vdev->igd_legacy_mode != ON_OFF_AUTO_OFF) &&
543 (gen >= 6 && gen <= 9) &&
544 !(gmch & IGD_GMCH_VGA_DISABLE) &&
545 !strcmp(MACHINE_GET_CLASS(qdev_get_machine())->family, "pc_piix") &&
546 (&vdev->pdev == pci_find_device(pci_device_root_bus(&vdev->pdev),
547 0, PCI_DEVFN(0x2, 0)))) {
548 /*
549 * IGD legacy mode requires:
550 * - VBIOS in ROM BAR or file
551 * - VGA IO/MMIO ranges are claimed by IGD
552 * - OpRegion
553 * - Same LPC bridge and Host bridge VID/DID/SVID/SSID as host
554 */
555 struct vfio_region_info *rom = NULL;
556
557 legacy_mode_enabled = true;
558 info_report("IGD legacy mode enabled, "
559 "use x-igd-legacy-mode=off to disable it if unwanted.");
560
561 /*
562 * Most of what we're doing here is to enable the ROM to run, so if
563 * there's no ROM, there's no point in setting up this quirk.
564 * NB. We only seem to get BIOS ROMs, so UEFI VM would need CSM support.
565 */
566 ret = vfio_device_get_region_info(&vdev->vbasedev,
567 VFIO_PCI_ROM_REGION_INDEX, &rom);
568 if ((ret || !rom->size) && !vdev->pdev.romfile) {
569 error_setg(&err, "Device has no ROM");
570 goto error;
571 }
572
573 /*
574 * If VGA is not already enabled, try to enable it. We shouldn't be
575 * using legacy mode without VGA.
576 */
577 if (!vdev->vga) {
578 if (vfio_populate_vga(vdev, &err)) {
579 vfio_pci_config_register_vga(vdev);
580 } else {
581 error_setg(&err, "Unable to enable VGA access");
582 goto error;
583 }
584 }
585
586 /* Enable OpRegion and LPC bridge quirk */
587 vdev->features |= VFIO_FEATURE_ENABLE_IGD_OPREGION;
588 vdev->features |= VFIO_FEATURE_ENABLE_IGD_LPC;
589 } else if (vdev->igd_legacy_mode == ON_OFF_AUTO_ON) {
590 error_setg(&err,
591 "Machine is not i440fx, assigned BDF is not 00:02.0, "
592 "or device %04x (gen %d) doesn't support legacy mode",
593 vdev->device_id, gen);
594 goto error;
595 }
596
597 /* Setup OpRegion access */
598 if ((vdev->features & VFIO_FEATURE_ENABLE_IGD_OPREGION) &&
599 !vfio_pci_igd_opregion_init(vdev, opregion, errp)) {
600 goto error;
601 }
602
603 /* Setup LPC bridge / Host bridge PCI IDs */
604 if ((vdev->features & VFIO_FEATURE_ENABLE_IGD_LPC) &&
605 !vfio_pci_igd_setup_lpc_bridge(vdev, errp)) {
606 goto error;
607 }
608
609 /*
610 * ASLS (OpRegion address) is read-only, emulated
611 * It contains HPA, guest firmware need to reprogram it with GPA.
612 */
613 pci_set_long(vdev->pdev.config + IGD_ASLS, 0);
614 pci_set_long(vdev->pdev.wmask + IGD_ASLS, ~0);
615 pci_set_long(vdev->emulated_config_bits + IGD_ASLS, ~0);
616
617 /*
618 * Allow user to override dsm size using x-igd-gms option, in multiples of
619 * 32MiB. This option should only be used when the desired size cannot be
620 * set from DVMT Pre-Allocated option in host BIOS.
621 */
622 if (vdev->igd_gms) {
623 if (!vfio_pci_igd_override_gms(gen, vdev->igd_gms, &gmch)) {
624 return false;
625 }
626
627 /* GMCH is read-only, emulated */
628 pci_set_long(vdev->pdev.config + IGD_GMCH, gmch);
629 pci_set_long(vdev->pdev.wmask + IGD_GMCH, 0);
630 pci_set_long(vdev->emulated_config_bits + IGD_GMCH, ~0);
631 }
632
633 if (gen > 0) {
634 gms_size = igd_stolen_memory_size(gen, gmch);
635
636 /* BDSM is read-write, emulated. BIOS needs to be able to write it */
637 if (gen < 11) {
638 pci_set_long(vdev->pdev.config + IGD_BDSM, 0);
639 pci_set_long(vdev->pdev.wmask + IGD_BDSM, ~0);
640 pci_set_long(vdev->emulated_config_bits + IGD_BDSM, ~0);
641 } else {
642 pci_set_quad(vdev->pdev.config + IGD_BDSM_GEN11, 0);
643 pci_set_quad(vdev->pdev.wmask + IGD_BDSM_GEN11, ~0);
644 pci_set_quad(vdev->emulated_config_bits + IGD_BDSM_GEN11, ~0);
645 }
646 }
647
648 /*
649 * Request reserved memory for stolen memory via fw_cfg. VM firmware
650 * must allocate a 1MB aligned reserved memory region below 4GB with
651 * the requested size (in bytes) for use by the IGD device. The base
652 * address of this reserved memory region must be written to the
653 * device BDSM register.
654 * For newer device without BDSM register, this fw_cfg item is 0.
655 */
656 bdsm_size = g_malloc(sizeof(*bdsm_size));
657 *bdsm_size = cpu_to_le64(gms_size);
658 fw_cfg_add_file(fw_cfg_find(), "etc/igd-bdsm-size",
659 bdsm_size, sizeof(*bdsm_size));
660
661 trace_vfio_pci_igd_bdsm_enabled(vdev->vbasedev.name, (gms_size / MiB));
662
663 return true;
664
665 error:
666 /*
667 * When legacy mode is implicity enabled, continue on error,
668 * to keep compatibility
669 */
670 if (legacy_mode_enabled && (vdev->igd_legacy_mode == ON_OFF_AUTO_AUTO)) {
671 error_report_err(err);
672 error_report("IGD legacy mode disabled");
673 return true;
674 }
675
676 error_propagate(errp, err);
677 return false;
678 }
679
680 /*
681 * KVMGT/GVT-g vGPU exposes an emulated OpRegion. So far, users have to specify
682 * x-igd-opregion=on to enable the access.
683 * TODO: Check VID/DID and enable opregion access automatically
684 */
vfio_pci_kvmgt_config_quirk(VFIOPCIDevice * vdev,Error ** errp)685 static bool vfio_pci_kvmgt_config_quirk(VFIOPCIDevice *vdev, Error **errp)
686 {
687 struct vfio_region_info *opregion = NULL;
688 int gen;
689
690 if (!vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, PCI_ANY_ID) ||
691 !vfio_is_vga(vdev)) {
692 return true;
693 }
694
695 /* FIXME: Cherryview is Gen8, but don't support GVT-g */
696 gen = igd_gen(vdev);
697 if (gen != 8 && gen != 9) {
698 return true;
699 }
700
701 if (!vfio_pci_igd_opregion_detect(vdev, &opregion)) {
702 /* Should never reach here, KVMGT always emulates OpRegion */
703 return false;
704 }
705
706 if ((vdev->features & VFIO_FEATURE_ENABLE_IGD_OPREGION) &&
707 !vfio_pci_igd_opregion_init(vdev, opregion, errp)) {
708 return false;
709 }
710
711 return true;
712 }
713
vfio_probe_igd_config_quirk(VFIOPCIDevice * vdev,Error ** errp)714 bool vfio_probe_igd_config_quirk(VFIOPCIDevice *vdev, Error **errp)
715 {
716 /* KVMGT/GVT-g vGPU is exposed as mdev */
717 if (vdev->vbasedev.mdev) {
718 return vfio_pci_kvmgt_config_quirk(vdev, errp);
719 }
720
721 return vfio_pci_igd_config_quirk(vdev, errp);
722 }
723