1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012-2015 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7 #ifndef __ARM64_KVM_HYP_SYSREG_SR_H__
8 #define __ARM64_KVM_HYP_SYSREG_SR_H__
9
10 #include <linux/compiler.h>
11 #include <linux/kvm_host.h>
12
13 #include <asm/kprobes.h>
14 #include <asm/kvm_asm.h>
15 #include <asm/kvm_emulate.h>
16 #include <asm/kvm_hyp.h>
17 #include <asm/kvm_mmu.h>
18
__sysreg_save_common_state(struct kvm_cpu_context * ctxt)19 static inline void __sysreg_save_common_state(struct kvm_cpu_context *ctxt)
20 {
21 ctxt_sys_reg(ctxt, MDSCR_EL1) = read_sysreg(mdscr_el1);
22 }
23
__sysreg_save_user_state(struct kvm_cpu_context * ctxt)24 static inline void __sysreg_save_user_state(struct kvm_cpu_context *ctxt)
25 {
26 ctxt_sys_reg(ctxt, TPIDR_EL0) = read_sysreg(tpidr_el0);
27 ctxt_sys_reg(ctxt, TPIDRRO_EL0) = read_sysreg(tpidrro_el0);
28 }
29
ctxt_has_mte(struct kvm_cpu_context * ctxt)30 static inline bool ctxt_has_mte(struct kvm_cpu_context *ctxt)
31 {
32 struct kvm_vcpu *vcpu = ctxt->__hyp_running_vcpu;
33
34 if (!vcpu)
35 vcpu = container_of(ctxt, struct kvm_vcpu, arch.ctxt);
36
37 return kvm_has_mte(kern_hyp_va(vcpu->kvm));
38 }
39
__sysreg_save_el1_state(struct kvm_cpu_context * ctxt)40 static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt)
41 {
42 ctxt_sys_reg(ctxt, SCTLR_EL1) = read_sysreg_el1(SYS_SCTLR);
43 ctxt_sys_reg(ctxt, CPACR_EL1) = read_sysreg_el1(SYS_CPACR);
44 ctxt_sys_reg(ctxt, TTBR0_EL1) = read_sysreg_el1(SYS_TTBR0);
45 ctxt_sys_reg(ctxt, TTBR1_EL1) = read_sysreg_el1(SYS_TTBR1);
46 ctxt_sys_reg(ctxt, TCR_EL1) = read_sysreg_el1(SYS_TCR);
47 if (cpus_have_final_cap(ARM64_HAS_TCR2))
48 ctxt_sys_reg(ctxt, TCR2_EL1) = read_sysreg_el1(SYS_TCR2);
49 ctxt_sys_reg(ctxt, ESR_EL1) = read_sysreg_el1(SYS_ESR);
50 ctxt_sys_reg(ctxt, AFSR0_EL1) = read_sysreg_el1(SYS_AFSR0);
51 ctxt_sys_reg(ctxt, AFSR1_EL1) = read_sysreg_el1(SYS_AFSR1);
52 ctxt_sys_reg(ctxt, FAR_EL1) = read_sysreg_el1(SYS_FAR);
53 ctxt_sys_reg(ctxt, MAIR_EL1) = read_sysreg_el1(SYS_MAIR);
54 ctxt_sys_reg(ctxt, VBAR_EL1) = read_sysreg_el1(SYS_VBAR);
55 ctxt_sys_reg(ctxt, CONTEXTIDR_EL1) = read_sysreg_el1(SYS_CONTEXTIDR);
56 ctxt_sys_reg(ctxt, AMAIR_EL1) = read_sysreg_el1(SYS_AMAIR);
57 ctxt_sys_reg(ctxt, CNTKCTL_EL1) = read_sysreg_el1(SYS_CNTKCTL);
58 if (cpus_have_final_cap(ARM64_HAS_S1PIE)) {
59 ctxt_sys_reg(ctxt, PIR_EL1) = read_sysreg_el1(SYS_PIR);
60 ctxt_sys_reg(ctxt, PIRE0_EL1) = read_sysreg_el1(SYS_PIRE0);
61 }
62 ctxt_sys_reg(ctxt, PAR_EL1) = read_sysreg_par();
63 ctxt_sys_reg(ctxt, TPIDR_EL1) = read_sysreg(tpidr_el1);
64
65 if (ctxt_has_mte(ctxt)) {
66 ctxt_sys_reg(ctxt, TFSR_EL1) = read_sysreg_el1(SYS_TFSR);
67 ctxt_sys_reg(ctxt, TFSRE0_EL1) = read_sysreg_s(SYS_TFSRE0_EL1);
68 }
69
70 ctxt_sys_reg(ctxt, SP_EL1) = read_sysreg(sp_el1);
71 ctxt_sys_reg(ctxt, ELR_EL1) = read_sysreg_el1(SYS_ELR);
72 ctxt_sys_reg(ctxt, SPSR_EL1) = read_sysreg_el1(SYS_SPSR);
73 }
74
__sysreg_save_el2_return_state(struct kvm_cpu_context * ctxt)75 static inline void __sysreg_save_el2_return_state(struct kvm_cpu_context *ctxt)
76 {
77 ctxt->regs.pc = read_sysreg_el2(SYS_ELR);
78 /*
79 * Guest PSTATE gets saved at guest fixup time in all
80 * cases. We still need to handle the nVHE host side here.
81 */
82 if (!has_vhe() && ctxt->__hyp_running_vcpu)
83 ctxt->regs.pstate = read_sysreg_el2(SYS_SPSR);
84
85 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN))
86 ctxt_sys_reg(ctxt, DISR_EL1) = read_sysreg_s(SYS_VDISR_EL2);
87 }
88
__sysreg_restore_common_state(struct kvm_cpu_context * ctxt)89 static inline void __sysreg_restore_common_state(struct kvm_cpu_context *ctxt)
90 {
91 write_sysreg(ctxt_sys_reg(ctxt, MDSCR_EL1), mdscr_el1);
92 }
93
__sysreg_restore_user_state(struct kvm_cpu_context * ctxt)94 static inline void __sysreg_restore_user_state(struct kvm_cpu_context *ctxt)
95 {
96 write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL0), tpidr_el0);
97 write_sysreg(ctxt_sys_reg(ctxt, TPIDRRO_EL0), tpidrro_el0);
98 }
99
__sysreg_restore_el1_state(struct kvm_cpu_context * ctxt)100 static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt)
101 {
102 write_sysreg(ctxt_sys_reg(ctxt, MPIDR_EL1), vmpidr_el2);
103
104 if (has_vhe() ||
105 !cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) {
106 write_sysreg_el1(ctxt_sys_reg(ctxt, SCTLR_EL1), SYS_SCTLR);
107 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR);
108 } else if (!ctxt->__hyp_running_vcpu) {
109 /*
110 * Must only be done for guest registers, hence the context
111 * test. We're coming from the host, so SCTLR.M is already
112 * set. Pairs with nVHE's __activate_traps().
113 */
114 write_sysreg_el1((ctxt_sys_reg(ctxt, TCR_EL1) |
115 TCR_EPD1_MASK | TCR_EPD0_MASK),
116 SYS_TCR);
117 isb();
118 }
119
120 write_sysreg_el1(ctxt_sys_reg(ctxt, CPACR_EL1), SYS_CPACR);
121 write_sysreg_el1(ctxt_sys_reg(ctxt, TTBR0_EL1), SYS_TTBR0);
122 write_sysreg_el1(ctxt_sys_reg(ctxt, TTBR1_EL1), SYS_TTBR1);
123 if (cpus_have_final_cap(ARM64_HAS_TCR2))
124 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR2_EL1), SYS_TCR2);
125 write_sysreg_el1(ctxt_sys_reg(ctxt, ESR_EL1), SYS_ESR);
126 write_sysreg_el1(ctxt_sys_reg(ctxt, AFSR0_EL1), SYS_AFSR0);
127 write_sysreg_el1(ctxt_sys_reg(ctxt, AFSR1_EL1), SYS_AFSR1);
128 write_sysreg_el1(ctxt_sys_reg(ctxt, FAR_EL1), SYS_FAR);
129 write_sysreg_el1(ctxt_sys_reg(ctxt, MAIR_EL1), SYS_MAIR);
130 write_sysreg_el1(ctxt_sys_reg(ctxt, VBAR_EL1), SYS_VBAR);
131 write_sysreg_el1(ctxt_sys_reg(ctxt, CONTEXTIDR_EL1), SYS_CONTEXTIDR);
132 write_sysreg_el1(ctxt_sys_reg(ctxt, AMAIR_EL1), SYS_AMAIR);
133 write_sysreg_el1(ctxt_sys_reg(ctxt, CNTKCTL_EL1), SYS_CNTKCTL);
134 if (cpus_have_final_cap(ARM64_HAS_S1PIE)) {
135 write_sysreg_el1(ctxt_sys_reg(ctxt, PIR_EL1), SYS_PIR);
136 write_sysreg_el1(ctxt_sys_reg(ctxt, PIRE0_EL1), SYS_PIRE0);
137 }
138 write_sysreg(ctxt_sys_reg(ctxt, PAR_EL1), par_el1);
139 write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL1), tpidr_el1);
140
141 if (ctxt_has_mte(ctxt)) {
142 write_sysreg_el1(ctxt_sys_reg(ctxt, TFSR_EL1), SYS_TFSR);
143 write_sysreg_s(ctxt_sys_reg(ctxt, TFSRE0_EL1), SYS_TFSRE0_EL1);
144 }
145
146 if (!has_vhe() &&
147 cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT) &&
148 ctxt->__hyp_running_vcpu) {
149 /*
150 * Must only be done for host registers, hence the context
151 * test. Pairs with nVHE's __deactivate_traps().
152 */
153 isb();
154 /*
155 * At this stage, and thanks to the above isb(), S2 is
156 * deconfigured and disabled. We can now restore the host's
157 * S1 configuration: SCTLR, and only then TCR.
158 */
159 write_sysreg_el1(ctxt_sys_reg(ctxt, SCTLR_EL1), SYS_SCTLR);
160 isb();
161 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR);
162 }
163
164 write_sysreg(ctxt_sys_reg(ctxt, SP_EL1), sp_el1);
165 write_sysreg_el1(ctxt_sys_reg(ctxt, ELR_EL1), SYS_ELR);
166 write_sysreg_el1(ctxt_sys_reg(ctxt, SPSR_EL1), SYS_SPSR);
167 }
168
169 /* Read the VCPU state's PSTATE, but translate (v)EL2 to EL1. */
to_hw_pstate(const struct kvm_cpu_context * ctxt)170 static inline u64 to_hw_pstate(const struct kvm_cpu_context *ctxt)
171 {
172 u64 mode = ctxt->regs.pstate & (PSR_MODE_MASK | PSR_MODE32_BIT);
173
174 switch (mode) {
175 case PSR_MODE_EL2t:
176 mode = PSR_MODE_EL1t;
177 break;
178 case PSR_MODE_EL2h:
179 mode = PSR_MODE_EL1h;
180 break;
181 }
182
183 return (ctxt->regs.pstate & ~(PSR_MODE_MASK | PSR_MODE32_BIT)) | mode;
184 }
185
__sysreg_restore_el2_return_state(struct kvm_cpu_context * ctxt)186 static inline void __sysreg_restore_el2_return_state(struct kvm_cpu_context *ctxt)
187 {
188 u64 pstate = to_hw_pstate(ctxt);
189 u64 mode = pstate & PSR_AA32_MODE_MASK;
190
191 /*
192 * Safety check to ensure we're setting the CPU up to enter the guest
193 * in a less privileged mode.
194 *
195 * If we are attempting a return to EL2 or higher in AArch64 state,
196 * program SPSR_EL2 with M=EL2h and the IL bit set which ensures that
197 * we'll take an illegal exception state exception immediately after
198 * the ERET to the guest. Attempts to return to AArch32 Hyp will
199 * result in an illegal exception return because EL2's execution state
200 * is determined by SCR_EL3.RW.
201 */
202 if (!(mode & PSR_MODE32_BIT) && mode >= PSR_MODE_EL2t)
203 pstate = PSR_MODE_EL2h | PSR_IL_BIT;
204
205 write_sysreg_el2(ctxt->regs.pc, SYS_ELR);
206 write_sysreg_el2(pstate, SYS_SPSR);
207
208 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN))
209 write_sysreg_s(ctxt_sys_reg(ctxt, DISR_EL1), SYS_VDISR_EL2);
210 }
211
__sysreg32_save_state(struct kvm_vcpu * vcpu)212 static inline void __sysreg32_save_state(struct kvm_vcpu *vcpu)
213 {
214 if (!vcpu_el1_is_32bit(vcpu))
215 return;
216
217 vcpu->arch.ctxt.spsr_abt = read_sysreg(spsr_abt);
218 vcpu->arch.ctxt.spsr_und = read_sysreg(spsr_und);
219 vcpu->arch.ctxt.spsr_irq = read_sysreg(spsr_irq);
220 vcpu->arch.ctxt.spsr_fiq = read_sysreg(spsr_fiq);
221
222 __vcpu_sys_reg(vcpu, DACR32_EL2) = read_sysreg(dacr32_el2);
223 __vcpu_sys_reg(vcpu, IFSR32_EL2) = read_sysreg(ifsr32_el2);
224
225 if (has_vhe() || vcpu_get_flag(vcpu, DEBUG_DIRTY))
226 __vcpu_sys_reg(vcpu, DBGVCR32_EL2) = read_sysreg(dbgvcr32_el2);
227 }
228
__sysreg32_restore_state(struct kvm_vcpu * vcpu)229 static inline void __sysreg32_restore_state(struct kvm_vcpu *vcpu)
230 {
231 if (!vcpu_el1_is_32bit(vcpu))
232 return;
233
234 write_sysreg(vcpu->arch.ctxt.spsr_abt, spsr_abt);
235 write_sysreg(vcpu->arch.ctxt.spsr_und, spsr_und);
236 write_sysreg(vcpu->arch.ctxt.spsr_irq, spsr_irq);
237 write_sysreg(vcpu->arch.ctxt.spsr_fiq, spsr_fiq);
238
239 write_sysreg(__vcpu_sys_reg(vcpu, DACR32_EL2), dacr32_el2);
240 write_sysreg(__vcpu_sys_reg(vcpu, IFSR32_EL2), ifsr32_el2);
241
242 if (has_vhe() || vcpu_get_flag(vcpu, DEBUG_DIRTY))
243 write_sysreg(__vcpu_sys_reg(vcpu, DBGVCR32_EL2), dbgvcr32_el2);
244 }
245
246 #endif /* __ARM64_KVM_HYP_SYSREG_SR_H__ */
247