1 /*
2 * QEMU Sun4u/Sun4v System Emulator
3 *
4 * Copyright (c) 2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qemu/error-report.h"
28 #include "qapi/error.h"
29 #include "qemu/datadir.h"
30 #include "cpu.h"
31 #include "hw/irq.h"
32 #include "hw/pci/pci.h"
33 #include "hw/pci/pci_bridge.h"
34 #include "hw/pci/pci_host.h"
35 #include "hw/qdev-properties.h"
36 #include "hw/pci-host/sabre.h"
37 #include "hw/char/serial.h"
38 #include "hw/char/parallel-isa.h"
39 #include "hw/rtc/m48t59.h"
40 #include "migration/vmstate.h"
41 #include "hw/input/i8042.h"
42 #include "hw/block/fdc.h"
43 #include "net/net.h"
44 #include "qemu/timer.h"
45 #include "sysemu/runstate.h"
46 #include "sysemu/sysemu.h"
47 #include "hw/boards.h"
48 #include "hw/nvram/sun_nvram.h"
49 #include "hw/nvram/chrp_nvram.h"
50 #include "hw/sparc/sparc64.h"
51 #include "hw/nvram/fw_cfg.h"
52 #include "hw/sysbus.h"
53 #include "hw/ide/pci.h"
54 #include "hw/loader.h"
55 #include "hw/fw-path-provider.h"
56 #include "elf.h"
57 #include "trace.h"
58 #include "qom/object.h"
59
60 #define KERNEL_LOAD_ADDR 0x00404000
61 #define CMDLINE_ADDR 0x003ff000
62 #define PROM_SIZE_MAX (4 * MiB)
63 #define PROM_VADDR 0x000ffd00000ULL
64 #define PBM_SPECIAL_BASE 0x1fe00000000ULL
65 #define PBM_MEM_BASE 0x1ff00000000ULL
66 #define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL)
67 #define PROM_FILENAME "openbios-sparc64"
68 #define NVRAM_SIZE 0x2000
69 #define BIOS_CFG_IOPORT 0x510
70 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
71 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
72 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
73
74 #define IVEC_MAX 0x40
75
76 struct hwdef {
77 uint16_t machine_id;
78 uint64_t prom_addr;
79 uint64_t console_serial_base;
80 };
81
82 struct EbusState {
83 /*< private >*/
84 PCIDevice parent_obj;
85
86 ISABus *isa_bus;
87 qemu_irq *isa_irqs_in;
88 qemu_irq isa_irqs_out[ISA_NUM_IRQS];
89 uint64_t console_serial_base;
90 MemoryRegion bar0;
91 MemoryRegion bar1;
92 };
93
94 #define TYPE_EBUS "ebus"
OBJECT_DECLARE_SIMPLE_TYPE(EbusState,EBUS)95 OBJECT_DECLARE_SIMPLE_TYPE(EbusState, EBUS)
96
97 const char *fw_cfg_arch_key_name(uint16_t key)
98 {
99 static const struct {
100 uint16_t key;
101 const char *name;
102 } fw_cfg_arch_wellknown_keys[] = {
103 {FW_CFG_SPARC64_WIDTH, "width"},
104 {FW_CFG_SPARC64_HEIGHT, "height"},
105 {FW_CFG_SPARC64_DEPTH, "depth"},
106 };
107
108 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
109 if (fw_cfg_arch_wellknown_keys[i].key == key) {
110 return fw_cfg_arch_wellknown_keys[i].name;
111 }
112 }
113 return NULL;
114 }
115
fw_cfg_boot_set(void * opaque,const char * boot_device,Error ** errp)116 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
117 Error **errp)
118 {
119 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
120 }
121
sun4u_NVRAM_set_params(Nvram * nvram,uint16_t NVRAM_size,const char * arch,ram_addr_t RAM_size,const char * boot_devices,uint32_t kernel_image,uint32_t kernel_size,const char * cmdline,uint32_t initrd_image,uint32_t initrd_size,uint32_t NVRAM_image,int width,int height,int depth,const uint8_t * macaddr)122 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size,
123 const char *arch, ram_addr_t RAM_size,
124 const char *boot_devices,
125 uint32_t kernel_image, uint32_t kernel_size,
126 const char *cmdline,
127 uint32_t initrd_image, uint32_t initrd_size,
128 uint32_t NVRAM_image,
129 int width, int height, int depth,
130 const uint8_t *macaddr)
131 {
132 unsigned int i;
133 int sysp_end;
134 uint8_t image[0x1ff0];
135 NvramClass *k = NVRAM_GET_CLASS(nvram);
136
137 memset(image, '\0', sizeof(image));
138
139 /* OpenBIOS nvram variables partition */
140 sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0);
141
142 /* Free space partition */
143 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
144
145 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
146
147 for (i = 0; i < sizeof(image); i++) {
148 (k->write)(nvram, i, image[i]);
149 }
150
151 return 0;
152 }
153
sun4u_load_kernel(const char * kernel_filename,const char * initrd_filename,ram_addr_t RAM_size,uint64_t * initrd_size,uint64_t * initrd_addr,uint64_t * kernel_addr,uint64_t * kernel_entry)154 static uint64_t sun4u_load_kernel(const char *kernel_filename,
155 const char *initrd_filename,
156 ram_addr_t RAM_size, uint64_t *initrd_size,
157 uint64_t *initrd_addr, uint64_t *kernel_addr,
158 uint64_t *kernel_entry)
159 {
160 int linux_boot;
161 unsigned int i;
162 long kernel_size;
163 uint8_t *ptr;
164 uint64_t kernel_top = 0;
165
166 linux_boot = (kernel_filename != NULL);
167
168 kernel_size = 0;
169 if (linux_boot) {
170 int bswap_needed;
171
172 #ifdef BSWAP_NEEDED
173 bswap_needed = 1;
174 #else
175 bswap_needed = 0;
176 #endif
177 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, kernel_entry,
178 kernel_addr, &kernel_top, NULL, 1, EM_SPARCV9, 0,
179 0);
180 if (kernel_size < 0) {
181 *kernel_addr = KERNEL_LOAD_ADDR;
182 *kernel_entry = KERNEL_LOAD_ADDR;
183 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
184 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
185 TARGET_PAGE_SIZE);
186 }
187 if (kernel_size < 0) {
188 kernel_size = load_image_targphys(kernel_filename,
189 KERNEL_LOAD_ADDR,
190 RAM_size - KERNEL_LOAD_ADDR);
191 }
192 if (kernel_size < 0) {
193 error_report("could not load kernel '%s'", kernel_filename);
194 exit(1);
195 }
196 /* load initrd above kernel */
197 *initrd_size = 0;
198 if (initrd_filename && kernel_top) {
199 *initrd_addr = TARGET_PAGE_ALIGN(kernel_top);
200
201 *initrd_size = load_image_targphys(initrd_filename,
202 *initrd_addr,
203 RAM_size - *initrd_addr);
204 if ((int)*initrd_size < 0) {
205 error_report("could not load initial ram disk '%s'",
206 initrd_filename);
207 exit(1);
208 }
209 }
210 if (*initrd_size > 0) {
211 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
212 ptr = rom_ptr(*kernel_addr + i, 32);
213 if (ptr && ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
214 stl_p(ptr + 24, *initrd_addr + *kernel_addr);
215 stl_p(ptr + 28, *initrd_size);
216 break;
217 }
218 }
219 }
220 }
221 return kernel_size;
222 }
223
224 typedef struct ResetData {
225 SPARCCPU *cpu;
226 uint64_t prom_addr;
227 } ResetData;
228
229 #define TYPE_SUN4U_POWER "power"
230 OBJECT_DECLARE_SIMPLE_TYPE(PowerDevice, SUN4U_POWER)
231
232 struct PowerDevice {
233 SysBusDevice parent_obj;
234
235 MemoryRegion power_mmio;
236 };
237
238 /* Power */
power_mem_read(void * opaque,hwaddr addr,unsigned size)239 static uint64_t power_mem_read(void *opaque, hwaddr addr, unsigned size)
240 {
241 return 0;
242 }
243
power_mem_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)244 static void power_mem_write(void *opaque, hwaddr addr,
245 uint64_t val, unsigned size)
246 {
247 /* According to a real Ultra 5, bit 24 controls the power */
248 if (val & 0x1000000) {
249 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
250 }
251 }
252
253 static const MemoryRegionOps power_mem_ops = {
254 .read = power_mem_read,
255 .write = power_mem_write,
256 .endianness = DEVICE_NATIVE_ENDIAN,
257 .valid = {
258 .min_access_size = 4,
259 .max_access_size = 4,
260 },
261 };
262
power_realize(DeviceState * dev,Error ** errp)263 static void power_realize(DeviceState *dev, Error **errp)
264 {
265 PowerDevice *d = SUN4U_POWER(dev);
266 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
267
268 memory_region_init_io(&d->power_mmio, OBJECT(dev), &power_mem_ops, d,
269 "power", sizeof(uint32_t));
270
271 sysbus_init_mmio(sbd, &d->power_mmio);
272 }
273
power_class_init(ObjectClass * klass,void * data)274 static void power_class_init(ObjectClass *klass, void *data)
275 {
276 DeviceClass *dc = DEVICE_CLASS(klass);
277
278 dc->realize = power_realize;
279 }
280
281 static const TypeInfo power_info = {
282 .name = TYPE_SUN4U_POWER,
283 .parent = TYPE_SYS_BUS_DEVICE,
284 .instance_size = sizeof(PowerDevice),
285 .class_init = power_class_init,
286 };
287
ebus_isa_irq_handler(void * opaque,int n,int level)288 static void ebus_isa_irq_handler(void *opaque, int n, int level)
289 {
290 EbusState *s = EBUS(opaque);
291 qemu_irq irq = s->isa_irqs_out[n];
292
293 /* Pass ISA bus IRQs onto their gpio equivalent */
294 trace_ebus_isa_irq_handler(n, level);
295 if (irq) {
296 qemu_set_irq(irq, level);
297 }
298 }
299
300 /* EBUS (Eight bit bus) bridge */
ebus_realize(PCIDevice * pci_dev,Error ** errp)301 static void ebus_realize(PCIDevice *pci_dev, Error **errp)
302 {
303 EbusState *s = EBUS(pci_dev);
304 ISADevice *isa_dev;
305 SysBusDevice *sbd;
306 DeviceState *dev;
307 DriveInfo *fd[MAX_FD];
308 int i;
309
310 s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(),
311 pci_address_space_io(pci_dev), errp);
312 if (!s->isa_bus) {
313 error_setg(errp, "unable to instantiate EBUS ISA bus");
314 return;
315 }
316
317 /* ISA bus */
318 s->isa_irqs_in = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS);
319 isa_bus_register_input_irqs(s->isa_bus, s->isa_irqs_in);
320 qdev_init_gpio_out_named(DEVICE(s), s->isa_irqs_out, "isa-irq",
321 ISA_NUM_IRQS);
322
323 /* Serial ports */
324 i = 0;
325 if (s->console_serial_base) {
326 serial_mm_init(pci_address_space(pci_dev), s->console_serial_base,
327 0, NULL, 115200, serial_hd(i), DEVICE_BIG_ENDIAN);
328 i++;
329 }
330 serial_hds_isa_init(s->isa_bus, i, MAX_ISA_SERIAL_PORTS);
331
332 /* Parallel ports */
333 parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS);
334
335 /* Keyboard */
336 isa_create_simple(s->isa_bus, TYPE_I8042);
337
338 /* Floppy */
339 for (i = 0; i < MAX_FD; i++) {
340 fd[i] = drive_get(IF_FLOPPY, 0, i);
341 }
342 isa_dev = isa_new(TYPE_ISA_FDC);
343 dev = DEVICE(isa_dev);
344 qdev_prop_set_uint32(dev, "dma", -1);
345 isa_realize_and_unref(isa_dev, s->isa_bus, &error_fatal);
346 isa_fdc_init_drives(isa_dev, fd);
347
348 /* Power */
349 dev = qdev_new(TYPE_SUN4U_POWER);
350 sbd = SYS_BUS_DEVICE(dev);
351 sysbus_realize_and_unref(sbd, &error_fatal);
352 memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240,
353 sysbus_mmio_get_region(sbd, 0));
354
355 /* PCI */
356 pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
357 pci_dev->config[0x05] = 0x00;
358 pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
359 pci_dev->config[0x07] = 0x03; // status = medium devsel
360 pci_dev->config[0x09] = 0x00; // programming i/f
361 pci_dev->config[0x0D] = 0x0a; // latency_timer
362
363 /*
364 * BAR0 is accessed by OpenBSD but not for ebus device access: allow any
365 * memory access to this region to succeed which allows the OpenBSD kernel
366 * to boot.
367 */
368 memory_region_init_io(&s->bar0, OBJECT(s), &unassigned_io_ops, s,
369 "bar0", 0x1000000);
370 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
371 memory_region_init_alias(&s->bar1, OBJECT(s), "bar1",
372 pci_address_space_io(pci_dev), 0, 0x8000);
373 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
374 }
375
376 static Property ebus_properties[] = {
377 DEFINE_PROP_UINT64("console-serial-base", EbusState,
378 console_serial_base, 0),
379 DEFINE_PROP_END_OF_LIST(),
380 };
381
ebus_class_init(ObjectClass * klass,void * data)382 static void ebus_class_init(ObjectClass *klass, void *data)
383 {
384 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
385 DeviceClass *dc = DEVICE_CLASS(klass);
386
387 k->realize = ebus_realize;
388 k->vendor_id = PCI_VENDOR_ID_SUN;
389 k->device_id = PCI_DEVICE_ID_SUN_EBUS;
390 k->revision = 0x01;
391 k->class_id = PCI_CLASS_BRIDGE_OTHER;
392 device_class_set_props(dc, ebus_properties);
393 }
394
395 static const TypeInfo ebus_info = {
396 .name = TYPE_EBUS,
397 .parent = TYPE_PCI_DEVICE,
398 .class_init = ebus_class_init,
399 .instance_size = sizeof(EbusState),
400 .interfaces = (InterfaceInfo[]) {
401 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
402 { },
403 },
404 };
405
406 #define TYPE_OPENPROM "openprom"
407 typedef struct PROMState PROMState;
408 DECLARE_INSTANCE_CHECKER(PROMState, OPENPROM,
409 TYPE_OPENPROM)
410
411 struct PROMState {
412 SysBusDevice parent_obj;
413
414 MemoryRegion prom;
415 };
416
translate_prom_address(void * opaque,uint64_t addr)417 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
418 {
419 hwaddr *base_addr = (hwaddr *)opaque;
420 return addr + *base_addr - PROM_VADDR;
421 }
422
423 /* Boot PROM (OpenBIOS) */
prom_init(hwaddr addr,const char * bios_name)424 static void prom_init(hwaddr addr, const char *bios_name)
425 {
426 DeviceState *dev;
427 SysBusDevice *s;
428 char *filename;
429 int ret;
430
431 dev = qdev_new(TYPE_OPENPROM);
432 s = SYS_BUS_DEVICE(dev);
433 sysbus_realize_and_unref(s, &error_fatal);
434
435 sysbus_mmio_map(s, 0, addr);
436
437 /* load boot prom */
438 if (bios_name == NULL) {
439 bios_name = PROM_FILENAME;
440 }
441 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
442 if (filename) {
443 ret = load_elf(filename, NULL, translate_prom_address, &addr,
444 NULL, NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0);
445 if (ret < 0 || ret > PROM_SIZE_MAX) {
446 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
447 }
448 g_free(filename);
449 } else {
450 ret = -1;
451 }
452 if (ret < 0 || ret > PROM_SIZE_MAX) {
453 error_report("could not load prom '%s'", bios_name);
454 exit(1);
455 }
456 }
457
prom_realize(DeviceState * ds,Error ** errp)458 static void prom_realize(DeviceState *ds, Error **errp)
459 {
460 PROMState *s = OPENPROM(ds);
461 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
462
463 if (!memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4u.prom",
464 PROM_SIZE_MAX, errp)) {
465 return;
466 }
467
468 vmstate_register_ram_global(&s->prom);
469 memory_region_set_readonly(&s->prom, true);
470 sysbus_init_mmio(dev, &s->prom);
471 }
472
473 static Property prom_properties[] = {
474 {/* end of property list */},
475 };
476
prom_class_init(ObjectClass * klass,void * data)477 static void prom_class_init(ObjectClass *klass, void *data)
478 {
479 DeviceClass *dc = DEVICE_CLASS(klass);
480
481 device_class_set_props(dc, prom_properties);
482 dc->realize = prom_realize;
483 }
484
485 static const TypeInfo prom_info = {
486 .name = TYPE_OPENPROM,
487 .parent = TYPE_SYS_BUS_DEVICE,
488 .instance_size = sizeof(PROMState),
489 .class_init = prom_class_init,
490 };
491
492
493 #define TYPE_SUN4U_MEMORY "memory"
494 typedef struct RamDevice RamDevice;
495 DECLARE_INSTANCE_CHECKER(RamDevice, SUN4U_RAM,
496 TYPE_SUN4U_MEMORY)
497
498 struct RamDevice {
499 SysBusDevice parent_obj;
500
501 MemoryRegion ram;
502 uint64_t size;
503 };
504
505 /* System RAM */
ram_realize(DeviceState * dev,Error ** errp)506 static void ram_realize(DeviceState *dev, Error **errp)
507 {
508 RamDevice *d = SUN4U_RAM(dev);
509 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
510
511 memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size,
512 &error_fatal);
513 vmstate_register_ram_global(&d->ram);
514 sysbus_init_mmio(sbd, &d->ram);
515 }
516
ram_init(hwaddr addr,ram_addr_t RAM_size)517 static void ram_init(hwaddr addr, ram_addr_t RAM_size)
518 {
519 DeviceState *dev;
520 SysBusDevice *s;
521 RamDevice *d;
522
523 /* allocate RAM */
524 dev = qdev_new(TYPE_SUN4U_MEMORY);
525 s = SYS_BUS_DEVICE(dev);
526
527 d = SUN4U_RAM(dev);
528 d->size = RAM_size;
529 sysbus_realize_and_unref(s, &error_fatal);
530
531 sysbus_mmio_map(s, 0, addr);
532 }
533
534 static Property ram_properties[] = {
535 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
536 DEFINE_PROP_END_OF_LIST(),
537 };
538
ram_class_init(ObjectClass * klass,void * data)539 static void ram_class_init(ObjectClass *klass, void *data)
540 {
541 DeviceClass *dc = DEVICE_CLASS(klass);
542
543 dc->realize = ram_realize;
544 device_class_set_props(dc, ram_properties);
545 }
546
547 static const TypeInfo ram_info = {
548 .name = TYPE_SUN4U_MEMORY,
549 .parent = TYPE_SYS_BUS_DEVICE,
550 .instance_size = sizeof(RamDevice),
551 .class_init = ram_class_init,
552 };
553
sun4uv_init(MemoryRegion * address_space_mem,MachineState * machine,const struct hwdef * hwdef)554 static void sun4uv_init(MemoryRegion *address_space_mem,
555 MachineState *machine,
556 const struct hwdef *hwdef)
557 {
558 MachineClass *mc = MACHINE_GET_CLASS(machine);
559 SPARCCPU *cpu;
560 Nvram *nvram;
561 unsigned int i;
562 uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
563 SabreState *sabre;
564 PCIBus *pci_bus, *pci_busA, *pci_busB;
565 PCIDevice *ebus, *pci_dev;
566 SysBusDevice *s;
567 DeviceState *iommu, *dev;
568 FWCfgState *fw_cfg;
569 NICInfo *nd;
570 MACAddr macaddr;
571 bool onboard_nic;
572
573 /* init CPUs */
574 cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr);
575
576 /* IOMMU */
577 iommu = qdev_new(TYPE_SUN4U_IOMMU);
578 sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu), &error_fatal);
579
580 /* set up devices */
581 ram_init(0, machine->ram_size);
582
583 prom_init(hwdef->prom_addr, machine->firmware);
584
585 /* Init sabre (PCI host bridge) */
586 sabre = SABRE(qdev_new(TYPE_SABRE));
587 qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE);
588 qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE);
589 object_property_set_link(OBJECT(sabre), "iommu", OBJECT(iommu),
590 &error_abort);
591 sysbus_realize_and_unref(SYS_BUS_DEVICE(sabre), &error_fatal);
592
593 /* sabre_config */
594 sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 0, PBM_SPECIAL_BASE);
595 /* PCI configuration space */
596 sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 1, PBM_SPECIAL_BASE + 0x1000000ULL);
597 /* pci_ioport */
598 sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 2, PBM_SPECIAL_BASE + 0x2000000ULL);
599
600 /* Wire up PCI interrupts to CPU */
601 for (i = 0; i < IVEC_MAX; i++) {
602 qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i,
603 qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i));
604 }
605
606 pci_bus = PCI_HOST_BRIDGE(sabre)->bus;
607 pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA);
608 pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB);
609
610 /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is
611 reserved (leaving no slots free after on-board devices) however slots
612 0-3 are free on busB */
613 pci_bus_set_slot_reserved_mask(pci_bus, 0xfffffffc);
614 pci_bus_set_slot_reserved_mask(pci_busA, 0xfffffff1);
615 pci_bus_set_slot_reserved_mask(pci_busB, 0xfffffff0);
616
617 ebus = pci_new_multifunction(PCI_DEVFN(1, 0), TYPE_EBUS);
618 qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base",
619 hwdef->console_serial_base);
620 pci_realize_and_unref(ebus, pci_busA, &error_fatal);
621
622 /* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */
623 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7,
624 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ));
625 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6,
626 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ));
627 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1,
628 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ));
629 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12,
630 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ));
631 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4,
632 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ));
633
634 switch (vga_interface_type) {
635 case VGA_STD:
636 pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA");
637 vga_interface_created = true;
638 break;
639 case VGA_NONE:
640 break;
641 default:
642 abort(); /* Should not happen - types are checked in vl.c already */
643 }
644
645 memset(&macaddr, 0, sizeof(MACAddr));
646 onboard_nic = false;
647
648 nd = qemu_find_nic_info(mc->default_nic, true, NULL);
649 if (nd) {
650 pci_dev = pci_new_multifunction(PCI_DEVFN(1, 1), mc->default_nic);
651 dev = &pci_dev->qdev;
652 qdev_set_nic_properties(dev, nd);
653 pci_realize_and_unref(pci_dev, pci_busA, &error_fatal);
654
655 memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr));
656 onboard_nic = true;
657 }
658 pci_init_nic_devices(pci_busB, mc->default_nic);
659
660 /* If we don't have an onboard NIC, grab a default MAC address so that
661 * we have a valid machine id */
662 if (!onboard_nic) {
663 qemu_macaddr_default_if_unset(&macaddr);
664 }
665
666 pci_dev = pci_new(PCI_DEVFN(3, 0), "cmd646-ide");
667 qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1);
668 pci_realize_and_unref(pci_dev, pci_busA, &error_fatal);
669 pci_ide_create_devs(pci_dev);
670
671 /* Map NVRAM into I/O (ebus) space */
672 dev = qdev_new("sysbus-m48t59");
673 qdev_prop_set_int32(dev, "base-year", 1968);
674 s = SYS_BUS_DEVICE(dev);
675 sysbus_realize_and_unref(s, &error_fatal);
676 memory_region_add_subregion(pci_address_space_io(ebus), 0x2000,
677 sysbus_mmio_get_region(s, 0));
678 nvram = NVRAM(dev);
679
680 initrd_size = 0;
681 initrd_addr = 0;
682 kernel_size = sun4u_load_kernel(machine->kernel_filename,
683 machine->initrd_filename,
684 machine->ram_size, &initrd_size, &initrd_addr,
685 &kernel_addr, &kernel_entry);
686
687 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size,
688 machine->boot_config.order,
689 kernel_addr, kernel_size,
690 machine->kernel_cmdline,
691 initrd_addr, initrd_size,
692 /* XXX: need an option to load a NVRAM image */
693 0,
694 graphic_width, graphic_height, graphic_depth,
695 (uint8_t *)&macaddr);
696
697 dev = qdev_new(TYPE_FW_CFG_IO);
698 qdev_prop_set_bit(dev, "dma_enabled", false);
699 object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev));
700 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
701 memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT,
702 &FW_CFG_IO(dev)->comb_iomem);
703
704 fw_cfg = FW_CFG(dev);
705 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus);
706 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
707 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
708 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
709 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
710 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
711 if (machine->kernel_cmdline) {
712 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
713 strlen(machine->kernel_cmdline) + 1);
714 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
715 } else {
716 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
717 }
718 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
719 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
720 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_config.order[0]);
721
722 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
723 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
724 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
725
726 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
727 }
728
729 enum {
730 sun4u_id = 0,
731 sun4v_id = 64,
732 };
733
734 /*
735 * Implementation of an interface to adjust firmware path
736 * for the bootindex property handling.
737 */
sun4u_fw_dev_path(FWPathProvider * p,BusState * bus,DeviceState * dev)738 static char *sun4u_fw_dev_path(FWPathProvider *p, BusState *bus,
739 DeviceState *dev)
740 {
741 PCIDevice *pci;
742
743 if (!strcmp(object_get_typename(OBJECT(dev)), "pbm-bridge")) {
744 pci = PCI_DEVICE(dev);
745
746 if (PCI_FUNC(pci->devfn)) {
747 return g_strdup_printf("pci@%x,%x", PCI_SLOT(pci->devfn),
748 PCI_FUNC(pci->devfn));
749 } else {
750 return g_strdup_printf("pci@%x", PCI_SLOT(pci->devfn));
751 }
752 }
753
754 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) {
755 return g_strdup("disk");
756 }
757
758 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) {
759 return g_strdup("cdrom");
760 }
761
762 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) {
763 return g_strdup("disk");
764 }
765
766 return NULL;
767 }
768
769 static const struct hwdef hwdefs[] = {
770 /* Sun4u generic PC-like machine */
771 {
772 .machine_id = sun4u_id,
773 .prom_addr = 0x1fff0000000ULL,
774 .console_serial_base = 0,
775 },
776 /* Sun4v generic PC-like machine */
777 {
778 .machine_id = sun4v_id,
779 .prom_addr = 0x1fff0000000ULL,
780 .console_serial_base = 0,
781 },
782 };
783
784 /* Sun4u hardware initialisation */
sun4u_init(MachineState * machine)785 static void sun4u_init(MachineState *machine)
786 {
787 sun4uv_init(get_system_memory(), machine, &hwdefs[0]);
788 }
789
790 /* Sun4v hardware initialisation */
sun4v_init(MachineState * machine)791 static void sun4v_init(MachineState *machine)
792 {
793 sun4uv_init(get_system_memory(), machine, &hwdefs[1]);
794 }
795
796 static GlobalProperty hw_compat_sparc64[] = {
797 { "virtio-pci", "disable-legacy", "on", .optional = true },
798 { "virtio-device", "iommu_platform", "on" },
799 };
800 static const size_t hw_compat_sparc64_len = G_N_ELEMENTS(hw_compat_sparc64);
801
sun4u_class_init(ObjectClass * oc,void * data)802 static void sun4u_class_init(ObjectClass *oc, void *data)
803 {
804 MachineClass *mc = MACHINE_CLASS(oc);
805 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
806
807 mc->desc = "Sun4u platform";
808 mc->init = sun4u_init;
809 mc->block_default_type = IF_IDE;
810 mc->max_cpus = 1; /* XXX for now */
811 mc->is_default = true;
812 mc->default_boot_order = "c";
813 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi");
814 mc->ignore_boot_device_suffixes = true;
815 mc->default_display = "std";
816 mc->default_nic = "sunhme";
817 mc->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL);
818 fwc->get_dev_path = sun4u_fw_dev_path;
819 compat_props_add(mc->compat_props, hw_compat_sparc64, hw_compat_sparc64_len);
820 }
821
822 static const TypeInfo sun4u_type = {
823 .name = MACHINE_TYPE_NAME("sun4u"),
824 .parent = TYPE_MACHINE,
825 .class_init = sun4u_class_init,
826 .interfaces = (InterfaceInfo[]) {
827 { TYPE_FW_PATH_PROVIDER },
828 { }
829 },
830 };
831
sun4v_class_init(ObjectClass * oc,void * data)832 static void sun4v_class_init(ObjectClass *oc, void *data)
833 {
834 MachineClass *mc = MACHINE_CLASS(oc);
835
836 mc->desc = "Sun4v platform";
837 mc->init = sun4v_init;
838 mc->block_default_type = IF_IDE;
839 mc->max_cpus = 1; /* XXX for now */
840 mc->default_boot_order = "c";
841 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1");
842 mc->default_display = "std";
843 mc->default_nic = "sunhme";
844 mc->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL);
845 }
846
847 static const TypeInfo sun4v_type = {
848 .name = MACHINE_TYPE_NAME("sun4v"),
849 .parent = TYPE_MACHINE,
850 .class_init = sun4v_class_init,
851 };
852
sun4u_register_types(void)853 static void sun4u_register_types(void)
854 {
855 type_register_static(&power_info);
856 type_register_static(&ebus_info);
857 type_register_static(&prom_info);
858 type_register_static(&ram_info);
859
860 type_register_static(&sun4u_type);
861 type_register_static(&sun4v_type);
862 }
863
864 type_init(sun4u_register_types)
865