1 /*
2 * Luminary Micro Stellaris peripherals
3 *
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
6 *
7 * This code is licensed under the GPL.
8 */
9
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "hw/core/split-irq.h"
13 #include "hw/sysbus.h"
14 #include "hw/sd/sd.h"
15 #include "hw/ssi/ssi.h"
16 #include "hw/arm/boot.h"
17 #include "qemu/timer.h"
18 #include "hw/i2c/i2c.h"
19 #include "net/net.h"
20 #include "hw/boards.h"
21 #include "qemu/log.h"
22 #include "exec/address-spaces.h"
23 #include "sysemu/sysemu.h"
24 #include "hw/arm/armv7m.h"
25 #include "hw/char/pl011.h"
26 #include "hw/input/stellaris_gamepad.h"
27 #include "hw/irq.h"
28 #include "hw/watchdog/cmsdk-apb-watchdog.h"
29 #include "migration/vmstate.h"
30 #include "hw/misc/unimp.h"
31 #include "hw/timer/stellaris-gptm.h"
32 #include "hw/qdev-clock.h"
33 #include "qom/object.h"
34 #include "qapi/qmp/qlist.h"
35 #include "ui/input.h"
36
37 #define GPIO_A 0
38 #define GPIO_B 1
39 #define GPIO_C 2
40 #define GPIO_D 3
41 #define GPIO_E 4
42 #define GPIO_F 5
43 #define GPIO_G 6
44
45 #define BP_OLED_I2C 0x01
46 #define BP_OLED_SSI 0x02
47 #define BP_GAMEPAD 0x04
48
49 #define NUM_IRQ_LINES 64
50 #define NUM_PRIO_BITS 3
51
52 typedef const struct {
53 const char *name;
54 uint32_t did0;
55 uint32_t did1;
56 uint32_t dc0;
57 uint32_t dc1;
58 uint32_t dc2;
59 uint32_t dc3;
60 uint32_t dc4;
61 uint32_t peripherals;
62 } stellaris_board_info;
63
64 /* System controller. */
65
66 #define TYPE_STELLARIS_SYS "stellaris-sys"
67 OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS)
68
69 struct ssys_state {
70 SysBusDevice parent_obj;
71
72 MemoryRegion iomem;
73 uint32_t pborctl;
74 uint32_t ldopctl;
75 uint32_t int_status;
76 uint32_t int_mask;
77 uint32_t resc;
78 uint32_t rcc;
79 uint32_t rcc2;
80 uint32_t rcgc[3];
81 uint32_t scgc[3];
82 uint32_t dcgc[3];
83 uint32_t clkvclr;
84 uint32_t ldoarst;
85 qemu_irq irq;
86 Clock *sysclk;
87 /* Properties (all read-only registers) */
88 uint32_t user0;
89 uint32_t user1;
90 uint32_t did0;
91 uint32_t did1;
92 uint32_t dc0;
93 uint32_t dc1;
94 uint32_t dc2;
95 uint32_t dc3;
96 uint32_t dc4;
97 };
98
ssys_update(ssys_state * s)99 static void ssys_update(ssys_state *s)
100 {
101 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0);
102 }
103
104 static uint32_t pllcfg_sandstorm[16] = {
105 0x31c0, /* 1 Mhz */
106 0x1ae0, /* 1.8432 Mhz */
107 0x18c0, /* 2 Mhz */
108 0xd573, /* 2.4576 Mhz */
109 0x37a6, /* 3.57954 Mhz */
110 0x1ae2, /* 3.6864 Mhz */
111 0x0c40, /* 4 Mhz */
112 0x98bc, /* 4.906 Mhz */
113 0x935b, /* 4.9152 Mhz */
114 0x09c0, /* 5 Mhz */
115 0x4dee, /* 5.12 Mhz */
116 0x0c41, /* 6 Mhz */
117 0x75db, /* 6.144 Mhz */
118 0x1ae6, /* 7.3728 Mhz */
119 0x0600, /* 8 Mhz */
120 0x585b /* 8.192 Mhz */
121 };
122
123 static uint32_t pllcfg_fury[16] = {
124 0x3200, /* 1 Mhz */
125 0x1b20, /* 1.8432 Mhz */
126 0x1900, /* 2 Mhz */
127 0xf42b, /* 2.4576 Mhz */
128 0x37e3, /* 3.57954 Mhz */
129 0x1b21, /* 3.6864 Mhz */
130 0x0c80, /* 4 Mhz */
131 0x98ee, /* 4.906 Mhz */
132 0xd5b4, /* 4.9152 Mhz */
133 0x0a00, /* 5 Mhz */
134 0x4e27, /* 5.12 Mhz */
135 0x1902, /* 6 Mhz */
136 0xec1c, /* 6.144 Mhz */
137 0x1b23, /* 7.3728 Mhz */
138 0x0640, /* 8 Mhz */
139 0xb11c /* 8.192 Mhz */
140 };
141
142 #define DID0_VER_MASK 0x70000000
143 #define DID0_VER_0 0x00000000
144 #define DID0_VER_1 0x10000000
145
146 #define DID0_CLASS_MASK 0x00FF0000
147 #define DID0_CLASS_SANDSTORM 0x00000000
148 #define DID0_CLASS_FURY 0x00010000
149
ssys_board_class(const ssys_state * s)150 static int ssys_board_class(const ssys_state *s)
151 {
152 uint32_t did0 = s->did0;
153 switch (did0 & DID0_VER_MASK) {
154 case DID0_VER_0:
155 return DID0_CLASS_SANDSTORM;
156 case DID0_VER_1:
157 switch (did0 & DID0_CLASS_MASK) {
158 case DID0_CLASS_SANDSTORM:
159 case DID0_CLASS_FURY:
160 return did0 & DID0_CLASS_MASK;
161 }
162 /* for unknown classes, fall through */
163 default:
164 /* This can only happen if the hardwired constant did0 value
165 * in this board's stellaris_board_info struct is wrong.
166 */
167 g_assert_not_reached();
168 }
169 }
170
ssys_read(void * opaque,hwaddr offset,unsigned size)171 static uint64_t ssys_read(void *opaque, hwaddr offset,
172 unsigned size)
173 {
174 ssys_state *s = (ssys_state *)opaque;
175
176 switch (offset) {
177 case 0x000: /* DID0 */
178 return s->did0;
179 case 0x004: /* DID1 */
180 return s->did1;
181 case 0x008: /* DC0 */
182 return s->dc0;
183 case 0x010: /* DC1 */
184 return s->dc1;
185 case 0x014: /* DC2 */
186 return s->dc2;
187 case 0x018: /* DC3 */
188 return s->dc3;
189 case 0x01c: /* DC4 */
190 return s->dc4;
191 case 0x030: /* PBORCTL */
192 return s->pborctl;
193 case 0x034: /* LDOPCTL */
194 return s->ldopctl;
195 case 0x040: /* SRCR0 */
196 return 0;
197 case 0x044: /* SRCR1 */
198 return 0;
199 case 0x048: /* SRCR2 */
200 return 0;
201 case 0x050: /* RIS */
202 return s->int_status;
203 case 0x054: /* IMC */
204 return s->int_mask;
205 case 0x058: /* MISC */
206 return s->int_status & s->int_mask;
207 case 0x05c: /* RESC */
208 return s->resc;
209 case 0x060: /* RCC */
210 return s->rcc;
211 case 0x064: /* PLLCFG */
212 {
213 int xtal;
214 xtal = (s->rcc >> 6) & 0xf;
215 switch (ssys_board_class(s)) {
216 case DID0_CLASS_FURY:
217 return pllcfg_fury[xtal];
218 case DID0_CLASS_SANDSTORM:
219 return pllcfg_sandstorm[xtal];
220 default:
221 g_assert_not_reached();
222 }
223 }
224 case 0x070: /* RCC2 */
225 return s->rcc2;
226 case 0x100: /* RCGC0 */
227 return s->rcgc[0];
228 case 0x104: /* RCGC1 */
229 return s->rcgc[1];
230 case 0x108: /* RCGC2 */
231 return s->rcgc[2];
232 case 0x110: /* SCGC0 */
233 return s->scgc[0];
234 case 0x114: /* SCGC1 */
235 return s->scgc[1];
236 case 0x118: /* SCGC2 */
237 return s->scgc[2];
238 case 0x120: /* DCGC0 */
239 return s->dcgc[0];
240 case 0x124: /* DCGC1 */
241 return s->dcgc[1];
242 case 0x128: /* DCGC2 */
243 return s->dcgc[2];
244 case 0x150: /* CLKVCLR */
245 return s->clkvclr;
246 case 0x160: /* LDOARST */
247 return s->ldoarst;
248 case 0x1e0: /* USER0 */
249 return s->user0;
250 case 0x1e4: /* USER1 */
251 return s->user1;
252 default:
253 qemu_log_mask(LOG_GUEST_ERROR,
254 "SSYS: read at bad offset 0x%x\n", (int)offset);
255 return 0;
256 }
257 }
258
ssys_use_rcc2(ssys_state * s)259 static bool ssys_use_rcc2(ssys_state *s)
260 {
261 return (s->rcc2 >> 31) & 0x1;
262 }
263
264 /*
265 * Calculate the system clock period. We only want to propagate
266 * this change to the rest of the system if we're not being called
267 * from migration post-load.
268 */
ssys_calculate_system_clock(ssys_state * s,bool propagate_clock)269 static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock)
270 {
271 int period_ns;
272 /*
273 * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input
274 * clock is 200MHz, which is a period of 5 ns. Dividing the clock
275 * frequency by X is the same as multiplying the period by X.
276 */
277 if (ssys_use_rcc2(s)) {
278 period_ns = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
279 } else {
280 period_ns = 5 * (((s->rcc >> 23) & 0xf) + 1);
281 }
282 clock_set_ns(s->sysclk, period_ns);
283 if (propagate_clock) {
284 clock_propagate(s->sysclk);
285 }
286 }
287
ssys_write(void * opaque,hwaddr offset,uint64_t value,unsigned size)288 static void ssys_write(void *opaque, hwaddr offset,
289 uint64_t value, unsigned size)
290 {
291 ssys_state *s = (ssys_state *)opaque;
292
293 switch (offset) {
294 case 0x030: /* PBORCTL */
295 s->pborctl = value & 0xffff;
296 break;
297 case 0x034: /* LDOPCTL */
298 s->ldopctl = value & 0x1f;
299 break;
300 case 0x040: /* SRCR0 */
301 case 0x044: /* SRCR1 */
302 case 0x048: /* SRCR2 */
303 qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n");
304 break;
305 case 0x054: /* IMC */
306 s->int_mask = value & 0x7f;
307 break;
308 case 0x058: /* MISC */
309 s->int_status &= ~value;
310 break;
311 case 0x05c: /* RESC */
312 s->resc = value & 0x3f;
313 break;
314 case 0x060: /* RCC */
315 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
316 /* PLL enable. */
317 s->int_status |= (1 << 6);
318 }
319 s->rcc = value;
320 ssys_calculate_system_clock(s, true);
321 break;
322 case 0x070: /* RCC2 */
323 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
324 break;
325 }
326
327 if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
328 /* PLL enable. */
329 s->int_status |= (1 << 6);
330 }
331 s->rcc2 = value;
332 ssys_calculate_system_clock(s, true);
333 break;
334 case 0x100: /* RCGC0 */
335 s->rcgc[0] = value;
336 break;
337 case 0x104: /* RCGC1 */
338 s->rcgc[1] = value;
339 break;
340 case 0x108: /* RCGC2 */
341 s->rcgc[2] = value;
342 break;
343 case 0x110: /* SCGC0 */
344 s->scgc[0] = value;
345 break;
346 case 0x114: /* SCGC1 */
347 s->scgc[1] = value;
348 break;
349 case 0x118: /* SCGC2 */
350 s->scgc[2] = value;
351 break;
352 case 0x120: /* DCGC0 */
353 s->dcgc[0] = value;
354 break;
355 case 0x124: /* DCGC1 */
356 s->dcgc[1] = value;
357 break;
358 case 0x128: /* DCGC2 */
359 s->dcgc[2] = value;
360 break;
361 case 0x150: /* CLKVCLR */
362 s->clkvclr = value;
363 break;
364 case 0x160: /* LDOARST */
365 s->ldoarst = value;
366 break;
367 default:
368 qemu_log_mask(LOG_GUEST_ERROR,
369 "SSYS: write at bad offset 0x%x\n", (int)offset);
370 }
371 ssys_update(s);
372 }
373
374 static const MemoryRegionOps ssys_ops = {
375 .read = ssys_read,
376 .write = ssys_write,
377 .endianness = DEVICE_NATIVE_ENDIAN,
378 };
379
stellaris_sys_reset_enter(Object * obj,ResetType type)380 static void stellaris_sys_reset_enter(Object *obj, ResetType type)
381 {
382 ssys_state *s = STELLARIS_SYS(obj);
383
384 s->pborctl = 0x7ffd;
385 s->rcc = 0x078e3ac0;
386
387 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
388 s->rcc2 = 0;
389 } else {
390 s->rcc2 = 0x07802810;
391 }
392 s->rcgc[0] = 1;
393 s->scgc[0] = 1;
394 s->dcgc[0] = 1;
395 }
396
stellaris_sys_reset_hold(Object * obj,ResetType type)397 static void stellaris_sys_reset_hold(Object *obj, ResetType type)
398 {
399 ssys_state *s = STELLARIS_SYS(obj);
400
401 /* OK to propagate clocks from the hold phase */
402 ssys_calculate_system_clock(s, true);
403 }
404
stellaris_sys_reset_exit(Object * obj,ResetType type)405 static void stellaris_sys_reset_exit(Object *obj, ResetType type)
406 {
407 }
408
stellaris_sys_post_load(void * opaque,int version_id)409 static int stellaris_sys_post_load(void *opaque, int version_id)
410 {
411 ssys_state *s = opaque;
412
413 ssys_calculate_system_clock(s, false);
414
415 return 0;
416 }
417
418 static const VMStateDescription vmstate_stellaris_sys = {
419 .name = "stellaris_sys",
420 .version_id = 2,
421 .minimum_version_id = 1,
422 .post_load = stellaris_sys_post_load,
423 .fields = (const VMStateField[]) {
424 VMSTATE_UINT32(pborctl, ssys_state),
425 VMSTATE_UINT32(ldopctl, ssys_state),
426 VMSTATE_UINT32(int_mask, ssys_state),
427 VMSTATE_UINT32(int_status, ssys_state),
428 VMSTATE_UINT32(resc, ssys_state),
429 VMSTATE_UINT32(rcc, ssys_state),
430 VMSTATE_UINT32_V(rcc2, ssys_state, 2),
431 VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3),
432 VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3),
433 VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3),
434 VMSTATE_UINT32(clkvclr, ssys_state),
435 VMSTATE_UINT32(ldoarst, ssys_state),
436 /* No field for sysclk -- handled in post-load instead */
437 VMSTATE_END_OF_LIST()
438 }
439 };
440
441 static Property stellaris_sys_properties[] = {
442 DEFINE_PROP_UINT32("user0", ssys_state, user0, 0),
443 DEFINE_PROP_UINT32("user1", ssys_state, user1, 0),
444 DEFINE_PROP_UINT32("did0", ssys_state, did0, 0),
445 DEFINE_PROP_UINT32("did1", ssys_state, did1, 0),
446 DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0),
447 DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0),
448 DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0),
449 DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0),
450 DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0),
451 DEFINE_PROP_END_OF_LIST()
452 };
453
stellaris_sys_instance_init(Object * obj)454 static void stellaris_sys_instance_init(Object *obj)
455 {
456 ssys_state *s = STELLARIS_SYS(obj);
457 SysBusDevice *sbd = SYS_BUS_DEVICE(s);
458
459 memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000);
460 sysbus_init_mmio(sbd, &s->iomem);
461 sysbus_init_irq(sbd, &s->irq);
462 s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK");
463 }
464
465 /*
466 * I2C controller.
467 * ??? For now we only implement the master interface.
468 */
469
470 #define TYPE_STELLARIS_I2C "stellaris-i2c"
471 OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C)
472
473 struct stellaris_i2c_state {
474 SysBusDevice parent_obj;
475
476 I2CBus *bus;
477 qemu_irq irq;
478 MemoryRegion iomem;
479 uint32_t msa;
480 uint32_t mcs;
481 uint32_t mdr;
482 uint32_t mtpr;
483 uint32_t mimr;
484 uint32_t mris;
485 uint32_t mcr;
486 };
487
488 #define STELLARIS_I2C_MCS_BUSY 0x01
489 #define STELLARIS_I2C_MCS_ERROR 0x02
490 #define STELLARIS_I2C_MCS_ADRACK 0x04
491 #define STELLARIS_I2C_MCS_DATACK 0x08
492 #define STELLARIS_I2C_MCS_ARBLST 0x10
493 #define STELLARIS_I2C_MCS_IDLE 0x20
494 #define STELLARIS_I2C_MCS_BUSBSY 0x40
495
stellaris_i2c_read(void * opaque,hwaddr offset,unsigned size)496 static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset,
497 unsigned size)
498 {
499 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
500
501 switch (offset) {
502 case 0x00: /* MSA */
503 return s->msa;
504 case 0x04: /* MCS */
505 /* We don't emulate timing, so the controller is never busy. */
506 return s->mcs | STELLARIS_I2C_MCS_IDLE;
507 case 0x08: /* MDR */
508 return s->mdr;
509 case 0x0c: /* MTPR */
510 return s->mtpr;
511 case 0x10: /* MIMR */
512 return s->mimr;
513 case 0x14: /* MRIS */
514 return s->mris;
515 case 0x18: /* MMIS */
516 return s->mris & s->mimr;
517 case 0x20: /* MCR */
518 return s->mcr;
519 default:
520 qemu_log_mask(LOG_GUEST_ERROR,
521 "stellaris_i2c: read at bad offset 0x%x\n", (int)offset);
522 return 0;
523 }
524 }
525
stellaris_i2c_update(stellaris_i2c_state * s)526 static void stellaris_i2c_update(stellaris_i2c_state *s)
527 {
528 int level;
529
530 level = (s->mris & s->mimr) != 0;
531 qemu_set_irq(s->irq, level);
532 }
533
stellaris_i2c_write(void * opaque,hwaddr offset,uint64_t value,unsigned size)534 static void stellaris_i2c_write(void *opaque, hwaddr offset,
535 uint64_t value, unsigned size)
536 {
537 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
538
539 switch (offset) {
540 case 0x00: /* MSA */
541 s->msa = value & 0xff;
542 break;
543 case 0x04: /* MCS */
544 if ((s->mcr & 0x10) == 0) {
545 /* Disabled. Do nothing. */
546 break;
547 }
548 /* Grab the bus if this is starting a transfer. */
549 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
550 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) {
551 s->mcs |= STELLARIS_I2C_MCS_ARBLST;
552 } else {
553 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST;
554 s->mcs |= STELLARIS_I2C_MCS_BUSBSY;
555 }
556 }
557 /* If we don't have the bus then indicate an error. */
558 if (!i2c_bus_busy(s->bus)
559 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
560 s->mcs |= STELLARIS_I2C_MCS_ERROR;
561 break;
562 }
563 s->mcs &= ~STELLARIS_I2C_MCS_ERROR;
564 if (value & 1) {
565 /* Transfer a byte. */
566 /* TODO: Handle errors. */
567 if (s->msa & 1) {
568 /* Recv */
569 s->mdr = i2c_recv(s->bus);
570 } else {
571 /* Send */
572 i2c_send(s->bus, s->mdr);
573 }
574 /* Raise an interrupt. */
575 s->mris |= 1;
576 }
577 if (value & 4) {
578 /* Finish transfer. */
579 i2c_end_transfer(s->bus);
580 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY;
581 }
582 break;
583 case 0x08: /* MDR */
584 s->mdr = value & 0xff;
585 break;
586 case 0x0c: /* MTPR */
587 s->mtpr = value & 0xff;
588 break;
589 case 0x10: /* MIMR */
590 s->mimr = 1;
591 break;
592 case 0x1c: /* MICR */
593 s->mris &= ~value;
594 break;
595 case 0x20: /* MCR */
596 if (value & 1) {
597 qemu_log_mask(LOG_UNIMP,
598 "stellaris_i2c: Loopback not implemented\n");
599 }
600 if (value & 0x20) {
601 qemu_log_mask(LOG_UNIMP,
602 "stellaris_i2c: Slave mode not implemented\n");
603 }
604 s->mcr = value & 0x31;
605 break;
606 default:
607 qemu_log_mask(LOG_GUEST_ERROR,
608 "stellaris_i2c: write at bad offset 0x%x\n", (int)offset);
609 }
610 stellaris_i2c_update(s);
611 }
612
stellaris_i2c_reset_enter(Object * obj,ResetType type)613 static void stellaris_i2c_reset_enter(Object *obj, ResetType type)
614 {
615 stellaris_i2c_state *s = STELLARIS_I2C(obj);
616
617 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
618 i2c_end_transfer(s->bus);
619 }
620
stellaris_i2c_reset_hold(Object * obj,ResetType type)621 static void stellaris_i2c_reset_hold(Object *obj, ResetType type)
622 {
623 stellaris_i2c_state *s = STELLARIS_I2C(obj);
624
625 s->msa = 0;
626 s->mcs = 0;
627 s->mdr = 0;
628 s->mtpr = 1;
629 s->mimr = 0;
630 s->mris = 0;
631 s->mcr = 0;
632 }
633
stellaris_i2c_reset_exit(Object * obj,ResetType type)634 static void stellaris_i2c_reset_exit(Object *obj, ResetType type)
635 {
636 stellaris_i2c_state *s = STELLARIS_I2C(obj);
637
638 stellaris_i2c_update(s);
639 }
640
641 static const MemoryRegionOps stellaris_i2c_ops = {
642 .read = stellaris_i2c_read,
643 .write = stellaris_i2c_write,
644 .endianness = DEVICE_NATIVE_ENDIAN,
645 };
646
647 static const VMStateDescription vmstate_stellaris_i2c = {
648 .name = "stellaris_i2c",
649 .version_id = 1,
650 .minimum_version_id = 1,
651 .fields = (const VMStateField[]) {
652 VMSTATE_UINT32(msa, stellaris_i2c_state),
653 VMSTATE_UINT32(mcs, stellaris_i2c_state),
654 VMSTATE_UINT32(mdr, stellaris_i2c_state),
655 VMSTATE_UINT32(mtpr, stellaris_i2c_state),
656 VMSTATE_UINT32(mimr, stellaris_i2c_state),
657 VMSTATE_UINT32(mris, stellaris_i2c_state),
658 VMSTATE_UINT32(mcr, stellaris_i2c_state),
659 VMSTATE_END_OF_LIST()
660 }
661 };
662
stellaris_i2c_init(Object * obj)663 static void stellaris_i2c_init(Object *obj)
664 {
665 DeviceState *dev = DEVICE(obj);
666 stellaris_i2c_state *s = STELLARIS_I2C(obj);
667 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
668 I2CBus *bus;
669
670 sysbus_init_irq(sbd, &s->irq);
671 bus = i2c_init_bus(dev, "i2c");
672 s->bus = bus;
673
674 memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s,
675 "i2c", 0x1000);
676 sysbus_init_mmio(sbd, &s->iomem);
677 }
678
679 /* Analogue to Digital Converter. This is only partially implemented,
680 enough for applications that use a combined ADC and timer tick. */
681
682 #define STELLARIS_ADC_EM_CONTROLLER 0
683 #define STELLARIS_ADC_EM_COMP 1
684 #define STELLARIS_ADC_EM_EXTERNAL 4
685 #define STELLARIS_ADC_EM_TIMER 5
686 #define STELLARIS_ADC_EM_PWM0 6
687 #define STELLARIS_ADC_EM_PWM1 7
688 #define STELLARIS_ADC_EM_PWM2 8
689
690 #define STELLARIS_ADC_FIFO_EMPTY 0x0100
691 #define STELLARIS_ADC_FIFO_FULL 0x1000
692
693 #define TYPE_STELLARIS_ADC "stellaris-adc"
694 typedef struct StellarisADCState StellarisADCState;
695 DECLARE_INSTANCE_CHECKER(StellarisADCState, STELLARIS_ADC, TYPE_STELLARIS_ADC)
696
697 struct StellarisADCState {
698 SysBusDevice parent_obj;
699
700 MemoryRegion iomem;
701 uint32_t actss;
702 uint32_t ris;
703 uint32_t im;
704 uint32_t emux;
705 uint32_t ostat;
706 uint32_t ustat;
707 uint32_t sspri;
708 uint32_t sac;
709 struct {
710 uint32_t state;
711 uint32_t data[16];
712 } fifo[4];
713 uint32_t ssmux[4];
714 uint32_t ssctl[4];
715 uint32_t noise;
716 qemu_irq irq[4];
717 };
718
stellaris_adc_fifo_read(StellarisADCState * s,int n)719 static uint32_t stellaris_adc_fifo_read(StellarisADCState *s, int n)
720 {
721 int tail;
722
723 tail = s->fifo[n].state & 0xf;
724 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) {
725 s->ustat |= 1 << n;
726 } else {
727 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf);
728 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL;
729 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf))
730 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY;
731 }
732 return s->fifo[n].data[tail];
733 }
734
stellaris_adc_fifo_write(StellarisADCState * s,int n,uint32_t value)735 static void stellaris_adc_fifo_write(StellarisADCState *s, int n,
736 uint32_t value)
737 {
738 int head;
739
740 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry
741 FIFO fir each sequencer. */
742 head = (s->fifo[n].state >> 4) & 0xf;
743 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) {
744 s->ostat |= 1 << n;
745 return;
746 }
747 s->fifo[n].data[head] = value;
748 head = (head + 1) & 0xf;
749 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY;
750 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4);
751 if ((s->fifo[n].state & 0xf) == head)
752 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
753 }
754
stellaris_adc_update(StellarisADCState * s)755 static void stellaris_adc_update(StellarisADCState *s)
756 {
757 int level;
758 int n;
759
760 for (n = 0; n < 4; n++) {
761 level = (s->ris & s->im & (1 << n)) != 0;
762 qemu_set_irq(s->irq[n], level);
763 }
764 }
765
stellaris_adc_trigger(void * opaque,int irq,int level)766 static void stellaris_adc_trigger(void *opaque, int irq, int level)
767 {
768 StellarisADCState *s = opaque;
769 int n;
770
771 for (n = 0; n < 4; n++) {
772 if ((s->actss & (1 << n)) == 0) {
773 continue;
774 }
775
776 if (((s->emux >> (n * 4)) & 0xff) != 5) {
777 continue;
778 }
779
780 /* Some applications use the ADC as a random number source, so introduce
781 some variation into the signal. */
782 s->noise = s->noise * 314159 + 1;
783 /* ??? actual inputs not implemented. Return an arbitrary value. */
784 stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7));
785 s->ris |= (1 << n);
786 stellaris_adc_update(s);
787 }
788 }
789
stellaris_adc_reset_hold(Object * obj,ResetType type)790 static void stellaris_adc_reset_hold(Object *obj, ResetType type)
791 {
792 StellarisADCState *s = STELLARIS_ADC(obj);
793 int n;
794
795 for (n = 0; n < 4; n++) {
796 s->ssmux[n] = 0;
797 s->ssctl[n] = 0;
798 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY;
799 }
800 }
801
stellaris_adc_read(void * opaque,hwaddr offset,unsigned size)802 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
803 unsigned size)
804 {
805 StellarisADCState *s = opaque;
806
807 /* TODO: Implement this. */
808 if (offset >= 0x40 && offset < 0xc0) {
809 int n;
810 n = (offset - 0x40) >> 5;
811 switch (offset & 0x1f) {
812 case 0x00: /* SSMUX */
813 return s->ssmux[n];
814 case 0x04: /* SSCTL */
815 return s->ssctl[n];
816 case 0x08: /* SSFIFO */
817 return stellaris_adc_fifo_read(s, n);
818 case 0x0c: /* SSFSTAT */
819 return s->fifo[n].state;
820 default:
821 break;
822 }
823 }
824 switch (offset) {
825 case 0x00: /* ACTSS */
826 return s->actss;
827 case 0x04: /* RIS */
828 return s->ris;
829 case 0x08: /* IM */
830 return s->im;
831 case 0x0c: /* ISC */
832 return s->ris & s->im;
833 case 0x10: /* OSTAT */
834 return s->ostat;
835 case 0x14: /* EMUX */
836 return s->emux;
837 case 0x18: /* USTAT */
838 return s->ustat;
839 case 0x20: /* SSPRI */
840 return s->sspri;
841 case 0x30: /* SAC */
842 return s->sac;
843 default:
844 qemu_log_mask(LOG_GUEST_ERROR,
845 "stellaris_adc: read at bad offset 0x%x\n", (int)offset);
846 return 0;
847 }
848 }
849
stellaris_adc_write(void * opaque,hwaddr offset,uint64_t value,unsigned size)850 static void stellaris_adc_write(void *opaque, hwaddr offset,
851 uint64_t value, unsigned size)
852 {
853 StellarisADCState *s = opaque;
854
855 /* TODO: Implement this. */
856 if (offset >= 0x40 && offset < 0xc0) {
857 int n;
858 n = (offset - 0x40) >> 5;
859 switch (offset & 0x1f) {
860 case 0x00: /* SSMUX */
861 s->ssmux[n] = value & 0x33333333;
862 return;
863 case 0x04: /* SSCTL */
864 if (value != 6) {
865 qemu_log_mask(LOG_UNIMP,
866 "ADC: Unimplemented sequence %" PRIx64 "\n",
867 value);
868 }
869 s->ssctl[n] = value;
870 return;
871 default:
872 break;
873 }
874 }
875 switch (offset) {
876 case 0x00: /* ACTSS */
877 s->actss = value & 0xf;
878 break;
879 case 0x08: /* IM */
880 s->im = value;
881 break;
882 case 0x0c: /* ISC */
883 s->ris &= ~value;
884 break;
885 case 0x10: /* OSTAT */
886 s->ostat &= ~value;
887 break;
888 case 0x14: /* EMUX */
889 s->emux = value;
890 break;
891 case 0x18: /* USTAT */
892 s->ustat &= ~value;
893 break;
894 case 0x20: /* SSPRI */
895 s->sspri = value;
896 break;
897 case 0x28: /* PSSI */
898 qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n");
899 break;
900 case 0x30: /* SAC */
901 s->sac = value;
902 break;
903 default:
904 qemu_log_mask(LOG_GUEST_ERROR,
905 "stellaris_adc: write at bad offset 0x%x\n", (int)offset);
906 }
907 stellaris_adc_update(s);
908 }
909
910 static const MemoryRegionOps stellaris_adc_ops = {
911 .read = stellaris_adc_read,
912 .write = stellaris_adc_write,
913 .endianness = DEVICE_NATIVE_ENDIAN,
914 };
915
916 static const VMStateDescription vmstate_stellaris_adc = {
917 .name = "stellaris_adc",
918 .version_id = 1,
919 .minimum_version_id = 1,
920 .fields = (const VMStateField[]) {
921 VMSTATE_UINT32(actss, StellarisADCState),
922 VMSTATE_UINT32(ris, StellarisADCState),
923 VMSTATE_UINT32(im, StellarisADCState),
924 VMSTATE_UINT32(emux, StellarisADCState),
925 VMSTATE_UINT32(ostat, StellarisADCState),
926 VMSTATE_UINT32(ustat, StellarisADCState),
927 VMSTATE_UINT32(sspri, StellarisADCState),
928 VMSTATE_UINT32(sac, StellarisADCState),
929 VMSTATE_UINT32(fifo[0].state, StellarisADCState),
930 VMSTATE_UINT32_ARRAY(fifo[0].data, StellarisADCState, 16),
931 VMSTATE_UINT32(ssmux[0], StellarisADCState),
932 VMSTATE_UINT32(ssctl[0], StellarisADCState),
933 VMSTATE_UINT32(fifo[1].state, StellarisADCState),
934 VMSTATE_UINT32_ARRAY(fifo[1].data, StellarisADCState, 16),
935 VMSTATE_UINT32(ssmux[1], StellarisADCState),
936 VMSTATE_UINT32(ssctl[1], StellarisADCState),
937 VMSTATE_UINT32(fifo[2].state, StellarisADCState),
938 VMSTATE_UINT32_ARRAY(fifo[2].data, StellarisADCState, 16),
939 VMSTATE_UINT32(ssmux[2], StellarisADCState),
940 VMSTATE_UINT32(ssctl[2], StellarisADCState),
941 VMSTATE_UINT32(fifo[3].state, StellarisADCState),
942 VMSTATE_UINT32_ARRAY(fifo[3].data, StellarisADCState, 16),
943 VMSTATE_UINT32(ssmux[3], StellarisADCState),
944 VMSTATE_UINT32(ssctl[3], StellarisADCState),
945 VMSTATE_UINT32(noise, StellarisADCState),
946 VMSTATE_END_OF_LIST()
947 }
948 };
949
stellaris_adc_init(Object * obj)950 static void stellaris_adc_init(Object *obj)
951 {
952 DeviceState *dev = DEVICE(obj);
953 StellarisADCState *s = STELLARIS_ADC(obj);
954 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
955 int n;
956
957 for (n = 0; n < 4; n++) {
958 sysbus_init_irq(sbd, &s->irq[n]);
959 }
960
961 memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s,
962 "adc", 0x1000);
963 sysbus_init_mmio(sbd, &s->iomem);
964 qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
965 }
966
967 /* Board init. */
968 static stellaris_board_info stellaris_boards[] = {
969 { "LM3S811EVB",
970 0,
971 0x0032000e,
972 0x001f001f, /* dc0 */
973 0x001132bf,
974 0x01071013,
975 0x3f0f01ff,
976 0x0000001f,
977 BP_OLED_I2C
978 },
979 { "LM3S6965EVB",
980 0x10010002,
981 0x1073402e,
982 0x00ff007f, /* dc0 */
983 0x001133ff,
984 0x030f5317,
985 0x0f0f87ff,
986 0x5000007f,
987 BP_OLED_SSI | BP_GAMEPAD
988 }
989 };
990
stellaris_init(MachineState * ms,stellaris_board_info * board)991 static void stellaris_init(MachineState *ms, stellaris_board_info *board)
992 {
993 static const int uart_irq[] = {5, 6, 33, 34};
994 static const int timer_irq[] = {19, 21, 23, 35};
995 static const uint32_t gpio_addr[7] =
996 { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
997 0x40024000, 0x40025000, 0x40026000};
998 static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
999
1000 /* Memory map of SoC devices, from
1001 * Stellaris LM3S6965 Microcontroller Data Sheet (rev I)
1002 * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf
1003 *
1004 * 40000000 wdtimer
1005 * 40002000 i2c (unimplemented)
1006 * 40004000 GPIO
1007 * 40005000 GPIO
1008 * 40006000 GPIO
1009 * 40007000 GPIO
1010 * 40008000 SSI
1011 * 4000c000 UART
1012 * 4000d000 UART
1013 * 4000e000 UART
1014 * 40020000 i2c
1015 * 40021000 i2c (unimplemented)
1016 * 40024000 GPIO
1017 * 40025000 GPIO
1018 * 40026000 GPIO
1019 * 40028000 PWM (unimplemented)
1020 * 4002c000 QEI (unimplemented)
1021 * 4002d000 QEI (unimplemented)
1022 * 40030000 gptimer
1023 * 40031000 gptimer
1024 * 40032000 gptimer
1025 * 40033000 gptimer
1026 * 40038000 ADC
1027 * 4003c000 analogue comparator (unimplemented)
1028 * 40048000 ethernet
1029 * 400fc000 hibernation module (unimplemented)
1030 * 400fd000 flash memory control (unimplemented)
1031 * 400fe000 system control
1032 */
1033
1034 Object *soc_container;
1035 DeviceState *gpio_dev[7], *nvic;
1036 qemu_irq gpio_in[7][8];
1037 qemu_irq gpio_out[7][8];
1038 qemu_irq adc;
1039 int sram_size;
1040 int flash_size;
1041 I2CBus *i2c;
1042 DeviceState *dev;
1043 DeviceState *ssys_dev;
1044 int i;
1045 int j;
1046 NICInfo *nd;
1047 MACAddr mac;
1048
1049 MemoryRegion *sram = g_new(MemoryRegion, 1);
1050 MemoryRegion *flash = g_new(MemoryRegion, 1);
1051 MemoryRegion *system_memory = get_system_memory();
1052
1053 flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024;
1054 sram_size = ((board->dc0 >> 18) + 1) * 1024;
1055
1056 soc_container = object_new("container");
1057 object_property_add_child(OBJECT(ms), "soc", soc_container);
1058
1059 /* Flash programming is done via the SCU, so pretend it is ROM. */
1060 memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size,
1061 &error_fatal);
1062 memory_region_add_subregion(system_memory, 0, flash);
1063
1064 memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size,
1065 &error_fatal);
1066 memory_region_add_subregion(system_memory, 0x20000000, sram);
1067
1068 /*
1069 * Create the system-registers object early, because we will
1070 * need its sysclk output.
1071 */
1072 ssys_dev = qdev_new(TYPE_STELLARIS_SYS);
1073 object_property_add_child(soc_container, "sys", OBJECT(ssys_dev));
1074
1075 /*
1076 * Most devices come preprogrammed with a MAC address in the user data.
1077 * Generate a MAC address now, if there isn't a matching -nic for it.
1078 */
1079 nd = qemu_find_nic_info("stellaris_enet", true, "stellaris");
1080 if (nd) {
1081 memcpy(mac.a, nd->macaddr.a, sizeof(mac.a));
1082 } else {
1083 qemu_macaddr_default_if_unset(&mac);
1084 }
1085
1086 qdev_prop_set_uint32(ssys_dev, "user0",
1087 mac.a[0] | (mac.a[1] << 8) | (mac.a[2] << 16));
1088 qdev_prop_set_uint32(ssys_dev, "user1",
1089 mac.a[3] | (mac.a[4] << 8) | (mac.a[5] << 16));
1090 qdev_prop_set_uint32(ssys_dev, "did0", board->did0);
1091 qdev_prop_set_uint32(ssys_dev, "did1", board->did1);
1092 qdev_prop_set_uint32(ssys_dev, "dc0", board->dc0);
1093 qdev_prop_set_uint32(ssys_dev, "dc1", board->dc1);
1094 qdev_prop_set_uint32(ssys_dev, "dc2", board->dc2);
1095 qdev_prop_set_uint32(ssys_dev, "dc3", board->dc3);
1096 qdev_prop_set_uint32(ssys_dev, "dc4", board->dc4);
1097 sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal);
1098
1099 nvic = qdev_new(TYPE_ARMV7M);
1100 object_property_add_child(soc_container, "v7m", OBJECT(nvic));
1101 qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
1102 qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS);
1103 qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
1104 qdev_prop_set_bit(nvic, "enable-bitband", true);
1105 qdev_connect_clock_in(nvic, "cpuclk",
1106 qdev_get_clock_out(ssys_dev, "SYSCLK"));
1107 /* This SoC does not connect the systick reference clock */
1108 object_property_set_link(OBJECT(nvic), "memory",
1109 OBJECT(get_system_memory()), &error_abort);
1110 /* This will exit with an error if the user passed us a bad cpu_type */
1111 sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal);
1112
1113 /* Now we can wire up the IRQ and MMIO of the system registers */
1114 sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000);
1115 sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev), 0, qdev_get_gpio_in(nvic, 28));
1116
1117 if (board->dc1 & (1 << 16)) {
1118 dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,
1119 qdev_get_gpio_in(nvic, 14),
1120 qdev_get_gpio_in(nvic, 15),
1121 qdev_get_gpio_in(nvic, 16),
1122 qdev_get_gpio_in(nvic, 17),
1123 NULL);
1124 adc = qdev_get_gpio_in(dev, 0);
1125 } else {
1126 adc = NULL;
1127 }
1128 for (i = 0; i < 4; i++) {
1129 if (board->dc2 & (0x10000 << i)) {
1130 SysBusDevice *sbd;
1131
1132 dev = qdev_new(TYPE_STELLARIS_GPTM);
1133 sbd = SYS_BUS_DEVICE(dev);
1134 object_property_add_child(soc_container, "gptm[*]", OBJECT(dev));
1135 qdev_connect_clock_in(dev, "clk",
1136 qdev_get_clock_out(ssys_dev, "SYSCLK"));
1137 sysbus_realize_and_unref(sbd, &error_fatal);
1138 sysbus_mmio_map(sbd, 0, 0x40030000 + i * 0x1000);
1139 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, timer_irq[i]));
1140 /* TODO: This is incorrect, but we get away with it because
1141 the ADC output is only ever pulsed. */
1142 qdev_connect_gpio_out(dev, 0, adc);
1143 }
1144 }
1145
1146 if (board->dc1 & (1 << 3)) { /* watchdog present */
1147 dev = qdev_new(TYPE_LUMINARY_WATCHDOG);
1148 object_property_add_child(soc_container, "wdg", OBJECT(dev));
1149 qdev_connect_clock_in(dev, "WDOGCLK",
1150 qdev_get_clock_out(ssys_dev, "SYSCLK"));
1151
1152 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1153 sysbus_mmio_map(SYS_BUS_DEVICE(dev),
1154 0,
1155 0x40000000u);
1156 sysbus_connect_irq(SYS_BUS_DEVICE(dev),
1157 0,
1158 qdev_get_gpio_in(nvic, 18));
1159 }
1160
1161
1162 for (i = 0; i < 7; i++) {
1163 if (board->dc4 & (1 << i)) {
1164 gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i],
1165 qdev_get_gpio_in(nvic,
1166 gpio_irq[i]));
1167 for (j = 0; j < 8; j++) {
1168 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j);
1169 gpio_out[i][j] = NULL;
1170 }
1171 }
1172 }
1173
1174 if (board->dc2 & (1 << 12)) {
1175 dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000,
1176 qdev_get_gpio_in(nvic, 8));
1177 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
1178 if (board->peripherals & BP_OLED_I2C) {
1179 i2c_slave_create_simple(i2c, "ssd0303", 0x3d);
1180 }
1181 }
1182
1183 for (i = 0; i < 4; i++) {
1184 if (board->dc2 & (1 << i)) {
1185 SysBusDevice *sbd;
1186
1187 dev = qdev_new("pl011_luminary");
1188 object_property_add_child(soc_container, "uart[*]", OBJECT(dev));
1189 sbd = SYS_BUS_DEVICE(dev);
1190 qdev_prop_set_chr(dev, "chardev", serial_hd(i));
1191 sysbus_realize_and_unref(sbd, &error_fatal);
1192 sysbus_mmio_map(sbd, 0, 0x4000c000 + i * 0x1000);
1193 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, uart_irq[i]));
1194 }
1195 }
1196 if (board->dc2 & (1 << 4)) {
1197 dev = sysbus_create_simple("pl022", 0x40008000,
1198 qdev_get_gpio_in(nvic, 7));
1199 if (board->peripherals & BP_OLED_SSI) {
1200 void *bus;
1201 DeviceState *sddev;
1202 DeviceState *ssddev;
1203 DriveInfo *dinfo;
1204 DeviceState *carddev;
1205 DeviceState *gpio_d_splitter;
1206 BlockBackend *blk;
1207
1208 /*
1209 * Some boards have both an OLED controller and SD card connected to
1210 * the same SSI port, with the SD card chip select connected to a
1211 * GPIO pin. Technically the OLED chip select is connected to the
1212 * SSI Fss pin. We do not bother emulating that as both devices
1213 * should never be selected simultaneously, and our OLED controller
1214 * ignores stray 0xff commands that occur when deselecting the SD
1215 * card.
1216 *
1217 * The h/w wiring is:
1218 * - GPIO pin D0 is wired to the active-low SD card chip select
1219 * - GPIO pin A3 is wired to the active-low OLED chip select
1220 * - The SoC wiring of the PL061 "auxiliary function" for A3 is
1221 * SSI0Fss ("frame signal"), which is an output from the SoC's
1222 * SSI controller. The SSI controller takes SSI0Fss low when it
1223 * transmits a frame, so it can work as a chip-select signal.
1224 * - GPIO A4 is aux-function SSI0Rx, and wired to the SD card Tx
1225 * (the OLED never sends data to the CPU, so no wiring needed)
1226 * - GPIO A5 is aux-function SSI0Tx, and wired to the SD card Rx
1227 * and the OLED display-data-in
1228 * - GPIO A2 is aux-function SSI0Clk, wired to SD card and OLED
1229 * serial-clock input
1230 * So a guest that wants to use the OLED can configure the PL061
1231 * to make pins A2, A3, A5 aux-function, so they are connected
1232 * directly to the SSI controller. When the SSI controller sends
1233 * data it asserts SSI0Fss which selects the OLED.
1234 * A guest that wants to use the SD card configures A2, A4 and A5
1235 * as aux-function, but leaves A3 as a software-controlled GPIO
1236 * line. It asserts the SD card chip-select by using the PL061
1237 * to control pin D0, and lets the SSI controller handle Clk, Tx
1238 * and Rx. (The SSI controller asserts Fss during tx cycles as
1239 * usual, but because A3 is not set to aux-function this is not
1240 * forwarded to the OLED, and so the OLED stays unselected.)
1241 *
1242 * The QEMU implementation instead is:
1243 * - GPIO pin D0 is wired to the active-low SD card chip select,
1244 * and also to the OLED chip-select which is implemented
1245 * as *active-high*
1246 * - SSI controller signals go to the devices regardless of
1247 * whether the guest programs A2, A4, A5 as aux-function or not
1248 *
1249 * The problem with this implementation is if the guest doesn't
1250 * care about the SD card and only uses the OLED. In that case it
1251 * may choose never to do anything with D0 (leaving it in its
1252 * default floating state, which reliably leaves the card disabled
1253 * because an SD card has a pullup on CS within the card itself),
1254 * and only set up A2, A3, A5. This for us would mean the OLED
1255 * never gets the chip-select assert it needs. We work around
1256 * this with a manual raise of D0 here (despite board creation
1257 * code being the wrong place to raise IRQ lines) to put the OLED
1258 * into an initially selected state.
1259 *
1260 * In theory the right way to model this would be:
1261 * - Implement aux-function support in the PL061, with an
1262 * extra set of AFIN and AFOUT GPIO lines (set up so that
1263 * if a GPIO line is in auxfn mode the main GPIO in and out
1264 * track the AFIN and AFOUT lines)
1265 * - Wire the AFOUT for D0 up to either a line from the
1266 * SSI controller that's pulled low around every transmit,
1267 * or at least to an always-0 line here on the board
1268 * - Make the ssd0323 OLED controller chipselect active-low
1269 */
1270 bus = qdev_get_child_bus(dev, "ssi");
1271 sddev = ssi_create_peripheral(bus, "ssi-sd");
1272
1273 dinfo = drive_get(IF_SD, 0, 0);
1274 blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
1275 carddev = qdev_new(TYPE_SD_CARD_SPI);
1276 qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal);
1277 qdev_realize_and_unref(carddev,
1278 qdev_get_child_bus(sddev, "sd-bus"),
1279 &error_fatal);
1280
1281 ssddev = qdev_new("ssd0323");
1282 object_property_add_child(OBJECT(ms), "oled", OBJECT(ssddev));
1283 qdev_prop_set_uint8(ssddev, "cs", 1);
1284 qdev_realize_and_unref(ssddev, bus, &error_fatal);
1285
1286 gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ);
1287 object_property_add_child(OBJECT(ms), "splitter",
1288 OBJECT(gpio_d_splitter));
1289 qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2);
1290 qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal);
1291 qdev_connect_gpio_out(
1292 gpio_d_splitter, 0,
1293 qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0));
1294 qdev_connect_gpio_out(
1295 gpio_d_splitter, 1,
1296 qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0));
1297 gpio_out[GPIO_D][0] = qdev_get_gpio_in(gpio_d_splitter, 0);
1298
1299 gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0);
1300
1301 /* Make sure the select pin is high. */
1302 qemu_irq_raise(gpio_out[GPIO_D][0]);
1303 }
1304 }
1305 if (board->dc4 & (1 << 28)) {
1306 DeviceState *enet;
1307
1308 enet = qdev_new("stellaris_enet");
1309 object_property_add_child(soc_container, "enet", OBJECT(enet));
1310 if (nd) {
1311 qdev_set_nic_properties(enet, nd);
1312 } else {
1313 qdev_prop_set_macaddr(enet, "mac", mac.a);
1314 }
1315
1316 sysbus_realize_and_unref(SYS_BUS_DEVICE(enet), &error_fatal);
1317 sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000);
1318 sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42));
1319 }
1320 if (board->peripherals & BP_GAMEPAD) {
1321 QList *gpad_keycode_list = qlist_new();
1322 static const int gpad_keycode[5] = {
1323 Q_KEY_CODE_UP, Q_KEY_CODE_DOWN, Q_KEY_CODE_LEFT,
1324 Q_KEY_CODE_RIGHT, Q_KEY_CODE_CTRL,
1325 };
1326 DeviceState *gpad;
1327
1328 gpad = qdev_new(TYPE_STELLARIS_GAMEPAD);
1329 object_property_add_child(OBJECT(ms), "gamepad", OBJECT(gpad));
1330 for (i = 0; i < ARRAY_SIZE(gpad_keycode); i++) {
1331 qlist_append_int(gpad_keycode_list, gpad_keycode[i]);
1332 }
1333 qdev_prop_set_array(gpad, "keycodes", gpad_keycode_list);
1334 sysbus_realize_and_unref(SYS_BUS_DEVICE(gpad), &error_fatal);
1335
1336 qdev_connect_gpio_out(gpad, 0,
1337 qemu_irq_invert(gpio_in[GPIO_E][0])); /* up */
1338 qdev_connect_gpio_out(gpad, 1,
1339 qemu_irq_invert(gpio_in[GPIO_E][1])); /* down */
1340 qdev_connect_gpio_out(gpad, 2,
1341 qemu_irq_invert(gpio_in[GPIO_E][2])); /* left */
1342 qdev_connect_gpio_out(gpad, 3,
1343 qemu_irq_invert(gpio_in[GPIO_E][3])); /* right */
1344 qdev_connect_gpio_out(gpad, 4,
1345 qemu_irq_invert(gpio_in[GPIO_F][1])); /* select */
1346 }
1347 for (i = 0; i < 7; i++) {
1348 if (board->dc4 & (1 << i)) {
1349 for (j = 0; j < 8; j++) {
1350 if (gpio_out[i][j]) {
1351 qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]);
1352 }
1353 }
1354 }
1355 }
1356
1357 /* Add dummy regions for the devices we don't implement yet,
1358 * so guest accesses don't cause unlogged crashes.
1359 */
1360 create_unimplemented_device("i2c-0", 0x40002000, 0x1000);
1361 create_unimplemented_device("i2c-2", 0x40021000, 0x1000);
1362 create_unimplemented_device("PWM", 0x40028000, 0x1000);
1363 create_unimplemented_device("QEI-0", 0x4002c000, 0x1000);
1364 create_unimplemented_device("QEI-1", 0x4002d000, 0x1000);
1365 create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000);
1366 create_unimplemented_device("hibernation", 0x400fc000, 0x1000);
1367 create_unimplemented_device("flash-control", 0x400fd000, 0x1000);
1368
1369 armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, 0, flash_size);
1370 }
1371
1372 /* FIXME: Figure out how to generate these from stellaris_boards. */
lm3s811evb_init(MachineState * machine)1373 static void lm3s811evb_init(MachineState *machine)
1374 {
1375 stellaris_init(machine, &stellaris_boards[0]);
1376 }
1377
lm3s6965evb_init(MachineState * machine)1378 static void lm3s6965evb_init(MachineState *machine)
1379 {
1380 stellaris_init(machine, &stellaris_boards[1]);
1381 }
1382
lm3s811evb_class_init(ObjectClass * oc,void * data)1383 static void lm3s811evb_class_init(ObjectClass *oc, void *data)
1384 {
1385 MachineClass *mc = MACHINE_CLASS(oc);
1386
1387 mc->desc = "Stellaris LM3S811EVB (Cortex-M3)";
1388 mc->init = lm3s811evb_init;
1389 mc->ignore_memory_transaction_failures = true;
1390 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
1391 }
1392
1393 static const TypeInfo lm3s811evb_type = {
1394 .name = MACHINE_TYPE_NAME("lm3s811evb"),
1395 .parent = TYPE_MACHINE,
1396 .class_init = lm3s811evb_class_init,
1397 };
1398
lm3s6965evb_class_init(ObjectClass * oc,void * data)1399 static void lm3s6965evb_class_init(ObjectClass *oc, void *data)
1400 {
1401 MachineClass *mc = MACHINE_CLASS(oc);
1402
1403 mc->desc = "Stellaris LM3S6965EVB (Cortex-M3)";
1404 mc->init = lm3s6965evb_init;
1405 mc->ignore_memory_transaction_failures = true;
1406 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
1407 }
1408
1409 static const TypeInfo lm3s6965evb_type = {
1410 .name = MACHINE_TYPE_NAME("lm3s6965evb"),
1411 .parent = TYPE_MACHINE,
1412 .class_init = lm3s6965evb_class_init,
1413 };
1414
stellaris_machine_init(void)1415 static void stellaris_machine_init(void)
1416 {
1417 type_register_static(&lm3s811evb_type);
1418 type_register_static(&lm3s6965evb_type);
1419 }
1420
type_init(stellaris_machine_init)1421 type_init(stellaris_machine_init)
1422
1423 static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
1424 {
1425 DeviceClass *dc = DEVICE_CLASS(klass);
1426 ResettableClass *rc = RESETTABLE_CLASS(klass);
1427
1428 rc->phases.enter = stellaris_i2c_reset_enter;
1429 rc->phases.hold = stellaris_i2c_reset_hold;
1430 rc->phases.exit = stellaris_i2c_reset_exit;
1431 dc->vmsd = &vmstate_stellaris_i2c;
1432 }
1433
1434 static const TypeInfo stellaris_i2c_info = {
1435 .name = TYPE_STELLARIS_I2C,
1436 .parent = TYPE_SYS_BUS_DEVICE,
1437 .instance_size = sizeof(stellaris_i2c_state),
1438 .instance_init = stellaris_i2c_init,
1439 .class_init = stellaris_i2c_class_init,
1440 };
1441
stellaris_adc_class_init(ObjectClass * klass,void * data)1442 static void stellaris_adc_class_init(ObjectClass *klass, void *data)
1443 {
1444 DeviceClass *dc = DEVICE_CLASS(klass);
1445 ResettableClass *rc = RESETTABLE_CLASS(klass);
1446
1447 rc->phases.hold = stellaris_adc_reset_hold;
1448 dc->vmsd = &vmstate_stellaris_adc;
1449 }
1450
1451 static const TypeInfo stellaris_adc_info = {
1452 .name = TYPE_STELLARIS_ADC,
1453 .parent = TYPE_SYS_BUS_DEVICE,
1454 .instance_size = sizeof(StellarisADCState),
1455 .instance_init = stellaris_adc_init,
1456 .class_init = stellaris_adc_class_init,
1457 };
1458
stellaris_sys_class_init(ObjectClass * klass,void * data)1459 static void stellaris_sys_class_init(ObjectClass *klass, void *data)
1460 {
1461 DeviceClass *dc = DEVICE_CLASS(klass);
1462 ResettableClass *rc = RESETTABLE_CLASS(klass);
1463
1464 dc->vmsd = &vmstate_stellaris_sys;
1465 rc->phases.enter = stellaris_sys_reset_enter;
1466 rc->phases.hold = stellaris_sys_reset_hold;
1467 rc->phases.exit = stellaris_sys_reset_exit;
1468 device_class_set_props(dc, stellaris_sys_properties);
1469 }
1470
1471 static const TypeInfo stellaris_sys_info = {
1472 .name = TYPE_STELLARIS_SYS,
1473 .parent = TYPE_SYS_BUS_DEVICE,
1474 .instance_size = sizeof(ssys_state),
1475 .instance_init = stellaris_sys_instance_init,
1476 .class_init = stellaris_sys_class_init,
1477 };
1478
stellaris_register_types(void)1479 static void stellaris_register_types(void)
1480 {
1481 type_register_static(&stellaris_i2c_info);
1482 type_register_static(&stellaris_adc_info);
1483 type_register_static(&stellaris_sys_info);
1484 }
1485
1486 type_init(stellaris_register_types)
1487