1 /*
2 * STM32 RCC (only reset and enable registers are implemented)
3 *
4 * Copyright (c) 2024 Román Cárdenas <rcardenas.rod@gmail.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/log.h"
27 #include "trace.h"
28 #include "hw/irq.h"
29 #include "migration/vmstate.h"
30 #include "hw/misc/stm32_rcc.h"
31
stm32_rcc_reset(DeviceState * dev)32 static void stm32_rcc_reset(DeviceState *dev)
33 {
34 STM32RccState *s = STM32_RCC(dev);
35
36 for (int i = 0; i < STM32_RCC_NREGS; i++) {
37 s->regs[i] = 0;
38 }
39 }
40
stm32_rcc_read(void * opaque,hwaddr addr,unsigned int size)41 static uint64_t stm32_rcc_read(void *opaque, hwaddr addr, unsigned int size)
42 {
43 STM32RccState *s = STM32_RCC(opaque);
44
45 uint32_t value = 0;
46 if (addr > STM32_RCC_DCKCFGR2) {
47 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n",
48 __func__, addr);
49 } else {
50 value = s->regs[addr >> 2];
51 }
52 trace_stm32_rcc_read(addr, value);
53 return value;
54 }
55
stm32_rcc_write(void * opaque,hwaddr addr,uint64_t val64,unsigned int size)56 static void stm32_rcc_write(void *opaque, hwaddr addr,
57 uint64_t val64, unsigned int size)
58 {
59 STM32RccState *s = STM32_RCC(opaque);
60 uint32_t value = val64;
61 uint32_t prev_value, new_value, irq_offset;
62
63 trace_stm32_rcc_write(value, addr);
64
65 if (addr > STM32_RCC_DCKCFGR2) {
66 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n",
67 __func__, addr);
68 return;
69 }
70
71 switch (addr) {
72 case STM32_RCC_AHB1_RSTR...STM32_RCC_APB2_RSTR:
73 prev_value = s->regs[addr / 4];
74 s->regs[addr / 4] = value;
75
76 irq_offset = ((addr - STM32_RCC_AHB1_RSTR) / 4) * 32;
77 for (int i = 0; i < 32; i++) {
78 new_value = extract32(value, i, 1);
79 if (extract32(prev_value, i, 1) && !new_value) {
80 trace_stm32_rcc_pulse_reset(irq_offset + i, new_value);
81 qemu_set_irq(s->reset_irq[irq_offset + i], new_value);
82 }
83 }
84 return;
85 case STM32_RCC_AHB1_ENR...STM32_RCC_APB2_ENR:
86 prev_value = s->regs[addr / 4];
87 s->regs[addr / 4] = value;
88
89 irq_offset = ((addr - STM32_RCC_AHB1_ENR) / 4) * 32;
90 for (int i = 0; i < 32; i++) {
91 new_value = extract32(value, i, 1);
92 if (!extract32(prev_value, i, 1) && new_value) {
93 trace_stm32_rcc_pulse_enable(irq_offset + i, new_value);
94 qemu_set_irq(s->enable_irq[irq_offset + i], new_value);
95 }
96 }
97 return;
98 default:
99 qemu_log_mask(
100 LOG_UNIMP,
101 "%s: The RCC peripheral only supports enable and reset in QEMU\n",
102 __func__
103 );
104 s->regs[addr >> 2] = value;
105 }
106 }
107
108 static const MemoryRegionOps stm32_rcc_ops = {
109 .read = stm32_rcc_read,
110 .write = stm32_rcc_write,
111 .endianness = DEVICE_NATIVE_ENDIAN,
112 };
113
stm32_rcc_init(Object * obj)114 static void stm32_rcc_init(Object *obj)
115 {
116 STM32RccState *s = STM32_RCC(obj);
117
118 memory_region_init_io(&s->mmio, obj, &stm32_rcc_ops, s,
119 TYPE_STM32_RCC, STM32_RCC_PERIPHERAL_SIZE);
120 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
121
122 qdev_init_gpio_out(DEVICE(obj), s->reset_irq, STM32_RCC_NIRQS);
123 qdev_init_gpio_out(DEVICE(obj), s->enable_irq, STM32_RCC_NIRQS);
124
125 for (int i = 0; i < STM32_RCC_NIRQS; i++) {
126 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->reset_irq[i]);
127 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->enable_irq[i]);
128 }
129 }
130
131 static const VMStateDescription vmstate_stm32_rcc = {
132 .name = TYPE_STM32_RCC,
133 .version_id = 1,
134 .minimum_version_id = 1,
135 .fields = (const VMStateField[]) {
136 VMSTATE_UINT32_ARRAY(regs, STM32RccState, STM32_RCC_NREGS),
137 VMSTATE_END_OF_LIST()
138 }
139 };
140
stm32_rcc_class_init(ObjectClass * klass,void * data)141 static void stm32_rcc_class_init(ObjectClass *klass, void *data)
142 {
143 DeviceClass *dc = DEVICE_CLASS(klass);
144
145 dc->vmsd = &vmstate_stm32_rcc;
146 device_class_set_legacy_reset(dc, stm32_rcc_reset);
147 }
148
149 static const TypeInfo stm32_rcc_info = {
150 .name = TYPE_STM32_RCC,
151 .parent = TYPE_SYS_BUS_DEVICE,
152 .instance_size = sizeof(STM32RccState),
153 .instance_init = stm32_rcc_init,
154 .class_init = stm32_rcc_class_init,
155 };
156
stm32_rcc_register_types(void)157 static void stm32_rcc_register_types(void)
158 {
159 type_register_static(&stm32_rcc_info);
160 }
161
162 type_init(stm32_rcc_register_types)
163