1 /*
2 * PowerMac NewWorld MacIO GPIO emulation
3 *
4 * Copyright (c) 2016 Benjamin Herrenschmidt
5 * Copyright (c) 2018 Mark Cave-Ayland
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "qemu/osdep.h"
27 #include "hw/qdev-properties.h"
28 #include "migration/vmstate.h"
29 #include "hw/misc/macio/macio.h"
30 #include "hw/misc/macio/gpio.h"
31 #include "hw/irq.h"
32 #include "hw/nmi.h"
33 #include "qemu/log.h"
34 #include "qemu/module.h"
35 #include "trace.h"
36
37
macio_set_gpio(MacIOGPIOState * s,uint32_t gpio,bool state)38 void macio_set_gpio(MacIOGPIOState *s, uint32_t gpio, bool state)
39 {
40 uint8_t new_reg;
41
42 trace_macio_set_gpio(gpio, state);
43
44 if (s->gpio_regs[gpio] & 4) {
45 qemu_log_mask(LOG_GUEST_ERROR,
46 "GPIO: Setting GPIO %d while it's an output\n", gpio);
47 }
48
49 new_reg = s->gpio_regs[gpio] & ~2;
50 if (state) {
51 new_reg |= 2;
52 }
53
54 if (new_reg == s->gpio_regs[gpio]) {
55 return;
56 }
57
58 s->gpio_regs[gpio] = new_reg;
59
60 /*
61 * Note that we probably need to get access to the MPIC config to
62 * decode polarity since qemu always use "raise" regardless.
63 *
64 * For now, we hard wire known GPIOs
65 */
66
67 switch (gpio) {
68 case 1:
69 /* Level low */
70 if (!state) {
71 trace_macio_gpio_irq_assert(gpio);
72 qemu_irq_raise(s->gpio_extirqs[gpio]);
73 } else {
74 trace_macio_gpio_irq_deassert(gpio);
75 qemu_irq_lower(s->gpio_extirqs[gpio]);
76 }
77 break;
78
79 case 9:
80 /* Edge, triggered by NMI below */
81 if (state) {
82 trace_macio_gpio_irq_assert(gpio);
83 qemu_irq_raise(s->gpio_extirqs[gpio]);
84 } else {
85 trace_macio_gpio_irq_deassert(gpio);
86 qemu_irq_lower(s->gpio_extirqs[gpio]);
87 }
88 break;
89
90 default:
91 qemu_log_mask(LOG_UNIMP, "GPIO: setting unimplemented GPIO %d", gpio);
92 }
93 }
94
macio_gpio_write(void * opaque,hwaddr addr,uint64_t value,unsigned size)95 static void macio_gpio_write(void *opaque, hwaddr addr, uint64_t value,
96 unsigned size)
97 {
98 MacIOGPIOState *s = opaque;
99 uint8_t ibit;
100
101 trace_macio_gpio_write(addr, value);
102
103 /* Levels regs are read-only */
104 if (addr < 8) {
105 return;
106 }
107
108 addr -= 8;
109 if (addr < 36) {
110 value &= ~2;
111
112 if (value & 4) {
113 ibit = (value & 1) << 1;
114 } else {
115 ibit = s->gpio_regs[addr] & 2;
116 }
117
118 s->gpio_regs[addr] = value | ibit;
119 }
120 }
121
macio_gpio_read(void * opaque,hwaddr addr,unsigned size)122 static uint64_t macio_gpio_read(void *opaque, hwaddr addr, unsigned size)
123 {
124 MacIOGPIOState *s = opaque;
125 uint64_t val = 0;
126
127 /* Levels regs */
128 if (addr < 8) {
129 val = s->gpio_levels[addr];
130 } else {
131 addr -= 8;
132
133 if (addr < 36) {
134 val = s->gpio_regs[addr];
135 }
136 }
137
138 trace_macio_gpio_write(addr, val);
139 return val;
140 }
141
142 static const MemoryRegionOps macio_gpio_ops = {
143 .read = macio_gpio_read,
144 .write = macio_gpio_write,
145 .endianness = DEVICE_LITTLE_ENDIAN,
146 .impl = {
147 .min_access_size = 1,
148 .max_access_size = 1,
149 },
150 };
151
macio_gpio_init(Object * obj)152 static void macio_gpio_init(Object *obj)
153 {
154 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
155 MacIOGPIOState *s = MACIO_GPIO(obj);
156 int i;
157
158 for (i = 0; i < 10; i++) {
159 sysbus_init_irq(sbd, &s->gpio_extirqs[i]);
160 }
161
162 memory_region_init_io(&s->gpiomem, OBJECT(s), &macio_gpio_ops, obj,
163 "gpio", 0x30);
164 sysbus_init_mmio(sbd, &s->gpiomem);
165 }
166
167 static const VMStateDescription vmstate_macio_gpio = {
168 .name = "macio_gpio",
169 .version_id = 0,
170 .minimum_version_id = 0,
171 .fields = (const VMStateField[]) {
172 VMSTATE_UINT8_ARRAY(gpio_levels, MacIOGPIOState, 8),
173 VMSTATE_UINT8_ARRAY(gpio_regs, MacIOGPIOState, 36),
174 VMSTATE_END_OF_LIST()
175 }
176 };
177
macio_gpio_reset(DeviceState * dev)178 static void macio_gpio_reset(DeviceState *dev)
179 {
180 MacIOGPIOState *s = MACIO_GPIO(dev);
181
182 /* GPIO 1 is up by default */
183 macio_set_gpio(s, 1, true);
184 }
185
macio_gpio_nmi(NMIState * n,int cpu_index,Error ** errp)186 static void macio_gpio_nmi(NMIState *n, int cpu_index, Error **errp)
187 {
188 macio_set_gpio(MACIO_GPIO(n), 9, true);
189 macio_set_gpio(MACIO_GPIO(n), 9, false);
190 }
191
macio_gpio_class_init(ObjectClass * oc,void * data)192 static void macio_gpio_class_init(ObjectClass *oc, void *data)
193 {
194 DeviceClass *dc = DEVICE_CLASS(oc);
195 NMIClass *nc = NMI_CLASS(oc);
196
197 dc->reset = macio_gpio_reset;
198 dc->vmsd = &vmstate_macio_gpio;
199 nc->nmi_monitor_handler = macio_gpio_nmi;
200 }
201
202 static const TypeInfo macio_gpio_init_info = {
203 .name = TYPE_MACIO_GPIO,
204 .parent = TYPE_SYS_BUS_DEVICE,
205 .instance_size = sizeof(MacIOGPIOState),
206 .instance_init = macio_gpio_init,
207 .class_init = macio_gpio_class_init,
208 .interfaces = (InterfaceInfo[]) {
209 { TYPE_NMI },
210 { }
211 },
212 };
213
macio_gpio_register_types(void)214 static void macio_gpio_register_types(void)
215 {
216 type_register_static(&macio_gpio_init_info);
217 }
218
219 type_init(macio_gpio_register_types)
220