1 /* 2 * ASPEED Hash and Crypto Engine 3 * 4 * Copyright (c) 2024 Seagate Technology LLC and/or its Affiliates 5 * Copyright (C) 2021 IBM Corp. 6 * 7 * SPDX-License-Identifier: GPL-2.0-or-later 8 */ 9 10 #ifndef ASPEED_HACE_H 11 #define ASPEED_HACE_H 12 13 #include "hw/sysbus.h" 14 #include "crypto/hash.h" 15 16 #define TYPE_ASPEED_HACE "aspeed.hace" 17 #define TYPE_ASPEED_AST2400_HACE TYPE_ASPEED_HACE "-ast2400" 18 #define TYPE_ASPEED_AST2500_HACE TYPE_ASPEED_HACE "-ast2500" 19 #define TYPE_ASPEED_AST2600_HACE TYPE_ASPEED_HACE "-ast2600" 20 #define TYPE_ASPEED_AST1030_HACE TYPE_ASPEED_HACE "-ast1030" 21 #define TYPE_ASPEED_AST2700_HACE TYPE_ASPEED_HACE "-ast2700" 22 23 OBJECT_DECLARE_TYPE(AspeedHACEState, AspeedHACEClass, ASPEED_HACE) 24 25 #define ASPEED_HACE_NR_REGS (0x9C >> 2) 26 #define ASPEED_HACE_MAX_SG 256 /* max number of entries */ 27 28 struct AspeedHACEState { 29 SysBusDevice parent; 30 31 MemoryRegion iomem; 32 qemu_irq irq; 33 34 uint32_t regs[ASPEED_HACE_NR_REGS]; 35 uint32_t total_req_len; 36 37 MemoryRegion *dram_mr; 38 AddressSpace dram_as; 39 40 QCryptoHash *hash_ctx; 41 }; 42 43 44 struct AspeedHACEClass { 45 SysBusDeviceClass parent_class; 46 47 uint32_t src_mask; 48 uint32_t dest_mask; 49 uint32_t key_mask; 50 uint32_t hash_mask; 51 bool raise_crypt_interrupt_workaround; 52 uint32_t src_hi_mask; 53 uint32_t dest_hi_mask; 54 uint32_t key_hi_mask; 55 bool has_dma64; 56 uint64_t mem_size; 57 }; 58 59 #endif /* ASPEED_HACE_H */ 60