xref: /openbmc/qemu/include/hw/i3c/aspeed_i3c.h (revision fd85e880b9f68a307f373751e9d714ea553e8466) 
1 /*
2  * ASPEED I3C Controller
3  *
4  * Copyright (C) 2021 ASPEED Technology Inc.
5  * Copyright (C) 2023 Google, LLC
6  *
7  * This code is licensed under the GPL version 2 or later.  See
8  * the COPYING file in the top-level directory.
9  */
10 
11 #ifndef ASPEED_I3C_H
12 #define ASPEED_I3C_H
13 
14 #include "hw/i3c/dw-i3c.h"
15 #include "hw/sysbus.h"
16 
17 #define TYPE_ASPEED_I3C "aspeed.i3c"
18 OBJECT_DECLARE_TYPE(AspeedI3CState, AspeedI3CClass, ASPEED_I3C)
19 
20 #define ASPEED_I3C_NR_REGS (0x70 >> 2)
21 #define ASPEED_I3C_NR_DEVICES 6
22 
23 typedef struct AspeedI3CState {
24     /* <private> */
25     SysBusDevice parent;
26 
27     /* <public> */
28     MemoryRegion iomem;
29     MemoryRegion iomem_container;
30     qemu_irq irq;
31 
32     uint32_t regs[ASPEED_I3C_NR_REGS];
33     DWI3C devices[ASPEED_I3C_NR_DEVICES];
34     uint8_t id;
35 } AspeedI3CState;
36 #endif /* ASPEED_I3C_H */
37 
38 I3CBus *aspeed_i3c_get_bus(AspeedI3CState *s, uint8_t bus_num);
39