1 /* 2 * MAX78000 SOC 3 * 4 * Copyright (c) 2025 Jackson Donaldson <jcksn@duck.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #ifndef HW_ARM_MAX78000_SOC_H 10 #define HW_ARM_MAX78000_SOC_H 11 12 #include "hw/or-irq.h" 13 #include "hw/arm/armv7m.h" 14 #include "hw/misc/max78000_aes.h" 15 #include "hw/misc/max78000_gcr.h" 16 #include "hw/misc/max78000_icc.h" 17 #include "hw/char/max78000_uart.h" 18 #include "hw/misc/max78000_trng.h" 19 #include "qom/object.h" 20 21 #define TYPE_MAX78000_SOC "max78000-soc" 22 OBJECT_DECLARE_SIMPLE_TYPE(MAX78000State, MAX78000_SOC) 23 24 #define FLASH_BASE_ADDRESS 0x10000000 25 #define FLASH_SIZE (512 * 1024) 26 #define SRAM_BASE_ADDRESS 0x20000000 27 #define SRAM_SIZE (128 * 1024) 28 29 /* The MAX78k has 2 instruction caches; only icc0 matters, icc1 is for RISC */ 30 #define MAX78000_NUM_ICC 2 31 #define MAX78000_NUM_UART 3 32 33 struct MAX78000State { 34 SysBusDevice parent_obj; 35 36 ARMv7MState armv7m; 37 38 MemoryRegion sram; 39 MemoryRegion flash; 40 41 Max78000GcrState gcr; 42 Max78000IccState icc[MAX78000_NUM_ICC]; 43 Max78000UartState uart[MAX78000_NUM_UART]; 44 Max78000TrngState trng; 45 Max78000AesState aes; 46 47 Clock *sysclk; 48 }; 49 50 #endif 51