xref: /openbmc/linux/arch/sparc/kernel/hvtramp.S (revision b2441318)
1/* SPDX-License-Identifier: GPL-2.0 */
2/* hvtramp.S: Hypervisor start-cpu trampoline code.
3 *
4 * Copyright (C) 2007, 2008 David S. Miller <davem@davemloft.net>
5 */
6
7
8#include <asm/thread_info.h>
9#include <asm/hypervisor.h>
10#include <asm/scratchpad.h>
11#include <asm/spitfire.h>
12#include <asm/hvtramp.h>
13#include <asm/pstate.h>
14#include <asm/ptrace.h>
15#include <asm/head.h>
16#include <asm/asi.h>
17#include <asm/pil.h>
18
19	.align		8
20	.globl		hv_cpu_startup, hv_cpu_startup_end
21
22	/* This code executes directly out of the hypervisor
23	 * with physical addressing (va==pa).  %o0 contains
24	 * our client argument which for Linux points to
25	 * a descriptor data structure which defines the
26	 * MMU entries we need to load up.
27	 *
28	 * After we set things up we enable the MMU and call
29	 * into the kernel.
30	 *
31	 * First setup basic privileged cpu state.
32	 */
33hv_cpu_startup:
34	SET_GL(0)
35	wrpr		%g0, PIL_NORMAL_MAX, %pil
36	wrpr		%g0, 0, %canrestore
37	wrpr		%g0, 0, %otherwin
38	wrpr		%g0, 6, %cansave
39	wrpr		%g0, 6, %cleanwin
40	wrpr		%g0, 0, %cwp
41	wrpr		%g0, 0, %wstate
42	wrpr		%g0, 0, %tl
43
44	sethi		%hi(sparc64_ttable_tl0), %g1
45	wrpr		%g1, %tba
46
47	mov		%o0, %l0
48
49	lduw		[%l0 + HVTRAMP_DESCR_CPU], %g1
50	mov		SCRATCHPAD_CPUID, %g2
51	stxa		%g1, [%g2] ASI_SCRATCHPAD
52
53	ldx		[%l0 + HVTRAMP_DESCR_FAULT_INFO_VA], %g2
54	stxa		%g2, [%g0] ASI_SCRATCHPAD
55
56	mov		0, %l1
57	lduw		[%l0 + HVTRAMP_DESCR_NUM_MAPPINGS], %l2
58	add		%l0, HVTRAMP_DESCR_MAPS, %l3
59
601:	ldx		[%l3 + HVTRAMP_MAPPING_VADDR], %o0
61	clr		%o1
62	ldx		[%l3 + HVTRAMP_MAPPING_TTE], %o2
63	mov		HV_MMU_IMMU | HV_MMU_DMMU, %o3
64	mov		HV_FAST_MMU_MAP_PERM_ADDR, %o5
65	ta		HV_FAST_TRAP
66
67	brnz,pn		%o0, 80f
68	 nop
69
70	add		%l1, 1, %l1
71	cmp		%l1, %l2
72	blt,a,pt	%xcc, 1b
73	 add		%l3, HVTRAMP_MAPPING_SIZE, %l3
74
75	ldx		[%l0 + HVTRAMP_DESCR_FAULT_INFO_PA], %o0
76	mov		HV_FAST_MMU_FAULT_AREA_CONF, %o5
77	ta		HV_FAST_TRAP
78
79	brnz,pn		%o0, 80f
80	 nop
81
82	wrpr		%g0, (PSTATE_PRIV | PSTATE_PEF), %pstate
83
84	ldx		[%l0 + HVTRAMP_DESCR_THREAD_REG], %l6
85
86	mov		1, %o0
87	set		1f, %o1
88	mov		HV_FAST_MMU_ENABLE, %o5
89	ta		HV_FAST_TRAP
90
91	ba,pt		%xcc, 80f
92	 nop
93
941:
95	wr		%g0, 0, %fprs
96	wr		%g0, ASI_P, %asi
97
98	mov		PRIMARY_CONTEXT, %g7
99	stxa		%g0, [%g7] ASI_MMU
100	membar		#Sync
101
102	mov		SECONDARY_CONTEXT, %g7
103	stxa		%g0, [%g7] ASI_MMU
104	membar		#Sync
105
106	mov		%l6, %g6
107	ldx		[%g6 + TI_TASK], %g4
108
109	mov		1, %g5
110	sllx		%g5, THREAD_SHIFT, %g5
111	sub		%g5, (STACKFRAME_SZ + STACK_BIAS), %g5
112	add		%g6, %g5, %sp
113
114	call		init_irqwork_curcpu
115	 nop
116	call		hard_smp_processor_id
117	 nop
118
119	call		sun4v_register_mondo_queues
120	 nop
121
122	call		init_cur_cpu_trap
123	 mov		%g6, %o0
124
125	wrpr		%g0, (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE), %pstate
126
127	call		smp_callin
128	 nop
129
130	call		cpu_panic
131	 nop
132
13380:	ba,pt		%xcc, 80b
134	 nop
135
136	.align		8
137hv_cpu_startup_end:
138