1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2022 Intel Corporation
4  */
5 
6 #ifndef __INTEL_GT_MCR__
7 #define __INTEL_GT_MCR__
8 
9 #include "intel_gt_types.h"
10 
11 void intel_gt_mcr_init(struct intel_gt *gt);
12 void intel_gt_mcr_lock(struct intel_gt *gt, unsigned long *flags);
13 void intel_gt_mcr_unlock(struct intel_gt *gt, unsigned long flags);
14 
15 u32 intel_gt_mcr_read(struct intel_gt *gt,
16 		      i915_mcr_reg_t reg,
17 		      int group, int instance);
18 u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_mcr_reg_t reg);
19 u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_mcr_reg_t reg);
20 
21 void intel_gt_mcr_unicast_write(struct intel_gt *gt,
22 				i915_mcr_reg_t reg, u32 value,
23 				int group, int instance);
24 void intel_gt_mcr_multicast_write(struct intel_gt *gt,
25 				  i915_mcr_reg_t reg, u32 value);
26 void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt,
27 				     i915_mcr_reg_t reg, u32 value);
28 
29 u32 intel_gt_mcr_multicast_rmw(struct intel_gt *gt, i915_mcr_reg_t reg,
30 			       u32 clear, u32 set);
31 
32 void intel_gt_mcr_get_nonterminated_steering(struct intel_gt *gt,
33 					     i915_mcr_reg_t reg,
34 					     u8 *group, u8 *instance);
35 
36 void intel_gt_mcr_report_steering(struct drm_printer *p, struct intel_gt *gt,
37 				  bool dump_table);
38 
39 void intel_gt_mcr_get_ss_steering(struct intel_gt *gt, unsigned int dss,
40 				  unsigned int *group, unsigned int *instance);
41 
42 int intel_gt_mcr_wait_for_reg(struct intel_gt *gt,
43 			      i915_mcr_reg_t reg,
44 			      u32 mask,
45 			      u32 value,
46 			      unsigned int fast_timeout_us,
47 			      unsigned int slow_timeout_ms);
48 
49 /*
50  * Helper for for_each_ss_steering loop.  On pre-Xe_HP platforms, subslice
51  * presence is determined by using the group/instance as direct lookups in the
52  * slice/subslice topology.  On Xe_HP and beyond, the steering is unrelated to
53  * the topology, so we lookup the DSS ID directly in "slice 0."
54  */
55 #define _HAS_SS(ss_, gt_, group_, instance_) ( \
56 	GRAPHICS_VER_FULL(gt_->i915) >= IP_VER(12, 50) ? \
57 		intel_sseu_has_subslice(&(gt_)->info.sseu, 0, ss_) : \
58 		intel_sseu_has_subslice(&(gt_)->info.sseu, group_, instance_))
59 
60 /*
61  * Loop over each subslice/DSS and determine the group and instance IDs that
62  * should be used to steer MCR accesses toward this DSS.
63  */
64 #define for_each_ss_steering(ss_, gt_, group_, instance_) \
65 	for (ss_ = 0, intel_gt_mcr_get_ss_steering(gt_, 0, &group_, &instance_); \
66 	     ss_ < I915_MAX_SS_FUSE_BITS; \
67 	     ss_++, intel_gt_mcr_get_ss_steering(gt_, ss_, &group_, &instance_)) \
68 		for_each_if(_HAS_SS(ss_, gt_, group_, instance_))
69 
70 #endif /* __INTEL_GT_MCR__ */
71