1 /*
2  * Copyright (C) 2019  Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included
12  * in all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20  */
21 
22 #ifndef _gc_10_3_0_OFFSET_HEADER
23 #define _gc_10_3_0_OFFSET_HEADER
24 
25 #define mmSQ_DEBUG_STS_GLOBAL                                                                          0x10A9
26 #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX                                                                 0
27 #define mmSQ_DEBUG_STS_GLOBAL2                                                                         0x10B0
28 #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX                                                                0
29 #define mmSQ_DEBUG                                                                                     0x10B1
30 #define mmSQ_DEBUG_BASE_IDX                                                                            0
31 
32 // addressBlock: gc_sdma0_sdma0dec
33 // base address: 0x4980
34 #define mmSDMA0_DEC_START                                                                              0x0000
35 #define mmSDMA0_DEC_START_BASE_IDX                                                                     0
36 #define mmSDMA0_GLOBAL_TIMESTAMP_LO                                                                    0x000f
37 #define mmSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX                                                           0
38 #define mmSDMA0_GLOBAL_TIMESTAMP_HI                                                                    0x0010
39 #define mmSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX                                                           0
40 #define mmSDMA0_PG_CNTL                                                                                0x0016
41 #define mmSDMA0_PG_CNTL_BASE_IDX                                                                       0
42 #define mmSDMA0_PG_CTX_LO                                                                              0x0017
43 #define mmSDMA0_PG_CTX_LO_BASE_IDX                                                                     0
44 #define mmSDMA0_PG_CTX_HI                                                                              0x0018
45 #define mmSDMA0_PG_CTX_HI_BASE_IDX                                                                     0
46 #define mmSDMA0_PG_CTX_CNTL                                                                            0x0019
47 #define mmSDMA0_PG_CTX_CNTL_BASE_IDX                                                                   0
48 #define mmSDMA0_POWER_CNTL                                                                             0x001a
49 #define mmSDMA0_POWER_CNTL_BASE_IDX                                                                    0
50 #define mmSDMA0_CLK_CTRL                                                                               0x001b
51 #define mmSDMA0_CLK_CTRL_BASE_IDX                                                                      0
52 #define mmSDMA0_CNTL                                                                                   0x001c
53 #define mmSDMA0_CNTL_BASE_IDX                                                                          0
54 #define mmSDMA0_CHICKEN_BITS                                                                           0x001d
55 #define mmSDMA0_CHICKEN_BITS_BASE_IDX                                                                  0
56 #define mmSDMA0_GB_ADDR_CONFIG                                                                         0x001e
57 #define mmSDMA0_GB_ADDR_CONFIG_BASE_IDX                                                                0
58 #define mmSDMA0_GB_ADDR_CONFIG_READ                                                                    0x001f
59 #define mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX                                                           0
60 #define mmSDMA0_RB_RPTR_FETCH_HI                                                                       0x0020
61 #define mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX                                                              0
62 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL                                                               0x0021
63 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX                                                      0
64 #define mmSDMA0_RB_RPTR_FETCH                                                                          0x0022
65 #define mmSDMA0_RB_RPTR_FETCH_BASE_IDX                                                                 0
66 #define mmSDMA0_IB_OFFSET_FETCH                                                                        0x0023
67 #define mmSDMA0_IB_OFFSET_FETCH_BASE_IDX                                                               0
68 #define mmSDMA0_PROGRAM                                                                                0x0024
69 #define mmSDMA0_PROGRAM_BASE_IDX                                                                       0
70 #define mmSDMA0_STATUS_REG                                                                             0x0025
71 #define mmSDMA0_STATUS_REG_BASE_IDX                                                                    0
72 #define mmSDMA0_STATUS1_REG                                                                            0x0026
73 #define mmSDMA0_STATUS1_REG_BASE_IDX                                                                   0
74 #define mmSDMA0_RD_BURST_CNTL                                                                          0x0027
75 #define mmSDMA0_RD_BURST_CNTL_BASE_IDX                                                                 0
76 #define mmSDMA0_HBM_PAGE_CONFIG                                                                        0x0028
77 #define mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX                                                               0
78 #define mmSDMA0_UCODE_CHECKSUM                                                                         0x0029
79 #define mmSDMA0_UCODE_CHECKSUM_BASE_IDX                                                                0
80 #define mmSDMA0_F32_CNTL                                                                               0x002a
81 #define mmSDMA0_F32_CNTL_BASE_IDX                                                                      0
82 #define mmSDMA0_FREEZE                                                                                 0x002b
83 #define mmSDMA0_FREEZE_BASE_IDX                                                                        0
84 #define mmSDMA0_PHASE0_QUANTUM                                                                         0x002c
85 #define mmSDMA0_PHASE0_QUANTUM_BASE_IDX                                                                0
86 #define mmSDMA0_PHASE1_QUANTUM                                                                         0x002d
87 #define mmSDMA0_PHASE1_QUANTUM_BASE_IDX                                                                0
88 #define mmSDMA0_EDC_CONFIG                                                                             0x0032
89 #define mmSDMA0_EDC_CONFIG_BASE_IDX                                                                    0
90 #define mmSDMA0_BA_THRESHOLD                                                                           0x0033
91 #define mmSDMA0_BA_THRESHOLD_BASE_IDX                                                                  0
92 #define mmSDMA0_ID                                                                                     0x0034
93 #define mmSDMA0_ID_BASE_IDX                                                                            0
94 #define mmSDMA0_VERSION                                                                                0x0035
95 #define mmSDMA0_VERSION_BASE_IDX                                                                       0
96 #define mmSDMA0_EDC_COUNTER                                                                            0x0036
97 #define mmSDMA0_EDC_COUNTER_BASE_IDX                                                                   0
98 #define mmSDMA0_EDC_COUNTER_CLEAR                                                                      0x0037
99 #define mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX                                                             0
100 #define mmSDMA0_STATUS2_REG                                                                            0x0038
101 #define mmSDMA0_STATUS2_REG_BASE_IDX                                                                   0
102 #define mmSDMA0_ATOMIC_CNTL                                                                            0x0039
103 #define mmSDMA0_ATOMIC_CNTL_BASE_IDX                                                                   0
104 #define mmSDMA0_ATOMIC_PREOP_LO                                                                        0x003a
105 #define mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX                                                               0
106 #define mmSDMA0_ATOMIC_PREOP_HI                                                                        0x003b
107 #define mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX                                                               0
108 #define mmSDMA0_UTCL1_CNTL                                                                             0x003c
109 #define mmSDMA0_UTCL1_CNTL_BASE_IDX                                                                    0
110 #define mmSDMA0_UTCL1_WATERMK                                                                          0x003d
111 #define mmSDMA0_UTCL1_WATERMK_BASE_IDX                                                                 0
112 #define mmSDMA0_UTCL1_RD_STATUS                                                                        0x003e
113 #define mmSDMA0_UTCL1_RD_STATUS_BASE_IDX                                                               0
114 #define mmSDMA0_UTCL1_WR_STATUS                                                                        0x003f
115 #define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX                                                               0
116 #define mmSDMA0_UTCL1_INV0                                                                             0x0040
117 #define mmSDMA0_UTCL1_INV0_BASE_IDX                                                                    0
118 #define mmSDMA0_UTCL1_INV1                                                                             0x0041
119 #define mmSDMA0_UTCL1_INV1_BASE_IDX                                                                    0
120 #define mmSDMA0_UTCL1_INV2                                                                             0x0042
121 #define mmSDMA0_UTCL1_INV2_BASE_IDX                                                                    0
122 #define mmSDMA0_UTCL1_RD_XNACK0                                                                        0x0043
123 #define mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX                                                               0
124 #define mmSDMA0_UTCL1_RD_XNACK1                                                                        0x0044
125 #define mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX                                                               0
126 #define mmSDMA0_UTCL1_WR_XNACK0                                                                        0x0045
127 #define mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX                                                               0
128 #define mmSDMA0_UTCL1_WR_XNACK1                                                                        0x0046
129 #define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX                                                               0
130 #define mmSDMA0_UTCL1_TIMEOUT                                                                          0x0047
131 #define mmSDMA0_UTCL1_TIMEOUT_BASE_IDX                                                                 0
132 #define mmSDMA0_UTCL1_PAGE                                                                             0x0048
133 #define mmSDMA0_UTCL1_PAGE_BASE_IDX                                                                    0
134 #define mmSDMA0_RELAX_ORDERING_LUT                                                                     0x004a
135 #define mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX                                                            0
136 #define mmSDMA0_CHICKEN_BITS_2                                                                         0x004b
137 #define mmSDMA0_CHICKEN_BITS_2_BASE_IDX                                                                0
138 #define mmSDMA0_STATUS3_REG                                                                            0x004c
139 #define mmSDMA0_STATUS3_REG_BASE_IDX                                                                   0
140 #define mmSDMA0_PHYSICAL_ADDR_LO                                                                       0x004d
141 #define mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX                                                              0
142 #define mmSDMA0_PHYSICAL_ADDR_HI                                                                       0x004e
143 #define mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX                                                              0
144 #define mmSDMA0_PHASE2_QUANTUM                                                                         0x004f
145 #define mmSDMA0_PHASE2_QUANTUM_BASE_IDX                                                                0
146 #define mmSDMA0_ERROR_LOG                                                                              0x0050
147 #define mmSDMA0_ERROR_LOG_BASE_IDX                                                                     0
148 #define mmSDMA0_PUB_DUMMY_REG0                                                                         0x0051
149 #define mmSDMA0_PUB_DUMMY_REG0_BASE_IDX                                                                0
150 #define mmSDMA0_PUB_DUMMY_REG1                                                                         0x0052
151 #define mmSDMA0_PUB_DUMMY_REG1_BASE_IDX                                                                0
152 #define mmSDMA0_PUB_DUMMY_REG2                                                                         0x0053
153 #define mmSDMA0_PUB_DUMMY_REG2_BASE_IDX                                                                0
154 #define mmSDMA0_PUB_DUMMY_REG3                                                                         0x0054
155 #define mmSDMA0_PUB_DUMMY_REG3_BASE_IDX                                                                0
156 #define mmSDMA0_F32_COUNTER                                                                            0x0055
157 #define mmSDMA0_F32_COUNTER_BASE_IDX                                                                   0
158 #define mmSDMA0_CRD_CNTL                                                                               0x005b
159 #define mmSDMA0_CRD_CNTL_BASE_IDX                                                                      0
160 #define mmSDMA0_AQL_STATUS                                                                             0x005f
161 #define mmSDMA0_AQL_STATUS_BASE_IDX                                                                    0
162 #define mmSDMA0_EA_DBIT_ADDR_DATA                                                                      0x0060
163 #define mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX                                                             0
164 #define mmSDMA0_EA_DBIT_ADDR_INDEX                                                                     0x0061
165 #define mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX                                                            0
166 #define mmSDMA0_TLBI_GCR_CNTL                                                                          0x0062
167 #define mmSDMA0_TLBI_GCR_CNTL_BASE_IDX                                                                 0
168 #define mmSDMA0_TILING_CONFIG                                                                          0x0063
169 #define mmSDMA0_TILING_CONFIG_BASE_IDX                                                                 0
170 #define mmSDMA0_INT_STATUS                                                                             0x0070
171 #define mmSDMA0_INT_STATUS_BASE_IDX                                                                    0
172 #define mmSDMA0_HOLE_ADDR_LO                                                                           0x0072
173 #define mmSDMA0_HOLE_ADDR_LO_BASE_IDX                                                                  0
174 #define mmSDMA0_HOLE_ADDR_HI                                                                           0x0073
175 #define mmSDMA0_HOLE_ADDR_HI_BASE_IDX                                                                  0
176 #define mmSDMA0_CLOCK_GATING_REG                                                                       0x0075
177 #define mmSDMA0_CLOCK_GATING_REG_BASE_IDX                                                              0
178 #define mmSDMA0_STATUS4_REG                                                                            0x0076
179 #define mmSDMA0_STATUS4_REG_BASE_IDX                                                                   0
180 #define mmSDMA0_SCRATCH_RAM_DATA                                                                       0x0077
181 #define mmSDMA0_SCRATCH_RAM_DATA_BASE_IDX                                                              0
182 #define mmSDMA0_SCRATCH_RAM_ADDR                                                                       0x0078
183 #define mmSDMA0_SCRATCH_RAM_ADDR_BASE_IDX                                                              0
184 #define mmSDMA0_TIMESTAMP_CNTL                                                                         0x0079
185 #define mmSDMA0_TIMESTAMP_CNTL_BASE_IDX                                                                0
186 #define mmSDMA0_STATUS5_REG                                                                            0x007a
187 #define mmSDMA0_STATUS5_REG_BASE_IDX                                                                   0
188 #define mmSDMA0_QUEUE_RESET_REQ                                                                        0x007b
189 #define mmSDMA0_QUEUE_RESET_REQ_BASE_IDX                                                               0
190 #define mmSDMA0_GFX_RB_CNTL                                                                            0x0080
191 #define mmSDMA0_GFX_RB_CNTL_BASE_IDX                                                                   0
192 #define mmSDMA0_GFX_RB_BASE                                                                            0x0081
193 #define mmSDMA0_GFX_RB_BASE_BASE_IDX                                                                   0
194 #define mmSDMA0_GFX_RB_BASE_HI                                                                         0x0082
195 #define mmSDMA0_GFX_RB_BASE_HI_BASE_IDX                                                                0
196 #define mmSDMA0_GFX_RB_RPTR                                                                            0x0083
197 #define mmSDMA0_GFX_RB_RPTR_BASE_IDX                                                                   0
198 #define mmSDMA0_GFX_RB_RPTR_HI                                                                         0x0084
199 #define mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX                                                                0
200 #define mmSDMA0_GFX_RB_WPTR                                                                            0x0085
201 #define mmSDMA0_GFX_RB_WPTR_BASE_IDX                                                                   0
202 #define mmSDMA0_GFX_RB_WPTR_HI                                                                         0x0086
203 #define mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX                                                                0
204 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL                                                                  0x0087
205 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX                                                         0
206 #define mmSDMA0_GFX_RB_RPTR_ADDR_HI                                                                    0x0088
207 #define mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX                                                           0
208 #define mmSDMA0_GFX_RB_RPTR_ADDR_LO                                                                    0x0089
209 #define mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX                                                           0
210 #define mmSDMA0_GFX_IB_CNTL                                                                            0x008a
211 #define mmSDMA0_GFX_IB_CNTL_BASE_IDX                                                                   0
212 #define mmSDMA0_GFX_IB_RPTR                                                                            0x008b
213 #define mmSDMA0_GFX_IB_RPTR_BASE_IDX                                                                   0
214 #define mmSDMA0_GFX_IB_OFFSET                                                                          0x008c
215 #define mmSDMA0_GFX_IB_OFFSET_BASE_IDX                                                                 0
216 #define mmSDMA0_GFX_IB_BASE_LO                                                                         0x008d
217 #define mmSDMA0_GFX_IB_BASE_LO_BASE_IDX                                                                0
218 #define mmSDMA0_GFX_IB_BASE_HI                                                                         0x008e
219 #define mmSDMA0_GFX_IB_BASE_HI_BASE_IDX                                                                0
220 #define mmSDMA0_GFX_IB_SIZE                                                                            0x008f
221 #define mmSDMA0_GFX_IB_SIZE_BASE_IDX                                                                   0
222 #define mmSDMA0_GFX_SKIP_CNTL                                                                          0x0090
223 #define mmSDMA0_GFX_SKIP_CNTL_BASE_IDX                                                                 0
224 #define mmSDMA0_GFX_CONTEXT_STATUS                                                                     0x0091
225 #define mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX                                                            0
226 #define mmSDMA0_GFX_DOORBELL                                                                           0x0092
227 #define mmSDMA0_GFX_DOORBELL_BASE_IDX                                                                  0
228 #define mmSDMA0_GFX_CONTEXT_CNTL                                                                       0x0093
229 #define mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX                                                              0
230 #define mmSDMA0_GFX_STATUS                                                                             0x00a8
231 #define mmSDMA0_GFX_STATUS_BASE_IDX                                                                    0
232 #define mmSDMA0_GFX_DOORBELL_LOG                                                                       0x00a9
233 #define mmSDMA0_GFX_DOORBELL_LOG_BASE_IDX                                                              0
234 #define mmSDMA0_GFX_WATERMARK                                                                          0x00aa
235 #define mmSDMA0_GFX_WATERMARK_BASE_IDX                                                                 0
236 #define mmSDMA0_GFX_DOORBELL_OFFSET                                                                    0x00ab
237 #define mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX                                                           0
238 #define mmSDMA0_GFX_CSA_ADDR_LO                                                                        0x00ac
239 #define mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX                                                               0
240 #define mmSDMA0_GFX_CSA_ADDR_HI                                                                        0x00ad
241 #define mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX                                                               0
242 #define mmSDMA0_GFX_IB_SUB_REMAIN                                                                      0x00af
243 #define mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX                                                             0
244 #define mmSDMA0_GFX_PREEMPT                                                                            0x00b0
245 #define mmSDMA0_GFX_PREEMPT_BASE_IDX                                                                   0
246 #define mmSDMA0_GFX_DUMMY_REG                                                                          0x00b1
247 #define mmSDMA0_GFX_DUMMY_REG_BASE_IDX                                                                 0
248 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI                                                               0x00b2
249 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                      0
250 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO                                                               0x00b3
251 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                      0
252 #define mmSDMA0_GFX_RB_AQL_CNTL                                                                        0x00b4
253 #define mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX                                                               0
254 #define mmSDMA0_GFX_MINOR_PTR_UPDATE                                                                   0x00b5
255 #define mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX                                                          0
256 #define mmSDMA0_GFX_MIDCMD_DATA0                                                                       0x00c0
257 #define mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX                                                              0
258 #define mmSDMA0_GFX_MIDCMD_DATA1                                                                       0x00c1
259 #define mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX                                                              0
260 #define mmSDMA0_GFX_MIDCMD_DATA2                                                                       0x00c2
261 #define mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX                                                              0
262 #define mmSDMA0_GFX_MIDCMD_DATA3                                                                       0x00c3
263 #define mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX                                                              0
264 #define mmSDMA0_GFX_MIDCMD_DATA4                                                                       0x00c4
265 #define mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX                                                              0
266 #define mmSDMA0_GFX_MIDCMD_DATA5                                                                       0x00c5
267 #define mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX                                                              0
268 #define mmSDMA0_GFX_MIDCMD_DATA6                                                                       0x00c6
269 #define mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX                                                              0
270 #define mmSDMA0_GFX_MIDCMD_DATA7                                                                       0x00c7
271 #define mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX                                                              0
272 #define mmSDMA0_GFX_MIDCMD_DATA8                                                                       0x00c8
273 #define mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX                                                              0
274 #define mmSDMA0_GFX_MIDCMD_DATA9                                                                       0x00c9
275 #define mmSDMA0_GFX_MIDCMD_DATA9_BASE_IDX                                                              0
276 #define mmSDMA0_GFX_MIDCMD_DATA10                                                                      0x00ca
277 #define mmSDMA0_GFX_MIDCMD_DATA10_BASE_IDX                                                             0
278 #define mmSDMA0_GFX_MIDCMD_CNTL                                                                        0x00cb
279 #define mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX                                                               0
280 #define mmSDMA0_PAGE_RB_CNTL                                                                           0x00d8
281 #define mmSDMA0_PAGE_RB_CNTL_BASE_IDX                                                                  0
282 #define mmSDMA0_PAGE_RB_BASE                                                                           0x00d9
283 #define mmSDMA0_PAGE_RB_BASE_BASE_IDX                                                                  0
284 #define mmSDMA0_PAGE_RB_BASE_HI                                                                        0x00da
285 #define mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX                                                               0
286 #define mmSDMA0_PAGE_RB_RPTR                                                                           0x00db
287 #define mmSDMA0_PAGE_RB_RPTR_BASE_IDX                                                                  0
288 #define mmSDMA0_PAGE_RB_RPTR_HI                                                                        0x00dc
289 #define mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX                                                               0
290 #define mmSDMA0_PAGE_RB_WPTR                                                                           0x00dd
291 #define mmSDMA0_PAGE_RB_WPTR_BASE_IDX                                                                  0
292 #define mmSDMA0_PAGE_RB_WPTR_HI                                                                        0x00de
293 #define mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX                                                               0
294 #define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL                                                                 0x00df
295 #define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
296 #define mmSDMA0_PAGE_RB_RPTR_ADDR_HI                                                                   0x00e0
297 #define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
298 #define mmSDMA0_PAGE_RB_RPTR_ADDR_LO                                                                   0x00e1
299 #define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
300 #define mmSDMA0_PAGE_IB_CNTL                                                                           0x00e2
301 #define mmSDMA0_PAGE_IB_CNTL_BASE_IDX                                                                  0
302 #define mmSDMA0_PAGE_IB_RPTR                                                                           0x00e3
303 #define mmSDMA0_PAGE_IB_RPTR_BASE_IDX                                                                  0
304 #define mmSDMA0_PAGE_IB_OFFSET                                                                         0x00e4
305 #define mmSDMA0_PAGE_IB_OFFSET_BASE_IDX                                                                0
306 #define mmSDMA0_PAGE_IB_BASE_LO                                                                        0x00e5
307 #define mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX                                                               0
308 #define mmSDMA0_PAGE_IB_BASE_HI                                                                        0x00e6
309 #define mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX                                                               0
310 #define mmSDMA0_PAGE_IB_SIZE                                                                           0x00e7
311 #define mmSDMA0_PAGE_IB_SIZE_BASE_IDX                                                                  0
312 #define mmSDMA0_PAGE_SKIP_CNTL                                                                         0x00e8
313 #define mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX                                                                0
314 #define mmSDMA0_PAGE_CONTEXT_STATUS                                                                    0x00e9
315 #define mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX                                                           0
316 #define mmSDMA0_PAGE_DOORBELL                                                                          0x00ea
317 #define mmSDMA0_PAGE_DOORBELL_BASE_IDX                                                                 0
318 #define mmSDMA0_PAGE_STATUS                                                                            0x0100
319 #define mmSDMA0_PAGE_STATUS_BASE_IDX                                                                   0
320 #define mmSDMA0_PAGE_DOORBELL_LOG                                                                      0x0101
321 #define mmSDMA0_PAGE_DOORBELL_LOG_BASE_IDX                                                             0
322 #define mmSDMA0_PAGE_WATERMARK                                                                         0x0102
323 #define mmSDMA0_PAGE_WATERMARK_BASE_IDX                                                                0
324 #define mmSDMA0_PAGE_DOORBELL_OFFSET                                                                   0x0103
325 #define mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX                                                          0
326 #define mmSDMA0_PAGE_CSA_ADDR_LO                                                                       0x0104
327 #define mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX                                                              0
328 #define mmSDMA0_PAGE_CSA_ADDR_HI                                                                       0x0105
329 #define mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX                                                              0
330 #define mmSDMA0_PAGE_IB_SUB_REMAIN                                                                     0x0107
331 #define mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX                                                            0
332 #define mmSDMA0_PAGE_PREEMPT                                                                           0x0108
333 #define mmSDMA0_PAGE_PREEMPT_BASE_IDX                                                                  0
334 #define mmSDMA0_PAGE_DUMMY_REG                                                                         0x0109
335 #define mmSDMA0_PAGE_DUMMY_REG_BASE_IDX                                                                0
336 #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI                                                              0x010a
337 #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
338 #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO                                                              0x010b
339 #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
340 #define mmSDMA0_PAGE_RB_AQL_CNTL                                                                       0x010c
341 #define mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX                                                              0
342 #define mmSDMA0_PAGE_MINOR_PTR_UPDATE                                                                  0x010d
343 #define mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX                                                         0
344 #define mmSDMA0_PAGE_MIDCMD_DATA0                                                                      0x0118
345 #define mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX                                                             0
346 #define mmSDMA0_PAGE_MIDCMD_DATA1                                                                      0x0119
347 #define mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX                                                             0
348 #define mmSDMA0_PAGE_MIDCMD_DATA2                                                                      0x011a
349 #define mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX                                                             0
350 #define mmSDMA0_PAGE_MIDCMD_DATA3                                                                      0x011b
351 #define mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX                                                             0
352 #define mmSDMA0_PAGE_MIDCMD_DATA4                                                                      0x011c
353 #define mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX                                                             0
354 #define mmSDMA0_PAGE_MIDCMD_DATA5                                                                      0x011d
355 #define mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX                                                             0
356 #define mmSDMA0_PAGE_MIDCMD_DATA6                                                                      0x011e
357 #define mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX                                                             0
358 #define mmSDMA0_PAGE_MIDCMD_DATA7                                                                      0x011f
359 #define mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX                                                             0
360 #define mmSDMA0_PAGE_MIDCMD_DATA8                                                                      0x0120
361 #define mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX                                                             0
362 #define mmSDMA0_PAGE_MIDCMD_DATA9                                                                      0x0121
363 #define mmSDMA0_PAGE_MIDCMD_DATA9_BASE_IDX                                                             0
364 #define mmSDMA0_PAGE_MIDCMD_DATA10                                                                     0x0122
365 #define mmSDMA0_PAGE_MIDCMD_DATA10_BASE_IDX                                                            0
366 #define mmSDMA0_PAGE_MIDCMD_CNTL                                                                       0x0123
367 #define mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX                                                              0
368 #define mmSDMA0_RLC0_RB_CNTL                                                                           0x0130
369 #define mmSDMA0_RLC0_RB_CNTL_BASE_IDX                                                                  0
370 #define mmSDMA0_RLC0_RB_BASE                                                                           0x0131
371 #define mmSDMA0_RLC0_RB_BASE_BASE_IDX                                                                  0
372 #define mmSDMA0_RLC0_RB_BASE_HI                                                                        0x0132
373 #define mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX                                                               0
374 #define mmSDMA0_RLC0_RB_RPTR                                                                           0x0133
375 #define mmSDMA0_RLC0_RB_RPTR_BASE_IDX                                                                  0
376 #define mmSDMA0_RLC0_RB_RPTR_HI                                                                        0x0134
377 #define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX                                                               0
378 #define mmSDMA0_RLC0_RB_WPTR                                                                           0x0135
379 #define mmSDMA0_RLC0_RB_WPTR_BASE_IDX                                                                  0
380 #define mmSDMA0_RLC0_RB_WPTR_HI                                                                        0x0136
381 #define mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX                                                               0
382 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL                                                                 0x0137
383 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
384 #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI                                                                   0x0138
385 #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
386 #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO                                                                   0x0139
387 #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
388 #define mmSDMA0_RLC0_IB_CNTL                                                                           0x013a
389 #define mmSDMA0_RLC0_IB_CNTL_BASE_IDX                                                                  0
390 #define mmSDMA0_RLC0_IB_RPTR                                                                           0x013b
391 #define mmSDMA0_RLC0_IB_RPTR_BASE_IDX                                                                  0
392 #define mmSDMA0_RLC0_IB_OFFSET                                                                         0x013c
393 #define mmSDMA0_RLC0_IB_OFFSET_BASE_IDX                                                                0
394 #define mmSDMA0_RLC0_IB_BASE_LO                                                                        0x013d
395 #define mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX                                                               0
396 #define mmSDMA0_RLC0_IB_BASE_HI                                                                        0x013e
397 #define mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX                                                               0
398 #define mmSDMA0_RLC0_IB_SIZE                                                                           0x013f
399 #define mmSDMA0_RLC0_IB_SIZE_BASE_IDX                                                                  0
400 #define mmSDMA0_RLC0_SKIP_CNTL                                                                         0x0140
401 #define mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX                                                                0
402 #define mmSDMA0_RLC0_CONTEXT_STATUS                                                                    0x0141
403 #define mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX                                                           0
404 #define mmSDMA0_RLC0_DOORBELL                                                                          0x0142
405 #define mmSDMA0_RLC0_DOORBELL_BASE_IDX                                                                 0
406 #define mmSDMA0_RLC0_STATUS                                                                            0x0158
407 #define mmSDMA0_RLC0_STATUS_BASE_IDX                                                                   0
408 #define mmSDMA0_RLC0_DOORBELL_LOG                                                                      0x0159
409 #define mmSDMA0_RLC0_DOORBELL_LOG_BASE_IDX                                                             0
410 #define mmSDMA0_RLC0_WATERMARK                                                                         0x015a
411 #define mmSDMA0_RLC0_WATERMARK_BASE_IDX                                                                0
412 #define mmSDMA0_RLC0_DOORBELL_OFFSET                                                                   0x015b
413 #define mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX                                                          0
414 #define mmSDMA0_RLC0_CSA_ADDR_LO                                                                       0x015c
415 #define mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX                                                              0
416 #define mmSDMA0_RLC0_CSA_ADDR_HI                                                                       0x015d
417 #define mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX                                                              0
418 #define mmSDMA0_RLC0_IB_SUB_REMAIN                                                                     0x015f
419 #define mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX                                                            0
420 #define mmSDMA0_RLC0_PREEMPT                                                                           0x0160
421 #define mmSDMA0_RLC0_PREEMPT_BASE_IDX                                                                  0
422 #define mmSDMA0_RLC0_DUMMY_REG                                                                         0x0161
423 #define mmSDMA0_RLC0_DUMMY_REG_BASE_IDX                                                                0
424 #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI                                                              0x0162
425 #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
426 #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO                                                              0x0163
427 #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
428 #define mmSDMA0_RLC0_RB_AQL_CNTL                                                                       0x0164
429 #define mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX                                                              0
430 #define mmSDMA0_RLC0_MINOR_PTR_UPDATE                                                                  0x0165
431 #define mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX                                                         0
432 #define mmSDMA0_RLC0_MIDCMD_DATA0                                                                      0x0170
433 #define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX                                                             0
434 #define mmSDMA0_RLC0_MIDCMD_DATA1                                                                      0x0171
435 #define mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX                                                             0
436 #define mmSDMA0_RLC0_MIDCMD_DATA2                                                                      0x0172
437 #define mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX                                                             0
438 #define mmSDMA0_RLC0_MIDCMD_DATA3                                                                      0x0173
439 #define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX                                                             0
440 #define mmSDMA0_RLC0_MIDCMD_DATA4                                                                      0x0174
441 #define mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX                                                             0
442 #define mmSDMA0_RLC0_MIDCMD_DATA5                                                                      0x0175
443 #define mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX                                                             0
444 #define mmSDMA0_RLC0_MIDCMD_DATA6                                                                      0x0176
445 #define mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX                                                             0
446 #define mmSDMA0_RLC0_MIDCMD_DATA7                                                                      0x0177
447 #define mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX                                                             0
448 #define mmSDMA0_RLC0_MIDCMD_DATA8                                                                      0x0178
449 #define mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX                                                             0
450 #define mmSDMA0_RLC0_MIDCMD_DATA9                                                                      0x0179
451 #define mmSDMA0_RLC0_MIDCMD_DATA9_BASE_IDX                                                             0
452 #define mmSDMA0_RLC0_MIDCMD_DATA10                                                                     0x017a
453 #define mmSDMA0_RLC0_MIDCMD_DATA10_BASE_IDX                                                            0
454 #define mmSDMA0_RLC0_MIDCMD_CNTL                                                                       0x017b
455 #define mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX                                                              0
456 #define mmSDMA0_RLC1_RB_CNTL                                                                           0x0188
457 #define mmSDMA0_RLC1_RB_CNTL_BASE_IDX                                                                  0
458 #define mmSDMA0_RLC1_RB_BASE                                                                           0x0189
459 #define mmSDMA0_RLC1_RB_BASE_BASE_IDX                                                                  0
460 #define mmSDMA0_RLC1_RB_BASE_HI                                                                        0x018a
461 #define mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX                                                               0
462 #define mmSDMA0_RLC1_RB_RPTR                                                                           0x018b
463 #define mmSDMA0_RLC1_RB_RPTR_BASE_IDX                                                                  0
464 #define mmSDMA0_RLC1_RB_RPTR_HI                                                                        0x018c
465 #define mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX                                                               0
466 #define mmSDMA0_RLC1_RB_WPTR                                                                           0x018d
467 #define mmSDMA0_RLC1_RB_WPTR_BASE_IDX                                                                  0
468 #define mmSDMA0_RLC1_RB_WPTR_HI                                                                        0x018e
469 #define mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX                                                               0
470 #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL                                                                 0x018f
471 #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
472 #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI                                                                   0x0190
473 #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
474 #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO                                                                   0x0191
475 #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
476 #define mmSDMA0_RLC1_IB_CNTL                                                                           0x0192
477 #define mmSDMA0_RLC1_IB_CNTL_BASE_IDX                                                                  0
478 #define mmSDMA0_RLC1_IB_RPTR                                                                           0x0193
479 #define mmSDMA0_RLC1_IB_RPTR_BASE_IDX                                                                  0
480 #define mmSDMA0_RLC1_IB_OFFSET                                                                         0x0194
481 #define mmSDMA0_RLC1_IB_OFFSET_BASE_IDX                                                                0
482 #define mmSDMA0_RLC1_IB_BASE_LO                                                                        0x0195
483 #define mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX                                                               0
484 #define mmSDMA0_RLC1_IB_BASE_HI                                                                        0x0196
485 #define mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX                                                               0
486 #define mmSDMA0_RLC1_IB_SIZE                                                                           0x0197
487 #define mmSDMA0_RLC1_IB_SIZE_BASE_IDX                                                                  0
488 #define mmSDMA0_RLC1_SKIP_CNTL                                                                         0x0198
489 #define mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX                                                                0
490 #define mmSDMA0_RLC1_CONTEXT_STATUS                                                                    0x0199
491 #define mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX                                                           0
492 #define mmSDMA0_RLC1_DOORBELL                                                                          0x019a
493 #define mmSDMA0_RLC1_DOORBELL_BASE_IDX                                                                 0
494 #define mmSDMA0_RLC1_STATUS                                                                            0x01b0
495 #define mmSDMA0_RLC1_STATUS_BASE_IDX                                                                   0
496 #define mmSDMA0_RLC1_DOORBELL_LOG                                                                      0x01b1
497 #define mmSDMA0_RLC1_DOORBELL_LOG_BASE_IDX                                                             0
498 #define mmSDMA0_RLC1_WATERMARK                                                                         0x01b2
499 #define mmSDMA0_RLC1_WATERMARK_BASE_IDX                                                                0
500 #define mmSDMA0_RLC1_DOORBELL_OFFSET                                                                   0x01b3
501 #define mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX                                                          0
502 #define mmSDMA0_RLC1_CSA_ADDR_LO                                                                       0x01b4
503 #define mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX                                                              0
504 #define mmSDMA0_RLC1_CSA_ADDR_HI                                                                       0x01b5
505 #define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX                                                              0
506 #define mmSDMA0_RLC1_IB_SUB_REMAIN                                                                     0x01b7
507 #define mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX                                                            0
508 #define mmSDMA0_RLC1_PREEMPT                                                                           0x01b8
509 #define mmSDMA0_RLC1_PREEMPT_BASE_IDX                                                                  0
510 #define mmSDMA0_RLC1_DUMMY_REG                                                                         0x01b9
511 #define mmSDMA0_RLC1_DUMMY_REG_BASE_IDX                                                                0
512 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI                                                              0x01ba
513 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
514 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO                                                              0x01bb
515 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
516 #define mmSDMA0_RLC1_RB_AQL_CNTL                                                                       0x01bc
517 #define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX                                                              0
518 #define mmSDMA0_RLC1_MINOR_PTR_UPDATE                                                                  0x01bd
519 #define mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX                                                         0
520 #define mmSDMA0_RLC1_MIDCMD_DATA0                                                                      0x01c8
521 #define mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX                                                             0
522 #define mmSDMA0_RLC1_MIDCMD_DATA1                                                                      0x01c9
523 #define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX                                                             0
524 #define mmSDMA0_RLC1_MIDCMD_DATA2                                                                      0x01ca
525 #define mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX                                                             0
526 #define mmSDMA0_RLC1_MIDCMD_DATA3                                                                      0x01cb
527 #define mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX                                                             0
528 #define mmSDMA0_RLC1_MIDCMD_DATA4                                                                      0x01cc
529 #define mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX                                                             0
530 #define mmSDMA0_RLC1_MIDCMD_DATA5                                                                      0x01cd
531 #define mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX                                                             0
532 #define mmSDMA0_RLC1_MIDCMD_DATA6                                                                      0x01ce
533 #define mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX                                                             0
534 #define mmSDMA0_RLC1_MIDCMD_DATA7                                                                      0x01cf
535 #define mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX                                                             0
536 #define mmSDMA0_RLC1_MIDCMD_DATA8                                                                      0x01d0
537 #define mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX                                                             0
538 #define mmSDMA0_RLC1_MIDCMD_DATA9                                                                      0x01d1
539 #define mmSDMA0_RLC1_MIDCMD_DATA9_BASE_IDX                                                             0
540 #define mmSDMA0_RLC1_MIDCMD_DATA10                                                                     0x01d2
541 #define mmSDMA0_RLC1_MIDCMD_DATA10_BASE_IDX                                                            0
542 #define mmSDMA0_RLC1_MIDCMD_CNTL                                                                       0x01d3
543 #define mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX                                                              0
544 #define mmSDMA0_RLC2_RB_CNTL                                                                           0x01e0
545 #define mmSDMA0_RLC2_RB_CNTL_BASE_IDX                                                                  0
546 #define mmSDMA0_RLC2_RB_BASE                                                                           0x01e1
547 #define mmSDMA0_RLC2_RB_BASE_BASE_IDX                                                                  0
548 #define mmSDMA0_RLC2_RB_BASE_HI                                                                        0x01e2
549 #define mmSDMA0_RLC2_RB_BASE_HI_BASE_IDX                                                               0
550 #define mmSDMA0_RLC2_RB_RPTR                                                                           0x01e3
551 #define mmSDMA0_RLC2_RB_RPTR_BASE_IDX                                                                  0
552 #define mmSDMA0_RLC2_RB_RPTR_HI                                                                        0x01e4
553 #define mmSDMA0_RLC2_RB_RPTR_HI_BASE_IDX                                                               0
554 #define mmSDMA0_RLC2_RB_WPTR                                                                           0x01e5
555 #define mmSDMA0_RLC2_RB_WPTR_BASE_IDX                                                                  0
556 #define mmSDMA0_RLC2_RB_WPTR_HI                                                                        0x01e6
557 #define mmSDMA0_RLC2_RB_WPTR_HI_BASE_IDX                                                               0
558 #define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL                                                                 0x01e7
559 #define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
560 #define mmSDMA0_RLC2_RB_RPTR_ADDR_HI                                                                   0x01e8
561 #define mmSDMA0_RLC2_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
562 #define mmSDMA0_RLC2_RB_RPTR_ADDR_LO                                                                   0x01e9
563 #define mmSDMA0_RLC2_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
564 #define mmSDMA0_RLC2_IB_CNTL                                                                           0x01ea
565 #define mmSDMA0_RLC2_IB_CNTL_BASE_IDX                                                                  0
566 #define mmSDMA0_RLC2_IB_RPTR                                                                           0x01eb
567 #define mmSDMA0_RLC2_IB_RPTR_BASE_IDX                                                                  0
568 #define mmSDMA0_RLC2_IB_OFFSET                                                                         0x01ec
569 #define mmSDMA0_RLC2_IB_OFFSET_BASE_IDX                                                                0
570 #define mmSDMA0_RLC2_IB_BASE_LO                                                                        0x01ed
571 #define mmSDMA0_RLC2_IB_BASE_LO_BASE_IDX                                                               0
572 #define mmSDMA0_RLC2_IB_BASE_HI                                                                        0x01ee
573 #define mmSDMA0_RLC2_IB_BASE_HI_BASE_IDX                                                               0
574 #define mmSDMA0_RLC2_IB_SIZE                                                                           0x01ef
575 #define mmSDMA0_RLC2_IB_SIZE_BASE_IDX                                                                  0
576 #define mmSDMA0_RLC2_SKIP_CNTL                                                                         0x01f0
577 #define mmSDMA0_RLC2_SKIP_CNTL_BASE_IDX                                                                0
578 #define mmSDMA0_RLC2_CONTEXT_STATUS                                                                    0x01f1
579 #define mmSDMA0_RLC2_CONTEXT_STATUS_BASE_IDX                                                           0
580 #define mmSDMA0_RLC2_DOORBELL                                                                          0x01f2
581 #define mmSDMA0_RLC2_DOORBELL_BASE_IDX                                                                 0
582 #define mmSDMA0_RLC2_STATUS                                                                            0x0208
583 #define mmSDMA0_RLC2_STATUS_BASE_IDX                                                                   0
584 #define mmSDMA0_RLC2_DOORBELL_LOG                                                                      0x0209
585 #define mmSDMA0_RLC2_DOORBELL_LOG_BASE_IDX                                                             0
586 #define mmSDMA0_RLC2_WATERMARK                                                                         0x020a
587 #define mmSDMA0_RLC2_WATERMARK_BASE_IDX                                                                0
588 #define mmSDMA0_RLC2_DOORBELL_OFFSET                                                                   0x020b
589 #define mmSDMA0_RLC2_DOORBELL_OFFSET_BASE_IDX                                                          0
590 #define mmSDMA0_RLC2_CSA_ADDR_LO                                                                       0x020c
591 #define mmSDMA0_RLC2_CSA_ADDR_LO_BASE_IDX                                                              0
592 #define mmSDMA0_RLC2_CSA_ADDR_HI                                                                       0x020d
593 #define mmSDMA0_RLC2_CSA_ADDR_HI_BASE_IDX                                                              0
594 #define mmSDMA0_RLC2_IB_SUB_REMAIN                                                                     0x020f
595 #define mmSDMA0_RLC2_IB_SUB_REMAIN_BASE_IDX                                                            0
596 #define mmSDMA0_RLC2_PREEMPT                                                                           0x0210
597 #define mmSDMA0_RLC2_PREEMPT_BASE_IDX                                                                  0
598 #define mmSDMA0_RLC2_DUMMY_REG                                                                         0x0211
599 #define mmSDMA0_RLC2_DUMMY_REG_BASE_IDX                                                                0
600 #define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI                                                              0x0212
601 #define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
602 #define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO                                                              0x0213
603 #define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
604 #define mmSDMA0_RLC2_RB_AQL_CNTL                                                                       0x0214
605 #define mmSDMA0_RLC2_RB_AQL_CNTL_BASE_IDX                                                              0
606 #define mmSDMA0_RLC2_MINOR_PTR_UPDATE                                                                  0x0215
607 #define mmSDMA0_RLC2_MINOR_PTR_UPDATE_BASE_IDX                                                         0
608 #define mmSDMA0_RLC2_MIDCMD_DATA0                                                                      0x0220
609 #define mmSDMA0_RLC2_MIDCMD_DATA0_BASE_IDX                                                             0
610 #define mmSDMA0_RLC2_MIDCMD_DATA1                                                                      0x0221
611 #define mmSDMA0_RLC2_MIDCMD_DATA1_BASE_IDX                                                             0
612 #define mmSDMA0_RLC2_MIDCMD_DATA2                                                                      0x0222
613 #define mmSDMA0_RLC2_MIDCMD_DATA2_BASE_IDX                                                             0
614 #define mmSDMA0_RLC2_MIDCMD_DATA3                                                                      0x0223
615 #define mmSDMA0_RLC2_MIDCMD_DATA3_BASE_IDX                                                             0
616 #define mmSDMA0_RLC2_MIDCMD_DATA4                                                                      0x0224
617 #define mmSDMA0_RLC2_MIDCMD_DATA4_BASE_IDX                                                             0
618 #define mmSDMA0_RLC2_MIDCMD_DATA5                                                                      0x0225
619 #define mmSDMA0_RLC2_MIDCMD_DATA5_BASE_IDX                                                             0
620 #define mmSDMA0_RLC2_MIDCMD_DATA6                                                                      0x0226
621 #define mmSDMA0_RLC2_MIDCMD_DATA6_BASE_IDX                                                             0
622 #define mmSDMA0_RLC2_MIDCMD_DATA7                                                                      0x0227
623 #define mmSDMA0_RLC2_MIDCMD_DATA7_BASE_IDX                                                             0
624 #define mmSDMA0_RLC2_MIDCMD_DATA8                                                                      0x0228
625 #define mmSDMA0_RLC2_MIDCMD_DATA8_BASE_IDX                                                             0
626 #define mmSDMA0_RLC2_MIDCMD_DATA9                                                                      0x0229
627 #define mmSDMA0_RLC2_MIDCMD_DATA9_BASE_IDX                                                             0
628 #define mmSDMA0_RLC2_MIDCMD_DATA10                                                                     0x022a
629 #define mmSDMA0_RLC2_MIDCMD_DATA10_BASE_IDX                                                            0
630 #define mmSDMA0_RLC2_MIDCMD_CNTL                                                                       0x022b
631 #define mmSDMA0_RLC2_MIDCMD_CNTL_BASE_IDX                                                              0
632 #define mmSDMA0_RLC3_RB_CNTL                                                                           0x0238
633 #define mmSDMA0_RLC3_RB_CNTL_BASE_IDX                                                                  0
634 #define mmSDMA0_RLC3_RB_BASE                                                                           0x0239
635 #define mmSDMA0_RLC3_RB_BASE_BASE_IDX                                                                  0
636 #define mmSDMA0_RLC3_RB_BASE_HI                                                                        0x023a
637 #define mmSDMA0_RLC3_RB_BASE_HI_BASE_IDX                                                               0
638 #define mmSDMA0_RLC3_RB_RPTR                                                                           0x023b
639 #define mmSDMA0_RLC3_RB_RPTR_BASE_IDX                                                                  0
640 #define mmSDMA0_RLC3_RB_RPTR_HI                                                                        0x023c
641 #define mmSDMA0_RLC3_RB_RPTR_HI_BASE_IDX                                                               0
642 #define mmSDMA0_RLC3_RB_WPTR                                                                           0x023d
643 #define mmSDMA0_RLC3_RB_WPTR_BASE_IDX                                                                  0
644 #define mmSDMA0_RLC3_RB_WPTR_HI                                                                        0x023e
645 #define mmSDMA0_RLC3_RB_WPTR_HI_BASE_IDX                                                               0
646 #define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL                                                                 0x023f
647 #define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
648 #define mmSDMA0_RLC3_RB_RPTR_ADDR_HI                                                                   0x0240
649 #define mmSDMA0_RLC3_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
650 #define mmSDMA0_RLC3_RB_RPTR_ADDR_LO                                                                   0x0241
651 #define mmSDMA0_RLC3_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
652 #define mmSDMA0_RLC3_IB_CNTL                                                                           0x0242
653 #define mmSDMA0_RLC3_IB_CNTL_BASE_IDX                                                                  0
654 #define mmSDMA0_RLC3_IB_RPTR                                                                           0x0243
655 #define mmSDMA0_RLC3_IB_RPTR_BASE_IDX                                                                  0
656 #define mmSDMA0_RLC3_IB_OFFSET                                                                         0x0244
657 #define mmSDMA0_RLC3_IB_OFFSET_BASE_IDX                                                                0
658 #define mmSDMA0_RLC3_IB_BASE_LO                                                                        0x0245
659 #define mmSDMA0_RLC3_IB_BASE_LO_BASE_IDX                                                               0
660 #define mmSDMA0_RLC3_IB_BASE_HI                                                                        0x0246
661 #define mmSDMA0_RLC3_IB_BASE_HI_BASE_IDX                                                               0
662 #define mmSDMA0_RLC3_IB_SIZE                                                                           0x0247
663 #define mmSDMA0_RLC3_IB_SIZE_BASE_IDX                                                                  0
664 #define mmSDMA0_RLC3_SKIP_CNTL                                                                         0x0248
665 #define mmSDMA0_RLC3_SKIP_CNTL_BASE_IDX                                                                0
666 #define mmSDMA0_RLC3_CONTEXT_STATUS                                                                    0x0249
667 #define mmSDMA0_RLC3_CONTEXT_STATUS_BASE_IDX                                                           0
668 #define mmSDMA0_RLC3_DOORBELL                                                                          0x024a
669 #define mmSDMA0_RLC3_DOORBELL_BASE_IDX                                                                 0
670 #define mmSDMA0_RLC3_STATUS                                                                            0x0260
671 #define mmSDMA0_RLC3_STATUS_BASE_IDX                                                                   0
672 #define mmSDMA0_RLC3_DOORBELL_LOG                                                                      0x0261
673 #define mmSDMA0_RLC3_DOORBELL_LOG_BASE_IDX                                                             0
674 #define mmSDMA0_RLC3_WATERMARK                                                                         0x0262
675 #define mmSDMA0_RLC3_WATERMARK_BASE_IDX                                                                0
676 #define mmSDMA0_RLC3_DOORBELL_OFFSET                                                                   0x0263
677 #define mmSDMA0_RLC3_DOORBELL_OFFSET_BASE_IDX                                                          0
678 #define mmSDMA0_RLC3_CSA_ADDR_LO                                                                       0x0264
679 #define mmSDMA0_RLC3_CSA_ADDR_LO_BASE_IDX                                                              0
680 #define mmSDMA0_RLC3_CSA_ADDR_HI                                                                       0x0265
681 #define mmSDMA0_RLC3_CSA_ADDR_HI_BASE_IDX                                                              0
682 #define mmSDMA0_RLC3_IB_SUB_REMAIN                                                                     0x0267
683 #define mmSDMA0_RLC3_IB_SUB_REMAIN_BASE_IDX                                                            0
684 #define mmSDMA0_RLC3_PREEMPT                                                                           0x0268
685 #define mmSDMA0_RLC3_PREEMPT_BASE_IDX                                                                  0
686 #define mmSDMA0_RLC3_DUMMY_REG                                                                         0x0269
687 #define mmSDMA0_RLC3_DUMMY_REG_BASE_IDX                                                                0
688 #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI                                                              0x026a
689 #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
690 #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO                                                              0x026b
691 #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
692 #define mmSDMA0_RLC3_RB_AQL_CNTL                                                                       0x026c
693 #define mmSDMA0_RLC3_RB_AQL_CNTL_BASE_IDX                                                              0
694 #define mmSDMA0_RLC3_MINOR_PTR_UPDATE                                                                  0x026d
695 #define mmSDMA0_RLC3_MINOR_PTR_UPDATE_BASE_IDX                                                         0
696 #define mmSDMA0_RLC3_MIDCMD_DATA0                                                                      0x0278
697 #define mmSDMA0_RLC3_MIDCMD_DATA0_BASE_IDX                                                             0
698 #define mmSDMA0_RLC3_MIDCMD_DATA1                                                                      0x0279
699 #define mmSDMA0_RLC3_MIDCMD_DATA1_BASE_IDX                                                             0
700 #define mmSDMA0_RLC3_MIDCMD_DATA2                                                                      0x027a
701 #define mmSDMA0_RLC3_MIDCMD_DATA2_BASE_IDX                                                             0
702 #define mmSDMA0_RLC3_MIDCMD_DATA3                                                                      0x027b
703 #define mmSDMA0_RLC3_MIDCMD_DATA3_BASE_IDX                                                             0
704 #define mmSDMA0_RLC3_MIDCMD_DATA4                                                                      0x027c
705 #define mmSDMA0_RLC3_MIDCMD_DATA4_BASE_IDX                                                             0
706 #define mmSDMA0_RLC3_MIDCMD_DATA5                                                                      0x027d
707 #define mmSDMA0_RLC3_MIDCMD_DATA5_BASE_IDX                                                             0
708 #define mmSDMA0_RLC3_MIDCMD_DATA6                                                                      0x027e
709 #define mmSDMA0_RLC3_MIDCMD_DATA6_BASE_IDX                                                             0
710 #define mmSDMA0_RLC3_MIDCMD_DATA7                                                                      0x027f
711 #define mmSDMA0_RLC3_MIDCMD_DATA7_BASE_IDX                                                             0
712 #define mmSDMA0_RLC3_MIDCMD_DATA8                                                                      0x0280
713 #define mmSDMA0_RLC3_MIDCMD_DATA8_BASE_IDX                                                             0
714 #define mmSDMA0_RLC3_MIDCMD_DATA9                                                                      0x0281
715 #define mmSDMA0_RLC3_MIDCMD_DATA9_BASE_IDX                                                             0
716 #define mmSDMA0_RLC3_MIDCMD_DATA10                                                                     0x0282
717 #define mmSDMA0_RLC3_MIDCMD_DATA10_BASE_IDX                                                            0
718 #define mmSDMA0_RLC3_MIDCMD_CNTL                                                                       0x0283
719 #define mmSDMA0_RLC3_MIDCMD_CNTL_BASE_IDX                                                              0
720 #define mmSDMA0_RLC4_RB_CNTL                                                                           0x0290
721 #define mmSDMA0_RLC4_RB_CNTL_BASE_IDX                                                                  0
722 #define mmSDMA0_RLC4_RB_BASE                                                                           0x0291
723 #define mmSDMA0_RLC4_RB_BASE_BASE_IDX                                                                  0
724 #define mmSDMA0_RLC4_RB_BASE_HI                                                                        0x0292
725 #define mmSDMA0_RLC4_RB_BASE_HI_BASE_IDX                                                               0
726 #define mmSDMA0_RLC4_RB_RPTR                                                                           0x0293
727 #define mmSDMA0_RLC4_RB_RPTR_BASE_IDX                                                                  0
728 #define mmSDMA0_RLC4_RB_RPTR_HI                                                                        0x0294
729 #define mmSDMA0_RLC4_RB_RPTR_HI_BASE_IDX                                                               0
730 #define mmSDMA0_RLC4_RB_WPTR                                                                           0x0295
731 #define mmSDMA0_RLC4_RB_WPTR_BASE_IDX                                                                  0
732 #define mmSDMA0_RLC4_RB_WPTR_HI                                                                        0x0296
733 #define mmSDMA0_RLC4_RB_WPTR_HI_BASE_IDX                                                               0
734 #define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL                                                                 0x0297
735 #define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
736 #define mmSDMA0_RLC4_RB_RPTR_ADDR_HI                                                                   0x0298
737 #define mmSDMA0_RLC4_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
738 #define mmSDMA0_RLC4_RB_RPTR_ADDR_LO                                                                   0x0299
739 #define mmSDMA0_RLC4_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
740 #define mmSDMA0_RLC4_IB_CNTL                                                                           0x029a
741 #define mmSDMA0_RLC4_IB_CNTL_BASE_IDX                                                                  0
742 #define mmSDMA0_RLC4_IB_RPTR                                                                           0x029b
743 #define mmSDMA0_RLC4_IB_RPTR_BASE_IDX                                                                  0
744 #define mmSDMA0_RLC4_IB_OFFSET                                                                         0x029c
745 #define mmSDMA0_RLC4_IB_OFFSET_BASE_IDX                                                                0
746 #define mmSDMA0_RLC4_IB_BASE_LO                                                                        0x029d
747 #define mmSDMA0_RLC4_IB_BASE_LO_BASE_IDX                                                               0
748 #define mmSDMA0_RLC4_IB_BASE_HI                                                                        0x029e
749 #define mmSDMA0_RLC4_IB_BASE_HI_BASE_IDX                                                               0
750 #define mmSDMA0_RLC4_IB_SIZE                                                                           0x029f
751 #define mmSDMA0_RLC4_IB_SIZE_BASE_IDX                                                                  0
752 #define mmSDMA0_RLC4_SKIP_CNTL                                                                         0x02a0
753 #define mmSDMA0_RLC4_SKIP_CNTL_BASE_IDX                                                                0
754 #define mmSDMA0_RLC4_CONTEXT_STATUS                                                                    0x02a1
755 #define mmSDMA0_RLC4_CONTEXT_STATUS_BASE_IDX                                                           0
756 #define mmSDMA0_RLC4_DOORBELL                                                                          0x02a2
757 #define mmSDMA0_RLC4_DOORBELL_BASE_IDX                                                                 0
758 #define mmSDMA0_RLC4_STATUS                                                                            0x02b8
759 #define mmSDMA0_RLC4_STATUS_BASE_IDX                                                                   0
760 #define mmSDMA0_RLC4_DOORBELL_LOG                                                                      0x02b9
761 #define mmSDMA0_RLC4_DOORBELL_LOG_BASE_IDX                                                             0
762 #define mmSDMA0_RLC4_WATERMARK                                                                         0x02ba
763 #define mmSDMA0_RLC4_WATERMARK_BASE_IDX                                                                0
764 #define mmSDMA0_RLC4_DOORBELL_OFFSET                                                                   0x02bb
765 #define mmSDMA0_RLC4_DOORBELL_OFFSET_BASE_IDX                                                          0
766 #define mmSDMA0_RLC4_CSA_ADDR_LO                                                                       0x02bc
767 #define mmSDMA0_RLC4_CSA_ADDR_LO_BASE_IDX                                                              0
768 #define mmSDMA0_RLC4_CSA_ADDR_HI                                                                       0x02bd
769 #define mmSDMA0_RLC4_CSA_ADDR_HI_BASE_IDX                                                              0
770 #define mmSDMA0_RLC4_IB_SUB_REMAIN                                                                     0x02bf
771 #define mmSDMA0_RLC4_IB_SUB_REMAIN_BASE_IDX                                                            0
772 #define mmSDMA0_RLC4_PREEMPT                                                                           0x02c0
773 #define mmSDMA0_RLC4_PREEMPT_BASE_IDX                                                                  0
774 #define mmSDMA0_RLC4_DUMMY_REG                                                                         0x02c1
775 #define mmSDMA0_RLC4_DUMMY_REG_BASE_IDX                                                                0
776 #define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI                                                              0x02c2
777 #define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
778 #define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO                                                              0x02c3
779 #define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
780 #define mmSDMA0_RLC4_RB_AQL_CNTL                                                                       0x02c4
781 #define mmSDMA0_RLC4_RB_AQL_CNTL_BASE_IDX                                                              0
782 #define mmSDMA0_RLC4_MINOR_PTR_UPDATE                                                                  0x02c5
783 #define mmSDMA0_RLC4_MINOR_PTR_UPDATE_BASE_IDX                                                         0
784 #define mmSDMA0_RLC4_MIDCMD_DATA0                                                                      0x02d0
785 #define mmSDMA0_RLC4_MIDCMD_DATA0_BASE_IDX                                                             0
786 #define mmSDMA0_RLC4_MIDCMD_DATA1                                                                      0x02d1
787 #define mmSDMA0_RLC4_MIDCMD_DATA1_BASE_IDX                                                             0
788 #define mmSDMA0_RLC4_MIDCMD_DATA2                                                                      0x02d2
789 #define mmSDMA0_RLC4_MIDCMD_DATA2_BASE_IDX                                                             0
790 #define mmSDMA0_RLC4_MIDCMD_DATA3                                                                      0x02d3
791 #define mmSDMA0_RLC4_MIDCMD_DATA3_BASE_IDX                                                             0
792 #define mmSDMA0_RLC4_MIDCMD_DATA4                                                                      0x02d4
793 #define mmSDMA0_RLC4_MIDCMD_DATA4_BASE_IDX                                                             0
794 #define mmSDMA0_RLC4_MIDCMD_DATA5                                                                      0x02d5
795 #define mmSDMA0_RLC4_MIDCMD_DATA5_BASE_IDX                                                             0
796 #define mmSDMA0_RLC4_MIDCMD_DATA6                                                                      0x02d6
797 #define mmSDMA0_RLC4_MIDCMD_DATA6_BASE_IDX                                                             0
798 #define mmSDMA0_RLC4_MIDCMD_DATA7                                                                      0x02d7
799 #define mmSDMA0_RLC4_MIDCMD_DATA7_BASE_IDX                                                             0
800 #define mmSDMA0_RLC4_MIDCMD_DATA8                                                                      0x02d8
801 #define mmSDMA0_RLC4_MIDCMD_DATA8_BASE_IDX                                                             0
802 #define mmSDMA0_RLC4_MIDCMD_DATA9                                                                      0x02d9
803 #define mmSDMA0_RLC4_MIDCMD_DATA9_BASE_IDX                                                             0
804 #define mmSDMA0_RLC4_MIDCMD_DATA10                                                                     0x02da
805 #define mmSDMA0_RLC4_MIDCMD_DATA10_BASE_IDX                                                            0
806 #define mmSDMA0_RLC4_MIDCMD_CNTL                                                                       0x02db
807 #define mmSDMA0_RLC4_MIDCMD_CNTL_BASE_IDX                                                              0
808 #define mmSDMA0_RLC5_RB_CNTL                                                                           0x02e8
809 #define mmSDMA0_RLC5_RB_CNTL_BASE_IDX                                                                  0
810 #define mmSDMA0_RLC5_RB_BASE                                                                           0x02e9
811 #define mmSDMA0_RLC5_RB_BASE_BASE_IDX                                                                  0
812 #define mmSDMA0_RLC5_RB_BASE_HI                                                                        0x02ea
813 #define mmSDMA0_RLC5_RB_BASE_HI_BASE_IDX                                                               0
814 #define mmSDMA0_RLC5_RB_RPTR                                                                           0x02eb
815 #define mmSDMA0_RLC5_RB_RPTR_BASE_IDX                                                                  0
816 #define mmSDMA0_RLC5_RB_RPTR_HI                                                                        0x02ec
817 #define mmSDMA0_RLC5_RB_RPTR_HI_BASE_IDX                                                               0
818 #define mmSDMA0_RLC5_RB_WPTR                                                                           0x02ed
819 #define mmSDMA0_RLC5_RB_WPTR_BASE_IDX                                                                  0
820 #define mmSDMA0_RLC5_RB_WPTR_HI                                                                        0x02ee
821 #define mmSDMA0_RLC5_RB_WPTR_HI_BASE_IDX                                                               0
822 #define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL                                                                 0x02ef
823 #define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
824 #define mmSDMA0_RLC5_RB_RPTR_ADDR_HI                                                                   0x02f0
825 #define mmSDMA0_RLC5_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
826 #define mmSDMA0_RLC5_RB_RPTR_ADDR_LO                                                                   0x02f1
827 #define mmSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
828 #define mmSDMA0_RLC5_IB_CNTL                                                                           0x02f2
829 #define mmSDMA0_RLC5_IB_CNTL_BASE_IDX                                                                  0
830 #define mmSDMA0_RLC5_IB_RPTR                                                                           0x02f3
831 #define mmSDMA0_RLC5_IB_RPTR_BASE_IDX                                                                  0
832 #define mmSDMA0_RLC5_IB_OFFSET                                                                         0x02f4
833 #define mmSDMA0_RLC5_IB_OFFSET_BASE_IDX                                                                0
834 #define mmSDMA0_RLC5_IB_BASE_LO                                                                        0x02f5
835 #define mmSDMA0_RLC5_IB_BASE_LO_BASE_IDX                                                               0
836 #define mmSDMA0_RLC5_IB_BASE_HI                                                                        0x02f6
837 #define mmSDMA0_RLC5_IB_BASE_HI_BASE_IDX                                                               0
838 #define mmSDMA0_RLC5_IB_SIZE                                                                           0x02f7
839 #define mmSDMA0_RLC5_IB_SIZE_BASE_IDX                                                                  0
840 #define mmSDMA0_RLC5_SKIP_CNTL                                                                         0x02f8
841 #define mmSDMA0_RLC5_SKIP_CNTL_BASE_IDX                                                                0
842 #define mmSDMA0_RLC5_CONTEXT_STATUS                                                                    0x02f9
843 #define mmSDMA0_RLC5_CONTEXT_STATUS_BASE_IDX                                                           0
844 #define mmSDMA0_RLC5_DOORBELL                                                                          0x02fa
845 #define mmSDMA0_RLC5_DOORBELL_BASE_IDX                                                                 0
846 #define mmSDMA0_RLC5_STATUS                                                                            0x0310
847 #define mmSDMA0_RLC5_STATUS_BASE_IDX                                                                   0
848 #define mmSDMA0_RLC5_DOORBELL_LOG                                                                      0x0311
849 #define mmSDMA0_RLC5_DOORBELL_LOG_BASE_IDX                                                             0
850 #define mmSDMA0_RLC5_WATERMARK                                                                         0x0312
851 #define mmSDMA0_RLC5_WATERMARK_BASE_IDX                                                                0
852 #define mmSDMA0_RLC5_DOORBELL_OFFSET                                                                   0x0313
853 #define mmSDMA0_RLC5_DOORBELL_OFFSET_BASE_IDX                                                          0
854 #define mmSDMA0_RLC5_CSA_ADDR_LO                                                                       0x0314
855 #define mmSDMA0_RLC5_CSA_ADDR_LO_BASE_IDX                                                              0
856 #define mmSDMA0_RLC5_CSA_ADDR_HI                                                                       0x0315
857 #define mmSDMA0_RLC5_CSA_ADDR_HI_BASE_IDX                                                              0
858 #define mmSDMA0_RLC5_IB_SUB_REMAIN                                                                     0x0317
859 #define mmSDMA0_RLC5_IB_SUB_REMAIN_BASE_IDX                                                            0
860 #define mmSDMA0_RLC5_PREEMPT                                                                           0x0318
861 #define mmSDMA0_RLC5_PREEMPT_BASE_IDX                                                                  0
862 #define mmSDMA0_RLC5_DUMMY_REG                                                                         0x0319
863 #define mmSDMA0_RLC5_DUMMY_REG_BASE_IDX                                                                0
864 #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI                                                              0x031a
865 #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
866 #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO                                                              0x031b
867 #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
868 #define mmSDMA0_RLC5_RB_AQL_CNTL                                                                       0x031c
869 #define mmSDMA0_RLC5_RB_AQL_CNTL_BASE_IDX                                                              0
870 #define mmSDMA0_RLC5_MINOR_PTR_UPDATE                                                                  0x031d
871 #define mmSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX                                                         0
872 #define mmSDMA0_RLC5_MIDCMD_DATA0                                                                      0x0328
873 #define mmSDMA0_RLC5_MIDCMD_DATA0_BASE_IDX                                                             0
874 #define mmSDMA0_RLC5_MIDCMD_DATA1                                                                      0x0329
875 #define mmSDMA0_RLC5_MIDCMD_DATA1_BASE_IDX                                                             0
876 #define mmSDMA0_RLC5_MIDCMD_DATA2                                                                      0x032a
877 #define mmSDMA0_RLC5_MIDCMD_DATA2_BASE_IDX                                                             0
878 #define mmSDMA0_RLC5_MIDCMD_DATA3                                                                      0x032b
879 #define mmSDMA0_RLC5_MIDCMD_DATA3_BASE_IDX                                                             0
880 #define mmSDMA0_RLC5_MIDCMD_DATA4                                                                      0x032c
881 #define mmSDMA0_RLC5_MIDCMD_DATA4_BASE_IDX                                                             0
882 #define mmSDMA0_RLC5_MIDCMD_DATA5                                                                      0x032d
883 #define mmSDMA0_RLC5_MIDCMD_DATA5_BASE_IDX                                                             0
884 #define mmSDMA0_RLC5_MIDCMD_DATA6                                                                      0x032e
885 #define mmSDMA0_RLC5_MIDCMD_DATA6_BASE_IDX                                                             0
886 #define mmSDMA0_RLC5_MIDCMD_DATA7                                                                      0x032f
887 #define mmSDMA0_RLC5_MIDCMD_DATA7_BASE_IDX                                                             0
888 #define mmSDMA0_RLC5_MIDCMD_DATA8                                                                      0x0330
889 #define mmSDMA0_RLC5_MIDCMD_DATA8_BASE_IDX                                                             0
890 #define mmSDMA0_RLC5_MIDCMD_DATA9                                                                      0x0331
891 #define mmSDMA0_RLC5_MIDCMD_DATA9_BASE_IDX                                                             0
892 #define mmSDMA0_RLC5_MIDCMD_DATA10                                                                     0x0332
893 #define mmSDMA0_RLC5_MIDCMD_DATA10_BASE_IDX                                                            0
894 #define mmSDMA0_RLC5_MIDCMD_CNTL                                                                       0x0333
895 #define mmSDMA0_RLC5_MIDCMD_CNTL_BASE_IDX                                                              0
896 #define mmSDMA0_RLC6_RB_CNTL                                                                           0x0340
897 #define mmSDMA0_RLC6_RB_CNTL_BASE_IDX                                                                  0
898 #define mmSDMA0_RLC6_RB_BASE                                                                           0x0341
899 #define mmSDMA0_RLC6_RB_BASE_BASE_IDX                                                                  0
900 #define mmSDMA0_RLC6_RB_BASE_HI                                                                        0x0342
901 #define mmSDMA0_RLC6_RB_BASE_HI_BASE_IDX                                                               0
902 #define mmSDMA0_RLC6_RB_RPTR                                                                           0x0343
903 #define mmSDMA0_RLC6_RB_RPTR_BASE_IDX                                                                  0
904 #define mmSDMA0_RLC6_RB_RPTR_HI                                                                        0x0344
905 #define mmSDMA0_RLC6_RB_RPTR_HI_BASE_IDX                                                               0
906 #define mmSDMA0_RLC6_RB_WPTR                                                                           0x0345
907 #define mmSDMA0_RLC6_RB_WPTR_BASE_IDX                                                                  0
908 #define mmSDMA0_RLC6_RB_WPTR_HI                                                                        0x0346
909 #define mmSDMA0_RLC6_RB_WPTR_HI_BASE_IDX                                                               0
910 #define mmSDMA0_RLC6_RB_WPTR_POLL_CNTL                                                                 0x0347
911 #define mmSDMA0_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
912 #define mmSDMA0_RLC6_RB_RPTR_ADDR_HI                                                                   0x0348
913 #define mmSDMA0_RLC6_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
914 #define mmSDMA0_RLC6_RB_RPTR_ADDR_LO                                                                   0x0349
915 #define mmSDMA0_RLC6_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
916 #define mmSDMA0_RLC6_IB_CNTL                                                                           0x034a
917 #define mmSDMA0_RLC6_IB_CNTL_BASE_IDX                                                                  0
918 #define mmSDMA0_RLC6_IB_RPTR                                                                           0x034b
919 #define mmSDMA0_RLC6_IB_RPTR_BASE_IDX                                                                  0
920 #define mmSDMA0_RLC6_IB_OFFSET                                                                         0x034c
921 #define mmSDMA0_RLC6_IB_OFFSET_BASE_IDX                                                                0
922 #define mmSDMA0_RLC6_IB_BASE_LO                                                                        0x034d
923 #define mmSDMA0_RLC6_IB_BASE_LO_BASE_IDX                                                               0
924 #define mmSDMA0_RLC6_IB_BASE_HI                                                                        0x034e
925 #define mmSDMA0_RLC6_IB_BASE_HI_BASE_IDX                                                               0
926 #define mmSDMA0_RLC6_IB_SIZE                                                                           0x034f
927 #define mmSDMA0_RLC6_IB_SIZE_BASE_IDX                                                                  0
928 #define mmSDMA0_RLC6_SKIP_CNTL                                                                         0x0350
929 #define mmSDMA0_RLC6_SKIP_CNTL_BASE_IDX                                                                0
930 #define mmSDMA0_RLC6_CONTEXT_STATUS                                                                    0x0351
931 #define mmSDMA0_RLC6_CONTEXT_STATUS_BASE_IDX                                                           0
932 #define mmSDMA0_RLC6_DOORBELL                                                                          0x0352
933 #define mmSDMA0_RLC6_DOORBELL_BASE_IDX                                                                 0
934 #define mmSDMA0_RLC6_STATUS                                                                            0x0368
935 #define mmSDMA0_RLC6_STATUS_BASE_IDX                                                                   0
936 #define mmSDMA0_RLC6_DOORBELL_LOG                                                                      0x0369
937 #define mmSDMA0_RLC6_DOORBELL_LOG_BASE_IDX                                                             0
938 #define mmSDMA0_RLC6_WATERMARK                                                                         0x036a
939 #define mmSDMA0_RLC6_WATERMARK_BASE_IDX                                                                0
940 #define mmSDMA0_RLC6_DOORBELL_OFFSET                                                                   0x036b
941 #define mmSDMA0_RLC6_DOORBELL_OFFSET_BASE_IDX                                                          0
942 #define mmSDMA0_RLC6_CSA_ADDR_LO                                                                       0x036c
943 #define mmSDMA0_RLC6_CSA_ADDR_LO_BASE_IDX                                                              0
944 #define mmSDMA0_RLC6_CSA_ADDR_HI                                                                       0x036d
945 #define mmSDMA0_RLC6_CSA_ADDR_HI_BASE_IDX                                                              0
946 #define mmSDMA0_RLC6_IB_SUB_REMAIN                                                                     0x036f
947 #define mmSDMA0_RLC6_IB_SUB_REMAIN_BASE_IDX                                                            0
948 #define mmSDMA0_RLC6_PREEMPT                                                                           0x0370
949 #define mmSDMA0_RLC6_PREEMPT_BASE_IDX                                                                  0
950 #define mmSDMA0_RLC6_DUMMY_REG                                                                         0x0371
951 #define mmSDMA0_RLC6_DUMMY_REG_BASE_IDX                                                                0
952 #define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI                                                              0x0372
953 #define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
954 #define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO                                                              0x0373
955 #define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
956 #define mmSDMA0_RLC6_RB_AQL_CNTL                                                                       0x0374
957 #define mmSDMA0_RLC6_RB_AQL_CNTL_BASE_IDX                                                              0
958 #define mmSDMA0_RLC6_MINOR_PTR_UPDATE                                                                  0x0375
959 #define mmSDMA0_RLC6_MINOR_PTR_UPDATE_BASE_IDX                                                         0
960 #define mmSDMA0_RLC6_MIDCMD_DATA0                                                                      0x0380
961 #define mmSDMA0_RLC6_MIDCMD_DATA0_BASE_IDX                                                             0
962 #define mmSDMA0_RLC6_MIDCMD_DATA1                                                                      0x0381
963 #define mmSDMA0_RLC6_MIDCMD_DATA1_BASE_IDX                                                             0
964 #define mmSDMA0_RLC6_MIDCMD_DATA2                                                                      0x0382
965 #define mmSDMA0_RLC6_MIDCMD_DATA2_BASE_IDX                                                             0
966 #define mmSDMA0_RLC6_MIDCMD_DATA3                                                                      0x0383
967 #define mmSDMA0_RLC6_MIDCMD_DATA3_BASE_IDX                                                             0
968 #define mmSDMA0_RLC6_MIDCMD_DATA4                                                                      0x0384
969 #define mmSDMA0_RLC6_MIDCMD_DATA4_BASE_IDX                                                             0
970 #define mmSDMA0_RLC6_MIDCMD_DATA5                                                                      0x0385
971 #define mmSDMA0_RLC6_MIDCMD_DATA5_BASE_IDX                                                             0
972 #define mmSDMA0_RLC6_MIDCMD_DATA6                                                                      0x0386
973 #define mmSDMA0_RLC6_MIDCMD_DATA6_BASE_IDX                                                             0
974 #define mmSDMA0_RLC6_MIDCMD_DATA7                                                                      0x0387
975 #define mmSDMA0_RLC6_MIDCMD_DATA7_BASE_IDX                                                             0
976 #define mmSDMA0_RLC6_MIDCMD_DATA8                                                                      0x0388
977 #define mmSDMA0_RLC6_MIDCMD_DATA8_BASE_IDX                                                             0
978 #define mmSDMA0_RLC6_MIDCMD_DATA9                                                                      0x0389
979 #define mmSDMA0_RLC6_MIDCMD_DATA9_BASE_IDX                                                             0
980 #define mmSDMA0_RLC6_MIDCMD_DATA10                                                                     0x038a
981 #define mmSDMA0_RLC6_MIDCMD_DATA10_BASE_IDX                                                            0
982 #define mmSDMA0_RLC6_MIDCMD_CNTL                                                                       0x038b
983 #define mmSDMA0_RLC6_MIDCMD_CNTL_BASE_IDX                                                              0
984 #define mmSDMA0_RLC7_RB_CNTL                                                                           0x0398
985 #define mmSDMA0_RLC7_RB_CNTL_BASE_IDX                                                                  0
986 #define mmSDMA0_RLC7_RB_BASE                                                                           0x0399
987 #define mmSDMA0_RLC7_RB_BASE_BASE_IDX                                                                  0
988 #define mmSDMA0_RLC7_RB_BASE_HI                                                                        0x039a
989 #define mmSDMA0_RLC7_RB_BASE_HI_BASE_IDX                                                               0
990 #define mmSDMA0_RLC7_RB_RPTR                                                                           0x039b
991 #define mmSDMA0_RLC7_RB_RPTR_BASE_IDX                                                                  0
992 #define mmSDMA0_RLC7_RB_RPTR_HI                                                                        0x039c
993 #define mmSDMA0_RLC7_RB_RPTR_HI_BASE_IDX                                                               0
994 #define mmSDMA0_RLC7_RB_WPTR                                                                           0x039d
995 #define mmSDMA0_RLC7_RB_WPTR_BASE_IDX                                                                  0
996 #define mmSDMA0_RLC7_RB_WPTR_HI                                                                        0x039e
997 #define mmSDMA0_RLC7_RB_WPTR_HI_BASE_IDX                                                               0
998 #define mmSDMA0_RLC7_RB_WPTR_POLL_CNTL                                                                 0x039f
999 #define mmSDMA0_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
1000 #define mmSDMA0_RLC7_RB_RPTR_ADDR_HI                                                                   0x03a0
1001 #define mmSDMA0_RLC7_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
1002 #define mmSDMA0_RLC7_RB_RPTR_ADDR_LO                                                                   0x03a1
1003 #define mmSDMA0_RLC7_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
1004 #define mmSDMA0_RLC7_IB_CNTL                                                                           0x03a2
1005 #define mmSDMA0_RLC7_IB_CNTL_BASE_IDX                                                                  0
1006 #define mmSDMA0_RLC7_IB_RPTR                                                                           0x03a3
1007 #define mmSDMA0_RLC7_IB_RPTR_BASE_IDX                                                                  0
1008 #define mmSDMA0_RLC7_IB_OFFSET                                                                         0x03a4
1009 #define mmSDMA0_RLC7_IB_OFFSET_BASE_IDX                                                                0
1010 #define mmSDMA0_RLC7_IB_BASE_LO                                                                        0x03a5
1011 #define mmSDMA0_RLC7_IB_BASE_LO_BASE_IDX                                                               0
1012 #define mmSDMA0_RLC7_IB_BASE_HI                                                                        0x03a6
1013 #define mmSDMA0_RLC7_IB_BASE_HI_BASE_IDX                                                               0
1014 #define mmSDMA0_RLC7_IB_SIZE                                                                           0x03a7
1015 #define mmSDMA0_RLC7_IB_SIZE_BASE_IDX                                                                  0
1016 #define mmSDMA0_RLC7_SKIP_CNTL                                                                         0x03a8
1017 #define mmSDMA0_RLC7_SKIP_CNTL_BASE_IDX                                                                0
1018 #define mmSDMA0_RLC7_CONTEXT_STATUS                                                                    0x03a9
1019 #define mmSDMA0_RLC7_CONTEXT_STATUS_BASE_IDX                                                           0
1020 #define mmSDMA0_RLC7_DOORBELL                                                                          0x03aa
1021 #define mmSDMA0_RLC7_DOORBELL_BASE_IDX                                                                 0
1022 #define mmSDMA0_RLC7_STATUS                                                                            0x03c0
1023 #define mmSDMA0_RLC7_STATUS_BASE_IDX                                                                   0
1024 #define mmSDMA0_RLC7_DOORBELL_LOG                                                                      0x03c1
1025 #define mmSDMA0_RLC7_DOORBELL_LOG_BASE_IDX                                                             0
1026 #define mmSDMA0_RLC7_WATERMARK                                                                         0x03c2
1027 #define mmSDMA0_RLC7_WATERMARK_BASE_IDX                                                                0
1028 #define mmSDMA0_RLC7_DOORBELL_OFFSET                                                                   0x03c3
1029 #define mmSDMA0_RLC7_DOORBELL_OFFSET_BASE_IDX                                                          0
1030 #define mmSDMA0_RLC7_CSA_ADDR_LO                                                                       0x03c4
1031 #define mmSDMA0_RLC7_CSA_ADDR_LO_BASE_IDX                                                              0
1032 #define mmSDMA0_RLC7_CSA_ADDR_HI                                                                       0x03c5
1033 #define mmSDMA0_RLC7_CSA_ADDR_HI_BASE_IDX                                                              0
1034 #define mmSDMA0_RLC7_IB_SUB_REMAIN                                                                     0x03c7
1035 #define mmSDMA0_RLC7_IB_SUB_REMAIN_BASE_IDX                                                            0
1036 #define mmSDMA0_RLC7_PREEMPT                                                                           0x03c8
1037 #define mmSDMA0_RLC7_PREEMPT_BASE_IDX                                                                  0
1038 #define mmSDMA0_RLC7_DUMMY_REG                                                                         0x03c9
1039 #define mmSDMA0_RLC7_DUMMY_REG_BASE_IDX                                                                0
1040 #define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI                                                              0x03ca
1041 #define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
1042 #define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO                                                              0x03cb
1043 #define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
1044 #define mmSDMA0_RLC7_RB_AQL_CNTL                                                                       0x03cc
1045 #define mmSDMA0_RLC7_RB_AQL_CNTL_BASE_IDX                                                              0
1046 #define mmSDMA0_RLC7_MINOR_PTR_UPDATE                                                                  0x03cd
1047 #define mmSDMA0_RLC7_MINOR_PTR_UPDATE_BASE_IDX                                                         0
1048 #define mmSDMA0_RLC7_MIDCMD_DATA0                                                                      0x03d8
1049 #define mmSDMA0_RLC7_MIDCMD_DATA0_BASE_IDX                                                             0
1050 #define mmSDMA0_RLC7_MIDCMD_DATA1                                                                      0x03d9
1051 #define mmSDMA0_RLC7_MIDCMD_DATA1_BASE_IDX                                                             0
1052 #define mmSDMA0_RLC7_MIDCMD_DATA2                                                                      0x03da
1053 #define mmSDMA0_RLC7_MIDCMD_DATA2_BASE_IDX                                                             0
1054 #define mmSDMA0_RLC7_MIDCMD_DATA3                                                                      0x03db
1055 #define mmSDMA0_RLC7_MIDCMD_DATA3_BASE_IDX                                                             0
1056 #define mmSDMA0_RLC7_MIDCMD_DATA4                                                                      0x03dc
1057 #define mmSDMA0_RLC7_MIDCMD_DATA4_BASE_IDX                                                             0
1058 #define mmSDMA0_RLC7_MIDCMD_DATA5                                                                      0x03dd
1059 #define mmSDMA0_RLC7_MIDCMD_DATA5_BASE_IDX                                                             0
1060 #define mmSDMA0_RLC7_MIDCMD_DATA6                                                                      0x03de
1061 #define mmSDMA0_RLC7_MIDCMD_DATA6_BASE_IDX                                                             0
1062 #define mmSDMA0_RLC7_MIDCMD_DATA7                                                                      0x03df
1063 #define mmSDMA0_RLC7_MIDCMD_DATA7_BASE_IDX                                                             0
1064 #define mmSDMA0_RLC7_MIDCMD_DATA8                                                                      0x03e0
1065 #define mmSDMA0_RLC7_MIDCMD_DATA8_BASE_IDX                                                             0
1066 #define mmSDMA0_RLC7_MIDCMD_DATA9                                                                      0x03e1
1067 #define mmSDMA0_RLC7_MIDCMD_DATA9_BASE_IDX                                                             0
1068 #define mmSDMA0_RLC7_MIDCMD_DATA10                                                                     0x03e2
1069 #define mmSDMA0_RLC7_MIDCMD_DATA10_BASE_IDX                                                            0
1070 #define mmSDMA0_RLC7_MIDCMD_CNTL                                                                       0x03e3
1071 #define mmSDMA0_RLC7_MIDCMD_CNTL_BASE_IDX                                                              0
1072 
1073 
1074 // addressBlock: gc_sdma1_sdma1dec
1075 // base address: 0x6180
1076 #define mmSDMA1_DEC_START                                                                              0x0600
1077 #define mmSDMA1_DEC_START_BASE_IDX                                                                     0
1078 #define mmSDMA1_GLOBAL_TIMESTAMP_LO                                                                    0x060f
1079 #define mmSDMA1_GLOBAL_TIMESTAMP_LO_BASE_IDX                                                           0
1080 #define mmSDMA1_GLOBAL_TIMESTAMP_HI                                                                    0x0610
1081 #define mmSDMA1_GLOBAL_TIMESTAMP_HI_BASE_IDX                                                           0
1082 #define mmSDMA1_PG_CNTL                                                                                0x0616
1083 #define mmSDMA1_PG_CNTL_BASE_IDX                                                                       0
1084 #define mmSDMA1_PG_CTX_LO                                                                              0x0617
1085 #define mmSDMA1_PG_CTX_LO_BASE_IDX                                                                     0
1086 #define mmSDMA1_PG_CTX_HI                                                                              0x0618
1087 #define mmSDMA1_PG_CTX_HI_BASE_IDX                                                                     0
1088 #define mmSDMA1_PG_CTX_CNTL                                                                            0x0619
1089 #define mmSDMA1_PG_CTX_CNTL_BASE_IDX                                                                   0
1090 #define mmSDMA1_POWER_CNTL                                                                             0x061a
1091 #define mmSDMA1_POWER_CNTL_BASE_IDX                                                                    0
1092 #define mmSDMA1_CLK_CTRL                                                                               0x061b
1093 #define mmSDMA1_CLK_CTRL_BASE_IDX                                                                      0
1094 #define mmSDMA1_CNTL                                                                                   0x061c
1095 #define mmSDMA1_CNTL_BASE_IDX                                                                          0
1096 #define mmSDMA1_CHICKEN_BITS                                                                           0x061d
1097 #define mmSDMA1_CHICKEN_BITS_BASE_IDX                                                                  0
1098 #define mmSDMA1_GB_ADDR_CONFIG                                                                         0x061e
1099 #define mmSDMA1_GB_ADDR_CONFIG_BASE_IDX                                                                0
1100 #define mmSDMA1_GB_ADDR_CONFIG_READ                                                                    0x061f
1101 #define mmSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX                                                           0
1102 #define mmSDMA1_RB_RPTR_FETCH_HI                                                                       0x0620
1103 #define mmSDMA1_RB_RPTR_FETCH_HI_BASE_IDX                                                              0
1104 #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL                                                               0x0621
1105 #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX                                                      0
1106 #define mmSDMA1_RB_RPTR_FETCH                                                                          0x0622
1107 #define mmSDMA1_RB_RPTR_FETCH_BASE_IDX                                                                 0
1108 #define mmSDMA1_IB_OFFSET_FETCH                                                                        0x0623
1109 #define mmSDMA1_IB_OFFSET_FETCH_BASE_IDX                                                               0
1110 #define mmSDMA1_PROGRAM                                                                                0x0624
1111 #define mmSDMA1_PROGRAM_BASE_IDX                                                                       0
1112 #define mmSDMA1_STATUS_REG                                                                             0x0625
1113 #define mmSDMA1_STATUS_REG_BASE_IDX                                                                    0
1114 #define mmSDMA1_STATUS1_REG                                                                            0x0626
1115 #define mmSDMA1_STATUS1_REG_BASE_IDX                                                                   0
1116 #define mmSDMA1_RD_BURST_CNTL                                                                          0x0627
1117 #define mmSDMA1_RD_BURST_CNTL_BASE_IDX                                                                 0
1118 #define mmSDMA1_HBM_PAGE_CONFIG                                                                        0x0628
1119 #define mmSDMA1_HBM_PAGE_CONFIG_BASE_IDX                                                               0
1120 #define mmSDMA1_UCODE_CHECKSUM                                                                         0x0629
1121 #define mmSDMA1_UCODE_CHECKSUM_BASE_IDX                                                                0
1122 #define mmSDMA1_F32_CNTL                                                                               0x062a
1123 #define mmSDMA1_F32_CNTL_BASE_IDX                                                                      0
1124 #define mmSDMA1_FREEZE                                                                                 0x062b
1125 #define mmSDMA1_FREEZE_BASE_IDX                                                                        0
1126 #define mmSDMA1_PHASE0_QUANTUM                                                                         0x062c
1127 #define mmSDMA1_PHASE0_QUANTUM_BASE_IDX                                                                0
1128 #define mmSDMA1_PHASE1_QUANTUM                                                                         0x062d
1129 #define mmSDMA1_PHASE1_QUANTUM_BASE_IDX                                                                0
1130 #define mmSDMA1_EDC_CONFIG                                                                             0x0632
1131 #define mmSDMA1_EDC_CONFIG_BASE_IDX                                                                    0
1132 #define mmSDMA1_BA_THRESHOLD                                                                           0x0633
1133 #define mmSDMA1_BA_THRESHOLD_BASE_IDX                                                                  0
1134 #define mmSDMA1_ID                                                                                     0x0634
1135 #define mmSDMA1_ID_BASE_IDX                                                                            0
1136 #define mmSDMA1_VERSION                                                                                0x0635
1137 #define mmSDMA1_VERSION_BASE_IDX                                                                       0
1138 #define mmSDMA1_EDC_COUNTER                                                                            0x0636
1139 #define mmSDMA1_EDC_COUNTER_BASE_IDX                                                                   0
1140 #define mmSDMA1_EDC_COUNTER_CLEAR                                                                      0x0637
1141 #define mmSDMA1_EDC_COUNTER_CLEAR_BASE_IDX                                                             0
1142 #define mmSDMA1_STATUS2_REG                                                                            0x0638
1143 #define mmSDMA1_STATUS2_REG_BASE_IDX                                                                   0
1144 #define mmSDMA1_ATOMIC_CNTL                                                                            0x0639
1145 #define mmSDMA1_ATOMIC_CNTL_BASE_IDX                                                                   0
1146 #define mmSDMA1_ATOMIC_PREOP_LO                                                                        0x063a
1147 #define mmSDMA1_ATOMIC_PREOP_LO_BASE_IDX                                                               0
1148 #define mmSDMA1_ATOMIC_PREOP_HI                                                                        0x063b
1149 #define mmSDMA1_ATOMIC_PREOP_HI_BASE_IDX                                                               0
1150 #define mmSDMA1_UTCL1_CNTL                                                                             0x063c
1151 #define mmSDMA1_UTCL1_CNTL_BASE_IDX                                                                    0
1152 #define mmSDMA1_UTCL1_WATERMK                                                                          0x063d
1153 #define mmSDMA1_UTCL1_WATERMK_BASE_IDX                                                                 0
1154 #define mmSDMA1_UTCL1_RD_STATUS                                                                        0x063e
1155 #define mmSDMA1_UTCL1_RD_STATUS_BASE_IDX                                                               0
1156 #define mmSDMA1_UTCL1_WR_STATUS                                                                        0x063f
1157 #define mmSDMA1_UTCL1_WR_STATUS_BASE_IDX                                                               0
1158 #define mmSDMA1_UTCL1_INV0                                                                             0x0640
1159 #define mmSDMA1_UTCL1_INV0_BASE_IDX                                                                    0
1160 #define mmSDMA1_UTCL1_INV1                                                                             0x0641
1161 #define mmSDMA1_UTCL1_INV1_BASE_IDX                                                                    0
1162 #define mmSDMA1_UTCL1_INV2                                                                             0x0642
1163 #define mmSDMA1_UTCL1_INV2_BASE_IDX                                                                    0
1164 #define mmSDMA1_UTCL1_RD_XNACK0                                                                        0x0643
1165 #define mmSDMA1_UTCL1_RD_XNACK0_BASE_IDX                                                               0
1166 #define mmSDMA1_UTCL1_RD_XNACK1                                                                        0x0644
1167 #define mmSDMA1_UTCL1_RD_XNACK1_BASE_IDX                                                               0
1168 #define mmSDMA1_UTCL1_WR_XNACK0                                                                        0x0645
1169 #define mmSDMA1_UTCL1_WR_XNACK0_BASE_IDX                                                               0
1170 #define mmSDMA1_UTCL1_WR_XNACK1                                                                        0x0646
1171 #define mmSDMA1_UTCL1_WR_XNACK1_BASE_IDX                                                               0
1172 #define mmSDMA1_UTCL1_TIMEOUT                                                                          0x0647
1173 #define mmSDMA1_UTCL1_TIMEOUT_BASE_IDX                                                                 0
1174 #define mmSDMA1_UTCL1_PAGE                                                                             0x0648
1175 #define mmSDMA1_UTCL1_PAGE_BASE_IDX                                                                    0
1176 #define mmSDMA1_RELAX_ORDERING_LUT                                                                     0x064a
1177 #define mmSDMA1_RELAX_ORDERING_LUT_BASE_IDX                                                            0
1178 #define mmSDMA1_CHICKEN_BITS_2                                                                         0x064b
1179 #define mmSDMA1_CHICKEN_BITS_2_BASE_IDX                                                                0
1180 #define mmSDMA1_STATUS3_REG                                                                            0x064c
1181 #define mmSDMA1_STATUS3_REG_BASE_IDX                                                                   0
1182 #define mmSDMA1_PHYSICAL_ADDR_LO                                                                       0x064d
1183 #define mmSDMA1_PHYSICAL_ADDR_LO_BASE_IDX                                                              0
1184 #define mmSDMA1_PHYSICAL_ADDR_HI                                                                       0x064e
1185 #define mmSDMA1_PHYSICAL_ADDR_HI_BASE_IDX                                                              0
1186 #define mmSDMA1_PHASE2_QUANTUM                                                                         0x064f
1187 #define mmSDMA1_PHASE2_QUANTUM_BASE_IDX                                                                0
1188 #define mmSDMA1_ERROR_LOG                                                                              0x0650
1189 #define mmSDMA1_ERROR_LOG_BASE_IDX                                                                     0
1190 #define mmSDMA1_PUB_DUMMY_REG0                                                                         0x0651
1191 #define mmSDMA1_PUB_DUMMY_REG0_BASE_IDX                                                                0
1192 #define mmSDMA1_PUB_DUMMY_REG1                                                                         0x0652
1193 #define mmSDMA1_PUB_DUMMY_REG1_BASE_IDX                                                                0
1194 #define mmSDMA1_PUB_DUMMY_REG2                                                                         0x0653
1195 #define mmSDMA1_PUB_DUMMY_REG2_BASE_IDX                                                                0
1196 #define mmSDMA1_PUB_DUMMY_REG3                                                                         0x0654
1197 #define mmSDMA1_PUB_DUMMY_REG3_BASE_IDX                                                                0
1198 #define mmSDMA1_F32_COUNTER                                                                            0x0655
1199 #define mmSDMA1_F32_COUNTER_BASE_IDX                                                                   0
1200 #define mmSDMA1_CRD_CNTL                                                                               0x065b
1201 #define mmSDMA1_CRD_CNTL_BASE_IDX                                                                      0
1202 #define mmSDMA1_AQL_STATUS                                                                             0x065f
1203 #define mmSDMA1_AQL_STATUS_BASE_IDX                                                                    0
1204 #define mmSDMA1_EA_DBIT_ADDR_DATA                                                                      0x0660
1205 #define mmSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX                                                             0
1206 #define mmSDMA1_EA_DBIT_ADDR_INDEX                                                                     0x0661
1207 #define mmSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX                                                            0
1208 #define mmSDMA1_TLBI_GCR_CNTL                                                                          0x0662
1209 #define mmSDMA1_TLBI_GCR_CNTL_BASE_IDX                                                                 0
1210 #define mmSDMA1_TILING_CONFIG                                                                          0x0663
1211 #define mmSDMA1_TILING_CONFIG_BASE_IDX                                                                 0
1212 #define mmSDMA1_INT_STATUS                                                                             0x0670
1213 #define mmSDMA1_INT_STATUS_BASE_IDX                                                                    0
1214 #define mmSDMA1_HOLE_ADDR_LO                                                                           0x0672
1215 #define mmSDMA1_HOLE_ADDR_LO_BASE_IDX                                                                  0
1216 #define mmSDMA1_HOLE_ADDR_HI                                                                           0x0673
1217 #define mmSDMA1_HOLE_ADDR_HI_BASE_IDX                                                                  0
1218 #define mmSDMA1_CLOCK_GATING_REG                                                                       0x0675
1219 #define mmSDMA1_CLOCK_GATING_REG_BASE_IDX                                                              0
1220 #define mmSDMA1_STATUS4_REG                                                                            0x0676
1221 #define mmSDMA1_STATUS4_REG_BASE_IDX                                                                   0
1222 #define mmSDMA1_SCRATCH_RAM_DATA                                                                       0x0677
1223 #define mmSDMA1_SCRATCH_RAM_DATA_BASE_IDX                                                              0
1224 #define mmSDMA1_SCRATCH_RAM_ADDR                                                                       0x0678
1225 #define mmSDMA1_SCRATCH_RAM_ADDR_BASE_IDX                                                              0
1226 #define mmSDMA1_TIMESTAMP_CNTL                                                                         0x0679
1227 #define mmSDMA1_TIMESTAMP_CNTL_BASE_IDX                                                                0
1228 #define mmSDMA1_STATUS5_REG                                                                            0x067a
1229 #define mmSDMA1_STATUS5_REG_BASE_IDX                                                                   0
1230 #define mmSDMA1_QUEUE_RESET_REQ                                                                        0x067b
1231 #define mmSDMA1_QUEUE_RESET_REQ_BASE_IDX                                                               0
1232 #define mmSDMA1_GFX_RB_CNTL                                                                            0x0680
1233 #define mmSDMA1_GFX_RB_CNTL_BASE_IDX                                                                   0
1234 #define mmSDMA1_GFX_RB_BASE                                                                            0x0681
1235 #define mmSDMA1_GFX_RB_BASE_BASE_IDX                                                                   0
1236 #define mmSDMA1_GFX_RB_BASE_HI                                                                         0x0682
1237 #define mmSDMA1_GFX_RB_BASE_HI_BASE_IDX                                                                0
1238 #define mmSDMA1_GFX_RB_RPTR                                                                            0x0683
1239 #define mmSDMA1_GFX_RB_RPTR_BASE_IDX                                                                   0
1240 #define mmSDMA1_GFX_RB_RPTR_HI                                                                         0x0684
1241 #define mmSDMA1_GFX_RB_RPTR_HI_BASE_IDX                                                                0
1242 #define mmSDMA1_GFX_RB_WPTR                                                                            0x0685
1243 #define mmSDMA1_GFX_RB_WPTR_BASE_IDX                                                                   0
1244 #define mmSDMA1_GFX_RB_WPTR_HI                                                                         0x0686
1245 #define mmSDMA1_GFX_RB_WPTR_HI_BASE_IDX                                                                0
1246 #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL                                                                  0x0687
1247 #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX                                                         0
1248 #define mmSDMA1_GFX_RB_RPTR_ADDR_HI                                                                    0x0688
1249 #define mmSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX                                                           0
1250 #define mmSDMA1_GFX_RB_RPTR_ADDR_LO                                                                    0x0689
1251 #define mmSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX                                                           0
1252 #define mmSDMA1_GFX_IB_CNTL                                                                            0x068a
1253 #define mmSDMA1_GFX_IB_CNTL_BASE_IDX                                                                   0
1254 #define mmSDMA1_GFX_IB_RPTR                                                                            0x068b
1255 #define mmSDMA1_GFX_IB_RPTR_BASE_IDX                                                                   0
1256 #define mmSDMA1_GFX_IB_OFFSET                                                                          0x068c
1257 #define mmSDMA1_GFX_IB_OFFSET_BASE_IDX                                                                 0
1258 #define mmSDMA1_GFX_IB_BASE_LO                                                                         0x068d
1259 #define mmSDMA1_GFX_IB_BASE_LO_BASE_IDX                                                                0
1260 #define mmSDMA1_GFX_IB_BASE_HI                                                                         0x068e
1261 #define mmSDMA1_GFX_IB_BASE_HI_BASE_IDX                                                                0
1262 #define mmSDMA1_GFX_IB_SIZE                                                                            0x068f
1263 #define mmSDMA1_GFX_IB_SIZE_BASE_IDX                                                                   0
1264 #define mmSDMA1_GFX_SKIP_CNTL                                                                          0x0690
1265 #define mmSDMA1_GFX_SKIP_CNTL_BASE_IDX                                                                 0
1266 #define mmSDMA1_GFX_CONTEXT_STATUS                                                                     0x0691
1267 #define mmSDMA1_GFX_CONTEXT_STATUS_BASE_IDX                                                            0
1268 #define mmSDMA1_GFX_DOORBELL                                                                           0x0692
1269 #define mmSDMA1_GFX_DOORBELL_BASE_IDX                                                                  0
1270 #define mmSDMA1_GFX_CONTEXT_CNTL                                                                       0x0693
1271 #define mmSDMA1_GFX_CONTEXT_CNTL_BASE_IDX                                                              0
1272 #define mmSDMA1_GFX_STATUS                                                                             0x06a8
1273 #define mmSDMA1_GFX_STATUS_BASE_IDX                                                                    0
1274 #define mmSDMA1_GFX_DOORBELL_LOG                                                                       0x06a9
1275 #define mmSDMA1_GFX_DOORBELL_LOG_BASE_IDX                                                              0
1276 #define mmSDMA1_GFX_WATERMARK                                                                          0x06aa
1277 #define mmSDMA1_GFX_WATERMARK_BASE_IDX                                                                 0
1278 #define mmSDMA1_GFX_DOORBELL_OFFSET                                                                    0x06ab
1279 #define mmSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX                                                           0
1280 #define mmSDMA1_GFX_CSA_ADDR_LO                                                                        0x06ac
1281 #define mmSDMA1_GFX_CSA_ADDR_LO_BASE_IDX                                                               0
1282 #define mmSDMA1_GFX_CSA_ADDR_HI                                                                        0x06ad
1283 #define mmSDMA1_GFX_CSA_ADDR_HI_BASE_IDX                                                               0
1284 #define mmSDMA1_GFX_IB_SUB_REMAIN                                                                      0x06af
1285 #define mmSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX                                                             0
1286 #define mmSDMA1_GFX_PREEMPT                                                                            0x06b0
1287 #define mmSDMA1_GFX_PREEMPT_BASE_IDX                                                                   0
1288 #define mmSDMA1_GFX_DUMMY_REG                                                                          0x06b1
1289 #define mmSDMA1_GFX_DUMMY_REG_BASE_IDX                                                                 0
1290 #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI                                                               0x06b2
1291 #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                      0
1292 #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO                                                               0x06b3
1293 #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                      0
1294 #define mmSDMA1_GFX_RB_AQL_CNTL                                                                        0x06b4
1295 #define mmSDMA1_GFX_RB_AQL_CNTL_BASE_IDX                                                               0
1296 #define mmSDMA1_GFX_MINOR_PTR_UPDATE                                                                   0x06b5
1297 #define mmSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX                                                          0
1298 #define mmSDMA1_GFX_MIDCMD_DATA0                                                                       0x06c0
1299 #define mmSDMA1_GFX_MIDCMD_DATA0_BASE_IDX                                                              0
1300 #define mmSDMA1_GFX_MIDCMD_DATA1                                                                       0x06c1
1301 #define mmSDMA1_GFX_MIDCMD_DATA1_BASE_IDX                                                              0
1302 #define mmSDMA1_GFX_MIDCMD_DATA2                                                                       0x06c2
1303 #define mmSDMA1_GFX_MIDCMD_DATA2_BASE_IDX                                                              0
1304 #define mmSDMA1_GFX_MIDCMD_DATA3                                                                       0x06c3
1305 #define mmSDMA1_GFX_MIDCMD_DATA3_BASE_IDX                                                              0
1306 #define mmSDMA1_GFX_MIDCMD_DATA4                                                                       0x06c4
1307 #define mmSDMA1_GFX_MIDCMD_DATA4_BASE_IDX                                                              0
1308 #define mmSDMA1_GFX_MIDCMD_DATA5                                                                       0x06c5
1309 #define mmSDMA1_GFX_MIDCMD_DATA5_BASE_IDX                                                              0
1310 #define mmSDMA1_GFX_MIDCMD_DATA6                                                                       0x06c6
1311 #define mmSDMA1_GFX_MIDCMD_DATA6_BASE_IDX                                                              0
1312 #define mmSDMA1_GFX_MIDCMD_DATA7                                                                       0x06c7
1313 #define mmSDMA1_GFX_MIDCMD_DATA7_BASE_IDX                                                              0
1314 #define mmSDMA1_GFX_MIDCMD_DATA8                                                                       0x06c8
1315 #define mmSDMA1_GFX_MIDCMD_DATA8_BASE_IDX                                                              0
1316 #define mmSDMA1_GFX_MIDCMD_DATA9                                                                       0x06c9
1317 #define mmSDMA1_GFX_MIDCMD_DATA9_BASE_IDX                                                              0
1318 #define mmSDMA1_GFX_MIDCMD_DATA10                                                                      0x06ca
1319 #define mmSDMA1_GFX_MIDCMD_DATA10_BASE_IDX                                                             0
1320 #define mmSDMA1_GFX_MIDCMD_CNTL                                                                        0x06cb
1321 #define mmSDMA1_GFX_MIDCMD_CNTL_BASE_IDX                                                               0
1322 #define mmSDMA1_PAGE_RB_CNTL                                                                           0x06d8
1323 #define mmSDMA1_PAGE_RB_CNTL_BASE_IDX                                                                  0
1324 #define mmSDMA1_PAGE_RB_BASE                                                                           0x06d9
1325 #define mmSDMA1_PAGE_RB_BASE_BASE_IDX                                                                  0
1326 #define mmSDMA1_PAGE_RB_BASE_HI                                                                        0x06da
1327 #define mmSDMA1_PAGE_RB_BASE_HI_BASE_IDX                                                               0
1328 #define mmSDMA1_PAGE_RB_RPTR                                                                           0x06db
1329 #define mmSDMA1_PAGE_RB_RPTR_BASE_IDX                                                                  0
1330 #define mmSDMA1_PAGE_RB_RPTR_HI                                                                        0x06dc
1331 #define mmSDMA1_PAGE_RB_RPTR_HI_BASE_IDX                                                               0
1332 #define mmSDMA1_PAGE_RB_WPTR                                                                           0x06dd
1333 #define mmSDMA1_PAGE_RB_WPTR_BASE_IDX                                                                  0
1334 #define mmSDMA1_PAGE_RB_WPTR_HI                                                                        0x06de
1335 #define mmSDMA1_PAGE_RB_WPTR_HI_BASE_IDX                                                               0
1336 #define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL                                                                 0x06df
1337 #define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
1338 #define mmSDMA1_PAGE_RB_RPTR_ADDR_HI                                                                   0x06e0
1339 #define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
1340 #define mmSDMA1_PAGE_RB_RPTR_ADDR_LO                                                                   0x06e1
1341 #define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
1342 #define mmSDMA1_PAGE_IB_CNTL                                                                           0x06e2
1343 #define mmSDMA1_PAGE_IB_CNTL_BASE_IDX                                                                  0
1344 #define mmSDMA1_PAGE_IB_RPTR                                                                           0x06e3
1345 #define mmSDMA1_PAGE_IB_RPTR_BASE_IDX                                                                  0
1346 #define mmSDMA1_PAGE_IB_OFFSET                                                                         0x06e4
1347 #define mmSDMA1_PAGE_IB_OFFSET_BASE_IDX                                                                0
1348 #define mmSDMA1_PAGE_IB_BASE_LO                                                                        0x06e5
1349 #define mmSDMA1_PAGE_IB_BASE_LO_BASE_IDX                                                               0
1350 #define mmSDMA1_PAGE_IB_BASE_HI                                                                        0x06e6
1351 #define mmSDMA1_PAGE_IB_BASE_HI_BASE_IDX                                                               0
1352 #define mmSDMA1_PAGE_IB_SIZE                                                                           0x06e7
1353 #define mmSDMA1_PAGE_IB_SIZE_BASE_IDX                                                                  0
1354 #define mmSDMA1_PAGE_SKIP_CNTL                                                                         0x06e8
1355 #define mmSDMA1_PAGE_SKIP_CNTL_BASE_IDX                                                                0
1356 #define mmSDMA1_PAGE_CONTEXT_STATUS                                                                    0x06e9
1357 #define mmSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX                                                           0
1358 #define mmSDMA1_PAGE_DOORBELL                                                                          0x06ea
1359 #define mmSDMA1_PAGE_DOORBELL_BASE_IDX                                                                 0
1360 #define mmSDMA1_PAGE_STATUS                                                                            0x0700
1361 #define mmSDMA1_PAGE_STATUS_BASE_IDX                                                                   0
1362 #define mmSDMA1_PAGE_DOORBELL_LOG                                                                      0x0701
1363 #define mmSDMA1_PAGE_DOORBELL_LOG_BASE_IDX                                                             0
1364 #define mmSDMA1_PAGE_WATERMARK                                                                         0x0702
1365 #define mmSDMA1_PAGE_WATERMARK_BASE_IDX                                                                0
1366 #define mmSDMA1_PAGE_DOORBELL_OFFSET                                                                   0x0703
1367 #define mmSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX                                                          0
1368 #define mmSDMA1_PAGE_CSA_ADDR_LO                                                                       0x0704
1369 #define mmSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX                                                              0
1370 #define mmSDMA1_PAGE_CSA_ADDR_HI                                                                       0x0705
1371 #define mmSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX                                                              0
1372 #define mmSDMA1_PAGE_IB_SUB_REMAIN                                                                     0x0707
1373 #define mmSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX                                                            0
1374 #define mmSDMA1_PAGE_PREEMPT                                                                           0x0708
1375 #define mmSDMA1_PAGE_PREEMPT_BASE_IDX                                                                  0
1376 #define mmSDMA1_PAGE_DUMMY_REG                                                                         0x0709
1377 #define mmSDMA1_PAGE_DUMMY_REG_BASE_IDX                                                                0
1378 #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI                                                              0x070a
1379 #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
1380 #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO                                                              0x070b
1381 #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
1382 #define mmSDMA1_PAGE_RB_AQL_CNTL                                                                       0x070c
1383 #define mmSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX                                                              0
1384 #define mmSDMA1_PAGE_MINOR_PTR_UPDATE                                                                  0x070d
1385 #define mmSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX                                                         0
1386 #define mmSDMA1_PAGE_MIDCMD_DATA0                                                                      0x0718
1387 #define mmSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX                                                             0
1388 #define mmSDMA1_PAGE_MIDCMD_DATA1                                                                      0x0719
1389 #define mmSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX                                                             0
1390 #define mmSDMA1_PAGE_MIDCMD_DATA2                                                                      0x071a
1391 #define mmSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX                                                             0
1392 #define mmSDMA1_PAGE_MIDCMD_DATA3                                                                      0x071b
1393 #define mmSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX                                                             0
1394 #define mmSDMA1_PAGE_MIDCMD_DATA4                                                                      0x071c
1395 #define mmSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX                                                             0
1396 #define mmSDMA1_PAGE_MIDCMD_DATA5                                                                      0x071d
1397 #define mmSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX                                                             0
1398 #define mmSDMA1_PAGE_MIDCMD_DATA6                                                                      0x071e
1399 #define mmSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX                                                             0
1400 #define mmSDMA1_PAGE_MIDCMD_DATA7                                                                      0x071f
1401 #define mmSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX                                                             0
1402 #define mmSDMA1_PAGE_MIDCMD_DATA8                                                                      0x0720
1403 #define mmSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX                                                             0
1404 #define mmSDMA1_PAGE_MIDCMD_DATA9                                                                      0x0721
1405 #define mmSDMA1_PAGE_MIDCMD_DATA9_BASE_IDX                                                             0
1406 #define mmSDMA1_PAGE_MIDCMD_DATA10                                                                     0x0722
1407 #define mmSDMA1_PAGE_MIDCMD_DATA10_BASE_IDX                                                            0
1408 #define mmSDMA1_PAGE_MIDCMD_CNTL                                                                       0x0723
1409 #define mmSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX                                                              0
1410 #define mmSDMA1_RLC0_RB_CNTL                                                                           0x0730
1411 #define mmSDMA1_RLC0_RB_CNTL_BASE_IDX                                                                  0
1412 #define mmSDMA1_RLC0_RB_BASE                                                                           0x0731
1413 #define mmSDMA1_RLC0_RB_BASE_BASE_IDX                                                                  0
1414 #define mmSDMA1_RLC0_RB_BASE_HI                                                                        0x0732
1415 #define mmSDMA1_RLC0_RB_BASE_HI_BASE_IDX                                                               0
1416 #define mmSDMA1_RLC0_RB_RPTR                                                                           0x0733
1417 #define mmSDMA1_RLC0_RB_RPTR_BASE_IDX                                                                  0
1418 #define mmSDMA1_RLC0_RB_RPTR_HI                                                                        0x0734
1419 #define mmSDMA1_RLC0_RB_RPTR_HI_BASE_IDX                                                               0
1420 #define mmSDMA1_RLC0_RB_WPTR                                                                           0x0735
1421 #define mmSDMA1_RLC0_RB_WPTR_BASE_IDX                                                                  0
1422 #define mmSDMA1_RLC0_RB_WPTR_HI                                                                        0x0736
1423 #define mmSDMA1_RLC0_RB_WPTR_HI_BASE_IDX                                                               0
1424 #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL                                                                 0x0737
1425 #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
1426 #define mmSDMA1_RLC0_RB_RPTR_ADDR_HI                                                                   0x0738
1427 #define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
1428 #define mmSDMA1_RLC0_RB_RPTR_ADDR_LO                                                                   0x0739
1429 #define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
1430 #define mmSDMA1_RLC0_IB_CNTL                                                                           0x073a
1431 #define mmSDMA1_RLC0_IB_CNTL_BASE_IDX                                                                  0
1432 #define mmSDMA1_RLC0_IB_RPTR                                                                           0x073b
1433 #define mmSDMA1_RLC0_IB_RPTR_BASE_IDX                                                                  0
1434 #define mmSDMA1_RLC0_IB_OFFSET                                                                         0x073c
1435 #define mmSDMA1_RLC0_IB_OFFSET_BASE_IDX                                                                0
1436 #define mmSDMA1_RLC0_IB_BASE_LO                                                                        0x073d
1437 #define mmSDMA1_RLC0_IB_BASE_LO_BASE_IDX                                                               0
1438 #define mmSDMA1_RLC0_IB_BASE_HI                                                                        0x073e
1439 #define mmSDMA1_RLC0_IB_BASE_HI_BASE_IDX                                                               0
1440 #define mmSDMA1_RLC0_IB_SIZE                                                                           0x073f
1441 #define mmSDMA1_RLC0_IB_SIZE_BASE_IDX                                                                  0
1442 #define mmSDMA1_RLC0_SKIP_CNTL                                                                         0x0740
1443 #define mmSDMA1_RLC0_SKIP_CNTL_BASE_IDX                                                                0
1444 #define mmSDMA1_RLC0_CONTEXT_STATUS                                                                    0x0741
1445 #define mmSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX                                                           0
1446 #define mmSDMA1_RLC0_DOORBELL                                                                          0x0742
1447 #define mmSDMA1_RLC0_DOORBELL_BASE_IDX                                                                 0
1448 #define mmSDMA1_RLC0_STATUS                                                                            0x0758
1449 #define mmSDMA1_RLC0_STATUS_BASE_IDX                                                                   0
1450 #define mmSDMA1_RLC0_DOORBELL_LOG                                                                      0x0759
1451 #define mmSDMA1_RLC0_DOORBELL_LOG_BASE_IDX                                                             0
1452 #define mmSDMA1_RLC0_WATERMARK                                                                         0x075a
1453 #define mmSDMA1_RLC0_WATERMARK_BASE_IDX                                                                0
1454 #define mmSDMA1_RLC0_DOORBELL_OFFSET                                                                   0x075b
1455 #define mmSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX                                                          0
1456 #define mmSDMA1_RLC0_CSA_ADDR_LO                                                                       0x075c
1457 #define mmSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX                                                              0
1458 #define mmSDMA1_RLC0_CSA_ADDR_HI                                                                       0x075d
1459 #define mmSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX                                                              0
1460 #define mmSDMA1_RLC0_IB_SUB_REMAIN                                                                     0x075f
1461 #define mmSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX                                                            0
1462 #define mmSDMA1_RLC0_PREEMPT                                                                           0x0760
1463 #define mmSDMA1_RLC0_PREEMPT_BASE_IDX                                                                  0
1464 #define mmSDMA1_RLC0_DUMMY_REG                                                                         0x0761
1465 #define mmSDMA1_RLC0_DUMMY_REG_BASE_IDX                                                                0
1466 #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI                                                              0x0762
1467 #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
1468 #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO                                                              0x0763
1469 #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
1470 #define mmSDMA1_RLC0_RB_AQL_CNTL                                                                       0x0764
1471 #define mmSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX                                                              0
1472 #define mmSDMA1_RLC0_MINOR_PTR_UPDATE                                                                  0x0765
1473 #define mmSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX                                                         0
1474 #define mmSDMA1_RLC0_MIDCMD_DATA0                                                                      0x0770
1475 #define mmSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX                                                             0
1476 #define mmSDMA1_RLC0_MIDCMD_DATA1                                                                      0x0771
1477 #define mmSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX                                                             0
1478 #define mmSDMA1_RLC0_MIDCMD_DATA2                                                                      0x0772
1479 #define mmSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX                                                             0
1480 #define mmSDMA1_RLC0_MIDCMD_DATA3                                                                      0x0773
1481 #define mmSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX                                                             0
1482 #define mmSDMA1_RLC0_MIDCMD_DATA4                                                                      0x0774
1483 #define mmSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX                                                             0
1484 #define mmSDMA1_RLC0_MIDCMD_DATA5                                                                      0x0775
1485 #define mmSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX                                                             0
1486 #define mmSDMA1_RLC0_MIDCMD_DATA6                                                                      0x0776
1487 #define mmSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX                                                             0
1488 #define mmSDMA1_RLC0_MIDCMD_DATA7                                                                      0x0777
1489 #define mmSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX                                                             0
1490 #define mmSDMA1_RLC0_MIDCMD_DATA8                                                                      0x0778
1491 #define mmSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX                                                             0
1492 #define mmSDMA1_RLC0_MIDCMD_DATA9                                                                      0x0779
1493 #define mmSDMA1_RLC0_MIDCMD_DATA9_BASE_IDX                                                             0
1494 #define mmSDMA1_RLC0_MIDCMD_DATA10                                                                     0x077a
1495 #define mmSDMA1_RLC0_MIDCMD_DATA10_BASE_IDX                                                            0
1496 #define mmSDMA1_RLC0_MIDCMD_CNTL                                                                       0x077b
1497 #define mmSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX                                                              0
1498 #define mmSDMA1_RLC1_RB_CNTL                                                                           0x0788
1499 #define mmSDMA1_RLC1_RB_CNTL_BASE_IDX                                                                  0
1500 #define mmSDMA1_RLC1_RB_BASE                                                                           0x0789
1501 #define mmSDMA1_RLC1_RB_BASE_BASE_IDX                                                                  0
1502 #define mmSDMA1_RLC1_RB_BASE_HI                                                                        0x078a
1503 #define mmSDMA1_RLC1_RB_BASE_HI_BASE_IDX                                                               0
1504 #define mmSDMA1_RLC1_RB_RPTR                                                                           0x078b
1505 #define mmSDMA1_RLC1_RB_RPTR_BASE_IDX                                                                  0
1506 #define mmSDMA1_RLC1_RB_RPTR_HI                                                                        0x078c
1507 #define mmSDMA1_RLC1_RB_RPTR_HI_BASE_IDX                                                               0
1508 #define mmSDMA1_RLC1_RB_WPTR                                                                           0x078d
1509 #define mmSDMA1_RLC1_RB_WPTR_BASE_IDX                                                                  0
1510 #define mmSDMA1_RLC1_RB_WPTR_HI                                                                        0x078e
1511 #define mmSDMA1_RLC1_RB_WPTR_HI_BASE_IDX                                                               0
1512 #define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL                                                                 0x078f
1513 #define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
1514 #define mmSDMA1_RLC1_RB_RPTR_ADDR_HI                                                                   0x0790
1515 #define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
1516 #define mmSDMA1_RLC1_RB_RPTR_ADDR_LO                                                                   0x0791
1517 #define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
1518 #define mmSDMA1_RLC1_IB_CNTL                                                                           0x0792
1519 #define mmSDMA1_RLC1_IB_CNTL_BASE_IDX                                                                  0
1520 #define mmSDMA1_RLC1_IB_RPTR                                                                           0x0793
1521 #define mmSDMA1_RLC1_IB_RPTR_BASE_IDX                                                                  0
1522 #define mmSDMA1_RLC1_IB_OFFSET                                                                         0x0794
1523 #define mmSDMA1_RLC1_IB_OFFSET_BASE_IDX                                                                0
1524 #define mmSDMA1_RLC1_IB_BASE_LO                                                                        0x0795
1525 #define mmSDMA1_RLC1_IB_BASE_LO_BASE_IDX                                                               0
1526 #define mmSDMA1_RLC1_IB_BASE_HI                                                                        0x0796
1527 #define mmSDMA1_RLC1_IB_BASE_HI_BASE_IDX                                                               0
1528 #define mmSDMA1_RLC1_IB_SIZE                                                                           0x0797
1529 #define mmSDMA1_RLC1_IB_SIZE_BASE_IDX                                                                  0
1530 #define mmSDMA1_RLC1_SKIP_CNTL                                                                         0x0798
1531 #define mmSDMA1_RLC1_SKIP_CNTL_BASE_IDX                                                                0
1532 #define mmSDMA1_RLC1_CONTEXT_STATUS                                                                    0x0799
1533 #define mmSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX                                                           0
1534 #define mmSDMA1_RLC1_DOORBELL                                                                          0x079a
1535 #define mmSDMA1_RLC1_DOORBELL_BASE_IDX                                                                 0
1536 #define mmSDMA1_RLC1_STATUS                                                                            0x07b0
1537 #define mmSDMA1_RLC1_STATUS_BASE_IDX                                                                   0
1538 #define mmSDMA1_RLC1_DOORBELL_LOG                                                                      0x07b1
1539 #define mmSDMA1_RLC1_DOORBELL_LOG_BASE_IDX                                                             0
1540 #define mmSDMA1_RLC1_WATERMARK                                                                         0x07b2
1541 #define mmSDMA1_RLC1_WATERMARK_BASE_IDX                                                                0
1542 #define mmSDMA1_RLC1_DOORBELL_OFFSET                                                                   0x07b3
1543 #define mmSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX                                                          0
1544 #define mmSDMA1_RLC1_CSA_ADDR_LO                                                                       0x07b4
1545 #define mmSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX                                                              0
1546 #define mmSDMA1_RLC1_CSA_ADDR_HI                                                                       0x07b5
1547 #define mmSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX                                                              0
1548 #define mmSDMA1_RLC1_IB_SUB_REMAIN                                                                     0x07b7
1549 #define mmSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX                                                            0
1550 #define mmSDMA1_RLC1_PREEMPT                                                                           0x07b8
1551 #define mmSDMA1_RLC1_PREEMPT_BASE_IDX                                                                  0
1552 #define mmSDMA1_RLC1_DUMMY_REG                                                                         0x07b9
1553 #define mmSDMA1_RLC1_DUMMY_REG_BASE_IDX                                                                0
1554 #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI                                                              0x07ba
1555 #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
1556 #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO                                                              0x07bb
1557 #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
1558 #define mmSDMA1_RLC1_RB_AQL_CNTL                                                                       0x07bc
1559 #define mmSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX                                                              0
1560 #define mmSDMA1_RLC1_MINOR_PTR_UPDATE                                                                  0x07bd
1561 #define mmSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX                                                         0
1562 #define mmSDMA1_RLC1_MIDCMD_DATA0                                                                      0x07c8
1563 #define mmSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX                                                             0
1564 #define mmSDMA1_RLC1_MIDCMD_DATA1                                                                      0x07c9
1565 #define mmSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX                                                             0
1566 #define mmSDMA1_RLC1_MIDCMD_DATA2                                                                      0x07ca
1567 #define mmSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX                                                             0
1568 #define mmSDMA1_RLC1_MIDCMD_DATA3                                                                      0x07cb
1569 #define mmSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX                                                             0
1570 #define mmSDMA1_RLC1_MIDCMD_DATA4                                                                      0x07cc
1571 #define mmSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX                                                             0
1572 #define mmSDMA1_RLC1_MIDCMD_DATA5                                                                      0x07cd
1573 #define mmSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX                                                             0
1574 #define mmSDMA1_RLC1_MIDCMD_DATA6                                                                      0x07ce
1575 #define mmSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX                                                             0
1576 #define mmSDMA1_RLC1_MIDCMD_DATA7                                                                      0x07cf
1577 #define mmSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX                                                             0
1578 #define mmSDMA1_RLC1_MIDCMD_DATA8                                                                      0x07d0
1579 #define mmSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX                                                             0
1580 #define mmSDMA1_RLC1_MIDCMD_DATA9                                                                      0x07d1
1581 #define mmSDMA1_RLC1_MIDCMD_DATA9_BASE_IDX                                                             0
1582 #define mmSDMA1_RLC1_MIDCMD_DATA10                                                                     0x07d2
1583 #define mmSDMA1_RLC1_MIDCMD_DATA10_BASE_IDX                                                            0
1584 #define mmSDMA1_RLC1_MIDCMD_CNTL                                                                       0x07d3
1585 #define mmSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX                                                              0
1586 #define mmSDMA1_RLC2_RB_CNTL                                                                           0x07e0
1587 #define mmSDMA1_RLC2_RB_CNTL_BASE_IDX                                                                  0
1588 #define mmSDMA1_RLC2_RB_BASE                                                                           0x07e1
1589 #define mmSDMA1_RLC2_RB_BASE_BASE_IDX                                                                  0
1590 #define mmSDMA1_RLC2_RB_BASE_HI                                                                        0x07e2
1591 #define mmSDMA1_RLC2_RB_BASE_HI_BASE_IDX                                                               0
1592 #define mmSDMA1_RLC2_RB_RPTR                                                                           0x07e3
1593 #define mmSDMA1_RLC2_RB_RPTR_BASE_IDX                                                                  0
1594 #define mmSDMA1_RLC2_RB_RPTR_HI                                                                        0x07e4
1595 #define mmSDMA1_RLC2_RB_RPTR_HI_BASE_IDX                                                               0
1596 #define mmSDMA1_RLC2_RB_WPTR                                                                           0x07e5
1597 #define mmSDMA1_RLC2_RB_WPTR_BASE_IDX                                                                  0
1598 #define mmSDMA1_RLC2_RB_WPTR_HI                                                                        0x07e6
1599 #define mmSDMA1_RLC2_RB_WPTR_HI_BASE_IDX                                                               0
1600 #define mmSDMA1_RLC2_RB_WPTR_POLL_CNTL                                                                 0x07e7
1601 #define mmSDMA1_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
1602 #define mmSDMA1_RLC2_RB_RPTR_ADDR_HI                                                                   0x07e8
1603 #define mmSDMA1_RLC2_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
1604 #define mmSDMA1_RLC2_RB_RPTR_ADDR_LO                                                                   0x07e9
1605 #define mmSDMA1_RLC2_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
1606 #define mmSDMA1_RLC2_IB_CNTL                                                                           0x07ea
1607 #define mmSDMA1_RLC2_IB_CNTL_BASE_IDX                                                                  0
1608 #define mmSDMA1_RLC2_IB_RPTR                                                                           0x07eb
1609 #define mmSDMA1_RLC2_IB_RPTR_BASE_IDX                                                                  0
1610 #define mmSDMA1_RLC2_IB_OFFSET                                                                         0x07ec
1611 #define mmSDMA1_RLC2_IB_OFFSET_BASE_IDX                                                                0
1612 #define mmSDMA1_RLC2_IB_BASE_LO                                                                        0x07ed
1613 #define mmSDMA1_RLC2_IB_BASE_LO_BASE_IDX                                                               0
1614 #define mmSDMA1_RLC2_IB_BASE_HI                                                                        0x07ee
1615 #define mmSDMA1_RLC2_IB_BASE_HI_BASE_IDX                                                               0
1616 #define mmSDMA1_RLC2_IB_SIZE                                                                           0x07ef
1617 #define mmSDMA1_RLC2_IB_SIZE_BASE_IDX                                                                  0
1618 #define mmSDMA1_RLC2_SKIP_CNTL                                                                         0x07f0
1619 #define mmSDMA1_RLC2_SKIP_CNTL_BASE_IDX                                                                0
1620 #define mmSDMA1_RLC2_CONTEXT_STATUS                                                                    0x07f1
1621 #define mmSDMA1_RLC2_CONTEXT_STATUS_BASE_IDX                                                           0
1622 #define mmSDMA1_RLC2_DOORBELL                                                                          0x07f2
1623 #define mmSDMA1_RLC2_DOORBELL_BASE_IDX                                                                 0
1624 #define mmSDMA1_RLC2_STATUS                                                                            0x0808
1625 #define mmSDMA1_RLC2_STATUS_BASE_IDX                                                                   0
1626 #define mmSDMA1_RLC2_DOORBELL_LOG                                                                      0x0809
1627 #define mmSDMA1_RLC2_DOORBELL_LOG_BASE_IDX                                                             0
1628 #define mmSDMA1_RLC2_WATERMARK                                                                         0x080a
1629 #define mmSDMA1_RLC2_WATERMARK_BASE_IDX                                                                0
1630 #define mmSDMA1_RLC2_DOORBELL_OFFSET                                                                   0x080b
1631 #define mmSDMA1_RLC2_DOORBELL_OFFSET_BASE_IDX                                                          0
1632 #define mmSDMA1_RLC2_CSA_ADDR_LO                                                                       0x080c
1633 #define mmSDMA1_RLC2_CSA_ADDR_LO_BASE_IDX                                                              0
1634 #define mmSDMA1_RLC2_CSA_ADDR_HI                                                                       0x080d
1635 #define mmSDMA1_RLC2_CSA_ADDR_HI_BASE_IDX                                                              0
1636 #define mmSDMA1_RLC2_IB_SUB_REMAIN                                                                     0x080f
1637 #define mmSDMA1_RLC2_IB_SUB_REMAIN_BASE_IDX                                                            0
1638 #define mmSDMA1_RLC2_PREEMPT                                                                           0x0810
1639 #define mmSDMA1_RLC2_PREEMPT_BASE_IDX                                                                  0
1640 #define mmSDMA1_RLC2_DUMMY_REG                                                                         0x0811
1641 #define mmSDMA1_RLC2_DUMMY_REG_BASE_IDX                                                                0
1642 #define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI                                                              0x0812
1643 #define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
1644 #define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO                                                              0x0813
1645 #define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
1646 #define mmSDMA1_RLC2_RB_AQL_CNTL                                                                       0x0814
1647 #define mmSDMA1_RLC2_RB_AQL_CNTL_BASE_IDX                                                              0
1648 #define mmSDMA1_RLC2_MINOR_PTR_UPDATE                                                                  0x0815
1649 #define mmSDMA1_RLC2_MINOR_PTR_UPDATE_BASE_IDX                                                         0
1650 #define mmSDMA1_RLC2_MIDCMD_DATA0                                                                      0x0820
1651 #define mmSDMA1_RLC2_MIDCMD_DATA0_BASE_IDX                                                             0
1652 #define mmSDMA1_RLC2_MIDCMD_DATA1                                                                      0x0821
1653 #define mmSDMA1_RLC2_MIDCMD_DATA1_BASE_IDX                                                             0
1654 #define mmSDMA1_RLC2_MIDCMD_DATA2                                                                      0x0822
1655 #define mmSDMA1_RLC2_MIDCMD_DATA2_BASE_IDX                                                             0
1656 #define mmSDMA1_RLC2_MIDCMD_DATA3                                                                      0x0823
1657 #define mmSDMA1_RLC2_MIDCMD_DATA3_BASE_IDX                                                             0
1658 #define mmSDMA1_RLC2_MIDCMD_DATA4                                                                      0x0824
1659 #define mmSDMA1_RLC2_MIDCMD_DATA4_BASE_IDX                                                             0
1660 #define mmSDMA1_RLC2_MIDCMD_DATA5                                                                      0x0825
1661 #define mmSDMA1_RLC2_MIDCMD_DATA5_BASE_IDX                                                             0
1662 #define mmSDMA1_RLC2_MIDCMD_DATA6                                                                      0x0826
1663 #define mmSDMA1_RLC2_MIDCMD_DATA6_BASE_IDX                                                             0
1664 #define mmSDMA1_RLC2_MIDCMD_DATA7                                                                      0x0827
1665 #define mmSDMA1_RLC2_MIDCMD_DATA7_BASE_IDX                                                             0
1666 #define mmSDMA1_RLC2_MIDCMD_DATA8                                                                      0x0828
1667 #define mmSDMA1_RLC2_MIDCMD_DATA8_BASE_IDX                                                             0
1668 #define mmSDMA1_RLC2_MIDCMD_DATA9                                                                      0x0829
1669 #define mmSDMA1_RLC2_MIDCMD_DATA9_BASE_IDX                                                             0
1670 #define mmSDMA1_RLC2_MIDCMD_DATA10                                                                     0x082a
1671 #define mmSDMA1_RLC2_MIDCMD_DATA10_BASE_IDX                                                            0
1672 #define mmSDMA1_RLC2_MIDCMD_CNTL                                                                       0x082b
1673 #define mmSDMA1_RLC2_MIDCMD_CNTL_BASE_IDX                                                              0
1674 #define mmSDMA1_RLC3_RB_CNTL                                                                           0x0838
1675 #define mmSDMA1_RLC3_RB_CNTL_BASE_IDX                                                                  0
1676 #define mmSDMA1_RLC3_RB_BASE                                                                           0x0839
1677 #define mmSDMA1_RLC3_RB_BASE_BASE_IDX                                                                  0
1678 #define mmSDMA1_RLC3_RB_BASE_HI                                                                        0x083a
1679 #define mmSDMA1_RLC3_RB_BASE_HI_BASE_IDX                                                               0
1680 #define mmSDMA1_RLC3_RB_RPTR                                                                           0x083b
1681 #define mmSDMA1_RLC3_RB_RPTR_BASE_IDX                                                                  0
1682 #define mmSDMA1_RLC3_RB_RPTR_HI                                                                        0x083c
1683 #define mmSDMA1_RLC3_RB_RPTR_HI_BASE_IDX                                                               0
1684 #define mmSDMA1_RLC3_RB_WPTR                                                                           0x083d
1685 #define mmSDMA1_RLC3_RB_WPTR_BASE_IDX                                                                  0
1686 #define mmSDMA1_RLC3_RB_WPTR_HI                                                                        0x083e
1687 #define mmSDMA1_RLC3_RB_WPTR_HI_BASE_IDX                                                               0
1688 #define mmSDMA1_RLC3_RB_WPTR_POLL_CNTL                                                                 0x083f
1689 #define mmSDMA1_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
1690 #define mmSDMA1_RLC3_RB_RPTR_ADDR_HI                                                                   0x0840
1691 #define mmSDMA1_RLC3_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
1692 #define mmSDMA1_RLC3_RB_RPTR_ADDR_LO                                                                   0x0841
1693 #define mmSDMA1_RLC3_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
1694 #define mmSDMA1_RLC3_IB_CNTL                                                                           0x0842
1695 #define mmSDMA1_RLC3_IB_CNTL_BASE_IDX                                                                  0
1696 #define mmSDMA1_RLC3_IB_RPTR                                                                           0x0843
1697 #define mmSDMA1_RLC3_IB_RPTR_BASE_IDX                                                                  0
1698 #define mmSDMA1_RLC3_IB_OFFSET                                                                         0x0844
1699 #define mmSDMA1_RLC3_IB_OFFSET_BASE_IDX                                                                0
1700 #define mmSDMA1_RLC3_IB_BASE_LO                                                                        0x0845
1701 #define mmSDMA1_RLC3_IB_BASE_LO_BASE_IDX                                                               0
1702 #define mmSDMA1_RLC3_IB_BASE_HI                                                                        0x0846
1703 #define mmSDMA1_RLC3_IB_BASE_HI_BASE_IDX                                                               0
1704 #define mmSDMA1_RLC3_IB_SIZE                                                                           0x0847
1705 #define mmSDMA1_RLC3_IB_SIZE_BASE_IDX                                                                  0
1706 #define mmSDMA1_RLC3_SKIP_CNTL                                                                         0x0848
1707 #define mmSDMA1_RLC3_SKIP_CNTL_BASE_IDX                                                                0
1708 #define mmSDMA1_RLC3_CONTEXT_STATUS                                                                    0x0849
1709 #define mmSDMA1_RLC3_CONTEXT_STATUS_BASE_IDX                                                           0
1710 #define mmSDMA1_RLC3_DOORBELL                                                                          0x084a
1711 #define mmSDMA1_RLC3_DOORBELL_BASE_IDX                                                                 0
1712 #define mmSDMA1_RLC3_STATUS                                                                            0x0860
1713 #define mmSDMA1_RLC3_STATUS_BASE_IDX                                                                   0
1714 #define mmSDMA1_RLC3_DOORBELL_LOG                                                                      0x0861
1715 #define mmSDMA1_RLC3_DOORBELL_LOG_BASE_IDX                                                             0
1716 #define mmSDMA1_RLC3_WATERMARK                                                                         0x0862
1717 #define mmSDMA1_RLC3_WATERMARK_BASE_IDX                                                                0
1718 #define mmSDMA1_RLC3_DOORBELL_OFFSET                                                                   0x0863
1719 #define mmSDMA1_RLC3_DOORBELL_OFFSET_BASE_IDX                                                          0
1720 #define mmSDMA1_RLC3_CSA_ADDR_LO                                                                       0x0864
1721 #define mmSDMA1_RLC3_CSA_ADDR_LO_BASE_IDX                                                              0
1722 #define mmSDMA1_RLC3_CSA_ADDR_HI                                                                       0x0865
1723 #define mmSDMA1_RLC3_CSA_ADDR_HI_BASE_IDX                                                              0
1724 #define mmSDMA1_RLC3_IB_SUB_REMAIN                                                                     0x0867
1725 #define mmSDMA1_RLC3_IB_SUB_REMAIN_BASE_IDX                                                            0
1726 #define mmSDMA1_RLC3_PREEMPT                                                                           0x0868
1727 #define mmSDMA1_RLC3_PREEMPT_BASE_IDX                                                                  0
1728 #define mmSDMA1_RLC3_DUMMY_REG                                                                         0x0869
1729 #define mmSDMA1_RLC3_DUMMY_REG_BASE_IDX                                                                0
1730 #define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI                                                              0x086a
1731 #define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
1732 #define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO                                                              0x086b
1733 #define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
1734 #define mmSDMA1_RLC3_RB_AQL_CNTL                                                                       0x086c
1735 #define mmSDMA1_RLC3_RB_AQL_CNTL_BASE_IDX                                                              0
1736 #define mmSDMA1_RLC3_MINOR_PTR_UPDATE                                                                  0x086d
1737 #define mmSDMA1_RLC3_MINOR_PTR_UPDATE_BASE_IDX                                                         0
1738 #define mmSDMA1_RLC3_MIDCMD_DATA0                                                                      0x0878
1739 #define mmSDMA1_RLC3_MIDCMD_DATA0_BASE_IDX                                                             0
1740 #define mmSDMA1_RLC3_MIDCMD_DATA1                                                                      0x0879
1741 #define mmSDMA1_RLC3_MIDCMD_DATA1_BASE_IDX                                                             0
1742 #define mmSDMA1_RLC3_MIDCMD_DATA2                                                                      0x087a
1743 #define mmSDMA1_RLC3_MIDCMD_DATA2_BASE_IDX                                                             0
1744 #define mmSDMA1_RLC3_MIDCMD_DATA3                                                                      0x087b
1745 #define mmSDMA1_RLC3_MIDCMD_DATA3_BASE_IDX                                                             0
1746 #define mmSDMA1_RLC3_MIDCMD_DATA4                                                                      0x087c
1747 #define mmSDMA1_RLC3_MIDCMD_DATA4_BASE_IDX                                                             0
1748 #define mmSDMA1_RLC3_MIDCMD_DATA5                                                                      0x087d
1749 #define mmSDMA1_RLC3_MIDCMD_DATA5_BASE_IDX                                                             0
1750 #define mmSDMA1_RLC3_MIDCMD_DATA6                                                                      0x087e
1751 #define mmSDMA1_RLC3_MIDCMD_DATA6_BASE_IDX                                                             0
1752 #define mmSDMA1_RLC3_MIDCMD_DATA7                                                                      0x087f
1753 #define mmSDMA1_RLC3_MIDCMD_DATA7_BASE_IDX                                                             0
1754 #define mmSDMA1_RLC3_MIDCMD_DATA8                                                                      0x0880
1755 #define mmSDMA1_RLC3_MIDCMD_DATA8_BASE_IDX                                                             0
1756 #define mmSDMA1_RLC3_MIDCMD_DATA9                                                                      0x0881
1757 #define mmSDMA1_RLC3_MIDCMD_DATA9_BASE_IDX                                                             0
1758 #define mmSDMA1_RLC3_MIDCMD_DATA10                                                                     0x0882
1759 #define mmSDMA1_RLC3_MIDCMD_DATA10_BASE_IDX                                                            0
1760 #define mmSDMA1_RLC3_MIDCMD_CNTL                                                                       0x0883
1761 #define mmSDMA1_RLC3_MIDCMD_CNTL_BASE_IDX                                                              0
1762 #define mmSDMA1_RLC4_RB_CNTL                                                                           0x0890
1763 #define mmSDMA1_RLC4_RB_CNTL_BASE_IDX                                                                  0
1764 #define mmSDMA1_RLC4_RB_BASE                                                                           0x0891
1765 #define mmSDMA1_RLC4_RB_BASE_BASE_IDX                                                                  0
1766 #define mmSDMA1_RLC4_RB_BASE_HI                                                                        0x0892
1767 #define mmSDMA1_RLC4_RB_BASE_HI_BASE_IDX                                                               0
1768 #define mmSDMA1_RLC4_RB_RPTR                                                                           0x0893
1769 #define mmSDMA1_RLC4_RB_RPTR_BASE_IDX                                                                  0
1770 #define mmSDMA1_RLC4_RB_RPTR_HI                                                                        0x0894
1771 #define mmSDMA1_RLC4_RB_RPTR_HI_BASE_IDX                                                               0
1772 #define mmSDMA1_RLC4_RB_WPTR                                                                           0x0895
1773 #define mmSDMA1_RLC4_RB_WPTR_BASE_IDX                                                                  0
1774 #define mmSDMA1_RLC4_RB_WPTR_HI                                                                        0x0896
1775 #define mmSDMA1_RLC4_RB_WPTR_HI_BASE_IDX                                                               0
1776 #define mmSDMA1_RLC4_RB_WPTR_POLL_CNTL                                                                 0x0897
1777 #define mmSDMA1_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
1778 #define mmSDMA1_RLC4_RB_RPTR_ADDR_HI                                                                   0x0898
1779 #define mmSDMA1_RLC4_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
1780 #define mmSDMA1_RLC4_RB_RPTR_ADDR_LO                                                                   0x0899
1781 #define mmSDMA1_RLC4_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
1782 #define mmSDMA1_RLC4_IB_CNTL                                                                           0x089a
1783 #define mmSDMA1_RLC4_IB_CNTL_BASE_IDX                                                                  0
1784 #define mmSDMA1_RLC4_IB_RPTR                                                                           0x089b
1785 #define mmSDMA1_RLC4_IB_RPTR_BASE_IDX                                                                  0
1786 #define mmSDMA1_RLC4_IB_OFFSET                                                                         0x089c
1787 #define mmSDMA1_RLC4_IB_OFFSET_BASE_IDX                                                                0
1788 #define mmSDMA1_RLC4_IB_BASE_LO                                                                        0x089d
1789 #define mmSDMA1_RLC4_IB_BASE_LO_BASE_IDX                                                               0
1790 #define mmSDMA1_RLC4_IB_BASE_HI                                                                        0x089e
1791 #define mmSDMA1_RLC4_IB_BASE_HI_BASE_IDX                                                               0
1792 #define mmSDMA1_RLC4_IB_SIZE                                                                           0x089f
1793 #define mmSDMA1_RLC4_IB_SIZE_BASE_IDX                                                                  0
1794 #define mmSDMA1_RLC4_SKIP_CNTL                                                                         0x08a0
1795 #define mmSDMA1_RLC4_SKIP_CNTL_BASE_IDX                                                                0
1796 #define mmSDMA1_RLC4_CONTEXT_STATUS                                                                    0x08a1
1797 #define mmSDMA1_RLC4_CONTEXT_STATUS_BASE_IDX                                                           0
1798 #define mmSDMA1_RLC4_DOORBELL                                                                          0x08a2
1799 #define mmSDMA1_RLC4_DOORBELL_BASE_IDX                                                                 0
1800 #define mmSDMA1_RLC4_STATUS                                                                            0x08b8
1801 #define mmSDMA1_RLC4_STATUS_BASE_IDX                                                                   0
1802 #define mmSDMA1_RLC4_DOORBELL_LOG                                                                      0x08b9
1803 #define mmSDMA1_RLC4_DOORBELL_LOG_BASE_IDX                                                             0
1804 #define mmSDMA1_RLC4_WATERMARK                                                                         0x08ba
1805 #define mmSDMA1_RLC4_WATERMARK_BASE_IDX                                                                0
1806 #define mmSDMA1_RLC4_DOORBELL_OFFSET                                                                   0x08bb
1807 #define mmSDMA1_RLC4_DOORBELL_OFFSET_BASE_IDX                                                          0
1808 #define mmSDMA1_RLC4_CSA_ADDR_LO                                                                       0x08bc
1809 #define mmSDMA1_RLC4_CSA_ADDR_LO_BASE_IDX                                                              0
1810 #define mmSDMA1_RLC4_CSA_ADDR_HI                                                                       0x08bd
1811 #define mmSDMA1_RLC4_CSA_ADDR_HI_BASE_IDX                                                              0
1812 #define mmSDMA1_RLC4_IB_SUB_REMAIN                                                                     0x08bf
1813 #define mmSDMA1_RLC4_IB_SUB_REMAIN_BASE_IDX                                                            0
1814 #define mmSDMA1_RLC4_PREEMPT                                                                           0x08c0
1815 #define mmSDMA1_RLC4_PREEMPT_BASE_IDX                                                                  0
1816 #define mmSDMA1_RLC4_DUMMY_REG                                                                         0x08c1
1817 #define mmSDMA1_RLC4_DUMMY_REG_BASE_IDX                                                                0
1818 #define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI                                                              0x08c2
1819 #define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
1820 #define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO                                                              0x08c3
1821 #define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
1822 #define mmSDMA1_RLC4_RB_AQL_CNTL                                                                       0x08c4
1823 #define mmSDMA1_RLC4_RB_AQL_CNTL_BASE_IDX                                                              0
1824 #define mmSDMA1_RLC4_MINOR_PTR_UPDATE                                                                  0x08c5
1825 #define mmSDMA1_RLC4_MINOR_PTR_UPDATE_BASE_IDX                                                         0
1826 #define mmSDMA1_RLC4_MIDCMD_DATA0                                                                      0x08d0
1827 #define mmSDMA1_RLC4_MIDCMD_DATA0_BASE_IDX                                                             0
1828 #define mmSDMA1_RLC4_MIDCMD_DATA1                                                                      0x08d1
1829 #define mmSDMA1_RLC4_MIDCMD_DATA1_BASE_IDX                                                             0
1830 #define mmSDMA1_RLC4_MIDCMD_DATA2                                                                      0x08d2
1831 #define mmSDMA1_RLC4_MIDCMD_DATA2_BASE_IDX                                                             0
1832 #define mmSDMA1_RLC4_MIDCMD_DATA3                                                                      0x08d3
1833 #define mmSDMA1_RLC4_MIDCMD_DATA3_BASE_IDX                                                             0
1834 #define mmSDMA1_RLC4_MIDCMD_DATA4                                                                      0x08d4
1835 #define mmSDMA1_RLC4_MIDCMD_DATA4_BASE_IDX                                                             0
1836 #define mmSDMA1_RLC4_MIDCMD_DATA5                                                                      0x08d5
1837 #define mmSDMA1_RLC4_MIDCMD_DATA5_BASE_IDX                                                             0
1838 #define mmSDMA1_RLC4_MIDCMD_DATA6                                                                      0x08d6
1839 #define mmSDMA1_RLC4_MIDCMD_DATA6_BASE_IDX                                                             0
1840 #define mmSDMA1_RLC4_MIDCMD_DATA7                                                                      0x08d7
1841 #define mmSDMA1_RLC4_MIDCMD_DATA7_BASE_IDX                                                             0
1842 #define mmSDMA1_RLC4_MIDCMD_DATA8                                                                      0x08d8
1843 #define mmSDMA1_RLC4_MIDCMD_DATA8_BASE_IDX                                                             0
1844 #define mmSDMA1_RLC4_MIDCMD_DATA9                                                                      0x08d9
1845 #define mmSDMA1_RLC4_MIDCMD_DATA9_BASE_IDX                                                             0
1846 #define mmSDMA1_RLC4_MIDCMD_DATA10                                                                     0x08da
1847 #define mmSDMA1_RLC4_MIDCMD_DATA10_BASE_IDX                                                            0
1848 #define mmSDMA1_RLC4_MIDCMD_CNTL                                                                       0x08db
1849 #define mmSDMA1_RLC4_MIDCMD_CNTL_BASE_IDX                                                              0
1850 #define mmSDMA1_RLC5_RB_CNTL                                                                           0x08e8
1851 #define mmSDMA1_RLC5_RB_CNTL_BASE_IDX                                                                  0
1852 #define mmSDMA1_RLC5_RB_BASE                                                                           0x08e9
1853 #define mmSDMA1_RLC5_RB_BASE_BASE_IDX                                                                  0
1854 #define mmSDMA1_RLC5_RB_BASE_HI                                                                        0x08ea
1855 #define mmSDMA1_RLC5_RB_BASE_HI_BASE_IDX                                                               0
1856 #define mmSDMA1_RLC5_RB_RPTR                                                                           0x08eb
1857 #define mmSDMA1_RLC5_RB_RPTR_BASE_IDX                                                                  0
1858 #define mmSDMA1_RLC5_RB_RPTR_HI                                                                        0x08ec
1859 #define mmSDMA1_RLC5_RB_RPTR_HI_BASE_IDX                                                               0
1860 #define mmSDMA1_RLC5_RB_WPTR                                                                           0x08ed
1861 #define mmSDMA1_RLC5_RB_WPTR_BASE_IDX                                                                  0
1862 #define mmSDMA1_RLC5_RB_WPTR_HI                                                                        0x08ee
1863 #define mmSDMA1_RLC5_RB_WPTR_HI_BASE_IDX                                                               0
1864 #define mmSDMA1_RLC5_RB_WPTR_POLL_CNTL                                                                 0x08ef
1865 #define mmSDMA1_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
1866 #define mmSDMA1_RLC5_RB_RPTR_ADDR_HI                                                                   0x08f0
1867 #define mmSDMA1_RLC5_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
1868 #define mmSDMA1_RLC5_RB_RPTR_ADDR_LO                                                                   0x08f1
1869 #define mmSDMA1_RLC5_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
1870 #define mmSDMA1_RLC5_IB_CNTL                                                                           0x08f2
1871 #define mmSDMA1_RLC5_IB_CNTL_BASE_IDX                                                                  0
1872 #define mmSDMA1_RLC5_IB_RPTR                                                                           0x08f3
1873 #define mmSDMA1_RLC5_IB_RPTR_BASE_IDX                                                                  0
1874 #define mmSDMA1_RLC5_IB_OFFSET                                                                         0x08f4
1875 #define mmSDMA1_RLC5_IB_OFFSET_BASE_IDX                                                                0
1876 #define mmSDMA1_RLC5_IB_BASE_LO                                                                        0x08f5
1877 #define mmSDMA1_RLC5_IB_BASE_LO_BASE_IDX                                                               0
1878 #define mmSDMA1_RLC5_IB_BASE_HI                                                                        0x08f6
1879 #define mmSDMA1_RLC5_IB_BASE_HI_BASE_IDX                                                               0
1880 #define mmSDMA1_RLC5_IB_SIZE                                                                           0x08f7
1881 #define mmSDMA1_RLC5_IB_SIZE_BASE_IDX                                                                  0
1882 #define mmSDMA1_RLC5_SKIP_CNTL                                                                         0x08f8
1883 #define mmSDMA1_RLC5_SKIP_CNTL_BASE_IDX                                                                0
1884 #define mmSDMA1_RLC5_CONTEXT_STATUS                                                                    0x08f9
1885 #define mmSDMA1_RLC5_CONTEXT_STATUS_BASE_IDX                                                           0
1886 #define mmSDMA1_RLC5_DOORBELL                                                                          0x08fa
1887 #define mmSDMA1_RLC5_DOORBELL_BASE_IDX                                                                 0
1888 #define mmSDMA1_RLC5_STATUS                                                                            0x0910
1889 #define mmSDMA1_RLC5_STATUS_BASE_IDX                                                                   0
1890 #define mmSDMA1_RLC5_DOORBELL_LOG                                                                      0x0911
1891 #define mmSDMA1_RLC5_DOORBELL_LOG_BASE_IDX                                                             0
1892 #define mmSDMA1_RLC5_WATERMARK                                                                         0x0912
1893 #define mmSDMA1_RLC5_WATERMARK_BASE_IDX                                                                0
1894 #define mmSDMA1_RLC5_DOORBELL_OFFSET                                                                   0x0913
1895 #define mmSDMA1_RLC5_DOORBELL_OFFSET_BASE_IDX                                                          0
1896 #define mmSDMA1_RLC5_CSA_ADDR_LO                                                                       0x0914
1897 #define mmSDMA1_RLC5_CSA_ADDR_LO_BASE_IDX                                                              0
1898 #define mmSDMA1_RLC5_CSA_ADDR_HI                                                                       0x0915
1899 #define mmSDMA1_RLC5_CSA_ADDR_HI_BASE_IDX                                                              0
1900 #define mmSDMA1_RLC5_IB_SUB_REMAIN                                                                     0x0917
1901 #define mmSDMA1_RLC5_IB_SUB_REMAIN_BASE_IDX                                                            0
1902 #define mmSDMA1_RLC5_PREEMPT                                                                           0x0918
1903 #define mmSDMA1_RLC5_PREEMPT_BASE_IDX                                                                  0
1904 #define mmSDMA1_RLC5_DUMMY_REG                                                                         0x0919
1905 #define mmSDMA1_RLC5_DUMMY_REG_BASE_IDX                                                                0
1906 #define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI                                                              0x091a
1907 #define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
1908 #define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO                                                              0x091b
1909 #define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
1910 #define mmSDMA1_RLC5_RB_AQL_CNTL                                                                       0x091c
1911 #define mmSDMA1_RLC5_RB_AQL_CNTL_BASE_IDX                                                              0
1912 #define mmSDMA1_RLC5_MINOR_PTR_UPDATE                                                                  0x091d
1913 #define mmSDMA1_RLC5_MINOR_PTR_UPDATE_BASE_IDX                                                         0
1914 #define mmSDMA1_RLC5_MIDCMD_DATA0                                                                      0x0928
1915 #define mmSDMA1_RLC5_MIDCMD_DATA0_BASE_IDX                                                             0
1916 #define mmSDMA1_RLC5_MIDCMD_DATA1                                                                      0x0929
1917 #define mmSDMA1_RLC5_MIDCMD_DATA1_BASE_IDX                                                             0
1918 #define mmSDMA1_RLC5_MIDCMD_DATA2                                                                      0x092a
1919 #define mmSDMA1_RLC5_MIDCMD_DATA2_BASE_IDX                                                             0
1920 #define mmSDMA1_RLC5_MIDCMD_DATA3                                                                      0x092b
1921 #define mmSDMA1_RLC5_MIDCMD_DATA3_BASE_IDX                                                             0
1922 #define mmSDMA1_RLC5_MIDCMD_DATA4                                                                      0x092c
1923 #define mmSDMA1_RLC5_MIDCMD_DATA4_BASE_IDX                                                             0
1924 #define mmSDMA1_RLC5_MIDCMD_DATA5                                                                      0x092d
1925 #define mmSDMA1_RLC5_MIDCMD_DATA5_BASE_IDX                                                             0
1926 #define mmSDMA1_RLC5_MIDCMD_DATA6                                                                      0x092e
1927 #define mmSDMA1_RLC5_MIDCMD_DATA6_BASE_IDX                                                             0
1928 #define mmSDMA1_RLC5_MIDCMD_DATA7                                                                      0x092f
1929 #define mmSDMA1_RLC5_MIDCMD_DATA7_BASE_IDX                                                             0
1930 #define mmSDMA1_RLC5_MIDCMD_DATA8                                                                      0x0930
1931 #define mmSDMA1_RLC5_MIDCMD_DATA8_BASE_IDX                                                             0
1932 #define mmSDMA1_RLC5_MIDCMD_DATA9                                                                      0x0931
1933 #define mmSDMA1_RLC5_MIDCMD_DATA9_BASE_IDX                                                             0
1934 #define mmSDMA1_RLC5_MIDCMD_DATA10                                                                     0x0932
1935 #define mmSDMA1_RLC5_MIDCMD_DATA10_BASE_IDX                                                            0
1936 #define mmSDMA1_RLC5_MIDCMD_CNTL                                                                       0x0933
1937 #define mmSDMA1_RLC5_MIDCMD_CNTL_BASE_IDX                                                              0
1938 #define mmSDMA1_RLC6_RB_CNTL                                                                           0x0940
1939 #define mmSDMA1_RLC6_RB_CNTL_BASE_IDX                                                                  0
1940 #define mmSDMA1_RLC6_RB_BASE                                                                           0x0941
1941 #define mmSDMA1_RLC6_RB_BASE_BASE_IDX                                                                  0
1942 #define mmSDMA1_RLC6_RB_BASE_HI                                                                        0x0942
1943 #define mmSDMA1_RLC6_RB_BASE_HI_BASE_IDX                                                               0
1944 #define mmSDMA1_RLC6_RB_RPTR                                                                           0x0943
1945 #define mmSDMA1_RLC6_RB_RPTR_BASE_IDX                                                                  0
1946 #define mmSDMA1_RLC6_RB_RPTR_HI                                                                        0x0944
1947 #define mmSDMA1_RLC6_RB_RPTR_HI_BASE_IDX                                                               0
1948 #define mmSDMA1_RLC6_RB_WPTR                                                                           0x0945
1949 #define mmSDMA1_RLC6_RB_WPTR_BASE_IDX                                                                  0
1950 #define mmSDMA1_RLC6_RB_WPTR_HI                                                                        0x0946
1951 #define mmSDMA1_RLC6_RB_WPTR_HI_BASE_IDX                                                               0
1952 #define mmSDMA1_RLC6_RB_WPTR_POLL_CNTL                                                                 0x0947
1953 #define mmSDMA1_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
1954 #define mmSDMA1_RLC6_RB_RPTR_ADDR_HI                                                                   0x0948
1955 #define mmSDMA1_RLC6_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
1956 #define mmSDMA1_RLC6_RB_RPTR_ADDR_LO                                                                   0x0949
1957 #define mmSDMA1_RLC6_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
1958 #define mmSDMA1_RLC6_IB_CNTL                                                                           0x094a
1959 #define mmSDMA1_RLC6_IB_CNTL_BASE_IDX                                                                  0
1960 #define mmSDMA1_RLC6_IB_RPTR                                                                           0x094b
1961 #define mmSDMA1_RLC6_IB_RPTR_BASE_IDX                                                                  0
1962 #define mmSDMA1_RLC6_IB_OFFSET                                                                         0x094c
1963 #define mmSDMA1_RLC6_IB_OFFSET_BASE_IDX                                                                0
1964 #define mmSDMA1_RLC6_IB_BASE_LO                                                                        0x094d
1965 #define mmSDMA1_RLC6_IB_BASE_LO_BASE_IDX                                                               0
1966 #define mmSDMA1_RLC6_IB_BASE_HI                                                                        0x094e
1967 #define mmSDMA1_RLC6_IB_BASE_HI_BASE_IDX                                                               0
1968 #define mmSDMA1_RLC6_IB_SIZE                                                                           0x094f
1969 #define mmSDMA1_RLC6_IB_SIZE_BASE_IDX                                                                  0
1970 #define mmSDMA1_RLC6_SKIP_CNTL                                                                         0x0950
1971 #define mmSDMA1_RLC6_SKIP_CNTL_BASE_IDX                                                                0
1972 #define mmSDMA1_RLC6_CONTEXT_STATUS                                                                    0x0951
1973 #define mmSDMA1_RLC6_CONTEXT_STATUS_BASE_IDX                                                           0
1974 #define mmSDMA1_RLC6_DOORBELL                                                                          0x0952
1975 #define mmSDMA1_RLC6_DOORBELL_BASE_IDX                                                                 0
1976 #define mmSDMA1_RLC6_STATUS                                                                            0x0968
1977 #define mmSDMA1_RLC6_STATUS_BASE_IDX                                                                   0
1978 #define mmSDMA1_RLC6_DOORBELL_LOG                                                                      0x0969
1979 #define mmSDMA1_RLC6_DOORBELL_LOG_BASE_IDX                                                             0
1980 #define mmSDMA1_RLC6_WATERMARK                                                                         0x096a
1981 #define mmSDMA1_RLC6_WATERMARK_BASE_IDX                                                                0
1982 #define mmSDMA1_RLC6_DOORBELL_OFFSET                                                                   0x096b
1983 #define mmSDMA1_RLC6_DOORBELL_OFFSET_BASE_IDX                                                          0
1984 #define mmSDMA1_RLC6_CSA_ADDR_LO                                                                       0x096c
1985 #define mmSDMA1_RLC6_CSA_ADDR_LO_BASE_IDX                                                              0
1986 #define mmSDMA1_RLC6_CSA_ADDR_HI                                                                       0x096d
1987 #define mmSDMA1_RLC6_CSA_ADDR_HI_BASE_IDX                                                              0
1988 #define mmSDMA1_RLC6_IB_SUB_REMAIN                                                                     0x096f
1989 #define mmSDMA1_RLC6_IB_SUB_REMAIN_BASE_IDX                                                            0
1990 #define mmSDMA1_RLC6_PREEMPT                                                                           0x0970
1991 #define mmSDMA1_RLC6_PREEMPT_BASE_IDX                                                                  0
1992 #define mmSDMA1_RLC6_DUMMY_REG                                                                         0x0971
1993 #define mmSDMA1_RLC6_DUMMY_REG_BASE_IDX                                                                0
1994 #define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI                                                              0x0972
1995 #define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
1996 #define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO                                                              0x0973
1997 #define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
1998 #define mmSDMA1_RLC6_RB_AQL_CNTL                                                                       0x0974
1999 #define mmSDMA1_RLC6_RB_AQL_CNTL_BASE_IDX                                                              0
2000 #define mmSDMA1_RLC6_MINOR_PTR_UPDATE                                                                  0x0975
2001 #define mmSDMA1_RLC6_MINOR_PTR_UPDATE_BASE_IDX                                                         0
2002 #define mmSDMA1_RLC6_MIDCMD_DATA0                                                                      0x0980
2003 #define mmSDMA1_RLC6_MIDCMD_DATA0_BASE_IDX                                                             0
2004 #define mmSDMA1_RLC6_MIDCMD_DATA1                                                                      0x0981
2005 #define mmSDMA1_RLC6_MIDCMD_DATA1_BASE_IDX                                                             0
2006 #define mmSDMA1_RLC6_MIDCMD_DATA2                                                                      0x0982
2007 #define mmSDMA1_RLC6_MIDCMD_DATA2_BASE_IDX                                                             0
2008 #define mmSDMA1_RLC6_MIDCMD_DATA3                                                                      0x0983
2009 #define mmSDMA1_RLC6_MIDCMD_DATA3_BASE_IDX                                                             0
2010 #define mmSDMA1_RLC6_MIDCMD_DATA4                                                                      0x0984
2011 #define mmSDMA1_RLC6_MIDCMD_DATA4_BASE_IDX                                                             0
2012 #define mmSDMA1_RLC6_MIDCMD_DATA5                                                                      0x0985
2013 #define mmSDMA1_RLC6_MIDCMD_DATA5_BASE_IDX                                                             0
2014 #define mmSDMA1_RLC6_MIDCMD_DATA6                                                                      0x0986
2015 #define mmSDMA1_RLC6_MIDCMD_DATA6_BASE_IDX                                                             0
2016 #define mmSDMA1_RLC6_MIDCMD_DATA7                                                                      0x0987
2017 #define mmSDMA1_RLC6_MIDCMD_DATA7_BASE_IDX                                                             0
2018 #define mmSDMA1_RLC6_MIDCMD_DATA8                                                                      0x0988
2019 #define mmSDMA1_RLC6_MIDCMD_DATA8_BASE_IDX                                                             0
2020 #define mmSDMA1_RLC6_MIDCMD_DATA9                                                                      0x0989
2021 #define mmSDMA1_RLC6_MIDCMD_DATA9_BASE_IDX                                                             0
2022 #define mmSDMA1_RLC6_MIDCMD_DATA10                                                                     0x098a
2023 #define mmSDMA1_RLC6_MIDCMD_DATA10_BASE_IDX                                                            0
2024 #define mmSDMA1_RLC6_MIDCMD_CNTL                                                                       0x098b
2025 #define mmSDMA1_RLC6_MIDCMD_CNTL_BASE_IDX                                                              0
2026 #define mmSDMA1_RLC7_RB_CNTL                                                                           0x0998
2027 #define mmSDMA1_RLC7_RB_CNTL_BASE_IDX                                                                  0
2028 #define mmSDMA1_RLC7_RB_BASE                                                                           0x0999
2029 #define mmSDMA1_RLC7_RB_BASE_BASE_IDX                                                                  0
2030 #define mmSDMA1_RLC7_RB_BASE_HI                                                                        0x099a
2031 #define mmSDMA1_RLC7_RB_BASE_HI_BASE_IDX                                                               0
2032 #define mmSDMA1_RLC7_RB_RPTR                                                                           0x099b
2033 #define mmSDMA1_RLC7_RB_RPTR_BASE_IDX                                                                  0
2034 #define mmSDMA1_RLC7_RB_RPTR_HI                                                                        0x099c
2035 #define mmSDMA1_RLC7_RB_RPTR_HI_BASE_IDX                                                               0
2036 #define mmSDMA1_RLC7_RB_WPTR                                                                           0x099d
2037 #define mmSDMA1_RLC7_RB_WPTR_BASE_IDX                                                                  0
2038 #define mmSDMA1_RLC7_RB_WPTR_HI                                                                        0x099e
2039 #define mmSDMA1_RLC7_RB_WPTR_HI_BASE_IDX                                                               0
2040 #define mmSDMA1_RLC7_RB_WPTR_POLL_CNTL                                                                 0x099f
2041 #define mmSDMA1_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
2042 #define mmSDMA1_RLC7_RB_RPTR_ADDR_HI                                                                   0x09a0
2043 #define mmSDMA1_RLC7_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
2044 #define mmSDMA1_RLC7_RB_RPTR_ADDR_LO                                                                   0x09a1
2045 #define mmSDMA1_RLC7_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
2046 #define mmSDMA1_RLC7_IB_CNTL                                                                           0x09a2
2047 #define mmSDMA1_RLC7_IB_CNTL_BASE_IDX                                                                  0
2048 #define mmSDMA1_RLC7_IB_RPTR                                                                           0x09a3
2049 #define mmSDMA1_RLC7_IB_RPTR_BASE_IDX                                                                  0
2050 #define mmSDMA1_RLC7_IB_OFFSET                                                                         0x09a4
2051 #define mmSDMA1_RLC7_IB_OFFSET_BASE_IDX                                                                0
2052 #define mmSDMA1_RLC7_IB_BASE_LO                                                                        0x09a5
2053 #define mmSDMA1_RLC7_IB_BASE_LO_BASE_IDX                                                               0
2054 #define mmSDMA1_RLC7_IB_BASE_HI                                                                        0x09a6
2055 #define mmSDMA1_RLC7_IB_BASE_HI_BASE_IDX                                                               0
2056 #define mmSDMA1_RLC7_IB_SIZE                                                                           0x09a7
2057 #define mmSDMA1_RLC7_IB_SIZE_BASE_IDX                                                                  0
2058 #define mmSDMA1_RLC7_SKIP_CNTL                                                                         0x09a8
2059 #define mmSDMA1_RLC7_SKIP_CNTL_BASE_IDX                                                                0
2060 #define mmSDMA1_RLC7_CONTEXT_STATUS                                                                    0x09a9
2061 #define mmSDMA1_RLC7_CONTEXT_STATUS_BASE_IDX                                                           0
2062 #define mmSDMA1_RLC7_DOORBELL                                                                          0x09aa
2063 #define mmSDMA1_RLC7_DOORBELL_BASE_IDX                                                                 0
2064 #define mmSDMA1_RLC7_STATUS                                                                            0x09c0
2065 #define mmSDMA1_RLC7_STATUS_BASE_IDX                                                                   0
2066 #define mmSDMA1_RLC7_DOORBELL_LOG                                                                      0x09c1
2067 #define mmSDMA1_RLC7_DOORBELL_LOG_BASE_IDX                                                             0
2068 #define mmSDMA1_RLC7_WATERMARK                                                                         0x09c2
2069 #define mmSDMA1_RLC7_WATERMARK_BASE_IDX                                                                0
2070 #define mmSDMA1_RLC7_DOORBELL_OFFSET                                                                   0x09c3
2071 #define mmSDMA1_RLC7_DOORBELL_OFFSET_BASE_IDX                                                          0
2072 #define mmSDMA1_RLC7_CSA_ADDR_LO                                                                       0x09c4
2073 #define mmSDMA1_RLC7_CSA_ADDR_LO_BASE_IDX                                                              0
2074 #define mmSDMA1_RLC7_CSA_ADDR_HI                                                                       0x09c5
2075 #define mmSDMA1_RLC7_CSA_ADDR_HI_BASE_IDX                                                              0
2076 #define mmSDMA1_RLC7_IB_SUB_REMAIN                                                                     0x09c7
2077 #define mmSDMA1_RLC7_IB_SUB_REMAIN_BASE_IDX                                                            0
2078 #define mmSDMA1_RLC7_PREEMPT                                                                           0x09c8
2079 #define mmSDMA1_RLC7_PREEMPT_BASE_IDX                                                                  0
2080 #define mmSDMA1_RLC7_DUMMY_REG                                                                         0x09c9
2081 #define mmSDMA1_RLC7_DUMMY_REG_BASE_IDX                                                                0
2082 #define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI                                                              0x09ca
2083 #define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
2084 #define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO                                                              0x09cb
2085 #define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
2086 #define mmSDMA1_RLC7_RB_AQL_CNTL                                                                       0x09cc
2087 #define mmSDMA1_RLC7_RB_AQL_CNTL_BASE_IDX                                                              0
2088 #define mmSDMA1_RLC7_MINOR_PTR_UPDATE                                                                  0x09cd
2089 #define mmSDMA1_RLC7_MINOR_PTR_UPDATE_BASE_IDX                                                         0
2090 #define mmSDMA1_RLC7_MIDCMD_DATA0                                                                      0x09d8
2091 #define mmSDMA1_RLC7_MIDCMD_DATA0_BASE_IDX                                                             0
2092 #define mmSDMA1_RLC7_MIDCMD_DATA1                                                                      0x09d9
2093 #define mmSDMA1_RLC7_MIDCMD_DATA1_BASE_IDX                                                             0
2094 #define mmSDMA1_RLC7_MIDCMD_DATA2                                                                      0x09da
2095 #define mmSDMA1_RLC7_MIDCMD_DATA2_BASE_IDX                                                             0
2096 #define mmSDMA1_RLC7_MIDCMD_DATA3                                                                      0x09db
2097 #define mmSDMA1_RLC7_MIDCMD_DATA3_BASE_IDX                                                             0
2098 #define mmSDMA1_RLC7_MIDCMD_DATA4                                                                      0x09dc
2099 #define mmSDMA1_RLC7_MIDCMD_DATA4_BASE_IDX                                                             0
2100 #define mmSDMA1_RLC7_MIDCMD_DATA5                                                                      0x09dd
2101 #define mmSDMA1_RLC7_MIDCMD_DATA5_BASE_IDX                                                             0
2102 #define mmSDMA1_RLC7_MIDCMD_DATA6                                                                      0x09de
2103 #define mmSDMA1_RLC7_MIDCMD_DATA6_BASE_IDX                                                             0
2104 #define mmSDMA1_RLC7_MIDCMD_DATA7                                                                      0x09df
2105 #define mmSDMA1_RLC7_MIDCMD_DATA7_BASE_IDX                                                             0
2106 #define mmSDMA1_RLC7_MIDCMD_DATA8                                                                      0x09e0
2107 #define mmSDMA1_RLC7_MIDCMD_DATA8_BASE_IDX                                                             0
2108 #define mmSDMA1_RLC7_MIDCMD_DATA9                                                                      0x09e1
2109 #define mmSDMA1_RLC7_MIDCMD_DATA9_BASE_IDX                                                             0
2110 #define mmSDMA1_RLC7_MIDCMD_DATA10                                                                     0x09e2
2111 #define mmSDMA1_RLC7_MIDCMD_DATA10_BASE_IDX                                                            0
2112 #define mmSDMA1_RLC7_MIDCMD_CNTL                                                                       0x09e3
2113 #define mmSDMA1_RLC7_MIDCMD_CNTL_BASE_IDX                                                              0
2114 
2115 
2116 // addressBlock: gc_grbmdec
2117 // base address: 0x8000
2118 #define mmGRBM_CNTL                                                                                    0x0da0
2119 #define mmGRBM_CNTL_BASE_IDX                                                                           0
2120 #define mmGRBM_SKEW_CNTL                                                                               0x0da1
2121 #define mmGRBM_SKEW_CNTL_BASE_IDX                                                                      0
2122 #define mmGRBM_STATUS2                                                                                 0x0da2
2123 #define mmGRBM_STATUS2_BASE_IDX                                                                        0
2124 #define mmGRBM_PWR_CNTL                                                                                0x0da3
2125 #define mmGRBM_PWR_CNTL_BASE_IDX                                                                       0
2126 #define mmGRBM_STATUS                                                                                  0x0da4
2127 #define mmGRBM_STATUS_BASE_IDX                                                                         0
2128 #define mmGRBM_STATUS_SE0                                                                              0x0da5
2129 #define mmGRBM_STATUS_SE0_BASE_IDX                                                                     0
2130 #define mmGRBM_STATUS_SE1                                                                              0x0da6
2131 #define mmGRBM_STATUS_SE1_BASE_IDX                                                                     0
2132 #define mmGRBM_STATUS3                                                                                 0x0da7
2133 #define mmGRBM_STATUS3_BASE_IDX                                                                        0
2134 #define mmGRBM_SOFT_RESET                                                                              0x0da8
2135 #define mmGRBM_SOFT_RESET_BASE_IDX                                                                     0
2136 #define mmGRBM_GFX_CLKEN_CNTL                                                                          0x0dac
2137 #define mmGRBM_GFX_CLKEN_CNTL_BASE_IDX                                                                 0
2138 #define mmGRBM_WAIT_IDLE_CLOCKS                                                                        0x0dad
2139 #define mmGRBM_WAIT_IDLE_CLOCKS_BASE_IDX                                                               0
2140 #define mmGRBM_STATUS_SE2                                                                              0x0dae
2141 #define mmGRBM_STATUS_SE2_BASE_IDX                                                                     0
2142 #define mmGRBM_STATUS_SE3                                                                              0x0daf
2143 #define mmGRBM_STATUS_SE3_BASE_IDX                                                                     0
2144 #define mmGRBM_READ_ERROR                                                                              0x0db6
2145 #define mmGRBM_READ_ERROR_BASE_IDX                                                                     0
2146 #define mmGRBM_READ_ERROR2                                                                             0x0db7
2147 #define mmGRBM_READ_ERROR2_BASE_IDX                                                                    0
2148 #define mmGRBM_INT_CNTL                                                                                0x0db8
2149 #define mmGRBM_INT_CNTL_BASE_IDX                                                                       0
2150 #define mmGRBM_TRAP_OP                                                                                 0x0db9
2151 #define mmGRBM_TRAP_OP_BASE_IDX                                                                        0
2152 #define mmGRBM_TRAP_ADDR                                                                               0x0dba
2153 #define mmGRBM_TRAP_ADDR_BASE_IDX                                                                      0
2154 #define mmGRBM_TRAP_ADDR_MSK                                                                           0x0dbb
2155 #define mmGRBM_TRAP_ADDR_MSK_BASE_IDX                                                                  0
2156 #define mmGRBM_TRAP_WD                                                                                 0x0dbc
2157 #define mmGRBM_TRAP_WD_BASE_IDX                                                                        0
2158 #define mmGRBM_TRAP_WD_MSK                                                                             0x0dbd
2159 #define mmGRBM_TRAP_WD_MSK_BASE_IDX                                                                    0
2160 #define mmGRBM_DSM_BYPASS                                                                              0x0dbe
2161 #define mmGRBM_DSM_BYPASS_BASE_IDX                                                                     0
2162 #define mmGRBM_WRITE_ERROR                                                                             0x0dbf
2163 #define mmGRBM_WRITE_ERROR_BASE_IDX                                                                    0
2164 #define mmGRBM_CHIP_REVISION                                                                           0x0dc1
2165 #define mmGRBM_CHIP_REVISION_BASE_IDX                                                                  0
2166 #define mmGRBM_GFX_CNTL                                                                                0x0dc2
2167 #define mmGRBM_GFX_CNTL_BASE_IDX                                                                       0
2168 #define mmGRBM_IH_CREDIT                                                                               0x0dc4
2169 #define mmGRBM_IH_CREDIT_BASE_IDX                                                                      0
2170 #define mmGRBM_PWR_CNTL2                                                                               0x0dc5
2171 #define mmGRBM_PWR_CNTL2_BASE_IDX                                                                      0
2172 #define mmGRBM_UTCL2_INVAL_RANGE_START                                                                 0x0dc6
2173 #define mmGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX                                                        0
2174 #define mmGRBM_UTCL2_INVAL_RANGE_END                                                                   0x0dc7
2175 #define mmGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX                                                          0
2176 #define mmGRBM_FENCE_RANGE0                                                                            0x0dca
2177 #define mmGRBM_FENCE_RANGE0_BASE_IDX                                                                   0
2178 #define mmGRBM_FENCE_RANGE1                                                                            0x0dcb
2179 #define mmGRBM_FENCE_RANGE1_BASE_IDX                                                                   0
2180 #define mmGRBM_NOWHERE                                                                                 0x0ddf
2181 #define mmGRBM_NOWHERE_BASE_IDX                                                                        0
2182 #define mmGRBM_SCRATCH_REG0                                                                            0x0de0
2183 #define mmGRBM_SCRATCH_REG0_BASE_IDX                                                                   0
2184 #define mmGRBM_SCRATCH_REG1                                                                            0x0de1
2185 #define mmGRBM_SCRATCH_REG1_BASE_IDX                                                                   0
2186 #define mmGRBM_SCRATCH_REG2                                                                            0x0de2
2187 #define mmGRBM_SCRATCH_REG2_BASE_IDX                                                                   0
2188 #define mmGRBM_SCRATCH_REG3                                                                            0x0de3
2189 #define mmGRBM_SCRATCH_REG3_BASE_IDX                                                                   0
2190 #define mmGRBM_SCRATCH_REG4                                                                            0x0de4
2191 #define mmGRBM_SCRATCH_REG4_BASE_IDX                                                                   0
2192 #define mmGRBM_SCRATCH_REG5                                                                            0x0de5
2193 #define mmGRBM_SCRATCH_REG5_BASE_IDX                                                                   0
2194 #define mmGRBM_SCRATCH_REG6                                                                            0x0de6
2195 #define mmGRBM_SCRATCH_REG6_BASE_IDX                                                                   0
2196 #define mmGRBM_SCRATCH_REG7                                                                            0x0de7
2197 #define mmGRBM_SCRATCH_REG7_BASE_IDX                                                                   0
2198 #define mmVIOLATION_DATA_ASYNC_VF_PROG                                                                 0x0df1
2199 #define mmVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX                                                        0
2200 
2201 
2202 // addressBlock: gc_cpdec
2203 // base address: 0x8200
2204 #define mmCP_CPC_STATUS                                                                                0x0e24
2205 #define mmCP_CPC_STATUS_BASE_IDX                                                                       0
2206 #define mmCP_CPC_BUSY_STAT                                                                             0x0e25
2207 #define mmCP_CPC_BUSY_STAT_BASE_IDX                                                                    0
2208 #define mmCP_CPC_STALLED_STAT1                                                                         0x0e26
2209 #define mmCP_CPC_STALLED_STAT1_BASE_IDX                                                                0
2210 #define mmCP_CPF_STATUS                                                                                0x0e27
2211 #define mmCP_CPF_STATUS_BASE_IDX                                                                       0
2212 #define mmCP_CPF_BUSY_STAT                                                                             0x0e28
2213 #define mmCP_CPF_BUSY_STAT_BASE_IDX                                                                    0
2214 #define mmCP_CPF_STALLED_STAT1                                                                         0x0e29
2215 #define mmCP_CPF_STALLED_STAT1_BASE_IDX                                                                0
2216 #define mmCP_CPC_BUSY_STAT2                                                                            0x0e2a
2217 #define mmCP_CPC_BUSY_STAT2_BASE_IDX                                                                   0
2218 #define mmCP_CPC_GRBM_FREE_COUNT                                                                       0x0e2b
2219 #define mmCP_CPC_GRBM_FREE_COUNT_BASE_IDX                                                              0
2220 #define mmCP_CPC_PRIV_VIOLATION_ADDR                                                                   0x0e2c
2221 #define mmCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX                                                          0
2222 #define mmCP_MEC_ME1_HEADER_DUMP                                                                       0x0e2e
2223 #define mmCP_MEC_ME1_HEADER_DUMP_BASE_IDX                                                              0
2224 #define mmCP_MEC_ME2_HEADER_DUMP                                                                       0x0e2f
2225 #define mmCP_MEC_ME2_HEADER_DUMP_BASE_IDX                                                              0
2226 #define mmCP_CPC_SCRATCH_INDEX                                                                         0x0e30
2227 #define mmCP_CPC_SCRATCH_INDEX_BASE_IDX                                                                0
2228 #define mmCP_CPC_SCRATCH_DATA                                                                          0x0e31
2229 #define mmCP_CPC_SCRATCH_DATA_BASE_IDX                                                                 0
2230 #define mmCP_CPF_GRBM_FREE_COUNT                                                                       0x0e32
2231 #define mmCP_CPF_GRBM_FREE_COUNT_BASE_IDX                                                              0
2232 #define mmCP_CPF_BUSY_STAT2                                                                            0x0e33
2233 #define mmCP_CPF_BUSY_STAT2_BASE_IDX                                                                   0
2234 #define mmCONFIG_RESERVED_REG0                                                                         0x0e34
2235 #define mmCONFIG_RESERVED_REG0_BASE_IDX                                                                0
2236 #define mmCONFIG_RESERVED_REG1                                                                         0x0e35
2237 #define mmCONFIG_RESERVED_REG1_BASE_IDX                                                                0
2238 #define mmCP_CPC_HALT_HYST_COUNT                                                                       0x0e47
2239 #define mmCP_CPC_HALT_HYST_COUNT_BASE_IDX                                                              0
2240 #define mmCP_CE_COMPARE_COUNT                                                                          0x0e60
2241 #define mmCP_CE_COMPARE_COUNT_BASE_IDX                                                                 0
2242 #define mmCP_CE_DE_COUNT                                                                               0x0e61
2243 #define mmCP_CE_DE_COUNT_BASE_IDX                                                                      0
2244 #define mmCP_DE_CE_COUNT                                                                               0x0e62
2245 #define mmCP_DE_CE_COUNT_BASE_IDX                                                                      0
2246 #define mmCP_DE_LAST_INVAL_COUNT                                                                       0x0e63
2247 #define mmCP_DE_LAST_INVAL_COUNT_BASE_IDX                                                              0
2248 #define mmCP_DE_DE_COUNT                                                                               0x0e64
2249 #define mmCP_DE_DE_COUNT_BASE_IDX                                                                      0
2250 #define mmCP_STALLED_STAT3                                                                             0x0f3c
2251 #define mmCP_STALLED_STAT3_BASE_IDX                                                                    0
2252 #define mmCP_STALLED_STAT1                                                                             0x0f3d
2253 #define mmCP_STALLED_STAT1_BASE_IDX                                                                    0
2254 #define mmCP_STALLED_STAT2                                                                             0x0f3e
2255 #define mmCP_STALLED_STAT2_BASE_IDX                                                                    0
2256 #define mmCP_BUSY_STAT                                                                                 0x0f3f
2257 #define mmCP_BUSY_STAT_BASE_IDX                                                                        0
2258 #define mmCP_STAT                                                                                      0x0f40
2259 #define mmCP_STAT_BASE_IDX                                                                             0
2260 #define mmCP_ME_HEADER_DUMP                                                                            0x0f41
2261 #define mmCP_ME_HEADER_DUMP_BASE_IDX                                                                   0
2262 #define mmCP_PFP_HEADER_DUMP                                                                           0x0f42
2263 #define mmCP_PFP_HEADER_DUMP_BASE_IDX                                                                  0
2264 #define mmCP_GRBM_FREE_COUNT                                                                           0x0f43
2265 #define mmCP_GRBM_FREE_COUNT_BASE_IDX                                                                  0
2266 #define mmCP_CE_HEADER_DUMP                                                                            0x0f44
2267 #define mmCP_CE_HEADER_DUMP_BASE_IDX                                                                   0
2268 #define mmCP_PFP_INSTR_PNTR                                                                            0x0f45
2269 #define mmCP_PFP_INSTR_PNTR_BASE_IDX                                                                   0
2270 #define mmCP_ME_INSTR_PNTR                                                                             0x0f46
2271 #define mmCP_ME_INSTR_PNTR_BASE_IDX                                                                    0
2272 #define mmCP_CE_INSTR_PNTR                                                                             0x0f47
2273 #define mmCP_CE_INSTR_PNTR_BASE_IDX                                                                    0
2274 #define mmCP_MEC1_INSTR_PNTR                                                                           0x0f48
2275 #define mmCP_MEC1_INSTR_PNTR_BASE_IDX                                                                  0
2276 #define mmCP_MEC2_INSTR_PNTR                                                                           0x0f49
2277 #define mmCP_MEC2_INSTR_PNTR_BASE_IDX                                                                  0
2278 #define mmCP_CSF_STAT                                                                                  0x0f54
2279 #define mmCP_CSF_STAT_BASE_IDX                                                                         0
2280 #define mmCP_MEC_CNTL                                                                                  0x0f55
2281 #define mmCP_MEC_CNTL_BASE_IDX                                                                         0
2282 #define mmCP_ME_CNTL                                                                                   0x0f56
2283 #define mmCP_ME_CNTL_BASE_IDX                                                                          0
2284 #define mmCP_CNTX_STAT                                                                                 0x0f58
2285 #define mmCP_CNTX_STAT_BASE_IDX                                                                        0
2286 #define mmCP_ME_PREEMPTION                                                                             0x0f59
2287 #define mmCP_ME_PREEMPTION_BASE_IDX                                                                    0
2288 #define mmCP_ROQ_THRESHOLDS                                                                            0x0f5c
2289 #define mmCP_ROQ_THRESHOLDS_BASE_IDX                                                                   0
2290 #define mmCP_MEQ_STQ_THRESHOLD                                                                         0x0f5d
2291 #define mmCP_MEQ_STQ_THRESHOLD_BASE_IDX                                                                0
2292 #define mmCP_RB2_RPTR                                                                                  0x0f5e
2293 #define mmCP_RB2_RPTR_BASE_IDX                                                                         0
2294 #define mmCP_RB1_RPTR                                                                                  0x0f5f
2295 #define mmCP_RB1_RPTR_BASE_IDX                                                                         0
2296 #define mmCP_RB0_RPTR                                                                                  0x0f60
2297 #define mmCP_RB0_RPTR_BASE_IDX                                                                         0
2298 #define mmCP_RB_RPTR                                                                                   0x0f60
2299 #define mmCP_RB_RPTR_BASE_IDX                                                                          0
2300 #define mmCP_RB_WPTR_DELAY                                                                             0x0f61
2301 #define mmCP_RB_WPTR_DELAY_BASE_IDX                                                                    0
2302 #define mmCP_RB_WPTR_POLL_CNTL                                                                         0x0f62
2303 #define mmCP_RB_WPTR_POLL_CNTL_BASE_IDX                                                                0
2304 #define mmCP_ROQ1_THRESHOLDS                                                                           0x0f75
2305 #define mmCP_ROQ1_THRESHOLDS_BASE_IDX                                                                  0
2306 #define mmCP_ROQ2_THRESHOLDS                                                                           0x0f76
2307 #define mmCP_ROQ2_THRESHOLDS_BASE_IDX                                                                  0
2308 #define mmCP_STQ_THRESHOLDS                                                                            0x0f77
2309 #define mmCP_STQ_THRESHOLDS_BASE_IDX                                                                   0
2310 #define mmCP_QUEUE_THRESHOLDS                                                                          0x0f78
2311 #define mmCP_QUEUE_THRESHOLDS_BASE_IDX                                                                 0
2312 #define mmCP_MEQ_THRESHOLDS                                                                            0x0f79
2313 #define mmCP_MEQ_THRESHOLDS_BASE_IDX                                                                   0
2314 #define mmCP_ROQ_AVAIL                                                                                 0x0f7a
2315 #define mmCP_ROQ_AVAIL_BASE_IDX                                                                        0
2316 #define mmCP_STQ_AVAIL                                                                                 0x0f7b
2317 #define mmCP_STQ_AVAIL_BASE_IDX                                                                        0
2318 #define mmCP_ROQ2_AVAIL                                                                                0x0f7c
2319 #define mmCP_ROQ2_AVAIL_BASE_IDX                                                                       0
2320 #define mmCP_MEQ_AVAIL                                                                                 0x0f7d
2321 #define mmCP_MEQ_AVAIL_BASE_IDX                                                                        0
2322 #define mmCP_CMD_INDEX                                                                                 0x0f7e
2323 #define mmCP_CMD_INDEX_BASE_IDX                                                                        0
2324 #define mmCP_CMD_DATA                                                                                  0x0f7f
2325 #define mmCP_CMD_DATA_BASE_IDX                                                                         0
2326 #define mmCP_ROQ_RB_STAT                                                                               0x0f80
2327 #define mmCP_ROQ_RB_STAT_BASE_IDX                                                                      0
2328 #define mmCP_ROQ_IB1_STAT                                                                              0x0f81
2329 #define mmCP_ROQ_IB1_STAT_BASE_IDX                                                                     0
2330 #define mmCP_ROQ_IB2_STAT                                                                              0x0f82
2331 #define mmCP_ROQ_IB2_STAT_BASE_IDX                                                                     0
2332 #define mmCP_STQ_STAT                                                                                  0x0f83
2333 #define mmCP_STQ_STAT_BASE_IDX                                                                         0
2334 #define mmCP_STQ_WR_STAT                                                                               0x0f84
2335 #define mmCP_STQ_WR_STAT_BASE_IDX                                                                      0
2336 #define mmCP_MEQ_STAT                                                                                  0x0f85
2337 #define mmCP_MEQ_STAT_BASE_IDX                                                                         0
2338 #define mmCP_CEQ1_AVAIL                                                                                0x0f86
2339 #define mmCP_CEQ1_AVAIL_BASE_IDX                                                                       0
2340 #define mmCP_CEQ2_AVAIL                                                                                0x0f87
2341 #define mmCP_CEQ2_AVAIL_BASE_IDX                                                                       0
2342 #define mmCP_CE_ROQ_RB_STAT                                                                            0x0f88
2343 #define mmCP_CE_ROQ_RB_STAT_BASE_IDX                                                                   0
2344 #define mmCP_CE_ROQ_IB1_STAT                                                                           0x0f89
2345 #define mmCP_CE_ROQ_IB1_STAT_BASE_IDX                                                                  0
2346 #define mmCP_CE_ROQ_IB2_STAT                                                                           0x0f8a
2347 #define mmCP_CE_ROQ_IB2_STAT_BASE_IDX                                                                  0
2348 #define mmCP_CE_ROQ_DB_STAT                                                                            0x0f8b
2349 #define mmCP_CE_ROQ_DB_STAT_BASE_IDX                                                                   0
2350 #define mmCP_ROQ3_THRESHOLDS                                                                           0x0f8c
2351 #define mmCP_ROQ3_THRESHOLDS_BASE_IDX                                                                  0
2352 #define mmCP_ROQ_DB_STAT                                                                               0x0f8d
2353 #define mmCP_ROQ_DB_STAT_BASE_IDX                                                                      0
2354 #define mmCP_PRIV_VIOLATION_ADDR                                                                       0x0f9a
2355 #define mmCP_PRIV_VIOLATION_ADDR_BASE_IDX                                                              0
2356 
2357 
2358 // addressBlock: gc_padec
2359 // base address: 0x8800
2360 #define mmVGT_CACHE_INVALIDATION                                                                       0x0fc0
2361 #define mmVGT_CACHE_INVALIDATION_BASE_IDX                                                              0
2362 #define mmVGT_ESGS_RING_SIZE                                                                           0x0fc1
2363 #define mmVGT_ESGS_RING_SIZE_BASE_IDX                                                                  0
2364 #define mmVGT_GSVS_RING_SIZE                                                                           0x0fc2
2365 #define mmVGT_GSVS_RING_SIZE_BASE_IDX                                                                  0
2366 #define mmVGT_TF_RING_SIZE                                                                             0x0fc3
2367 #define mmVGT_TF_RING_SIZE_BASE_IDX                                                                    0
2368 #define mmVGT_HS_OFFCHIP_PARAM                                                                         0x0fc4
2369 #define mmVGT_HS_OFFCHIP_PARAM_BASE_IDX                                                                0
2370 #define mmVGT_TF_MEMORY_BASE                                                                           0x0fc5
2371 #define mmVGT_TF_MEMORY_BASE_BASE_IDX                                                                  0
2372 #define mmVGT_TF_MEMORY_BASE_HI                                                                        0x0fc6
2373 #define mmVGT_TF_MEMORY_BASE_HI_BASE_IDX                                                               0
2374 #define mmVGT_VTX_VECT_EJECT_REG                                                                       0x0fcc
2375 #define mmVGT_VTX_VECT_EJECT_REG_BASE_IDX                                                              0
2376 #define mmVGT_DMA_DATA_FIFO_DEPTH                                                                      0x0fcd
2377 #define mmVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX                                                             0
2378 #define mmVGT_DMA_REQ_FIFO_DEPTH                                                                       0x0fce
2379 #define mmVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX                                                              0
2380 #define mmVGT_DRAW_INIT_FIFO_DEPTH                                                                     0x0fcf
2381 #define mmVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX                                                            0
2382 #define mmVGT_LAST_COPY_STATE                                                                          0x0fd0
2383 #define mmVGT_LAST_COPY_STATE_BASE_IDX                                                                 0
2384 #define mmVGT_FIFO_DEPTHS                                                                              0x0fd4
2385 #define mmVGT_FIFO_DEPTHS_BASE_IDX                                                                     0
2386 #define mmVGT_GS_VERTEX_REUSE                                                                          0x0fd5
2387 #define mmVGT_GS_VERTEX_REUSE_BASE_IDX                                                                 0
2388 #define mmVGT_MC_LAT_CNTL                                                                              0x0fd6
2389 #define mmVGT_MC_LAT_CNTL_BASE_IDX                                                                     0
2390 #define mmIA_UTCL1_STATUS_2                                                                            0x0fd7
2391 #define mmIA_UTCL1_STATUS_2_BASE_IDX                                                                   0
2392 #define mmWD_CNTL_STATUS                                                                               0x0fdf
2393 #define mmWD_CNTL_STATUS_BASE_IDX                                                                      0
2394 #define mmCC_GC_PRIM_CONFIG                                                                            0x0fe0
2395 #define mmCC_GC_PRIM_CONFIG_BASE_IDX                                                                   0
2396 #define mmGC_USER_PRIM_CONFIG                                                                          0x0fe1
2397 #define mmGC_USER_PRIM_CONFIG_BASE_IDX                                                                 0
2398 #define mmWD_QOS                                                                                       0x0fe2
2399 #define mmWD_QOS_BASE_IDX                                                                              0
2400 #define mmWD_UTCL1_CNTL                                                                                0x0fe3
2401 #define mmWD_UTCL1_CNTL_BASE_IDX                                                                       0
2402 #define mmWD_UTCL1_STATUS                                                                              0x0fe4
2403 #define mmWD_UTCL1_STATUS_BASE_IDX                                                                     0
2404 #define mmGE_PC_CNTL                                                                                   0x0fe5
2405 #define mmGE_PC_CNTL_BASE_IDX                                                                          0
2406 #define mmIA_UTCL1_CNTL                                                                                0x0fe6
2407 #define mmIA_UTCL1_CNTL_BASE_IDX                                                                       0
2408 #define mmIA_UTCL1_STATUS                                                                              0x0fe7
2409 #define mmIA_UTCL1_STATUS_BASE_IDX                                                                     0
2410 #define mmCC_GC_SA_UNIT_DISABLE                                                                        0x0fe9
2411 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX                                                               0
2412 #define mmGC_USER_SA_UNIT_DISABLE                                                                      0x0fea
2413 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX                                                             0
2414 #define mmVGT_SYS_CONFIG                                                                               0x1003
2415 #define mmVGT_SYS_CONFIG_BASE_IDX                                                                      0
2416 #define mmGE_PRIV_CONTROL                                                                              0x1004
2417 #define mmGE_PRIV_CONTROL_BASE_IDX                                                                     0
2418 #define mmGE_STATUS                                                                                    0x1005
2419 #define mmGE_STATUS_BASE_IDX                                                                           0
2420 #define mmVGT_VS_MAX_WAVE_ID                                                                           0x1008
2421 #define mmVGT_VS_MAX_WAVE_ID_BASE_IDX                                                                  0
2422 #define mmVGT_GS_MAX_WAVE_ID                                                                           0x1009
2423 #define mmVGT_GS_MAX_WAVE_ID_BASE_IDX                                                                  0
2424 #define mmCC_GC_SHADER_ARRAY_CONFIG_GEN1                                                               0x100a
2425 #define mmCC_GC_SHADER_ARRAY_CONFIG_GEN1_BASE_IDX                                                      0
2426 #define mmCC_GC_SHADER_ARRAY_CONFIG_GEN0                                                               0x100b
2427 #define mmCC_GC_SHADER_ARRAY_CONFIG_GEN0_BASE_IDX                                                      0
2428 #define mmGFX_PIPE_CONTROL                                                                             0x100d
2429 #define mmGFX_PIPE_CONTROL_BASE_IDX                                                                    0
2430 #define mmCC_GC_SHADER_ARRAY_CONFIG                                                                    0x100f
2431 #define mmCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX                                                           0
2432 #define mmGC_USER_SHADER_ARRAY_CONFIG                                                                  0x1010
2433 #define mmGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX                                                         0
2434 #define mmVGT_DMA_PRIMITIVE_TYPE                                                                       0x1011
2435 #define mmVGT_DMA_PRIMITIVE_TYPE_BASE_IDX                                                              0
2436 #define mmVGT_DMA_CONTROL                                                                              0x1012
2437 #define mmVGT_DMA_CONTROL_BASE_IDX                                                                     0
2438 #define mmVGT_DMA_LS_HS_CONFIG                                                                         0x1013
2439 #define mmVGT_DMA_LS_HS_CONFIG_BASE_IDX                                                                0
2440 #define mmVGT_STRMOUT_DELAY                                                                            0x1015
2441 #define mmVGT_STRMOUT_DELAY_BASE_IDX                                                                   0
2442 #define mmWD_BUF_RESOURCE_1                                                                            0x1016
2443 #define mmWD_BUF_RESOURCE_1_BASE_IDX                                                                   0
2444 #define mmWD_BUF_RESOURCE_2                                                                            0x1017
2445 #define mmWD_BUF_RESOURCE_2_BASE_IDX                                                                   0
2446 #define mmPA_CL_CNTL_STATUS                                                                            0x1024
2447 #define mmPA_CL_CNTL_STATUS_BASE_IDX                                                                   0
2448 #define mmPA_CL_ENHANCE                                                                                0x1025
2449 #define mmPA_CL_ENHANCE_BASE_IDX                                                                       0
2450 #define mmPA_SU_CNTL_STATUS                                                                            0x1034
2451 #define mmPA_SU_CNTL_STATUS_BASE_IDX                                                                   0
2452 #define mmPA_SC_FIFO_DEPTH_CNTL                                                                        0x1035
2453 #define mmPA_SC_FIFO_DEPTH_CNTL_BASE_IDX                                                               0
2454 #define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK                                                                0x1060
2455 #define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX                                                       0
2456 #define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK                                                               0x1061
2457 #define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX                                                      0
2458 #define mmPA_SC_TRAP_SCREEN_HV_LOCK                                                                    0x1062
2459 #define mmPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX                                                           0
2460 #define mmPA_SC_FORCE_EOV_MAX_CNTS                                                                     0x1069
2461 #define mmPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX                                                            0
2462 #define mmPA_SC_BINNER_EVENT_CNTL_0                                                                    0x106c
2463 #define mmPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX                                                           0
2464 #define mmPA_SC_BINNER_EVENT_CNTL_1                                                                    0x106d
2465 #define mmPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX                                                           0
2466 #define mmPA_SC_BINNER_EVENT_CNTL_2                                                                    0x106e
2467 #define mmPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX                                                           0
2468 #define mmPA_SC_BINNER_EVENT_CNTL_3                                                                    0x106f
2469 #define mmPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX                                                           0
2470 #define mmPA_SC_BINNER_TIMEOUT_COUNTER                                                                 0x1070
2471 #define mmPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX                                                        0
2472 #define mmPA_SC_BINNER_PERF_CNTL_0                                                                     0x1071
2473 #define mmPA_SC_BINNER_PERF_CNTL_0_BASE_IDX                                                            0
2474 #define mmPA_SC_BINNER_PERF_CNTL_1                                                                     0x1072
2475 #define mmPA_SC_BINNER_PERF_CNTL_1_BASE_IDX                                                            0
2476 #define mmPA_SC_BINNER_PERF_CNTL_2                                                                     0x1073
2477 #define mmPA_SC_BINNER_PERF_CNTL_2_BASE_IDX                                                            0
2478 #define mmPA_SC_BINNER_PERF_CNTL_3                                                                     0x1074
2479 #define mmPA_SC_BINNER_PERF_CNTL_3_BASE_IDX                                                            0
2480 #define mmPA_SC_ENHANCE_2                                                                              0x107c
2481 #define mmPA_SC_ENHANCE_2_BASE_IDX                                                                     0
2482 #define mmPA_SC_ENHANCE_INTERNAL                                                                       0x107d
2483 #define mmPA_SC_ENHANCE_INTERNAL_BASE_IDX                                                              0
2484 #define mmPA_SC_BINNER_CNTL_OVERRIDE                                                                   0x107e
2485 #define mmPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX                                                          0
2486 #define mmPA_SC_PBB_OVERRIDE_FLAG                                                                      0x107f
2487 #define mmPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX                                                             0
2488 #define mmPA_PH_INTERFACE_FIFO_SIZE                                                                    0x1080
2489 #define mmPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX                                                           0
2490 #define mmPA_PH_ENHANCE                                                                                0x1081
2491 #define mmPA_PH_ENHANCE_BASE_IDX                                                                       0
2492 #define mmPA_SC_BC_WAVE_BREAK                                                                          0x1084
2493 #define mmPA_SC_BC_WAVE_BREAK_BASE_IDX                                                                 0
2494 #define mmPA_SC_ENHANCE_3                                                                              0x1085
2495 #define mmPA_SC_ENHANCE_3_BASE_IDX                                                                     0
2496 #define mmPA_SC_FIFO_SIZE                                                                              0x1093
2497 #define mmPA_SC_FIFO_SIZE_BASE_IDX                                                                     0
2498 #define mmPA_SC_IF_FIFO_SIZE                                                                           0x1095
2499 #define mmPA_SC_IF_FIFO_SIZE_BASE_IDX                                                                  0
2500 #define mmPA_SC_PKR_WAVE_TABLE_CNTL                                                                    0x1098
2501 #define mmPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX                                                           0
2502 #define mmPA_SIDEBAND_REQUEST_DELAYS                                                                   0x109b
2503 #define mmPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX                                                          0
2504 #define mmPA_SC_ENHANCE                                                                                0x109c
2505 #define mmPA_SC_ENHANCE_BASE_IDX                                                                       0
2506 #define mmPA_SC_ENHANCE_1                                                                              0x109d
2507 #define mmPA_SC_ENHANCE_1_BASE_IDX                                                                     0
2508 #define mmPA_SC_DSM_CNTL                                                                               0x109e
2509 #define mmPA_SC_DSM_CNTL_BASE_IDX                                                                      0
2510 #define mmPA_SC_TILE_STEERING_CREST_OVERRIDE                                                           0x109f
2511 #define mmPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX                                                  0
2512 
2513 
2514 // addressBlock: gc_sqdec
2515 // base address: 0x8c00
2516 #define mmSQ_CONFIG                                                                                    0x10a0
2517 #define mmSQ_CONFIG_BASE_IDX                                                                           0
2518 #define mmSQC_CONFIG                                                                                   0x10a1
2519 #define mmSQC_CONFIG_BASE_IDX                                                                          0
2520 #define mmLDS_CONFIG                                                                                   0x10a2
2521 #define mmLDS_CONFIG_BASE_IDX                                                                          0
2522 #define mmSQ_RANDOM_WAVE_PRI                                                                           0x10a3
2523 #define mmSQ_RANDOM_WAVE_PRI_BASE_IDX                                                                  0
2524 #define mmSQG_STATUS                                                                                   0x10a4
2525 #define mmSQG_STATUS_BASE_IDX                                                                          0
2526 #define mmSQ_FIFO_SIZES                                                                                0x10a5
2527 #define mmSQ_FIFO_SIZES_BASE_IDX                                                                       0
2528 #define mmSQ_DSM_CNTL                                                                                  0x10a6
2529 #define mmSQ_DSM_CNTL_BASE_IDX                                                                         0
2530 #define mmSQ_DSM_CNTL2                                                                                 0x10a7
2531 #define mmSQ_DSM_CNTL2_BASE_IDX                                                                        0
2532 #define mmSQ_RUNTIME_CONFIG                                                                            0x10a8
2533 #define mmSQ_RUNTIME_CONFIG_BASE_IDX                                                                   0
2534 #define mmSH_MEM_BASES                                                                                 0x10aa
2535 #define mmSH_MEM_BASES_BASE_IDX                                                                        0
2536 #define mmSP_CONFIG                                                                                    0x10ab
2537 #define mmSP_CONFIG_BASE_IDX                                                                           0
2538 #define mmSQ_ARB_CONFIG                                                                                0x10ac
2539 #define mmSQ_ARB_CONFIG_BASE_IDX                                                                       0
2540 #define mmSH_MEM_CONFIG                                                                                0x10ad
2541 #define mmSH_MEM_CONFIG_BASE_IDX                                                                       0
2542 #define mmSQ_SHADER_TBA_LO                                                                             0x10b2
2543 #define mmSQ_SHADER_TBA_LO_BASE_IDX                                                                    0
2544 #define mmSQ_SHADER_TBA_HI                                                                             0x10b3
2545 #define mmSQ_SHADER_TBA_HI_BASE_IDX                                                                    0
2546 #define mmSQ_SHADER_TMA_LO                                                                             0x10b4
2547 #define mmSQ_SHADER_TMA_LO_BASE_IDX                                                                    0
2548 #define mmSQ_SHADER_TMA_HI                                                                             0x10b5
2549 #define mmSQ_SHADER_TMA_HI_BASE_IDX                                                                    0
2550 #define mmSQG_UTCL0_CNTL1                                                                              0x10b7
2551 #define mmSQG_UTCL0_CNTL1_BASE_IDX                                                                     0
2552 #define mmSQG_UTCL0_CNTL2                                                                              0x10b8
2553 #define mmSQG_UTCL0_CNTL2_BASE_IDX                                                                     0
2554 #define mmSQG_UTCL0_STATUS                                                                             0x10b9
2555 #define mmSQG_UTCL0_STATUS_BASE_IDX                                                                    0
2556 #define mmSQG_CONFIG                                                                                   0x10ba
2557 #define mmSQG_CONFIG_BASE_IDX                                                                          0
2558 #define mmCC_GC_SHADER_RATE_CONFIG                                                                     0x10bc
2559 #define mmCC_GC_SHADER_RATE_CONFIG_BASE_IDX                                                            0
2560 #define mmGC_USER_SHADER_RATE_CONFIG                                                                   0x10bd
2561 #define mmGC_USER_SHADER_RATE_CONFIG_BASE_IDX                                                          0
2562 #define mmSQ_INTERRUPT_AUTO_MASK                                                                       0x10be
2563 #define mmSQ_INTERRUPT_AUTO_MASK_BASE_IDX                                                              0
2564 #define mmSQ_INTERRUPT_MSG_CTRL                                                                        0x10bf
2565 #define mmSQ_INTERRUPT_MSG_CTRL_BASE_IDX                                                               0
2566 #define mmSQ_WATCH0_ADDR_H                                                                             0x10d0
2567 #define mmSQ_WATCH0_ADDR_H_BASE_IDX                                                                    0
2568 #define mmSQ_WATCH0_ADDR_L                                                                             0x10d1
2569 #define mmSQ_WATCH0_ADDR_L_BASE_IDX                                                                    0
2570 #define mmSQ_WATCH0_CNTL                                                                               0x10d2
2571 #define mmSQ_WATCH0_CNTL_BASE_IDX                                                                      0
2572 #define mmSQ_WATCH1_ADDR_H                                                                             0x10d3
2573 #define mmSQ_WATCH1_ADDR_H_BASE_IDX                                                                    0
2574 #define mmSQ_WATCH1_ADDR_L                                                                             0x10d4
2575 #define mmSQ_WATCH1_ADDR_L_BASE_IDX                                                                    0
2576 #define mmSQ_WATCH1_CNTL                                                                               0x10d5
2577 #define mmSQ_WATCH1_CNTL_BASE_IDX                                                                      0
2578 #define mmSQ_WATCH2_ADDR_H                                                                             0x10d6
2579 #define mmSQ_WATCH2_ADDR_H_BASE_IDX                                                                    0
2580 #define mmSQ_WATCH2_ADDR_L                                                                             0x10d7
2581 #define mmSQ_WATCH2_ADDR_L_BASE_IDX                                                                    0
2582 #define mmSQ_WATCH2_CNTL                                                                               0x10d8
2583 #define mmSQ_WATCH2_CNTL_BASE_IDX                                                                      0
2584 #define mmSQ_WATCH3_ADDR_H                                                                             0x10d9
2585 #define mmSQ_WATCH3_ADDR_H_BASE_IDX                                                                    0
2586 #define mmSQ_WATCH3_ADDR_L                                                                             0x10da
2587 #define mmSQ_WATCH3_ADDR_L_BASE_IDX                                                                    0
2588 #define mmSQ_WATCH3_CNTL                                                                               0x10db
2589 #define mmSQ_WATCH3_CNTL_BASE_IDX                                                                      0
2590 #define mmSQ_THREAD_TRACE_BUF0_BASE                                                                    0x10e0
2591 #define mmSQ_THREAD_TRACE_BUF0_BASE_BASE_IDX                                                           0
2592 #define mmSQ_THREAD_TRACE_BUF0_SIZE                                                                    0x10e1
2593 #define mmSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX                                                           0
2594 #define mmSQ_THREAD_TRACE_BUF1_BASE                                                                    0x10e2
2595 #define mmSQ_THREAD_TRACE_BUF1_BASE_BASE_IDX                                                           0
2596 #define mmSQ_THREAD_TRACE_BUF1_SIZE                                                                    0x10e3
2597 #define mmSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX                                                           0
2598 #define mmSQ_THREAD_TRACE_WPTR                                                                         0x10e4
2599 #define mmSQ_THREAD_TRACE_WPTR_BASE_IDX                                                                0
2600 #define mmSQ_THREAD_TRACE_MASK                                                                         0x10e5
2601 #define mmSQ_THREAD_TRACE_MASK_BASE_IDX                                                                0
2602 #define mmSQ_THREAD_TRACE_TOKEN_MASK                                                                   0x10e6
2603 #define mmSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX                                                          0
2604 #define mmSQ_THREAD_TRACE_CTRL                                                                         0x10e7
2605 #define mmSQ_THREAD_TRACE_CTRL_BASE_IDX                                                                0
2606 #define mmSQ_THREAD_TRACE_STATUS                                                                       0x10e8
2607 #define mmSQ_THREAD_TRACE_STATUS_BASE_IDX                                                              0
2608 #define mmSQ_THREAD_TRACE_DROPPED_CNTR                                                                 0x10e9
2609 #define mmSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX                                                        0
2610 #define mmSQ_THREAD_TRACE_GFX_DRAW_CNTR                                                                0x10eb
2611 #define mmSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX                                                       0
2612 #define mmSQ_THREAD_TRACE_GFX_MARKER_CNTR                                                              0x10ec
2613 #define mmSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX                                                     0
2614 #define mmSQ_THREAD_TRACE_HP3D_DRAW_CNTR                                                               0x10ed
2615 #define mmSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX                                                      0
2616 #define mmSQ_THREAD_TRACE_HP3D_MARKER_CNTR                                                             0x10ee
2617 #define mmSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX                                                    0
2618 #define mmSQ_THREAD_TRACE_STATUS2                                                                      0x10ef
2619 #define mmSQ_THREAD_TRACE_STATUS2_BASE_IDX                                                             0
2620 #define mmSQ_IND_INDEX                                                                                 0x1118
2621 #define mmSQ_IND_INDEX_BASE_IDX                                                                        0
2622 #define mmSQ_IND_DATA                                                                                  0x1119
2623 #define mmSQ_IND_DATA_BASE_IDX                                                                         0
2624 #define mmSQ_CMD                                                                                       0x111b
2625 #define mmSQ_CMD_BASE_IDX                                                                              0
2626 #define mmSQ_TIME_HI                                                                                   0x111c
2627 #define mmSQ_TIME_HI_BASE_IDX                                                                          0
2628 #define mmSQ_TIME_LO                                                                                   0x111d
2629 #define mmSQ_TIME_LO_BASE_IDX                                                                          0
2630 #define mmSQ_LB_CTR_CTRL                                                                               0x1138
2631 #define mmSQ_LB_CTR_CTRL_BASE_IDX                                                                      0
2632 #define mmSQ_LB_DATA0                                                                                  0x1139
2633 #define mmSQ_LB_DATA0_BASE_IDX                                                                         0
2634 #define mmSQ_LB_DATA1                                                                                  0x113a
2635 #define mmSQ_LB_DATA1_BASE_IDX                                                                         0
2636 #define mmSQ_LB_DATA2                                                                                  0x113b
2637 #define mmSQ_LB_DATA2_BASE_IDX                                                                         0
2638 #define mmSQ_LB_DATA3                                                                                  0x113c
2639 #define mmSQ_LB_DATA3_BASE_IDX                                                                         0
2640 #define mmSQ_LB_CTR_SEL0                                                                               0x113d
2641 #define mmSQ_LB_CTR_SEL0_BASE_IDX                                                                      0
2642 #define mmSQ_LB_CTR_SEL1                                                                               0x113e
2643 #define mmSQ_LB_CTR_SEL1_BASE_IDX                                                                      0
2644 #define mmSQ_EDC_CNT                                                                                   0x1146
2645 #define mmSQ_EDC_CNT_BASE_IDX                                                                          0
2646 #define mmSQ_EDC_FUE_CNTL                                                                              0x1147
2647 #define mmSQ_EDC_FUE_CNTL_BASE_IDX                                                                     0
2648 #define mmSQ_WREXEC_EXEC_HI                                                                            0x1151
2649 #define mmSQ_WREXEC_EXEC_HI_BASE_IDX                                                                   0
2650 #define mmSQ_WREXEC_EXEC_LO                                                                            0x1151
2651 #define mmSQ_WREXEC_EXEC_LO_BASE_IDX                                                                   0
2652 #define mmSQC_ICACHE_UTCL0_CNTL1                                                                       0x1173
2653 #define mmSQC_ICACHE_UTCL0_CNTL1_BASE_IDX                                                              0
2654 #define mmSQC_ICACHE_UTCL0_CNTL2                                                                       0x1174
2655 #define mmSQC_ICACHE_UTCL0_CNTL2_BASE_IDX                                                              0
2656 #define mmSQC_DCACHE_UTCL0_CNTL1                                                                       0x1175
2657 #define mmSQC_DCACHE_UTCL0_CNTL1_BASE_IDX                                                              0
2658 #define mmSQC_DCACHE_UTCL0_CNTL2                                                                       0x1176
2659 #define mmSQC_DCACHE_UTCL0_CNTL2_BASE_IDX                                                              0
2660 #define mmSQC_ICACHE_UTCL0_STATUS                                                                      0x1177
2661 #define mmSQC_ICACHE_UTCL0_STATUS_BASE_IDX                                                             0
2662 #define mmSQC_DCACHE_UTCL0_STATUS                                                                      0x1178
2663 #define mmSQC_DCACHE_UTCL0_STATUS_BASE_IDX                                                             0
2664 
2665 
2666 // addressBlock: gc_shsdec
2667 // base address: 0x9000
2668 #define mmSX_DEBUG_1                                                                                   0x11b8
2669 #define mmSX_DEBUG_1_BASE_IDX                                                                          0
2670 #define mmSPI_PS_MAX_WAVE_ID                                                                           0x11da
2671 #define mmSPI_PS_MAX_WAVE_ID_BASE_IDX                                                                  0
2672 #define mmSPI_START_PHASE                                                                              0x11db
2673 #define mmSPI_START_PHASE_BASE_IDX                                                                     0
2674 #define mmSPI_GFX_CNTL                                                                                 0x11dc
2675 #define mmSPI_GFX_CNTL_BASE_IDX                                                                        0
2676 #define mmSPI_DSM_CNTL                                                                                 0x11e3
2677 #define mmSPI_DSM_CNTL_BASE_IDX                                                                        0
2678 #define mmSPI_DSM_CNTL2                                                                                0x11e4
2679 #define mmSPI_DSM_CNTL2_BASE_IDX                                                                       0
2680 #define mmSPI_EDC_CNT                                                                                  0x11e5
2681 #define mmSPI_EDC_CNT_BASE_IDX                                                                         0
2682 #define mmSPI_USER_ACCUM_VMID_CNTL                                                                     0x11eb
2683 #define mmSPI_USER_ACCUM_VMID_CNTL_BASE_IDX                                                            0
2684 #define mmSPI_CONFIG_CNTL                                                                              0x11ec
2685 #define mmSPI_CONFIG_CNTL_BASE_IDX                                                                     0
2686 #define mmSPI_WAVE_LIMIT_CNTL                                                                          0x11ed
2687 #define mmSPI_WAVE_LIMIT_CNTL_BASE_IDX                                                                 0
2688 #define mmSPI_CONFIG_CNTL_2                                                                            0x11ee
2689 #define mmSPI_CONFIG_CNTL_2_BASE_IDX                                                                   0
2690 #define mmSPI_CONFIG_CNTL_1                                                                            0x11ef
2691 #define mmSPI_CONFIG_CNTL_1_BASE_IDX                                                                   0
2692 #define mmSPI_CONFIG_PS_CU_EN                                                                          0x11f2
2693 #define mmSPI_CONFIG_PS_CU_EN_BASE_IDX                                                                 0
2694 #define mmSPI_WF_LIFETIME_CNTL                                                                         0x124a
2695 #define mmSPI_WF_LIFETIME_CNTL_BASE_IDX                                                                0
2696 #define mmSPI_WF_LIFETIME_LIMIT_0                                                                      0x124b
2697 #define mmSPI_WF_LIFETIME_LIMIT_0_BASE_IDX                                                             0
2698 #define mmSPI_WF_LIFETIME_LIMIT_1                                                                      0x124c
2699 #define mmSPI_WF_LIFETIME_LIMIT_1_BASE_IDX                                                             0
2700 #define mmSPI_WF_LIFETIME_LIMIT_2                                                                      0x124d
2701 #define mmSPI_WF_LIFETIME_LIMIT_2_BASE_IDX                                                             0
2702 #define mmSPI_WF_LIFETIME_LIMIT_3                                                                      0x124e
2703 #define mmSPI_WF_LIFETIME_LIMIT_3_BASE_IDX                                                             0
2704 #define mmSPI_WF_LIFETIME_LIMIT_4                                                                      0x124f
2705 #define mmSPI_WF_LIFETIME_LIMIT_4_BASE_IDX                                                             0
2706 #define mmSPI_WF_LIFETIME_LIMIT_5                                                                      0x1250
2707 #define mmSPI_WF_LIFETIME_LIMIT_5_BASE_IDX                                                             0
2708 #define mmSPI_WF_LIFETIME_STATUS_0                                                                     0x1255
2709 #define mmSPI_WF_LIFETIME_STATUS_0_BASE_IDX                                                            0
2710 #define mmSPI_WF_LIFETIME_STATUS_1                                                                     0x1256
2711 #define mmSPI_WF_LIFETIME_STATUS_1_BASE_IDX                                                            0
2712 #define mmSPI_WF_LIFETIME_STATUS_2                                                                     0x1257
2713 #define mmSPI_WF_LIFETIME_STATUS_2_BASE_IDX                                                            0
2714 #define mmSPI_WF_LIFETIME_STATUS_4                                                                     0x1259
2715 #define mmSPI_WF_LIFETIME_STATUS_4_BASE_IDX                                                            0
2716 #define mmSPI_WF_LIFETIME_STATUS_6                                                                     0x125b
2717 #define mmSPI_WF_LIFETIME_STATUS_6_BASE_IDX                                                            0
2718 #define mmSPI_WF_LIFETIME_STATUS_7                                                                     0x125c
2719 #define mmSPI_WF_LIFETIME_STATUS_7_BASE_IDX                                                            0
2720 #define mmSPI_WF_LIFETIME_STATUS_8                                                                     0x125d
2721 #define mmSPI_WF_LIFETIME_STATUS_8_BASE_IDX                                                            0
2722 #define mmSPI_WF_LIFETIME_STATUS_9                                                                     0x125e
2723 #define mmSPI_WF_LIFETIME_STATUS_9_BASE_IDX                                                            0
2724 #define mmSPI_WF_LIFETIME_STATUS_11                                                                    0x1260
2725 #define mmSPI_WF_LIFETIME_STATUS_11_BASE_IDX                                                           0
2726 #define mmSPI_WF_LIFETIME_STATUS_13                                                                    0x1262
2727 #define mmSPI_WF_LIFETIME_STATUS_13_BASE_IDX                                                           0
2728 #define mmSPI_WF_LIFETIME_STATUS_14                                                                    0x1263
2729 #define mmSPI_WF_LIFETIME_STATUS_14_BASE_IDX                                                           0
2730 #define mmSPI_WF_LIFETIME_STATUS_15                                                                    0x1264
2731 #define mmSPI_WF_LIFETIME_STATUS_15_BASE_IDX                                                           0
2732 #define mmSPI_WF_LIFETIME_STATUS_16                                                                    0x1265
2733 #define mmSPI_WF_LIFETIME_STATUS_16_BASE_IDX                                                           0
2734 #define mmSPI_WF_LIFETIME_STATUS_17                                                                    0x1266
2735 #define mmSPI_WF_LIFETIME_STATUS_17_BASE_IDX                                                           0
2736 #define mmSPI_WF_LIFETIME_STATUS_18                                                                    0x1267
2737 #define mmSPI_WF_LIFETIME_STATUS_18_BASE_IDX                                                           0
2738 #define mmSPI_WF_LIFETIME_STATUS_19                                                                    0x1268
2739 #define mmSPI_WF_LIFETIME_STATUS_19_BASE_IDX                                                           0
2740 #define mmSPI_WF_LIFETIME_STATUS_20                                                                    0x1269
2741 #define mmSPI_WF_LIFETIME_STATUS_20_BASE_IDX                                                           0
2742 #define mmSPI_WF_LIFETIME_STATUS_21                                                                    0x126b
2743 #define mmSPI_WF_LIFETIME_STATUS_21_BASE_IDX                                                           0
2744 #define mmSPI_LB_CTR_CTRL                                                                              0x1274
2745 #define mmSPI_LB_CTR_CTRL_BASE_IDX                                                                     0
2746 #define mmSPI_LB_WGP_MASK                                                                              0x1275
2747 #define mmSPI_LB_WGP_MASK_BASE_IDX                                                                     0
2748 #define mmSPI_LB_DATA_REG                                                                              0x1276
2749 #define mmSPI_LB_DATA_REG_BASE_IDX                                                                     0
2750 #define mmSPI_PG_ENABLE_STATIC_WGP_MASK                                                                0x1277
2751 #define mmSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX                                                       0
2752 #define mmSPI_GDS_CREDITS                                                                              0x1278
2753 #define mmSPI_GDS_CREDITS_BASE_IDX                                                                     0
2754 #define mmSPI_SX_EXPORT_BUFFER_SIZES                                                                   0x1279
2755 #define mmSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX                                                          0
2756 #define mmSPI_SX_SCOREBOARD_BUFFER_SIZES                                                               0x127a
2757 #define mmSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX                                                      0
2758 #define mmSPI_CSQ_WF_ACTIVE_STATUS                                                                     0x127b
2759 #define mmSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX                                                            0
2760 #define mmSPI_CSQ_WF_ACTIVE_COUNT_0                                                                    0x127c
2761 #define mmSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX                                                           0
2762 #define mmSPI_CSQ_WF_ACTIVE_COUNT_1                                                                    0x127d
2763 #define mmSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX                                                           0
2764 #define mmSPI_CSQ_WF_ACTIVE_COUNT_2                                                                    0x127e
2765 #define mmSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX                                                           0
2766 #define mmSPI_CSQ_WF_ACTIVE_COUNT_3                                                                    0x127f
2767 #define mmSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX                                                           0
2768 #define mmSPI_LB_DATA_WAVES                                                                            0x1284
2769 #define mmSPI_LB_DATA_WAVES_BASE_IDX                                                                   0
2770 #define mmSPI_LB_DATA_PERWGP_WAVE_HSGS                                                                 0x1285
2771 #define mmSPI_LB_DATA_PERWGP_WAVE_HSGS_BASE_IDX                                                        0
2772 #define mmSPI_LB_DATA_PERWGP_WAVE_VSPS                                                                 0x1286
2773 #define mmSPI_LB_DATA_PERWGP_WAVE_VSPS_BASE_IDX                                                        0
2774 #define mmSPI_LB_DATA_PERWGP_WAVE_CS                                                                   0x1287
2775 #define mmSPI_LB_DATA_PERWGP_WAVE_CS_BASE_IDX                                                          0
2776 #define mmSPI_P0_TRAP_SCREEN_PSBA_LO                                                                   0x128c
2777 #define mmSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX                                                          0
2778 #define mmSPI_P0_TRAP_SCREEN_PSBA_HI                                                                   0x128d
2779 #define mmSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX                                                          0
2780 #define mmSPI_P0_TRAP_SCREEN_PSMA_LO                                                                   0x128e
2781 #define mmSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX                                                          0
2782 #define mmSPI_P0_TRAP_SCREEN_PSMA_HI                                                                   0x128f
2783 #define mmSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX                                                          0
2784 #define mmSPI_P0_TRAP_SCREEN_GPR_MIN                                                                   0x1290
2785 #define mmSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX                                                          0
2786 #define mmSPI_P1_TRAP_SCREEN_PSBA_LO                                                                   0x1291
2787 #define mmSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX                                                          0
2788 #define mmSPI_P1_TRAP_SCREEN_PSBA_HI                                                                   0x1292
2789 #define mmSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX                                                          0
2790 #define mmSPI_P1_TRAP_SCREEN_PSMA_LO                                                                   0x1293
2791 #define mmSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX                                                          0
2792 #define mmSPI_P1_TRAP_SCREEN_PSMA_HI                                                                   0x1294
2793 #define mmSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX                                                          0
2794 #define mmSPI_P1_TRAP_SCREEN_GPR_MIN                                                                   0x1295
2795 #define mmSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX                                                          0
2796 
2797 
2798 // addressBlock: gc_tpdec
2799 // base address: 0x9400
2800 #define mmTD_STATUS                                                                                    0x12c6
2801 #define mmTD_STATUS_BASE_IDX                                                                           0
2802 #define mmTD_DSM_CNTL                                                                                  0x12cf
2803 #define mmTD_DSM_CNTL_BASE_IDX                                                                         0
2804 #define mmTD_DSM_CNTL2                                                                                 0x12d0
2805 #define mmTD_DSM_CNTL2_BASE_IDX                                                                        0
2806 #define mmTD_SCRATCH                                                                                   0x12d3
2807 #define mmTD_SCRATCH_BASE_IDX                                                                          0
2808 #define mmTA_CNTL                                                                                      0x12e1
2809 #define mmTA_CNTL_BASE_IDX                                                                             0
2810 #define mmTA_RESERVED_010C                                                                             0x12e3
2811 #define mmTA_RESERVED_010C_BASE_IDX                                                                    0
2812 #define mmTA_STATUS                                                                                    0x12e8
2813 #define mmTA_STATUS_BASE_IDX                                                                           0
2814 #define mmTA_SCRATCH                                                                                   0x1304
2815 #define mmTA_SCRATCH_BASE_IDX                                                                          0
2816 
2817 
2818 // addressBlock: gc_gdsdec
2819 // base address: 0x9700
2820 #define mmGDS_CONFIG                                                                                   0x1360
2821 #define mmGDS_CONFIG_BASE_IDX                                                                          0
2822 #define mmGDS_CNTL_STATUS                                                                              0x1361
2823 #define mmGDS_CNTL_STATUS_BASE_IDX                                                                     0
2824 #define mmGDS_ENHANCE                                                                                  0x1362
2825 #define mmGDS_ENHANCE_BASE_IDX                                                                         0
2826 #define mmGDS_PROTECTION_FAULT                                                                         0x1363
2827 #define mmGDS_PROTECTION_FAULT_BASE_IDX                                                                0
2828 #define mmGDS_VM_PROTECTION_FAULT                                                                      0x1364
2829 #define mmGDS_VM_PROTECTION_FAULT_BASE_IDX                                                             0
2830 #define mmGDS_EDC_CNT                                                                                  0x1365
2831 #define mmGDS_EDC_CNT_BASE_IDX                                                                         0
2832 #define mmGDS_EDC_GRBM_CNT                                                                             0x1366
2833 #define mmGDS_EDC_GRBM_CNT_BASE_IDX                                                                    0
2834 #define mmGDS_EDC_OA_DED                                                                               0x1367
2835 #define mmGDS_EDC_OA_DED_BASE_IDX                                                                      0
2836 #define mmGDS_DSM_CNTL                                                                                 0x136a
2837 #define mmGDS_DSM_CNTL_BASE_IDX                                                                        0
2838 #define mmGDS_EDC_OA_PHY_CNT                                                                           0x136b
2839 #define mmGDS_EDC_OA_PHY_CNT_BASE_IDX                                                                  0
2840 #define mmGDS_EDC_OA_PIPE_CNT                                                                          0x136c
2841 #define mmGDS_EDC_OA_PIPE_CNT_BASE_IDX                                                                 0
2842 #define mmGDS_DSM_CNTL2                                                                                0x136d
2843 #define mmGDS_DSM_CNTL2_BASE_IDX                                                                       0
2844 #define mmGDS_WD_GDS_CSB                                                                               0x136e
2845 #define mmGDS_WD_GDS_CSB_BASE_IDX                                                                      0
2846 
2847 
2848 // addressBlock: gc_rbdec
2849 // base address: 0x9800
2850 #define mmDB_DEBUG                                                                                     0x13ac
2851 #define mmDB_DEBUG_BASE_IDX                                                                            0
2852 #define mmDB_DEBUG2                                                                                    0x13ad
2853 #define mmDB_DEBUG2_BASE_IDX                                                                           0
2854 #define mmDB_DEBUG3                                                                                    0x13ae
2855 #define mmDB_DEBUG3_BASE_IDX                                                                           0
2856 #define mmDB_DEBUG4                                                                                    0x13af
2857 #define mmDB_DEBUG4_BASE_IDX                                                                           0
2858 #define mmDB_ETILE_STUTTER_CONTROL                                                                     0x13b0
2859 #define mmDB_ETILE_STUTTER_CONTROL_BASE_IDX                                                            0
2860 #define mmDB_LTILE_STUTTER_CONTROL                                                                     0x13b1
2861 #define mmDB_LTILE_STUTTER_CONTROL_BASE_IDX                                                            0
2862 #define mmDB_EQUAD_STUTTER_CONTROL                                                                     0x13b2
2863 #define mmDB_EQUAD_STUTTER_CONTROL_BASE_IDX                                                            0
2864 #define mmDB_LQUAD_STUTTER_CONTROL                                                                     0x13b3
2865 #define mmDB_LQUAD_STUTTER_CONTROL_BASE_IDX                                                            0
2866 #define mmDB_CREDIT_LIMIT                                                                              0x13b4
2867 #define mmDB_CREDIT_LIMIT_BASE_IDX                                                                     0
2868 #define mmDB_WATERMARKS                                                                                0x13b5
2869 #define mmDB_WATERMARKS_BASE_IDX                                                                       0
2870 #define mmDB_SUBTILE_CONTROL                                                                           0x13b6
2871 #define mmDB_SUBTILE_CONTROL_BASE_IDX                                                                  0
2872 #define mmDB_FREE_CACHELINES                                                                           0x13b7
2873 #define mmDB_FREE_CACHELINES_BASE_IDX                                                                  0
2874 #define mmDB_FIFO_DEPTH1                                                                               0x13b8
2875 #define mmDB_FIFO_DEPTH1_BASE_IDX                                                                      0
2876 #define mmDB_FIFO_DEPTH2                                                                               0x13b9
2877 #define mmDB_FIFO_DEPTH2_BASE_IDX                                                                      0
2878 #define mmDB_LAST_OF_BURST_CONFIG                                                                      0x13ba
2879 #define mmDB_LAST_OF_BURST_CONFIG_BASE_IDX                                                             0
2880 #define mmDB_RING_CONTROL                                                                              0x13bb
2881 #define mmDB_RING_CONTROL_BASE_IDX                                                                     0
2882 #define mmDB_MEM_ARB_WATERMARKS                                                                        0x13bc
2883 #define mmDB_MEM_ARB_WATERMARKS_BASE_IDX                                                               0
2884 #define mmDB_FIFO_DEPTH3                                                                               0x13bd
2885 #define mmDB_FIFO_DEPTH3_BASE_IDX                                                                      0
2886 #define mmDB_RMI_BC_GL2_CACHE_CONTROL                                                                  0x13be
2887 #define mmDB_RMI_BC_GL2_CACHE_CONTROL_BASE_IDX                                                         0
2888 #define mmDB_EXCEPTION_CONTROL                                                                         0x13bf
2889 #define mmDB_EXCEPTION_CONTROL_BASE_IDX                                                                0
2890 #define mmDB_DFSM_CONFIG                                                                               0x13d0
2891 #define mmDB_DFSM_CONFIG_BASE_IDX                                                                      0
2892 #define mmDB_DEBUG5                                                                                    0x13d1
2893 #define mmDB_DEBUG5_BASE_IDX                                                                           0
2894 #define mmDB_DFSM_TILES_IN_FLIGHT                                                                      0x13d2
2895 #define mmDB_DFSM_TILES_IN_FLIGHT_BASE_IDX                                                             0
2896 #define mmDB_DFSM_PRIMS_IN_FLIGHT                                                                      0x13d3
2897 #define mmDB_DFSM_PRIMS_IN_FLIGHT_BASE_IDX                                                             0
2898 #define mmDB_DFSM_WATCHDOG                                                                             0x13d4
2899 #define mmDB_DFSM_WATCHDOG_BASE_IDX                                                                    0
2900 #define mmDB_DFSM_FLUSH_ENABLE                                                                         0x13d5
2901 #define mmDB_DFSM_FLUSH_ENABLE_BASE_IDX                                                                0
2902 #define mmDB_DFSM_FLUSH_AUX_EVENT                                                                      0x13d6
2903 #define mmDB_DFSM_FLUSH_AUX_EVENT_BASE_IDX                                                             0
2904 #define mmDB_FGCG_SRAMS_CLK_CTRL                                                                       0x13d7
2905 #define mmDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX                                                              0
2906 #define mmDB_FGCG_INTERFACES_CLK_CTRL                                                                  0x13d8
2907 #define mmDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX                                                         0
2908 #define mmCC_RB_REDUNDANCY                                                                             0x13dc
2909 #define mmCC_RB_REDUNDANCY_BASE_IDX                                                                    0
2910 #define mmCC_RB_BACKEND_DISABLE                                                                        0x13dd
2911 #define mmCC_RB_BACKEND_DISABLE_BASE_IDX                                                               0
2912 #define mmGB_ADDR_CONFIG                                                                               0x13de
2913 #define mmGB_ADDR_CONFIG_BASE_IDX                                                                      0
2914 #define mmGB_BACKEND_MAP                                                                               0x13df
2915 #define mmGB_BACKEND_MAP_BASE_IDX                                                                      0
2916 #define mmGB_GPU_ID                                                                                    0x13e0
2917 #define mmGB_GPU_ID_BASE_IDX                                                                           0
2918 #define mmCC_RB_DAISY_CHAIN                                                                            0x13e1
2919 #define mmCC_RB_DAISY_CHAIN_BASE_IDX                                                                   0
2920 #define mmGB_ADDR_CONFIG_READ                                                                          0x13e2
2921 #define mmGB_ADDR_CONFIG_READ_BASE_IDX                                                                 0
2922 #define mmCB_HW_CONTROL_4                                                                              0x1422
2923 #define mmCB_HW_CONTROL_4_BASE_IDX                                                                     0
2924 #define mmCB_HW_CONTROL_3                                                                              0x1423
2925 #define mmCB_HW_CONTROL_3_BASE_IDX                                                                     0
2926 #define mmCB_HW_CONTROL                                                                                0x1424
2927 #define mmCB_HW_CONTROL_BASE_IDX                                                                       0
2928 #define mmCB_HW_CONTROL_1                                                                              0x1425
2929 #define mmCB_HW_CONTROL_1_BASE_IDX                                                                     0
2930 #define mmCB_HW_CONTROL_2                                                                              0x1426
2931 #define mmCB_HW_CONTROL_2_BASE_IDX                                                                     0
2932 #define mmCB_DCC_CONFIG                                                                                0x1427
2933 #define mmCB_DCC_CONFIG_BASE_IDX                                                                       0
2934 #define mmCB_HW_MEM_ARBITER_RD                                                                         0x1428
2935 #define mmCB_HW_MEM_ARBITER_RD_BASE_IDX                                                                0
2936 #define mmCB_HW_MEM_ARBITER_WR                                                                         0x1429
2937 #define mmCB_HW_MEM_ARBITER_WR_BASE_IDX                                                                0
2938 #define mmCB_RMI_BC_GL2_CACHE_CONTROL                                                                  0x142a
2939 #define mmCB_RMI_BC_GL2_CACHE_CONTROL_BASE_IDX                                                         0
2940 #define mmCB_STUTTER_CONTROL_CMASK_RDLAT                                                               0x142b
2941 #define mmCB_STUTTER_CONTROL_CMASK_RDLAT_BASE_IDX                                                      0
2942 #define mmCB_STUTTER_CONTROL_FMASK_RDLAT                                                               0x142c
2943 #define mmCB_STUTTER_CONTROL_FMASK_RDLAT_BASE_IDX                                                      0
2944 #define mmCB_STUTTER_CONTROL_COLOR_RDLAT                                                               0x142d
2945 #define mmCB_STUTTER_CONTROL_COLOR_RDLAT_BASE_IDX                                                      0
2946 #define mmCB_CACHE_EVICT_POINTS                                                                        0x142e
2947 #define mmCB_CACHE_EVICT_POINTS_BASE_IDX                                                               0
2948 #define mmGC_USER_RB_REDUNDANCY                                                                        0x147e
2949 #define mmGC_USER_RB_REDUNDANCY_BASE_IDX                                                               0
2950 #define mmGC_USER_RB_BACKEND_DISABLE                                                                   0x147f
2951 #define mmGC_USER_RB_BACKEND_DISABLE_BASE_IDX                                                          0
2952 
2953 
2954 // addressBlock: gc_gceadec2
2955 // base address: 0x9c00
2956 #define mmGCEA_MISC                                                                                    0x14a2
2957 #define mmGCEA_MISC_BASE_IDX                                                                           0
2958 #define mmGCEA_LATENCY_SAMPLING                                                                        0x14a3
2959 #define mmGCEA_LATENCY_SAMPLING_BASE_IDX                                                               0
2960 #define mmGCEA_DSM_CNTL                                                                                0x14b4
2961 #define mmGCEA_DSM_CNTL_BASE_IDX                                                                       0
2962 #define mmGCEA_DSM_CNTLA                                                                               0x14b5
2963 #define mmGCEA_DSM_CNTLA_BASE_IDX                                                                      0
2964 #define mmGCEA_DSM_CNTLB                                                                               0x14b6
2965 #define mmGCEA_DSM_CNTLB_BASE_IDX                                                                      0
2966 #define mmGCEA_DSM_CNTL2                                                                               0x14b7
2967 #define mmGCEA_DSM_CNTL2_BASE_IDX                                                                      0
2968 #define mmGCEA_DSM_CNTL2A                                                                              0x14b8
2969 #define mmGCEA_DSM_CNTL2A_BASE_IDX                                                                     0
2970 #define mmGCEA_DSM_CNTL2B                                                                              0x14b9
2971 #define mmGCEA_DSM_CNTL2B_BASE_IDX                                                                     0
2972 #define mmGCEA_GL2C_XBR_CREDITS                                                                        0x14ba
2973 #define mmGCEA_GL2C_XBR_CREDITS_BASE_IDX                                                               0
2974 #define mmGCEA_GL2C_XBR_MAXBURST                                                                       0x14bb
2975 #define mmGCEA_GL2C_XBR_MAXBURST_BASE_IDX                                                              0
2976 #define mmGCEA_PROBE_CNTL                                                                              0x14bc
2977 #define mmGCEA_PROBE_CNTL_BASE_IDX                                                                     0
2978 #define mmGCEA_PROBE_MAP                                                                               0x14bd
2979 #define mmGCEA_PROBE_MAP_BASE_IDX                                                                      0
2980 #define mmGCEA_ERR_STATUS                                                                              0x14be
2981 #define mmGCEA_ERR_STATUS_BASE_IDX                                                                     0
2982 #define mmGCEA_MISC2                                                                                   0x14bf
2983 #define mmGCEA_MISC2_BASE_IDX                                                                          0
2984 
2985 
2986 // addressBlock: gc_spipdec2
2987 // base address: 0x9c80
2988 #define mmSPI_PQEV_CTRL                                                                                0x14c0
2989 #define mmSPI_PQEV_CTRL_BASE_IDX                                                                       0
2990 #define mmSPI_EXP_THROTTLE_CTRL                                                                        0x14c3
2991 #define mmSPI_EXP_THROTTLE_CTRL_BASE_IDX                                                               0
2992 
2993 
2994 // addressBlock: gc_gceadec3
2995 // base address: 0x9dc0
2996 #define mmGCEA_RRET_MEM_RESERVE                                                                        0x1518
2997 #define mmGCEA_RRET_MEM_RESERVE_BASE_IDX                                                               0
2998 
2999 
3000 // addressBlock: gc_rmi_rmidec
3001 // base address: 0x9e00
3002 #define mmRMI_GENERAL_CNTL                                                                             0x1520
3003 #define mmRMI_GENERAL_CNTL_BASE_IDX                                                                    0
3004 #define mmRMI_GENERAL_CNTL1                                                                            0x1521
3005 #define mmRMI_GENERAL_CNTL1_BASE_IDX                                                                   0
3006 #define mmRMI_GENERAL_STATUS                                                                           0x1522
3007 #define mmRMI_GENERAL_STATUS_BASE_IDX                                                                  0
3008 #define mmRMI_SUBBLOCK_STATUS0                                                                         0x1523
3009 #define mmRMI_SUBBLOCK_STATUS0_BASE_IDX                                                                0
3010 #define mmRMI_SUBBLOCK_STATUS1                                                                         0x1524
3011 #define mmRMI_SUBBLOCK_STATUS1_BASE_IDX                                                                0
3012 #define mmRMI_SUBBLOCK_STATUS2                                                                         0x1525
3013 #define mmRMI_SUBBLOCK_STATUS2_BASE_IDX                                                                0
3014 #define mmRMI_SUBBLOCK_STATUS3                                                                         0x1526
3015 #define mmRMI_SUBBLOCK_STATUS3_BASE_IDX                                                                0
3016 #define mmRMI_XBAR_CONFIG                                                                              0x1527
3017 #define mmRMI_XBAR_CONFIG_BASE_IDX                                                                     0
3018 #define mmRMI_PROBE_POP_LOGIC_CNTL                                                                     0x1528
3019 #define mmRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX                                                            0
3020 #define mmRMI_UTC_XNACK_N_MISC_CNTL                                                                    0x1529
3021 #define mmRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX                                                           0
3022 #define mmRMI_DEMUX_CNTL                                                                               0x152a
3023 #define mmRMI_DEMUX_CNTL_BASE_IDX                                                                      0
3024 #define mmRMI_UTCL1_CNTL1                                                                              0x152b
3025 #define mmRMI_UTCL1_CNTL1_BASE_IDX                                                                     0
3026 #define mmRMI_UTCL1_CNTL2                                                                              0x152c
3027 #define mmRMI_UTCL1_CNTL2_BASE_IDX                                                                     0
3028 #define mmRMI_UTC_UNIT_CONFIG                                                                          0x152d
3029 #define mmRMI_UTC_UNIT_CONFIG_BASE_IDX                                                                 0
3030 #define mmRMI_TCIW_FORMATTER0_CNTL                                                                     0x152e
3031 #define mmRMI_TCIW_FORMATTER0_CNTL_BASE_IDX                                                            0
3032 #define mmRMI_TCIW_FORMATTER1_CNTL                                                                     0x152f
3033 #define mmRMI_TCIW_FORMATTER1_CNTL_BASE_IDX                                                            0
3034 #define mmRMI_SCOREBOARD_CNTL                                                                          0x1530
3035 #define mmRMI_SCOREBOARD_CNTL_BASE_IDX                                                                 0
3036 #define mmRMI_SCOREBOARD_STATUS0                                                                       0x1531
3037 #define mmRMI_SCOREBOARD_STATUS0_BASE_IDX                                                              0
3038 #define mmRMI_SCOREBOARD_STATUS1                                                                       0x1532
3039 #define mmRMI_SCOREBOARD_STATUS1_BASE_IDX                                                              0
3040 #define mmRMI_SCOREBOARD_STATUS2                                                                       0x1533
3041 #define mmRMI_SCOREBOARD_STATUS2_BASE_IDX                                                              0
3042 #define mmRMI_XBAR_ARBITER_CONFIG                                                                      0x1534
3043 #define mmRMI_XBAR_ARBITER_CONFIG_BASE_IDX                                                             0
3044 #define mmRMI_XBAR_ARBITER_CONFIG_1                                                                    0x1535
3045 #define mmRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX                                                           0
3046 #define mmRMI_CLOCK_CNTRL                                                                              0x1536
3047 #define mmRMI_CLOCK_CNTRL_BASE_IDX                                                                     0
3048 #define mmRMI_UTCL1_STATUS                                                                             0x1537
3049 #define mmRMI_UTCL1_STATUS_BASE_IDX                                                                    0
3050 #define mmRMI_RB_GLX_CID_MAP                                                                           0x1538
3051 #define mmRMI_RB_GLX_CID_MAP_BASE_IDX                                                                  0
3052 #define mmRMI_SPARE                                                                                    0x153f
3053 #define mmRMI_SPARE_BASE_IDX                                                                           0
3054 #define mmRMI_SPARE_1                                                                                  0x1540
3055 #define mmRMI_SPARE_1_BASE_IDX                                                                         0
3056 #define mmRMI_SPARE_2                                                                                  0x1541
3057 #define mmRMI_SPARE_2_BASE_IDX                                                                         0
3058 #define mmCC_RMI_REDUNDANCY                                                                            0x1542
3059 #define mmCC_RMI_REDUNDANCY_BASE_IDX                                                                   0
3060 #define mmGC_USER_RMI_REDUNDANCY                                                                       0x1543
3061 #define mmGC_USER_RMI_REDUNDANCY_BASE_IDX                                                              0
3062 
3063 
3064 // addressBlock: gc_dbgu_gfx_dbgudec
3065 // base address: 0x9f00
3066 
3067 
3068 // addressBlock: gc_pmmdec
3069 // base address: 0x9f80
3070 #define mmGCR_GENERAL_CNTL                                                                             0x1580
3071 #define mmGCR_GENERAL_CNTL_BASE_IDX                                                                    0
3072 #define mmGCR_CMD_STATUS                                                                               0x1582
3073 #define mmGCR_CMD_STATUS_BASE_IDX                                                                      0
3074 #define mmGCR_SPARE                                                                                    0x1583
3075 #define mmGCR_SPARE_BASE_IDX                                                                           0
3076 #define mmPMM_GENERAL_CNTL                                                                             0x1585
3077 #define mmPMM_GENERAL_CNTL_BASE_IDX                                                                    0
3078 #define mmGCR_PIO_CNTL                                                                                 0x1586
3079 #define mmGCR_PIO_CNTL_BASE_IDX                                                                        0
3080 #define mmGCR_PIO_DATA                                                                                 0x1587
3081 #define mmGCR_PIO_DATA_BASE_IDX                                                                        0
3082 
3083 
3084 // addressBlock: gc_utcl1dec
3085 // base address: 0x9fa0
3086 #define mmUTCL1_CTRL                                                                                   0x1588
3087 #define mmUTCL1_CTRL_BASE_IDX                                                                          0
3088 #define mmUTCL1_ALOG                                                                                   0x1589
3089 #define mmUTCL1_ALOG_BASE_IDX                                                                          0
3090 #define mmUTCL1_UTCL0_INVREQ_DISABLE                                                                   0x158a
3091 #define mmUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX                                                          0
3092 #define mmGCRD_SA_TARGETS_DISABLE                                                                      0x158b
3093 #define mmGCRD_SA_TARGETS_DISABLE_BASE_IDX                                                             0
3094 #define mmUTCL1_STATUS                                                                                 0x158c
3095 #define mmUTCL1_STATUS_BASE_IDX                                                                        0
3096 
3097 
3098 // addressBlock: gc_gcvml2pfdec
3099 // base address: 0xa070
3100 #define mmGCVM_L2_CNTL                                                                                 0x15bc
3101 #define mmGCVM_L2_CNTL_BASE_IDX                                                                        0
3102 #define mmGCVM_L2_CNTL2                                                                                0x15bd
3103 #define mmGCVM_L2_CNTL2_BASE_IDX                                                                       0
3104 #define mmGCVM_L2_CNTL3                                                                                0x15be
3105 #define mmGCVM_L2_CNTL3_BASE_IDX                                                                       0
3106 #define mmGCVM_L2_STATUS                                                                               0x15bf
3107 #define mmGCVM_L2_STATUS_BASE_IDX                                                                      0
3108 #define mmGCVM_DUMMY_PAGE_FAULT_CNTL                                                                   0x15c0
3109 #define mmGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX                                                          0
3110 #define mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32                                                              0x15c1
3111 #define mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX                                                     0
3112 #define mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32                                                              0x15c2
3113 #define mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX                                                     0
3114 #define mmGCVM_INVALIDATE_CNTL                                                                         0x15c3
3115 #define mmGCVM_INVALIDATE_CNTL_BASE_IDX                                                                0
3116 #define mmGCVM_L2_PROTECTION_FAULT_CNTL                                                                0x15c4
3117 #define mmGCVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX                                                       0
3118 #define mmGCVM_L2_PROTECTION_FAULT_CNTL2                                                               0x15c5
3119 #define mmGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX                                                      0
3120 #define mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3                                                            0x15c6
3121 #define mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX                                                   0
3122 #define mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4                                                            0x15c7
3123 #define mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX                                                   0
3124 #define mmGCVM_L2_PROTECTION_FAULT_STATUS                                                              0x15c8
3125 #define mmGCVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX                                                     0
3126 #define mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32                                                           0x15c9
3127 #define mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX                                                  0
3128 #define mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32                                                           0x15ca
3129 #define mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX                                                  0
3130 #define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32                                                   0x15cb
3131 #define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX                                          0
3132 #define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32                                                   0x15cc
3133 #define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX                                          0
3134 #define mmGCVM_DEBUG                                                                                   0x15cd
3135 #define mmGCVM_DEBUG_BASE_IDX                                                                          0
3136 #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32                                             0x15ce
3137 #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX                                    0
3138 #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32                                             0x15cf
3139 #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX                                    0
3140 #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32                                            0x15d0
3141 #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX                                   0
3142 #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32                                            0x15d1
3143 #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX                                   0
3144 #define mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32                                                0x15d2
3145 #define mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX                                       0
3146 #define mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32                                                0x15d3
3147 #define mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX                                       0
3148 #define mmGCVM_L2_CNTL4                                                                                0x15d4
3149 #define mmGCVM_L2_CNTL4_BASE_IDX                                                                       0
3150 #define mmGCVM_L2_MM_GROUP_RT_CLASSES                                                                  0x15d5
3151 #define mmGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX                                                         0
3152 #define mmGCVM_L2_BANK_SELECT_RESERVED_CID                                                             0x15d6
3153 #define mmGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX                                                    0
3154 #define mmGCVM_L2_BANK_SELECT_RESERVED_CID2                                                            0x15d7
3155 #define mmGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX                                                   0
3156 #define mmGCVM_L2_CACHE_PARITY_CNTL                                                                    0x15d8
3157 #define mmGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX                                                           0
3158 #define mmGCVM_L2_IH_LOG_CNTL                                                                          0x15d9
3159 #define mmGCVM_L2_IH_LOG_CNTL_BASE_IDX                                                                 0
3160 #define mmGCVM_L2_CNTL5                                                                                0x15dc
3161 #define mmGCVM_L2_CNTL5_BASE_IDX                                                                       0
3162 #define mmGCVM_L2_GCR_CNTL                                                                             0x15dd
3163 #define mmGCVM_L2_GCR_CNTL_BASE_IDX                                                                    0
3164 #define mmGCVML2_WALKER_MACRO_THROTTLE_TIME                                                            0x15de
3165 #define mmGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX                                                   0
3166 #define mmGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT                                                     0x15df
3167 #define mmGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX                                            0
3168 #define mmGCVML2_WALKER_MICRO_THROTTLE_TIME                                                            0x15e0
3169 #define mmGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX                                                   0
3170 #define mmGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT                                                     0x15e1
3171 #define mmGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX                                            0
3172 #define mmGCVM_L2_PTE_CACHE_DUMP_CNTL                                                                  0x15e3
3173 #define mmGCVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX                                                         0
3174 #define mmGCVM_L2_PTE_CACHE_DUMP_READ                                                                  0x15e4
3175 #define mmGCVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX                                                         0
3176 
3177 
3178 // addressBlock: gc_gcvml2vcdec
3179 // base address: 0xa170
3180 #define mmGCVM_CONTEXT0_CNTL                                                                           0x15fc
3181 #define mmGCVM_CONTEXT0_CNTL_BASE_IDX                                                                  0
3182 #define mmGCVM_CONTEXT1_CNTL                                                                           0x15fd
3183 #define mmGCVM_CONTEXT1_CNTL_BASE_IDX                                                                  0
3184 #define mmGCVM_CONTEXT2_CNTL                                                                           0x15fe
3185 #define mmGCVM_CONTEXT2_CNTL_BASE_IDX                                                                  0
3186 #define mmGCVM_CONTEXT3_CNTL                                                                           0x15ff
3187 #define mmGCVM_CONTEXT3_CNTL_BASE_IDX                                                                  0
3188 #define mmGCVM_CONTEXT4_CNTL                                                                           0x1600
3189 #define mmGCVM_CONTEXT4_CNTL_BASE_IDX                                                                  0
3190 #define mmGCVM_CONTEXT5_CNTL                                                                           0x1601
3191 #define mmGCVM_CONTEXT5_CNTL_BASE_IDX                                                                  0
3192 #define mmGCVM_CONTEXT6_CNTL                                                                           0x1602
3193 #define mmGCVM_CONTEXT6_CNTL_BASE_IDX                                                                  0
3194 #define mmGCVM_CONTEXT7_CNTL                                                                           0x1603
3195 #define mmGCVM_CONTEXT7_CNTL_BASE_IDX                                                                  0
3196 #define mmGCVM_CONTEXT8_CNTL                                                                           0x1604
3197 #define mmGCVM_CONTEXT8_CNTL_BASE_IDX                                                                  0
3198 #define mmGCVM_CONTEXT9_CNTL                                                                           0x1605
3199 #define mmGCVM_CONTEXT9_CNTL_BASE_IDX                                                                  0
3200 #define mmGCVM_CONTEXT10_CNTL                                                                          0x1606
3201 #define mmGCVM_CONTEXT10_CNTL_BASE_IDX                                                                 0
3202 #define mmGCVM_CONTEXT11_CNTL                                                                          0x1607
3203 #define mmGCVM_CONTEXT11_CNTL_BASE_IDX                                                                 0
3204 #define mmGCVM_CONTEXT12_CNTL                                                                          0x1608
3205 #define mmGCVM_CONTEXT12_CNTL_BASE_IDX                                                                 0
3206 #define mmGCVM_CONTEXT13_CNTL                                                                          0x1609
3207 #define mmGCVM_CONTEXT13_CNTL_BASE_IDX                                                                 0
3208 #define mmGCVM_CONTEXT14_CNTL                                                                          0x160a
3209 #define mmGCVM_CONTEXT14_CNTL_BASE_IDX                                                                 0
3210 #define mmGCVM_CONTEXT15_CNTL                                                                          0x160b
3211 #define mmGCVM_CONTEXT15_CNTL_BASE_IDX                                                                 0
3212 #define mmGCVM_CONTEXTS_DISABLE                                                                        0x160c
3213 #define mmGCVM_CONTEXTS_DISABLE_BASE_IDX                                                               0
3214 #define mmGCVM_INVALIDATE_ENG0_SEM                                                                     0x160d
3215 #define mmGCVM_INVALIDATE_ENG0_SEM_BASE_IDX                                                            0
3216 #define mmGCVM_INVALIDATE_ENG1_SEM                                                                     0x160e
3217 #define mmGCVM_INVALIDATE_ENG1_SEM_BASE_IDX                                                            0
3218 #define mmGCVM_INVALIDATE_ENG2_SEM                                                                     0x160f
3219 #define mmGCVM_INVALIDATE_ENG2_SEM_BASE_IDX                                                            0
3220 #define mmGCVM_INVALIDATE_ENG3_SEM                                                                     0x1610
3221 #define mmGCVM_INVALIDATE_ENG3_SEM_BASE_IDX                                                            0
3222 #define mmGCVM_INVALIDATE_ENG4_SEM                                                                     0x1611
3223 #define mmGCVM_INVALIDATE_ENG4_SEM_BASE_IDX                                                            0
3224 #define mmGCVM_INVALIDATE_ENG5_SEM                                                                     0x1612
3225 #define mmGCVM_INVALIDATE_ENG5_SEM_BASE_IDX                                                            0
3226 #define mmGCVM_INVALIDATE_ENG6_SEM                                                                     0x1613
3227 #define mmGCVM_INVALIDATE_ENG6_SEM_BASE_IDX                                                            0
3228 #define mmGCVM_INVALIDATE_ENG7_SEM                                                                     0x1614
3229 #define mmGCVM_INVALIDATE_ENG7_SEM_BASE_IDX                                                            0
3230 #define mmGCVM_INVALIDATE_ENG8_SEM                                                                     0x1615
3231 #define mmGCVM_INVALIDATE_ENG8_SEM_BASE_IDX                                                            0
3232 #define mmGCVM_INVALIDATE_ENG9_SEM                                                                     0x1616
3233 #define mmGCVM_INVALIDATE_ENG9_SEM_BASE_IDX                                                            0
3234 #define mmGCVM_INVALIDATE_ENG10_SEM                                                                    0x1617
3235 #define mmGCVM_INVALIDATE_ENG10_SEM_BASE_IDX                                                           0
3236 #define mmGCVM_INVALIDATE_ENG11_SEM                                                                    0x1618
3237 #define mmGCVM_INVALIDATE_ENG11_SEM_BASE_IDX                                                           0
3238 #define mmGCVM_INVALIDATE_ENG12_SEM                                                                    0x1619
3239 #define mmGCVM_INVALIDATE_ENG12_SEM_BASE_IDX                                                           0
3240 #define mmGCVM_INVALIDATE_ENG13_SEM                                                                    0x161a
3241 #define mmGCVM_INVALIDATE_ENG13_SEM_BASE_IDX                                                           0
3242 #define mmGCVM_INVALIDATE_ENG14_SEM                                                                    0x161b
3243 #define mmGCVM_INVALIDATE_ENG14_SEM_BASE_IDX                                                           0
3244 #define mmGCVM_INVALIDATE_ENG15_SEM                                                                    0x161c
3245 #define mmGCVM_INVALIDATE_ENG15_SEM_BASE_IDX                                                           0
3246 #define mmGCVM_INVALIDATE_ENG16_SEM                                                                    0x161d
3247 #define mmGCVM_INVALIDATE_ENG16_SEM_BASE_IDX                                                           0
3248 #define mmGCVM_INVALIDATE_ENG17_SEM                                                                    0x161e
3249 #define mmGCVM_INVALIDATE_ENG17_SEM_BASE_IDX                                                           0
3250 #define mmGCVM_INVALIDATE_ENG0_REQ                                                                     0x161f
3251 #define mmGCVM_INVALIDATE_ENG0_REQ_BASE_IDX                                                            0
3252 #define mmGCVM_INVALIDATE_ENG1_REQ                                                                     0x1620
3253 #define mmGCVM_INVALIDATE_ENG1_REQ_BASE_IDX                                                            0
3254 #define mmGCVM_INVALIDATE_ENG2_REQ                                                                     0x1621
3255 #define mmGCVM_INVALIDATE_ENG2_REQ_BASE_IDX                                                            0
3256 #define mmGCVM_INVALIDATE_ENG3_REQ                                                                     0x1622
3257 #define mmGCVM_INVALIDATE_ENG3_REQ_BASE_IDX                                                            0
3258 #define mmGCVM_INVALIDATE_ENG4_REQ                                                                     0x1623
3259 #define mmGCVM_INVALIDATE_ENG4_REQ_BASE_IDX                                                            0
3260 #define mmGCVM_INVALIDATE_ENG5_REQ                                                                     0x1624
3261 #define mmGCVM_INVALIDATE_ENG5_REQ_BASE_IDX                                                            0
3262 #define mmGCVM_INVALIDATE_ENG6_REQ                                                                     0x1625
3263 #define mmGCVM_INVALIDATE_ENG6_REQ_BASE_IDX                                                            0
3264 #define mmGCVM_INVALIDATE_ENG7_REQ                                                                     0x1626
3265 #define mmGCVM_INVALIDATE_ENG7_REQ_BASE_IDX                                                            0
3266 #define mmGCVM_INVALIDATE_ENG8_REQ                                                                     0x1627
3267 #define mmGCVM_INVALIDATE_ENG8_REQ_BASE_IDX                                                            0
3268 #define mmGCVM_INVALIDATE_ENG9_REQ                                                                     0x1628
3269 #define mmGCVM_INVALIDATE_ENG9_REQ_BASE_IDX                                                            0
3270 #define mmGCVM_INVALIDATE_ENG10_REQ                                                                    0x1629
3271 #define mmGCVM_INVALIDATE_ENG10_REQ_BASE_IDX                                                           0
3272 #define mmGCVM_INVALIDATE_ENG11_REQ                                                                    0x162a
3273 #define mmGCVM_INVALIDATE_ENG11_REQ_BASE_IDX                                                           0
3274 #define mmGCVM_INVALIDATE_ENG12_REQ                                                                    0x162b
3275 #define mmGCVM_INVALIDATE_ENG12_REQ_BASE_IDX                                                           0
3276 #define mmGCVM_INVALIDATE_ENG13_REQ                                                                    0x162c
3277 #define mmGCVM_INVALIDATE_ENG13_REQ_BASE_IDX                                                           0
3278 #define mmGCVM_INVALIDATE_ENG14_REQ                                                                    0x162d
3279 #define mmGCVM_INVALIDATE_ENG14_REQ_BASE_IDX                                                           0
3280 #define mmGCVM_INVALIDATE_ENG15_REQ                                                                    0x162e
3281 #define mmGCVM_INVALIDATE_ENG15_REQ_BASE_IDX                                                           0
3282 #define mmGCVM_INVALIDATE_ENG16_REQ                                                                    0x162f
3283 #define mmGCVM_INVALIDATE_ENG16_REQ_BASE_IDX                                                           0
3284 #define mmGCVM_INVALIDATE_ENG17_REQ                                                                    0x1630
3285 #define mmGCVM_INVALIDATE_ENG17_REQ_BASE_IDX                                                           0
3286 #define mmGCVM_INVALIDATE_ENG0_ACK                                                                     0x1631
3287 #define mmGCVM_INVALIDATE_ENG0_ACK_BASE_IDX                                                            0
3288 #define mmGCVM_INVALIDATE_ENG1_ACK                                                                     0x1632
3289 #define mmGCVM_INVALIDATE_ENG1_ACK_BASE_IDX                                                            0
3290 #define mmGCVM_INVALIDATE_ENG2_ACK                                                                     0x1633
3291 #define mmGCVM_INVALIDATE_ENG2_ACK_BASE_IDX                                                            0
3292 #define mmGCVM_INVALIDATE_ENG3_ACK                                                                     0x1634
3293 #define mmGCVM_INVALIDATE_ENG3_ACK_BASE_IDX                                                            0
3294 #define mmGCVM_INVALIDATE_ENG4_ACK                                                                     0x1635
3295 #define mmGCVM_INVALIDATE_ENG4_ACK_BASE_IDX                                                            0
3296 #define mmGCVM_INVALIDATE_ENG5_ACK                                                                     0x1636
3297 #define mmGCVM_INVALIDATE_ENG5_ACK_BASE_IDX                                                            0
3298 #define mmGCVM_INVALIDATE_ENG6_ACK                                                                     0x1637
3299 #define mmGCVM_INVALIDATE_ENG6_ACK_BASE_IDX                                                            0
3300 #define mmGCVM_INVALIDATE_ENG7_ACK                                                                     0x1638
3301 #define mmGCVM_INVALIDATE_ENG7_ACK_BASE_IDX                                                            0
3302 #define mmGCVM_INVALIDATE_ENG8_ACK                                                                     0x1639
3303 #define mmGCVM_INVALIDATE_ENG8_ACK_BASE_IDX                                                            0
3304 #define mmGCVM_INVALIDATE_ENG9_ACK                                                                     0x163a
3305 #define mmGCVM_INVALIDATE_ENG9_ACK_BASE_IDX                                                            0
3306 #define mmGCVM_INVALIDATE_ENG10_ACK                                                                    0x163b
3307 #define mmGCVM_INVALIDATE_ENG10_ACK_BASE_IDX                                                           0
3308 #define mmGCVM_INVALIDATE_ENG11_ACK                                                                    0x163c
3309 #define mmGCVM_INVALIDATE_ENG11_ACK_BASE_IDX                                                           0
3310 #define mmGCVM_INVALIDATE_ENG12_ACK                                                                    0x163d
3311 #define mmGCVM_INVALIDATE_ENG12_ACK_BASE_IDX                                                           0
3312 #define mmGCVM_INVALIDATE_ENG13_ACK                                                                    0x163e
3313 #define mmGCVM_INVALIDATE_ENG13_ACK_BASE_IDX                                                           0
3314 #define mmGCVM_INVALIDATE_ENG14_ACK                                                                    0x163f
3315 #define mmGCVM_INVALIDATE_ENG14_ACK_BASE_IDX                                                           0
3316 #define mmGCVM_INVALIDATE_ENG15_ACK                                                                    0x1640
3317 #define mmGCVM_INVALIDATE_ENG15_ACK_BASE_IDX                                                           0
3318 #define mmGCVM_INVALIDATE_ENG16_ACK                                                                    0x1641
3319 #define mmGCVM_INVALIDATE_ENG16_ACK_BASE_IDX                                                           0
3320 #define mmGCVM_INVALIDATE_ENG17_ACK                                                                    0x1642
3321 #define mmGCVM_INVALIDATE_ENG17_ACK_BASE_IDX                                                           0
3322 #define mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32                                                         0x1643
3323 #define mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX                                                0
3324 #define mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32                                                         0x1644
3325 #define mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX                                                0
3326 #define mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32                                                         0x1645
3327 #define mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX                                                0
3328 #define mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32                                                         0x1646
3329 #define mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX                                                0
3330 #define mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32                                                         0x1647
3331 #define mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX                                                0
3332 #define mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32                                                         0x1648
3333 #define mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX                                                0
3334 #define mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32                                                         0x1649
3335 #define mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX                                                0
3336 #define mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32                                                         0x164a
3337 #define mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX                                                0
3338 #define mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32                                                         0x164b
3339 #define mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX                                                0
3340 #define mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32                                                         0x164c
3341 #define mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX                                                0
3342 #define mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32                                                         0x164d
3343 #define mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX                                                0
3344 #define mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32                                                         0x164e
3345 #define mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX                                                0
3346 #define mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32                                                         0x164f
3347 #define mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX                                                0
3348 #define mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32                                                         0x1650
3349 #define mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX                                                0
3350 #define mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32                                                         0x1651
3351 #define mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX                                                0
3352 #define mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32                                                         0x1652
3353 #define mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX                                                0
3354 #define mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32                                                         0x1653
3355 #define mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX                                                0
3356 #define mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32                                                         0x1654
3357 #define mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX                                                0
3358 #define mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32                                                         0x1655
3359 #define mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX                                                0
3360 #define mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32                                                         0x1656
3361 #define mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX                                                0
3362 #define mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32                                                        0x1657
3363 #define mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX                                               0
3364 #define mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32                                                        0x1658
3365 #define mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX                                               0
3366 #define mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32                                                        0x1659
3367 #define mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX                                               0
3368 #define mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32                                                        0x165a
3369 #define mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX                                               0
3370 #define mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32                                                        0x165b
3371 #define mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX                                               0
3372 #define mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32                                                        0x165c
3373 #define mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX                                               0
3374 #define mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32                                                        0x165d
3375 #define mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX                                               0
3376 #define mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32                                                        0x165e
3377 #define mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX                                               0
3378 #define mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32                                                        0x165f
3379 #define mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX                                               0
3380 #define mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32                                                        0x1660
3381 #define mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX                                               0
3382 #define mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32                                                        0x1661
3383 #define mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX                                               0
3384 #define mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32                                                        0x1662
3385 #define mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX                                               0
3386 #define mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32                                                        0x1663
3387 #define mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX                                               0
3388 #define mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32                                                        0x1664
3389 #define mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX                                               0
3390 #define mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32                                                        0x1665
3391 #define mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX                                               0
3392 #define mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32                                                        0x1666
3393 #define mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX                                               0
3394 #define mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32                                                      0x1667
3395 #define mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3396 #define mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32                                                      0x1668
3397 #define mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3398 #define mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32                                                      0x1669
3399 #define mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3400 #define mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32                                                      0x166a
3401 #define mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3402 #define mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32                                                      0x166b
3403 #define mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3404 #define mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32                                                      0x166c
3405 #define mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3406 #define mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32                                                      0x166d
3407 #define mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3408 #define mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32                                                      0x166e
3409 #define mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3410 #define mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32                                                      0x166f
3411 #define mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3412 #define mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32                                                      0x1670
3413 #define mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3414 #define mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32                                                      0x1671
3415 #define mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3416 #define mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32                                                      0x1672
3417 #define mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3418 #define mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32                                                      0x1673
3419 #define mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3420 #define mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32                                                      0x1674
3421 #define mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3422 #define mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32                                                      0x1675
3423 #define mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3424 #define mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32                                                      0x1676
3425 #define mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3426 #define mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32                                                      0x1677
3427 #define mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3428 #define mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32                                                      0x1678
3429 #define mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3430 #define mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32                                                      0x1679
3431 #define mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3432 #define mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32                                                      0x167a
3433 #define mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3434 #define mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32                                                     0x167b
3435 #define mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            0
3436 #define mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32                                                     0x167c
3437 #define mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            0
3438 #define mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32                                                     0x167d
3439 #define mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            0
3440 #define mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32                                                     0x167e
3441 #define mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            0
3442 #define mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32                                                     0x167f
3443 #define mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            0
3444 #define mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32                                                     0x1680
3445 #define mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            0
3446 #define mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32                                                     0x1681
3447 #define mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            0
3448 #define mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32                                                     0x1682
3449 #define mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            0
3450 #define mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32                                                     0x1683
3451 #define mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            0
3452 #define mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32                                                     0x1684
3453 #define mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            0
3454 #define mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32                                                     0x1685
3455 #define mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            0
3456 #define mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32                                                     0x1686
3457 #define mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            0
3458 #define mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32                                                     0x1687
3459 #define mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3460 #define mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32                                                     0x1688
3461 #define mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3462 #define mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32                                                     0x1689
3463 #define mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3464 #define mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32                                                     0x168a
3465 #define mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3466 #define mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32                                                     0x168b
3467 #define mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3468 #define mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32                                                     0x168c
3469 #define mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3470 #define mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32                                                     0x168d
3471 #define mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3472 #define mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32                                                     0x168e
3473 #define mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3474 #define mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32                                                     0x168f
3475 #define mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3476 #define mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32                                                     0x1690
3477 #define mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3478 #define mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32                                                     0x1691
3479 #define mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3480 #define mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32                                                     0x1692
3481 #define mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3482 #define mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32                                                     0x1693
3483 #define mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3484 #define mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32                                                     0x1694
3485 #define mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3486 #define mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32                                                     0x1695
3487 #define mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3488 #define mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32                                                     0x1696
3489 #define mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3490 #define mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32                                                     0x1697
3491 #define mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3492 #define mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32                                                     0x1698
3493 #define mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3494 #define mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32                                                     0x1699
3495 #define mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3496 #define mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32                                                     0x169a
3497 #define mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3498 #define mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32                                                    0x169b
3499 #define mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           0
3500 #define mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32                                                    0x169c
3501 #define mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           0
3502 #define mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32                                                    0x169d
3503 #define mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           0
3504 #define mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32                                                    0x169e
3505 #define mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           0
3506 #define mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32                                                    0x169f
3507 #define mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           0
3508 #define mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32                                                    0x16a0
3509 #define mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           0
3510 #define mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32                                                    0x16a1
3511 #define mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           0
3512 #define mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32                                                    0x16a2
3513 #define mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           0
3514 #define mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32                                                    0x16a3
3515 #define mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           0
3516 #define mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32                                                    0x16a4
3517 #define mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           0
3518 #define mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32                                                    0x16a5
3519 #define mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           0
3520 #define mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32                                                    0x16a6
3521 #define mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           0
3522 #define mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32                                                       0x16a7
3523 #define mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3524 #define mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32                                                       0x16a8
3525 #define mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3526 #define mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32                                                       0x16a9
3527 #define mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3528 #define mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32                                                       0x16aa
3529 #define mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3530 #define mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32                                                       0x16ab
3531 #define mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3532 #define mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32                                                       0x16ac
3533 #define mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3534 #define mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32                                                       0x16ad
3535 #define mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3536 #define mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32                                                       0x16ae
3537 #define mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3538 #define mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32                                                       0x16af
3539 #define mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3540 #define mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32                                                       0x16b0
3541 #define mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3542 #define mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32                                                       0x16b1
3543 #define mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3544 #define mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32                                                       0x16b2
3545 #define mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3546 #define mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32                                                       0x16b3
3547 #define mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3548 #define mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32                                                       0x16b4
3549 #define mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3550 #define mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32                                                       0x16b5
3551 #define mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3552 #define mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32                                                       0x16b6
3553 #define mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3554 #define mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32                                                       0x16b7
3555 #define mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3556 #define mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32                                                       0x16b8
3557 #define mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3558 #define mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32                                                       0x16b9
3559 #define mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3560 #define mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32                                                       0x16ba
3561 #define mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3562 #define mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32                                                      0x16bb
3563 #define mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             0
3564 #define mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32                                                      0x16bc
3565 #define mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             0
3566 #define mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32                                                      0x16bd
3567 #define mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             0
3568 #define mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32                                                      0x16be
3569 #define mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             0
3570 #define mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32                                                      0x16bf
3571 #define mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             0
3572 #define mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32                                                      0x16c0
3573 #define mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             0
3574 #define mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32                                                      0x16c1
3575 #define mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             0
3576 #define mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32                                                      0x16c2
3577 #define mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             0
3578 #define mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32                                                      0x16c3
3579 #define mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             0
3580 #define mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32                                                      0x16c4
3581 #define mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             0
3582 #define mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32                                                      0x16c5
3583 #define mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             0
3584 #define mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32                                                      0x16c6
3585 #define mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             0
3586 #define mmGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                                    0x16c7
3587 #define mmGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                           0
3588 #define mmGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x16c8
3589 #define mmGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  0
3590 #define mmGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x16c9
3591 #define mmGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  0
3592 #define mmGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x16ca
3593 #define mmGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  0
3594 #define mmGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x16cb
3595 #define mmGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  0
3596 #define mmGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x16cc
3597 #define mmGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  0
3598 #define mmGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x16cd
3599 #define mmGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  0
3600 #define mmGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x16ce
3601 #define mmGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  0
3602 #define mmGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x16cf
3603 #define mmGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  0
3604 #define mmGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x16d0
3605 #define mmGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  0
3606 #define mmGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                           0x16d1
3607 #define mmGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                  0
3608 #define mmGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x16d2
3609 #define mmGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 0
3610 #define mmGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x16d3
3611 #define mmGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 0
3612 #define mmGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x16d4
3613 #define mmGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 0
3614 #define mmGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x16d5
3615 #define mmGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 0
3616 #define mmGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x16d6
3617 #define mmGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 0
3618 #define mmGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES                                          0x16d7
3619 #define mmGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX                                 0
3620 
3621 
3622 // addressBlock: gc_gcvmsharedpfdec
3623 // base address: 0xa500
3624 #define mmGCMC_VM_NB_MMIOBASE                                                                          0x16e0
3625 #define mmGCMC_VM_NB_MMIOBASE_BASE_IDX                                                                 0
3626 #define mmGCMC_VM_NB_MMIOLIMIT                                                                         0x16e1
3627 #define mmGCMC_VM_NB_MMIOLIMIT_BASE_IDX                                                                0
3628 #define mmGCMC_VM_NB_PCI_CTRL                                                                          0x16e2
3629 #define mmGCMC_VM_NB_PCI_CTRL_BASE_IDX                                                                 0
3630 #define mmGCMC_VM_NB_PCI_ARB                                                                           0x16e3
3631 #define mmGCMC_VM_NB_PCI_ARB_BASE_IDX                                                                  0
3632 #define mmGCMC_VM_NB_TOP_OF_DRAM_SLOT1                                                                 0x16e4
3633 #define mmGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX                                                        0
3634 #define mmGCMC_VM_NB_LOWER_TOP_OF_DRAM2                                                                0x16e5
3635 #define mmGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX                                                       0
3636 #define mmGCMC_VM_NB_UPPER_TOP_OF_DRAM2                                                                0x16e6
3637 #define mmGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX                                                       0
3638 #define mmGCMC_VM_FB_OFFSET                                                                            0x16e7
3639 #define mmGCMC_VM_FB_OFFSET_BASE_IDX                                                                   0
3640 #define mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB                                                     0x16e8
3641 #define mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX                                            0
3642 #define mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB                                                     0x16e9
3643 #define mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX                                            0
3644 #define mmGCMC_VM_STEERING                                                                             0x16ea
3645 #define mmGCMC_VM_STEERING_BASE_IDX                                                                    0
3646 #define mmGCMC_SHARED_VIRT_RESET_REQ                                                                   0x16eb
3647 #define mmGCMC_SHARED_VIRT_RESET_REQ_BASE_IDX                                                          0
3648 #define mmGCMC_MEM_POWER_LS                                                                            0x16ec
3649 #define mmGCMC_MEM_POWER_LS_BASE_IDX                                                                   0
3650 #define mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_START                                                         0x16ed
3651 #define mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX                                                0
3652 #define mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END                                                           0x16ee
3653 #define mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX                                                  0
3654 #define mmGCMC_VM_APT_CNTL                                                                             0x16ef
3655 #define mmGCMC_VM_APT_CNTL_BASE_IDX                                                                    0
3656 #define mmGCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL                                                          0x16f0
3657 #define mmGCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX                                                 0
3658 #define mmGCMC_VM_LOCAL_HBM_ADDRESS_START                                                              0x16f1
3659 #define mmGCMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX                                                     0
3660 #define mmGCMC_VM_LOCAL_HBM_ADDRESS_END                                                                0x16f2
3661 #define mmGCMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX                                                       0
3662 #define mmGCMC_SHARED_ACTIVE_FCN_ID                                                                    0x16f4
3663 #define mmGCMC_SHARED_ACTIVE_FCN_ID_BASE_IDX                                                           0
3664 #define mmGCMC_SHARED_VIRT_RESET_REQ2                                                                  0x16f5
3665 #define mmGCMC_SHARED_VIRT_RESET_REQ2_BASE_IDX                                                         0
3666 #define mmGCMC_VM_XGMI_LFB_CNTL                                                                        0x16f7
3667 #define mmGCMC_VM_XGMI_LFB_CNTL_BASE_IDX                                                               0
3668 #define mmGCMC_VM_XGMI_LFB_SIZE                                                                        0x16f8
3669 #define mmGCMC_VM_XGMI_LFB_SIZE_BASE_IDX                                                               0
3670 #define mmGCMC_VM_FB_NOALLOC_CNTL                                                                      0x16f9
3671 #define mmGCMC_VM_FB_NOALLOC_CNTL_BASE_IDX                                                             0
3672 #define mmGCUTCL2_HARVEST_BYPASS_GROUPS                                                                0x16fa
3673 #define mmGCUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX                                                       0
3674 
3675 
3676 // addressBlock: gc_gcvmsharedvcdec
3677 // base address: 0xa570
3678 #define mmGCMC_VM_FB_LOCATION_BASE                                                                     0x16fc
3679 #define mmGCMC_VM_FB_LOCATION_BASE_BASE_IDX                                                            0
3680 #define mmGCMC_VM_FB_LOCATION_TOP                                                                      0x16fd
3681 #define mmGCMC_VM_FB_LOCATION_TOP_BASE_IDX                                                             0
3682 #define mmGCMC_VM_AGP_TOP                                                                              0x16fe
3683 #define mmGCMC_VM_AGP_TOP_BASE_IDX                                                                     0
3684 #define mmGCMC_VM_AGP_BOT                                                                              0x16ff
3685 #define mmGCMC_VM_AGP_BOT_BASE_IDX                                                                     0
3686 #define mmGCMC_VM_AGP_BASE                                                                             0x1700
3687 #define mmGCMC_VM_AGP_BASE_BASE_IDX                                                                    0
3688 #define mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR                                                             0x1701
3689 #define mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                                    0
3690 #define mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR                                                            0x1702
3691 #define mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                                   0
3692 #define mmGCMC_VM_MX_L1_TLB_CNTL                                                                       0x1703
3693 #define mmGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX                                                              0
3694 
3695 
3696 // addressBlock: gc_gceadec
3697 // base address: 0xa800
3698 #define mmGCEA_DRAM_RD_CLI2GRP_MAP0                                                                    0x17a0
3699 #define mmGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX                                                           0
3700 #define mmGCEA_DRAM_RD_CLI2GRP_MAP1                                                                    0x17a1
3701 #define mmGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX                                                           0
3702 #define mmGCEA_DRAM_WR_CLI2GRP_MAP0                                                                    0x17a2
3703 #define mmGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX                                                           0
3704 #define mmGCEA_DRAM_WR_CLI2GRP_MAP1                                                                    0x17a3
3705 #define mmGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX                                                           0
3706 #define mmGCEA_DRAM_RD_GRP2VC_MAP                                                                      0x17a4
3707 #define mmGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX                                                             0
3708 #define mmGCEA_DRAM_WR_GRP2VC_MAP                                                                      0x17a5
3709 #define mmGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX                                                             0
3710 #define mmGCEA_DRAM_RD_LAZY                                                                            0x17a6
3711 #define mmGCEA_DRAM_RD_LAZY_BASE_IDX                                                                   0
3712 #define mmGCEA_DRAM_WR_LAZY                                                                            0x17a7
3713 #define mmGCEA_DRAM_WR_LAZY_BASE_IDX                                                                   0
3714 #define mmGCEA_DRAM_RD_CAM_CNTL                                                                        0x17a8
3715 #define mmGCEA_DRAM_RD_CAM_CNTL_BASE_IDX                                                               0
3716 #define mmGCEA_DRAM_WR_CAM_CNTL                                                                        0x17a9
3717 #define mmGCEA_DRAM_WR_CAM_CNTL_BASE_IDX                                                               0
3718 #define mmGCEA_DRAM_PAGE_BURST                                                                         0x17aa
3719 #define mmGCEA_DRAM_PAGE_BURST_BASE_IDX                                                                0
3720 #define mmGCEA_DRAM_RD_PRI_AGE                                                                         0x17ab
3721 #define mmGCEA_DRAM_RD_PRI_AGE_BASE_IDX                                                                0
3722 #define mmGCEA_DRAM_WR_PRI_AGE                                                                         0x17ac
3723 #define mmGCEA_DRAM_WR_PRI_AGE_BASE_IDX                                                                0
3724 #define mmGCEA_DRAM_RD_PRI_QUEUING                                                                     0x17ad
3725 #define mmGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX                                                            0
3726 #define mmGCEA_DRAM_WR_PRI_QUEUING                                                                     0x17ae
3727 #define mmGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX                                                            0
3728 #define mmGCEA_DRAM_RD_PRI_FIXED                                                                       0x17af
3729 #define mmGCEA_DRAM_RD_PRI_FIXED_BASE_IDX                                                              0
3730 #define mmGCEA_DRAM_WR_PRI_FIXED                                                                       0x17b0
3731 #define mmGCEA_DRAM_WR_PRI_FIXED_BASE_IDX                                                              0
3732 #define mmGCEA_DRAM_RD_PRI_URGENCY                                                                     0x17b1
3733 #define mmGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX                                                            0
3734 #define mmGCEA_DRAM_WR_PRI_URGENCY                                                                     0x17b2
3735 #define mmGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX                                                            0
3736 #define mmGCEA_DRAM_RD_PRI_QUANT_PRI1                                                                  0x17b3
3737 #define mmGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX                                                         0
3738 #define mmGCEA_DRAM_RD_PRI_QUANT_PRI2                                                                  0x17b4
3739 #define mmGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX                                                         0
3740 #define mmGCEA_DRAM_RD_PRI_QUANT_PRI3                                                                  0x17b5
3741 #define mmGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX                                                         0
3742 #define mmGCEA_DRAM_WR_PRI_QUANT_PRI1                                                                  0x17b6
3743 #define mmGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX                                                         0
3744 #define mmGCEA_DRAM_WR_PRI_QUANT_PRI2                                                                  0x17b7
3745 #define mmGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX                                                         0
3746 #define mmGCEA_DRAM_WR_PRI_QUANT_PRI3                                                                  0x17b8
3747 #define mmGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX                                                         0
3748 #define mmGCEA_IO_RD_CLI2GRP_MAP0                                                                      0x187d
3749 #define mmGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX                                                             0
3750 #define mmGCEA_IO_RD_CLI2GRP_MAP1                                                                      0x187e
3751 #define mmGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX                                                             0
3752 #define mmGCEA_IO_WR_CLI2GRP_MAP0                                                                      0x187f
3753 #define mmGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX                                                             0
3754 #define mmGCEA_IO_WR_CLI2GRP_MAP1                                                                      0x1880
3755 #define mmGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX                                                             0
3756 #define mmGCEA_IO_RD_COMBINE_FLUSH                                                                     0x1881
3757 #define mmGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX                                                            0
3758 #define mmGCEA_IO_WR_COMBINE_FLUSH                                                                     0x1882
3759 #define mmGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX                                                            0
3760 #define mmGCEA_IO_GROUP_BURST                                                                          0x1883
3761 #define mmGCEA_IO_GROUP_BURST_BASE_IDX                                                                 0
3762 #define mmGCEA_IO_RD_PRI_AGE                                                                           0x1884
3763 #define mmGCEA_IO_RD_PRI_AGE_BASE_IDX                                                                  0
3764 #define mmGCEA_IO_WR_PRI_AGE                                                                           0x1885
3765 #define mmGCEA_IO_WR_PRI_AGE_BASE_IDX                                                                  0
3766 #define mmGCEA_IO_RD_PRI_QUEUING                                                                       0x1886
3767 #define mmGCEA_IO_RD_PRI_QUEUING_BASE_IDX                                                              0
3768 #define mmGCEA_IO_WR_PRI_QUEUING                                                                       0x1887
3769 #define mmGCEA_IO_WR_PRI_QUEUING_BASE_IDX                                                              0
3770 #define mmGCEA_IO_RD_PRI_FIXED                                                                         0x1888
3771 #define mmGCEA_IO_RD_PRI_FIXED_BASE_IDX                                                                0
3772 #define mmGCEA_IO_WR_PRI_FIXED                                                                         0x1889
3773 #define mmGCEA_IO_WR_PRI_FIXED_BASE_IDX                                                                0
3774 #define mmGCEA_IO_RD_PRI_URGENCY                                                                       0x188a
3775 #define mmGCEA_IO_RD_PRI_URGENCY_BASE_IDX                                                              0
3776 #define mmGCEA_IO_WR_PRI_URGENCY                                                                       0x188b
3777 #define mmGCEA_IO_WR_PRI_URGENCY_BASE_IDX                                                              0
3778 #define mmGCEA_IO_RD_PRI_URGENCY_MASKING                                                               0x188c
3779 #define mmGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX                                                      0
3780 #define mmGCEA_IO_WR_PRI_URGENCY_MASKING                                                               0x188d
3781 #define mmGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX                                                      0
3782 #define mmGCEA_IO_RD_PRI_QUANT_PRI1                                                                    0x188e
3783 #define mmGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX                                                           0
3784 #define mmGCEA_IO_RD_PRI_QUANT_PRI2                                                                    0x188f
3785 #define mmGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX                                                           0
3786 #define mmGCEA_IO_RD_PRI_QUANT_PRI3                                                                    0x1890
3787 #define mmGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX                                                           0
3788 #define mmGCEA_IO_WR_PRI_QUANT_PRI1                                                                    0x1891
3789 #define mmGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX                                                           0
3790 #define mmGCEA_IO_WR_PRI_QUANT_PRI2                                                                    0x1892
3791 #define mmGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX                                                           0
3792 #define mmGCEA_IO_WR_PRI_QUANT_PRI3                                                                    0x1893
3793 #define mmGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX                                                           0
3794 
3795 
3796 // addressBlock: gc_tcdec
3797 // base address: 0xac00
3798 #define mmTCP_INVALIDATE                                                                               0x18a0
3799 #define mmTCP_INVALIDATE_BASE_IDX                                                                      0
3800 #define mmTCP_STATUS                                                                                   0x18a1
3801 #define mmTCP_STATUS_BASE_IDX                                                                          0
3802 #define mmTCP_EDC_CNT                                                                                  0x18b7
3803 #define mmTCP_EDC_CNT_BASE_IDX                                                                         0
3804 #define mmTCI_STATUS                                                                                   0x1901
3805 #define mmTCI_STATUS_BASE_IDX                                                                          0
3806 #define mmTCI_CNTL_1                                                                                   0x1902
3807 #define mmTCI_CNTL_1_BASE_IDX                                                                          0
3808 #define mmTCI_CNTL_2                                                                                   0x1903
3809 #define mmTCI_CNTL_2_BASE_IDX                                                                          0
3810 
3811 
3812 // addressBlock: gc_shdec
3813 // base address: 0xb000
3814 #define mmSPI_SHADER_PGM_RSRC4_PS                                                                      0x19a1
3815 #define mmSPI_SHADER_PGM_RSRC4_PS_BASE_IDX                                                             0
3816 #define mmSPI_SHADER_PGM_CHKSUM_PS                                                                     0x19a6
3817 #define mmSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX                                                            0
3818 #define mmSPI_SHADER_PGM_RSRC3_PS                                                                      0x19a7
3819 #define mmSPI_SHADER_PGM_RSRC3_PS_BASE_IDX                                                             0
3820 #define mmSPI_SHADER_PGM_LO_PS                                                                         0x19a8
3821 #define mmSPI_SHADER_PGM_LO_PS_BASE_IDX                                                                0
3822 #define mmSPI_SHADER_PGM_HI_PS                                                                         0x19a9
3823 #define mmSPI_SHADER_PGM_HI_PS_BASE_IDX                                                                0
3824 #define mmSPI_SHADER_PGM_RSRC1_PS                                                                      0x19aa
3825 #define mmSPI_SHADER_PGM_RSRC1_PS_BASE_IDX                                                             0
3826 #define mmSPI_SHADER_PGM_RSRC2_PS                                                                      0x19ab
3827 #define mmSPI_SHADER_PGM_RSRC2_PS_BASE_IDX                                                             0
3828 #define mmSPI_SHADER_USER_DATA_PS_0                                                                    0x19ac
3829 #define mmSPI_SHADER_USER_DATA_PS_0_BASE_IDX                                                           0
3830 #define mmSPI_SHADER_USER_DATA_PS_1                                                                    0x19ad
3831 #define mmSPI_SHADER_USER_DATA_PS_1_BASE_IDX                                                           0
3832 #define mmSPI_SHADER_USER_DATA_PS_2                                                                    0x19ae
3833 #define mmSPI_SHADER_USER_DATA_PS_2_BASE_IDX                                                           0
3834 #define mmSPI_SHADER_USER_DATA_PS_3                                                                    0x19af
3835 #define mmSPI_SHADER_USER_DATA_PS_3_BASE_IDX                                                           0
3836 #define mmSPI_SHADER_USER_DATA_PS_4                                                                    0x19b0
3837 #define mmSPI_SHADER_USER_DATA_PS_4_BASE_IDX                                                           0
3838 #define mmSPI_SHADER_USER_DATA_PS_5                                                                    0x19b1
3839 #define mmSPI_SHADER_USER_DATA_PS_5_BASE_IDX                                                           0
3840 #define mmSPI_SHADER_USER_DATA_PS_6                                                                    0x19b2
3841 #define mmSPI_SHADER_USER_DATA_PS_6_BASE_IDX                                                           0
3842 #define mmSPI_SHADER_USER_DATA_PS_7                                                                    0x19b3
3843 #define mmSPI_SHADER_USER_DATA_PS_7_BASE_IDX                                                           0
3844 #define mmSPI_SHADER_USER_DATA_PS_8                                                                    0x19b4
3845 #define mmSPI_SHADER_USER_DATA_PS_8_BASE_IDX                                                           0
3846 #define mmSPI_SHADER_USER_DATA_PS_9                                                                    0x19b5
3847 #define mmSPI_SHADER_USER_DATA_PS_9_BASE_IDX                                                           0
3848 #define mmSPI_SHADER_USER_DATA_PS_10                                                                   0x19b6
3849 #define mmSPI_SHADER_USER_DATA_PS_10_BASE_IDX                                                          0
3850 #define mmSPI_SHADER_USER_DATA_PS_11                                                                   0x19b7
3851 #define mmSPI_SHADER_USER_DATA_PS_11_BASE_IDX                                                          0
3852 #define mmSPI_SHADER_USER_DATA_PS_12                                                                   0x19b8
3853 #define mmSPI_SHADER_USER_DATA_PS_12_BASE_IDX                                                          0
3854 #define mmSPI_SHADER_USER_DATA_PS_13                                                                   0x19b9
3855 #define mmSPI_SHADER_USER_DATA_PS_13_BASE_IDX                                                          0
3856 #define mmSPI_SHADER_USER_DATA_PS_14                                                                   0x19ba
3857 #define mmSPI_SHADER_USER_DATA_PS_14_BASE_IDX                                                          0
3858 #define mmSPI_SHADER_USER_DATA_PS_15                                                                   0x19bb
3859 #define mmSPI_SHADER_USER_DATA_PS_15_BASE_IDX                                                          0
3860 #define mmSPI_SHADER_USER_DATA_PS_16                                                                   0x19bc
3861 #define mmSPI_SHADER_USER_DATA_PS_16_BASE_IDX                                                          0
3862 #define mmSPI_SHADER_USER_DATA_PS_17                                                                   0x19bd
3863 #define mmSPI_SHADER_USER_DATA_PS_17_BASE_IDX                                                          0
3864 #define mmSPI_SHADER_USER_DATA_PS_18                                                                   0x19be
3865 #define mmSPI_SHADER_USER_DATA_PS_18_BASE_IDX                                                          0
3866 #define mmSPI_SHADER_USER_DATA_PS_19                                                                   0x19bf
3867 #define mmSPI_SHADER_USER_DATA_PS_19_BASE_IDX                                                          0
3868 #define mmSPI_SHADER_USER_DATA_PS_20                                                                   0x19c0
3869 #define mmSPI_SHADER_USER_DATA_PS_20_BASE_IDX                                                          0
3870 #define mmSPI_SHADER_USER_DATA_PS_21                                                                   0x19c1
3871 #define mmSPI_SHADER_USER_DATA_PS_21_BASE_IDX                                                          0
3872 #define mmSPI_SHADER_USER_DATA_PS_22                                                                   0x19c2
3873 #define mmSPI_SHADER_USER_DATA_PS_22_BASE_IDX                                                          0
3874 #define mmSPI_SHADER_USER_DATA_PS_23                                                                   0x19c3
3875 #define mmSPI_SHADER_USER_DATA_PS_23_BASE_IDX                                                          0
3876 #define mmSPI_SHADER_USER_DATA_PS_24                                                                   0x19c4
3877 #define mmSPI_SHADER_USER_DATA_PS_24_BASE_IDX                                                          0
3878 #define mmSPI_SHADER_USER_DATA_PS_25                                                                   0x19c5
3879 #define mmSPI_SHADER_USER_DATA_PS_25_BASE_IDX                                                          0
3880 #define mmSPI_SHADER_USER_DATA_PS_26                                                                   0x19c6
3881 #define mmSPI_SHADER_USER_DATA_PS_26_BASE_IDX                                                          0
3882 #define mmSPI_SHADER_USER_DATA_PS_27                                                                   0x19c7
3883 #define mmSPI_SHADER_USER_DATA_PS_27_BASE_IDX                                                          0
3884 #define mmSPI_SHADER_USER_DATA_PS_28                                                                   0x19c8
3885 #define mmSPI_SHADER_USER_DATA_PS_28_BASE_IDX                                                          0
3886 #define mmSPI_SHADER_USER_DATA_PS_29                                                                   0x19c9
3887 #define mmSPI_SHADER_USER_DATA_PS_29_BASE_IDX                                                          0
3888 #define mmSPI_SHADER_USER_DATA_PS_30                                                                   0x19ca
3889 #define mmSPI_SHADER_USER_DATA_PS_30_BASE_IDX                                                          0
3890 #define mmSPI_SHADER_USER_DATA_PS_31                                                                   0x19cb
3891 #define mmSPI_SHADER_USER_DATA_PS_31_BASE_IDX                                                          0
3892 #define mmSPI_SHADER_REQ_CTRL_PS                                                                       0x19d0
3893 #define mmSPI_SHADER_REQ_CTRL_PS_BASE_IDX                                                              0
3894 #define mmSPI_SHADER_USER_ACCUM_PS_0                                                                   0x19d2
3895 #define mmSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX                                                          0
3896 #define mmSPI_SHADER_USER_ACCUM_PS_1                                                                   0x19d3
3897 #define mmSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX                                                          0
3898 #define mmSPI_SHADER_USER_ACCUM_PS_2                                                                   0x19d4
3899 #define mmSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX                                                          0
3900 #define mmSPI_SHADER_USER_ACCUM_PS_3                                                                   0x19d5
3901 #define mmSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX                                                          0
3902 #define mmSPI_SHADER_PGM_RSRC4_VS                                                                      0x19e1
3903 #define mmSPI_SHADER_PGM_RSRC4_VS_BASE_IDX                                                             0
3904 #define mmSPI_SHADER_PGM_CHKSUM_VS                                                                     0x19e5
3905 #define mmSPI_SHADER_PGM_CHKSUM_VS_BASE_IDX                                                            0
3906 #define mmSPI_SHADER_PGM_RSRC3_VS                                                                      0x19e6
3907 #define mmSPI_SHADER_PGM_RSRC3_VS_BASE_IDX                                                             0
3908 #define mmSPI_SHADER_LATE_ALLOC_VS                                                                     0x19e7
3909 #define mmSPI_SHADER_LATE_ALLOC_VS_BASE_IDX                                                            0
3910 #define mmSPI_SHADER_PGM_LO_VS                                                                         0x19e8
3911 #define mmSPI_SHADER_PGM_LO_VS_BASE_IDX                                                                0
3912 #define mmSPI_SHADER_PGM_HI_VS                                                                         0x19e9
3913 #define mmSPI_SHADER_PGM_HI_VS_BASE_IDX                                                                0
3914 #define mmSPI_SHADER_PGM_RSRC1_VS                                                                      0x19ea
3915 #define mmSPI_SHADER_PGM_RSRC1_VS_BASE_IDX                                                             0
3916 #define mmSPI_SHADER_PGM_RSRC2_VS                                                                      0x19eb
3917 #define mmSPI_SHADER_PGM_RSRC2_VS_BASE_IDX                                                             0
3918 #define mmSPI_SHADER_USER_DATA_VS_0                                                                    0x19ec
3919 #define mmSPI_SHADER_USER_DATA_VS_0_BASE_IDX                                                           0
3920 #define mmSPI_SHADER_USER_DATA_VS_1                                                                    0x19ed
3921 #define mmSPI_SHADER_USER_DATA_VS_1_BASE_IDX                                                           0
3922 #define mmSPI_SHADER_USER_DATA_VS_2                                                                    0x19ee
3923 #define mmSPI_SHADER_USER_DATA_VS_2_BASE_IDX                                                           0
3924 #define mmSPI_SHADER_USER_DATA_VS_3                                                                    0x19ef
3925 #define mmSPI_SHADER_USER_DATA_VS_3_BASE_IDX                                                           0
3926 #define mmSPI_SHADER_USER_DATA_VS_4                                                                    0x19f0
3927 #define mmSPI_SHADER_USER_DATA_VS_4_BASE_IDX                                                           0
3928 #define mmSPI_SHADER_USER_DATA_VS_5                                                                    0x19f1
3929 #define mmSPI_SHADER_USER_DATA_VS_5_BASE_IDX                                                           0
3930 #define mmSPI_SHADER_USER_DATA_VS_6                                                                    0x19f2
3931 #define mmSPI_SHADER_USER_DATA_VS_6_BASE_IDX                                                           0
3932 #define mmSPI_SHADER_USER_DATA_VS_7                                                                    0x19f3
3933 #define mmSPI_SHADER_USER_DATA_VS_7_BASE_IDX                                                           0
3934 #define mmSPI_SHADER_USER_DATA_VS_8                                                                    0x19f4
3935 #define mmSPI_SHADER_USER_DATA_VS_8_BASE_IDX                                                           0
3936 #define mmSPI_SHADER_USER_DATA_VS_9                                                                    0x19f5
3937 #define mmSPI_SHADER_USER_DATA_VS_9_BASE_IDX                                                           0
3938 #define mmSPI_SHADER_USER_DATA_VS_10                                                                   0x19f6
3939 #define mmSPI_SHADER_USER_DATA_VS_10_BASE_IDX                                                          0
3940 #define mmSPI_SHADER_USER_DATA_VS_11                                                                   0x19f7
3941 #define mmSPI_SHADER_USER_DATA_VS_11_BASE_IDX                                                          0
3942 #define mmSPI_SHADER_USER_DATA_VS_12                                                                   0x19f8
3943 #define mmSPI_SHADER_USER_DATA_VS_12_BASE_IDX                                                          0
3944 #define mmSPI_SHADER_USER_DATA_VS_13                                                                   0x19f9
3945 #define mmSPI_SHADER_USER_DATA_VS_13_BASE_IDX                                                          0
3946 #define mmSPI_SHADER_USER_DATA_VS_14                                                                   0x19fa
3947 #define mmSPI_SHADER_USER_DATA_VS_14_BASE_IDX                                                          0
3948 #define mmSPI_SHADER_USER_DATA_VS_15                                                                   0x19fb
3949 #define mmSPI_SHADER_USER_DATA_VS_15_BASE_IDX                                                          0
3950 #define mmSPI_SHADER_USER_DATA_VS_16                                                                   0x19fc
3951 #define mmSPI_SHADER_USER_DATA_VS_16_BASE_IDX                                                          0
3952 #define mmSPI_SHADER_USER_DATA_VS_17                                                                   0x19fd
3953 #define mmSPI_SHADER_USER_DATA_VS_17_BASE_IDX                                                          0
3954 #define mmSPI_SHADER_USER_DATA_VS_18                                                                   0x19fe
3955 #define mmSPI_SHADER_USER_DATA_VS_18_BASE_IDX                                                          0
3956 #define mmSPI_SHADER_USER_DATA_VS_19                                                                   0x19ff
3957 #define mmSPI_SHADER_USER_DATA_VS_19_BASE_IDX                                                          0
3958 #define mmSPI_SHADER_USER_DATA_VS_20                                                                   0x1a00
3959 #define mmSPI_SHADER_USER_DATA_VS_20_BASE_IDX                                                          0
3960 #define mmSPI_SHADER_USER_DATA_VS_21                                                                   0x1a01
3961 #define mmSPI_SHADER_USER_DATA_VS_21_BASE_IDX                                                          0
3962 #define mmSPI_SHADER_USER_DATA_VS_22                                                                   0x1a02
3963 #define mmSPI_SHADER_USER_DATA_VS_22_BASE_IDX                                                          0
3964 #define mmSPI_SHADER_USER_DATA_VS_23                                                                   0x1a03
3965 #define mmSPI_SHADER_USER_DATA_VS_23_BASE_IDX                                                          0
3966 #define mmSPI_SHADER_USER_DATA_VS_24                                                                   0x1a04
3967 #define mmSPI_SHADER_USER_DATA_VS_24_BASE_IDX                                                          0
3968 #define mmSPI_SHADER_USER_DATA_VS_25                                                                   0x1a05
3969 #define mmSPI_SHADER_USER_DATA_VS_25_BASE_IDX                                                          0
3970 #define mmSPI_SHADER_USER_DATA_VS_26                                                                   0x1a06
3971 #define mmSPI_SHADER_USER_DATA_VS_26_BASE_IDX                                                          0
3972 #define mmSPI_SHADER_USER_DATA_VS_27                                                                   0x1a07
3973 #define mmSPI_SHADER_USER_DATA_VS_27_BASE_IDX                                                          0
3974 #define mmSPI_SHADER_USER_DATA_VS_28                                                                   0x1a08
3975 #define mmSPI_SHADER_USER_DATA_VS_28_BASE_IDX                                                          0
3976 #define mmSPI_SHADER_USER_DATA_VS_29                                                                   0x1a09
3977 #define mmSPI_SHADER_USER_DATA_VS_29_BASE_IDX                                                          0
3978 #define mmSPI_SHADER_USER_DATA_VS_30                                                                   0x1a0a
3979 #define mmSPI_SHADER_USER_DATA_VS_30_BASE_IDX                                                          0
3980 #define mmSPI_SHADER_USER_DATA_VS_31                                                                   0x1a0b
3981 #define mmSPI_SHADER_USER_DATA_VS_31_BASE_IDX                                                          0
3982 #define mmSPI_SHADER_REQ_CTRL_VS                                                                       0x1a10
3983 #define mmSPI_SHADER_REQ_CTRL_VS_BASE_IDX                                                              0
3984 #define mmSPI_SHADER_USER_ACCUM_VS_0                                                                   0x1a12
3985 #define mmSPI_SHADER_USER_ACCUM_VS_0_BASE_IDX                                                          0
3986 #define mmSPI_SHADER_USER_ACCUM_VS_1                                                                   0x1a13
3987 #define mmSPI_SHADER_USER_ACCUM_VS_1_BASE_IDX                                                          0
3988 #define mmSPI_SHADER_USER_ACCUM_VS_2                                                                   0x1a14
3989 #define mmSPI_SHADER_USER_ACCUM_VS_2_BASE_IDX                                                          0
3990 #define mmSPI_SHADER_USER_ACCUM_VS_3                                                                   0x1a15
3991 #define mmSPI_SHADER_USER_ACCUM_VS_3_BASE_IDX                                                          0
3992 #define mmSPI_SHADER_PGM_RSRC2_GS_VS                                                                   0x1a1b
3993 #define mmSPI_SHADER_PGM_RSRC2_GS_VS_BASE_IDX                                                          0
3994 #define mmSPI_SHADER_PGM_CHKSUM_GS                                                                     0x1a20
3995 #define mmSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX                                                            0
3996 #define mmSPI_SHADER_PGM_RSRC4_GS                                                                      0x1a21
3997 #define mmSPI_SHADER_PGM_RSRC4_GS_BASE_IDX                                                             0
3998 #define mmSPI_SHADER_USER_DATA_ADDR_LO_GS                                                              0x1a22
3999 #define mmSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX                                                     0
4000 #define mmSPI_SHADER_USER_DATA_ADDR_HI_GS                                                              0x1a23
4001 #define mmSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX                                                     0
4002 #define mmSPI_SHADER_PGM_LO_ES_GS                                                                      0x1a24
4003 #define mmSPI_SHADER_PGM_LO_ES_GS_BASE_IDX                                                             0
4004 #define mmSPI_SHADER_PGM_HI_ES_GS                                                                      0x1a25
4005 #define mmSPI_SHADER_PGM_HI_ES_GS_BASE_IDX                                                             0
4006 #define mmSPI_SHADER_PGM_RSRC3_GS                                                                      0x1a27
4007 #define mmSPI_SHADER_PGM_RSRC3_GS_BASE_IDX                                                             0
4008 #define mmSPI_SHADER_PGM_LO_GS                                                                         0x1a28
4009 #define mmSPI_SHADER_PGM_LO_GS_BASE_IDX                                                                0
4010 #define mmSPI_SHADER_PGM_HI_GS                                                                         0x1a29
4011 #define mmSPI_SHADER_PGM_HI_GS_BASE_IDX                                                                0
4012 #define mmSPI_SHADER_PGM_RSRC1_GS                                                                      0x1a2a
4013 #define mmSPI_SHADER_PGM_RSRC1_GS_BASE_IDX                                                             0
4014 #define mmSPI_SHADER_PGM_RSRC2_GS                                                                      0x1a2b
4015 #define mmSPI_SHADER_PGM_RSRC2_GS_BASE_IDX                                                             0
4016 #define mmSPI_SHADER_USER_DATA_GS_0                                                                    0x1a2c
4017 #define mmSPI_SHADER_USER_DATA_GS_0_BASE_IDX                                                           0
4018 #define mmSPI_SHADER_USER_DATA_GS_1                                                                    0x1a2d
4019 #define mmSPI_SHADER_USER_DATA_GS_1_BASE_IDX                                                           0
4020 #define mmSPI_SHADER_USER_DATA_GS_2                                                                    0x1a2e
4021 #define mmSPI_SHADER_USER_DATA_GS_2_BASE_IDX                                                           0
4022 #define mmSPI_SHADER_USER_DATA_GS_3                                                                    0x1a2f
4023 #define mmSPI_SHADER_USER_DATA_GS_3_BASE_IDX                                                           0
4024 #define mmSPI_SHADER_USER_DATA_GS_4                                                                    0x1a30
4025 #define mmSPI_SHADER_USER_DATA_GS_4_BASE_IDX                                                           0
4026 #define mmSPI_SHADER_USER_DATA_GS_5                                                                    0x1a31
4027 #define mmSPI_SHADER_USER_DATA_GS_5_BASE_IDX                                                           0
4028 #define mmSPI_SHADER_USER_DATA_GS_6                                                                    0x1a32
4029 #define mmSPI_SHADER_USER_DATA_GS_6_BASE_IDX                                                           0
4030 #define mmSPI_SHADER_USER_DATA_GS_7                                                                    0x1a33
4031 #define mmSPI_SHADER_USER_DATA_GS_7_BASE_IDX                                                           0
4032 #define mmSPI_SHADER_USER_DATA_GS_8                                                                    0x1a34
4033 #define mmSPI_SHADER_USER_DATA_GS_8_BASE_IDX                                                           0
4034 #define mmSPI_SHADER_USER_DATA_GS_9                                                                    0x1a35
4035 #define mmSPI_SHADER_USER_DATA_GS_9_BASE_IDX                                                           0
4036 #define mmSPI_SHADER_USER_DATA_GS_10                                                                   0x1a36
4037 #define mmSPI_SHADER_USER_DATA_GS_10_BASE_IDX                                                          0
4038 #define mmSPI_SHADER_USER_DATA_GS_11                                                                   0x1a37
4039 #define mmSPI_SHADER_USER_DATA_GS_11_BASE_IDX                                                          0
4040 #define mmSPI_SHADER_USER_DATA_GS_12                                                                   0x1a38
4041 #define mmSPI_SHADER_USER_DATA_GS_12_BASE_IDX                                                          0
4042 #define mmSPI_SHADER_USER_DATA_GS_13                                                                   0x1a39
4043 #define mmSPI_SHADER_USER_DATA_GS_13_BASE_IDX                                                          0
4044 #define mmSPI_SHADER_USER_DATA_GS_14                                                                   0x1a3a
4045 #define mmSPI_SHADER_USER_DATA_GS_14_BASE_IDX                                                          0
4046 #define mmSPI_SHADER_USER_DATA_GS_15                                                                   0x1a3b
4047 #define mmSPI_SHADER_USER_DATA_GS_15_BASE_IDX                                                          0
4048 #define mmSPI_SHADER_USER_DATA_GS_16                                                                   0x1a3c
4049 #define mmSPI_SHADER_USER_DATA_GS_16_BASE_IDX                                                          0
4050 #define mmSPI_SHADER_USER_DATA_GS_17                                                                   0x1a3d
4051 #define mmSPI_SHADER_USER_DATA_GS_17_BASE_IDX                                                          0
4052 #define mmSPI_SHADER_USER_DATA_GS_18                                                                   0x1a3e
4053 #define mmSPI_SHADER_USER_DATA_GS_18_BASE_IDX                                                          0
4054 #define mmSPI_SHADER_USER_DATA_GS_19                                                                   0x1a3f
4055 #define mmSPI_SHADER_USER_DATA_GS_19_BASE_IDX                                                          0
4056 #define mmSPI_SHADER_USER_DATA_GS_20                                                                   0x1a40
4057 #define mmSPI_SHADER_USER_DATA_GS_20_BASE_IDX                                                          0
4058 #define mmSPI_SHADER_USER_DATA_GS_21                                                                   0x1a41
4059 #define mmSPI_SHADER_USER_DATA_GS_21_BASE_IDX                                                          0
4060 #define mmSPI_SHADER_USER_DATA_GS_22                                                                   0x1a42
4061 #define mmSPI_SHADER_USER_DATA_GS_22_BASE_IDX                                                          0
4062 #define mmSPI_SHADER_USER_DATA_GS_23                                                                   0x1a43
4063 #define mmSPI_SHADER_USER_DATA_GS_23_BASE_IDX                                                          0
4064 #define mmSPI_SHADER_USER_DATA_GS_24                                                                   0x1a44
4065 #define mmSPI_SHADER_USER_DATA_GS_24_BASE_IDX                                                          0
4066 #define mmSPI_SHADER_USER_DATA_GS_25                                                                   0x1a45
4067 #define mmSPI_SHADER_USER_DATA_GS_25_BASE_IDX                                                          0
4068 #define mmSPI_SHADER_USER_DATA_GS_26                                                                   0x1a46
4069 #define mmSPI_SHADER_USER_DATA_GS_26_BASE_IDX                                                          0
4070 #define mmSPI_SHADER_USER_DATA_GS_27                                                                   0x1a47
4071 #define mmSPI_SHADER_USER_DATA_GS_27_BASE_IDX                                                          0
4072 #define mmSPI_SHADER_USER_DATA_GS_28                                                                   0x1a48
4073 #define mmSPI_SHADER_USER_DATA_GS_28_BASE_IDX                                                          0
4074 #define mmSPI_SHADER_USER_DATA_GS_29                                                                   0x1a49
4075 #define mmSPI_SHADER_USER_DATA_GS_29_BASE_IDX                                                          0
4076 #define mmSPI_SHADER_USER_DATA_GS_30                                                                   0x1a4a
4077 #define mmSPI_SHADER_USER_DATA_GS_30_BASE_IDX                                                          0
4078 #define mmSPI_SHADER_USER_DATA_GS_31                                                                   0x1a4b
4079 #define mmSPI_SHADER_USER_DATA_GS_31_BASE_IDX                                                          0
4080 #define mmSPI_SHADER_REQ_CTRL_ESGS                                                                     0x1a50
4081 #define mmSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX                                                            0
4082 #define mmSPI_SHADER_USER_ACCUM_ESGS_0                                                                 0x1a52
4083 #define mmSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX                                                        0
4084 #define mmSPI_SHADER_USER_ACCUM_ESGS_1                                                                 0x1a53
4085 #define mmSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX                                                        0
4086 #define mmSPI_SHADER_USER_ACCUM_ESGS_2                                                                 0x1a54
4087 #define mmSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX                                                        0
4088 #define mmSPI_SHADER_USER_ACCUM_ESGS_3                                                                 0x1a55
4089 #define mmSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX                                                        0
4090 #define mmSPI_SHADER_PGM_LO_ES                                                                         0x1a68
4091 #define mmSPI_SHADER_PGM_LO_ES_BASE_IDX                                                                0
4092 #define mmSPI_SHADER_PGM_HI_ES                                                                         0x1a69
4093 #define mmSPI_SHADER_PGM_HI_ES_BASE_IDX                                                                0
4094 #define mmSPI_SHADER_PGM_CHKSUM_HS                                                                     0x1aa0
4095 #define mmSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX                                                            0
4096 #define mmSPI_SHADER_PGM_RSRC4_HS                                                                      0x1aa1
4097 #define mmSPI_SHADER_PGM_RSRC4_HS_BASE_IDX                                                             0
4098 #define mmSPI_SHADER_USER_DATA_ADDR_LO_HS                                                              0x1aa2
4099 #define mmSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX                                                     0
4100 #define mmSPI_SHADER_USER_DATA_ADDR_HI_HS                                                              0x1aa3
4101 #define mmSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX                                                     0
4102 #define mmSPI_SHADER_PGM_LO_LS_HS                                                                      0x1aa4
4103 #define mmSPI_SHADER_PGM_LO_LS_HS_BASE_IDX                                                             0
4104 #define mmSPI_SHADER_PGM_HI_LS_HS                                                                      0x1aa5
4105 #define mmSPI_SHADER_PGM_HI_LS_HS_BASE_IDX                                                             0
4106 #define mmSPI_SHADER_PGM_RSRC3_HS                                                                      0x1aa7
4107 #define mmSPI_SHADER_PGM_RSRC3_HS_BASE_IDX                                                             0
4108 #define mmSPI_SHADER_PGM_LO_HS                                                                         0x1aa8
4109 #define mmSPI_SHADER_PGM_LO_HS_BASE_IDX                                                                0
4110 #define mmSPI_SHADER_PGM_HI_HS                                                                         0x1aa9
4111 #define mmSPI_SHADER_PGM_HI_HS_BASE_IDX                                                                0
4112 #define mmSPI_SHADER_PGM_RSRC1_HS                                                                      0x1aaa
4113 #define mmSPI_SHADER_PGM_RSRC1_HS_BASE_IDX                                                             0
4114 #define mmSPI_SHADER_PGM_RSRC2_HS                                                                      0x1aab
4115 #define mmSPI_SHADER_PGM_RSRC2_HS_BASE_IDX                                                             0
4116 #define mmSPI_SHADER_USER_DATA_HS_0                                                                    0x1aac
4117 #define mmSPI_SHADER_USER_DATA_HS_0_BASE_IDX                                                           0
4118 #define mmSPI_SHADER_USER_DATA_HS_1                                                                    0x1aad
4119 #define mmSPI_SHADER_USER_DATA_HS_1_BASE_IDX                                                           0
4120 #define mmSPI_SHADER_USER_DATA_HS_2                                                                    0x1aae
4121 #define mmSPI_SHADER_USER_DATA_HS_2_BASE_IDX                                                           0
4122 #define mmSPI_SHADER_USER_DATA_HS_3                                                                    0x1aaf
4123 #define mmSPI_SHADER_USER_DATA_HS_3_BASE_IDX                                                           0
4124 #define mmSPI_SHADER_USER_DATA_HS_4                                                                    0x1ab0
4125 #define mmSPI_SHADER_USER_DATA_HS_4_BASE_IDX                                                           0
4126 #define mmSPI_SHADER_USER_DATA_HS_5                                                                    0x1ab1
4127 #define mmSPI_SHADER_USER_DATA_HS_5_BASE_IDX                                                           0
4128 #define mmSPI_SHADER_USER_DATA_HS_6                                                                    0x1ab2
4129 #define mmSPI_SHADER_USER_DATA_HS_6_BASE_IDX                                                           0
4130 #define mmSPI_SHADER_USER_DATA_HS_7                                                                    0x1ab3
4131 #define mmSPI_SHADER_USER_DATA_HS_7_BASE_IDX                                                           0
4132 #define mmSPI_SHADER_USER_DATA_HS_8                                                                    0x1ab4
4133 #define mmSPI_SHADER_USER_DATA_HS_8_BASE_IDX                                                           0
4134 #define mmSPI_SHADER_USER_DATA_HS_9                                                                    0x1ab5
4135 #define mmSPI_SHADER_USER_DATA_HS_9_BASE_IDX                                                           0
4136 #define mmSPI_SHADER_USER_DATA_HS_10                                                                   0x1ab6
4137 #define mmSPI_SHADER_USER_DATA_HS_10_BASE_IDX                                                          0
4138 #define mmSPI_SHADER_USER_DATA_HS_11                                                                   0x1ab7
4139 #define mmSPI_SHADER_USER_DATA_HS_11_BASE_IDX                                                          0
4140 #define mmSPI_SHADER_USER_DATA_HS_12                                                                   0x1ab8
4141 #define mmSPI_SHADER_USER_DATA_HS_12_BASE_IDX                                                          0
4142 #define mmSPI_SHADER_USER_DATA_HS_13                                                                   0x1ab9
4143 #define mmSPI_SHADER_USER_DATA_HS_13_BASE_IDX                                                          0
4144 #define mmSPI_SHADER_USER_DATA_HS_14                                                                   0x1aba
4145 #define mmSPI_SHADER_USER_DATA_HS_14_BASE_IDX                                                          0
4146 #define mmSPI_SHADER_USER_DATA_HS_15                                                                   0x1abb
4147 #define mmSPI_SHADER_USER_DATA_HS_15_BASE_IDX                                                          0
4148 #define mmSPI_SHADER_USER_DATA_HS_16                                                                   0x1abc
4149 #define mmSPI_SHADER_USER_DATA_HS_16_BASE_IDX                                                          0
4150 #define mmSPI_SHADER_USER_DATA_HS_17                                                                   0x1abd
4151 #define mmSPI_SHADER_USER_DATA_HS_17_BASE_IDX                                                          0
4152 #define mmSPI_SHADER_USER_DATA_HS_18                                                                   0x1abe
4153 #define mmSPI_SHADER_USER_DATA_HS_18_BASE_IDX                                                          0
4154 #define mmSPI_SHADER_USER_DATA_HS_19                                                                   0x1abf
4155 #define mmSPI_SHADER_USER_DATA_HS_19_BASE_IDX                                                          0
4156 #define mmSPI_SHADER_USER_DATA_HS_20                                                                   0x1ac0
4157 #define mmSPI_SHADER_USER_DATA_HS_20_BASE_IDX                                                          0
4158 #define mmSPI_SHADER_USER_DATA_HS_21                                                                   0x1ac1
4159 #define mmSPI_SHADER_USER_DATA_HS_21_BASE_IDX                                                          0
4160 #define mmSPI_SHADER_USER_DATA_HS_22                                                                   0x1ac2
4161 #define mmSPI_SHADER_USER_DATA_HS_22_BASE_IDX                                                          0
4162 #define mmSPI_SHADER_USER_DATA_HS_23                                                                   0x1ac3
4163 #define mmSPI_SHADER_USER_DATA_HS_23_BASE_IDX                                                          0
4164 #define mmSPI_SHADER_USER_DATA_HS_24                                                                   0x1ac4
4165 #define mmSPI_SHADER_USER_DATA_HS_24_BASE_IDX                                                          0
4166 #define mmSPI_SHADER_USER_DATA_HS_25                                                                   0x1ac5
4167 #define mmSPI_SHADER_USER_DATA_HS_25_BASE_IDX                                                          0
4168 #define mmSPI_SHADER_USER_DATA_HS_26                                                                   0x1ac6
4169 #define mmSPI_SHADER_USER_DATA_HS_26_BASE_IDX                                                          0
4170 #define mmSPI_SHADER_USER_DATA_HS_27                                                                   0x1ac7
4171 #define mmSPI_SHADER_USER_DATA_HS_27_BASE_IDX                                                          0
4172 #define mmSPI_SHADER_USER_DATA_HS_28                                                                   0x1ac8
4173 #define mmSPI_SHADER_USER_DATA_HS_28_BASE_IDX                                                          0
4174 #define mmSPI_SHADER_USER_DATA_HS_29                                                                   0x1ac9
4175 #define mmSPI_SHADER_USER_DATA_HS_29_BASE_IDX                                                          0
4176 #define mmSPI_SHADER_USER_DATA_HS_30                                                                   0x1aca
4177 #define mmSPI_SHADER_USER_DATA_HS_30_BASE_IDX                                                          0
4178 #define mmSPI_SHADER_USER_DATA_HS_31                                                                   0x1acb
4179 #define mmSPI_SHADER_USER_DATA_HS_31_BASE_IDX                                                          0
4180 #define mmSPI_SHADER_REQ_CTRL_LSHS                                                                     0x1ad0
4181 #define mmSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX                                                            0
4182 #define mmSPI_SHADER_USER_ACCUM_LSHS_0                                                                 0x1ad2
4183 #define mmSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX                                                        0
4184 #define mmSPI_SHADER_USER_ACCUM_LSHS_1                                                                 0x1ad3
4185 #define mmSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX                                                        0
4186 #define mmSPI_SHADER_USER_ACCUM_LSHS_2                                                                 0x1ad4
4187 #define mmSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX                                                        0
4188 #define mmSPI_SHADER_USER_ACCUM_LSHS_3                                                                 0x1ad5
4189 #define mmSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX                                                        0
4190 #define mmSPI_SHADER_PGM_LO_LS                                                                         0x1ae8
4191 #define mmSPI_SHADER_PGM_LO_LS_BASE_IDX                                                                0
4192 #define mmSPI_SHADER_PGM_HI_LS                                                                         0x1ae9
4193 #define mmSPI_SHADER_PGM_HI_LS_BASE_IDX                                                                0
4194 #define mmCOMPUTE_DISPATCH_INITIATOR                                                                   0x1ba0
4195 #define mmCOMPUTE_DISPATCH_INITIATOR_BASE_IDX                                                          0
4196 #define mmCOMPUTE_DIM_X                                                                                0x1ba1
4197 #define mmCOMPUTE_DIM_X_BASE_IDX                                                                       0
4198 #define mmCOMPUTE_DIM_Y                                                                                0x1ba2
4199 #define mmCOMPUTE_DIM_Y_BASE_IDX                                                                       0
4200 #define mmCOMPUTE_DIM_Z                                                                                0x1ba3
4201 #define mmCOMPUTE_DIM_Z_BASE_IDX                                                                       0
4202 #define mmCOMPUTE_START_X                                                                              0x1ba4
4203 #define mmCOMPUTE_START_X_BASE_IDX                                                                     0
4204 #define mmCOMPUTE_START_Y                                                                              0x1ba5
4205 #define mmCOMPUTE_START_Y_BASE_IDX                                                                     0
4206 #define mmCOMPUTE_START_Z                                                                              0x1ba6
4207 #define mmCOMPUTE_START_Z_BASE_IDX                                                                     0
4208 #define mmCOMPUTE_NUM_THREAD_X                                                                         0x1ba7
4209 #define mmCOMPUTE_NUM_THREAD_X_BASE_IDX                                                                0
4210 #define mmCOMPUTE_NUM_THREAD_Y                                                                         0x1ba8
4211 #define mmCOMPUTE_NUM_THREAD_Y_BASE_IDX                                                                0
4212 #define mmCOMPUTE_NUM_THREAD_Z                                                                         0x1ba9
4213 #define mmCOMPUTE_NUM_THREAD_Z_BASE_IDX                                                                0
4214 #define mmCOMPUTE_PIPELINESTAT_ENABLE                                                                  0x1baa
4215 #define mmCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX                                                         0
4216 #define mmCOMPUTE_PERFCOUNT_ENABLE                                                                     0x1bab
4217 #define mmCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX                                                            0
4218 #define mmCOMPUTE_PGM_LO                                                                               0x1bac
4219 #define mmCOMPUTE_PGM_LO_BASE_IDX                                                                      0
4220 #define mmCOMPUTE_PGM_HI                                                                               0x1bad
4221 #define mmCOMPUTE_PGM_HI_BASE_IDX                                                                      0
4222 #define mmCOMPUTE_DISPATCH_PKT_ADDR_LO                                                                 0x1bae
4223 #define mmCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX                                                        0
4224 #define mmCOMPUTE_DISPATCH_PKT_ADDR_HI                                                                 0x1baf
4225 #define mmCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX                                                        0
4226 #define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO                                                             0x1bb0
4227 #define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX                                                    0
4228 #define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI                                                             0x1bb1
4229 #define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX                                                    0
4230 #define mmCOMPUTE_PGM_RSRC1                                                                            0x1bb2
4231 #define mmCOMPUTE_PGM_RSRC1_BASE_IDX                                                                   0
4232 #define mmCOMPUTE_PGM_RSRC2                                                                            0x1bb3
4233 #define mmCOMPUTE_PGM_RSRC2_BASE_IDX                                                                   0
4234 #define mmCOMPUTE_VMID                                                                                 0x1bb4
4235 #define mmCOMPUTE_VMID_BASE_IDX                                                                        0
4236 #define mmCOMPUTE_RESOURCE_LIMITS                                                                      0x1bb5
4237 #define mmCOMPUTE_RESOURCE_LIMITS_BASE_IDX                                                             0
4238 #define mmCOMPUTE_DESTINATION_EN_SE0                                                                   0x1bb6
4239 #define mmCOMPUTE_DESTINATION_EN_SE0_BASE_IDX                                                          0
4240 #define mmCOMPUTE_STATIC_THREAD_MGMT_SE0                                                               0x1bb6
4241 #define mmCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX                                                      0
4242 #define mmCOMPUTE_DESTINATION_EN_SE1                                                                   0x1bb7
4243 #define mmCOMPUTE_DESTINATION_EN_SE1_BASE_IDX                                                          0
4244 #define mmCOMPUTE_STATIC_THREAD_MGMT_SE1                                                               0x1bb7
4245 #define mmCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX                                                      0
4246 #define mmCOMPUTE_TMPRING_SIZE                                                                         0x1bb8
4247 #define mmCOMPUTE_TMPRING_SIZE_BASE_IDX                                                                0
4248 #define mmCOMPUTE_DESTINATION_EN_SE2                                                                   0x1bb9
4249 #define mmCOMPUTE_DESTINATION_EN_SE2_BASE_IDX                                                          0
4250 #define mmCOMPUTE_STATIC_THREAD_MGMT_SE2                                                               0x1bb9
4251 #define mmCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX                                                      0
4252 #define mmCOMPUTE_DESTINATION_EN_SE3                                                                   0x1bba
4253 #define mmCOMPUTE_DESTINATION_EN_SE3_BASE_IDX                                                          0
4254 #define mmCOMPUTE_STATIC_THREAD_MGMT_SE3                                                               0x1bba
4255 #define mmCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX                                                      0
4256 #define mmCOMPUTE_RESTART_X                                                                            0x1bbb
4257 #define mmCOMPUTE_RESTART_X_BASE_IDX                                                                   0
4258 #define mmCOMPUTE_RESTART_Y                                                                            0x1bbc
4259 #define mmCOMPUTE_RESTART_Y_BASE_IDX                                                                   0
4260 #define mmCOMPUTE_RESTART_Z                                                                            0x1bbd
4261 #define mmCOMPUTE_RESTART_Z_BASE_IDX                                                                   0
4262 #define mmCOMPUTE_THREAD_TRACE_ENABLE                                                                  0x1bbe
4263 #define mmCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX                                                         0
4264 #define mmCOMPUTE_MISC_RESERVED                                                                        0x1bbf
4265 #define mmCOMPUTE_MISC_RESERVED_BASE_IDX                                                               0
4266 #define mmCOMPUTE_DISPATCH_ID                                                                          0x1bc0
4267 #define mmCOMPUTE_DISPATCH_ID_BASE_IDX                                                                 0
4268 #define mmCOMPUTE_THREADGROUP_ID                                                                       0x1bc1
4269 #define mmCOMPUTE_THREADGROUP_ID_BASE_IDX                                                              0
4270 #define mmCOMPUTE_REQ_CTRL                                                                             0x1bc2
4271 #define mmCOMPUTE_REQ_CTRL_BASE_IDX                                                                    0
4272 #define mmCOMPUTE_USER_ACCUM_0                                                                         0x1bc4
4273 #define mmCOMPUTE_USER_ACCUM_0_BASE_IDX                                                                0
4274 #define mmCOMPUTE_USER_ACCUM_1                                                                         0x1bc5
4275 #define mmCOMPUTE_USER_ACCUM_1_BASE_IDX                                                                0
4276 #define mmCOMPUTE_USER_ACCUM_2                                                                         0x1bc6
4277 #define mmCOMPUTE_USER_ACCUM_2_BASE_IDX                                                                0
4278 #define mmCOMPUTE_USER_ACCUM_3                                                                         0x1bc7
4279 #define mmCOMPUTE_USER_ACCUM_3_BASE_IDX                                                                0
4280 #define mmCOMPUTE_PGM_RSRC3                                                                            0x1bc8
4281 #define mmCOMPUTE_PGM_RSRC3_BASE_IDX                                                                   0
4282 #define mmCOMPUTE_DDID_INDEX                                                                           0x1bc9
4283 #define mmCOMPUTE_DDID_INDEX_BASE_IDX                                                                  0
4284 #define mmCOMPUTE_SHADER_CHKSUM                                                                        0x1bca
4285 #define mmCOMPUTE_SHADER_CHKSUM_BASE_IDX                                                               0
4286 #define mmCOMPUTE_RELAUNCH                                                                             0x1bcb
4287 #define mmCOMPUTE_RELAUNCH_BASE_IDX                                                                    0
4288 #define mmCOMPUTE_WAVE_RESTORE_ADDR_LO                                                                 0x1bcc
4289 #define mmCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX                                                        0
4290 #define mmCOMPUTE_WAVE_RESTORE_ADDR_HI                                                                 0x1bcd
4291 #define mmCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX                                                        0
4292 #define mmCOMPUTE_RELAUNCH2                                                                            0x1bce
4293 #define mmCOMPUTE_RELAUNCH2_BASE_IDX                                                                   0
4294 #define mmCOMPUTE_USER_DATA_0                                                                          0x1be0
4295 #define mmCOMPUTE_USER_DATA_0_BASE_IDX                                                                 0
4296 #define mmCOMPUTE_USER_DATA_1                                                                          0x1be1
4297 #define mmCOMPUTE_USER_DATA_1_BASE_IDX                                                                 0
4298 #define mmCOMPUTE_USER_DATA_2                                                                          0x1be2
4299 #define mmCOMPUTE_USER_DATA_2_BASE_IDX                                                                 0
4300 #define mmCOMPUTE_USER_DATA_3                                                                          0x1be3
4301 #define mmCOMPUTE_USER_DATA_3_BASE_IDX                                                                 0
4302 #define mmCOMPUTE_USER_DATA_4                                                                          0x1be4
4303 #define mmCOMPUTE_USER_DATA_4_BASE_IDX                                                                 0
4304 #define mmCOMPUTE_USER_DATA_5                                                                          0x1be5
4305 #define mmCOMPUTE_USER_DATA_5_BASE_IDX                                                                 0
4306 #define mmCOMPUTE_USER_DATA_6                                                                          0x1be6
4307 #define mmCOMPUTE_USER_DATA_6_BASE_IDX                                                                 0
4308 #define mmCOMPUTE_USER_DATA_7                                                                          0x1be7
4309 #define mmCOMPUTE_USER_DATA_7_BASE_IDX                                                                 0
4310 #define mmCOMPUTE_USER_DATA_8                                                                          0x1be8
4311 #define mmCOMPUTE_USER_DATA_8_BASE_IDX                                                                 0
4312 #define mmCOMPUTE_USER_DATA_9                                                                          0x1be9
4313 #define mmCOMPUTE_USER_DATA_9_BASE_IDX                                                                 0
4314 #define mmCOMPUTE_USER_DATA_10                                                                         0x1bea
4315 #define mmCOMPUTE_USER_DATA_10_BASE_IDX                                                                0
4316 #define mmCOMPUTE_USER_DATA_11                                                                         0x1beb
4317 #define mmCOMPUTE_USER_DATA_11_BASE_IDX                                                                0
4318 #define mmCOMPUTE_USER_DATA_12                                                                         0x1bec
4319 #define mmCOMPUTE_USER_DATA_12_BASE_IDX                                                                0
4320 #define mmCOMPUTE_USER_DATA_13                                                                         0x1bed
4321 #define mmCOMPUTE_USER_DATA_13_BASE_IDX                                                                0
4322 #define mmCOMPUTE_USER_DATA_14                                                                         0x1bee
4323 #define mmCOMPUTE_USER_DATA_14_BASE_IDX                                                                0
4324 #define mmCOMPUTE_USER_DATA_15                                                                         0x1bef
4325 #define mmCOMPUTE_USER_DATA_15_BASE_IDX                                                                0
4326 #define mmCOMPUTE_DISPATCH_TUNNEL                                                                      0x1c1d
4327 #define mmCOMPUTE_DISPATCH_TUNNEL_BASE_IDX                                                             0
4328 #define mmCOMPUTE_DISPATCH_END                                                                         0x1c1e
4329 #define mmCOMPUTE_DISPATCH_END_BASE_IDX                                                                0
4330 #define mmCOMPUTE_NOWHERE                                                                              0x1c1f
4331 #define mmCOMPUTE_NOWHERE_BASE_IDX                                                                     0
4332 #define mmSH_RESERVED_REG0                                                                             0x1c20
4333 #define mmSH_RESERVED_REG0_BASE_IDX                                                                    0
4334 #define mmSH_RESERVED_REG1                                                                             0x1c21
4335 #define mmSH_RESERVED_REG1_BASE_IDX                                                                    0
4336 
4337 
4338 // addressBlock: gc_cppdec
4339 // base address: 0xc080
4340 #define mmCP_EOPQ_WAIT_TIME                                                                            0x1dd5
4341 #define mmCP_EOPQ_WAIT_TIME_BASE_IDX                                                                   0
4342 #define mmCP_CPC_MGCG_SYNC_CNTL                                                                        0x1dd6
4343 #define mmCP_CPC_MGCG_SYNC_CNTL_BASE_IDX                                                               0
4344 #define mmCPC_INT_INFO                                                                                 0x1dd7
4345 #define mmCPC_INT_INFO_BASE_IDX                                                                        0
4346 #define mmCP_VIRT_STATUS                                                                               0x1dd8
4347 #define mmCP_VIRT_STATUS_BASE_IDX                                                                      0
4348 #define mmCPC_INT_ADDR                                                                                 0x1dd9
4349 #define mmCPC_INT_ADDR_BASE_IDX                                                                        0
4350 #define mmCPC_INT_PASID                                                                                0x1dda
4351 #define mmCPC_INT_PASID_BASE_IDX                                                                       0
4352 #define mmCP_GFX_ERROR                                                                                 0x1ddb
4353 #define mmCP_GFX_ERROR_BASE_IDX                                                                        0
4354 #define mmCPG_UTCL1_CNTL                                                                               0x1ddc
4355 #define mmCPG_UTCL1_CNTL_BASE_IDX                                                                      0
4356 #define mmCPC_UTCL1_CNTL                                                                               0x1ddd
4357 #define mmCPC_UTCL1_CNTL_BASE_IDX                                                                      0
4358 #define mmCPF_UTCL1_CNTL                                                                               0x1dde
4359 #define mmCPF_UTCL1_CNTL_BASE_IDX                                                                      0
4360 #define mmCP_AQL_SMM_STATUS                                                                            0x1ddf
4361 #define mmCP_AQL_SMM_STATUS_BASE_IDX                                                                   0
4362 #define mmCP_RB0_BASE                                                                                  0x1de0
4363 #define mmCP_RB0_BASE_BASE_IDX                                                                         0
4364 #define mmCP_RB_BASE                                                                                   0x1de0
4365 #define mmCP_RB_BASE_BASE_IDX                                                                          0
4366 #define mmCP_RB0_CNTL                                                                                  0x1de1
4367 #define mmCP_RB0_CNTL_BASE_IDX                                                                         0
4368 #define mmCP_RB_CNTL                                                                                   0x1de1
4369 #define mmCP_RB_CNTL_BASE_IDX                                                                          0
4370 #define mmCP_RB_RPTR_WR                                                                                0x1de2
4371 #define mmCP_RB_RPTR_WR_BASE_IDX                                                                       0
4372 #define mmCP_RB0_RPTR_ADDR                                                                             0x1de3
4373 #define mmCP_RB0_RPTR_ADDR_BASE_IDX                                                                    0
4374 #define mmCP_RB_RPTR_ADDR                                                                              0x1de3
4375 #define mmCP_RB_RPTR_ADDR_BASE_IDX                                                                     0
4376 #define mmCP_RB0_RPTR_ADDR_HI                                                                          0x1de4
4377 #define mmCP_RB0_RPTR_ADDR_HI_BASE_IDX                                                                 0
4378 #define mmCP_RB_RPTR_ADDR_HI                                                                           0x1de4
4379 #define mmCP_RB_RPTR_ADDR_HI_BASE_IDX                                                                  0
4380 #define mmCP_RB0_BUFSZ_MASK                                                                            0x1de5
4381 #define mmCP_RB0_BUFSZ_MASK_BASE_IDX                                                                   0
4382 #define mmCP_RB_BUFSZ_MASK                                                                             0x1de5
4383 #define mmCP_RB_BUFSZ_MASK_BASE_IDX                                                                    0
4384 #define mmCP_INT_CNTL                                                                                  0x1de9
4385 #define mmCP_INT_CNTL_BASE_IDX                                                                         0
4386 #define mmCP_INT_STATUS                                                                                0x1dea
4387 #define mmCP_INT_STATUS_BASE_IDX                                                                       0
4388 #define mmCP_DEVICE_ID                                                                                 0x1deb
4389 #define mmCP_DEVICE_ID_BASE_IDX                                                                        0
4390 #define mmCP_ME0_PIPE_PRIORITY_CNTS                                                                    0x1dec
4391 #define mmCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX                                                           0
4392 #define mmCP_RING_PRIORITY_CNTS                                                                        0x1dec
4393 #define mmCP_RING_PRIORITY_CNTS_BASE_IDX                                                               0
4394 #define mmCP_ME0_PIPE0_PRIORITY                                                                        0x1ded
4395 #define mmCP_ME0_PIPE0_PRIORITY_BASE_IDX                                                               0
4396 #define mmCP_RING0_PRIORITY                                                                            0x1ded
4397 #define mmCP_RING0_PRIORITY_BASE_IDX                                                                   0
4398 #define mmCP_ME0_PIPE1_PRIORITY                                                                        0x1dee
4399 #define mmCP_ME0_PIPE1_PRIORITY_BASE_IDX                                                               0
4400 #define mmCP_RING1_PRIORITY                                                                            0x1dee
4401 #define mmCP_RING1_PRIORITY_BASE_IDX                                                                   0
4402 #define mmCP_ME0_PIPE2_PRIORITY                                                                        0x1def
4403 #define mmCP_ME0_PIPE2_PRIORITY_BASE_IDX                                                               0
4404 #define mmCP_RING2_PRIORITY                                                                            0x1def
4405 #define mmCP_RING2_PRIORITY_BASE_IDX                                                                   0
4406 #define mmCP_FATAL_ERROR                                                                               0x1df0
4407 #define mmCP_FATAL_ERROR_BASE_IDX                                                                      0
4408 #define mmCP_RB_VMID                                                                                   0x1df1
4409 #define mmCP_RB_VMID_BASE_IDX                                                                          0
4410 #define mmCP_ME0_PIPE0_VMID                                                                            0x1df2
4411 #define mmCP_ME0_PIPE0_VMID_BASE_IDX                                                                   0
4412 #define mmCP_ME0_PIPE1_VMID                                                                            0x1df3
4413 #define mmCP_ME0_PIPE1_VMID_BASE_IDX                                                                   0
4414 #define mmCP_RB0_WPTR                                                                                  0x1df4
4415 #define mmCP_RB0_WPTR_BASE_IDX                                                                         0
4416 #define mmCP_RB_WPTR                                                                                   0x1df4
4417 #define mmCP_RB_WPTR_BASE_IDX                                                                          0
4418 #define mmCP_RB0_WPTR_HI                                                                               0x1df5
4419 #define mmCP_RB0_WPTR_HI_BASE_IDX                                                                      0
4420 #define mmCP_RB_WPTR_HI                                                                                0x1df5
4421 #define mmCP_RB_WPTR_HI_BASE_IDX                                                                       0
4422 #define mmCP_RB1_WPTR                                                                                  0x1df6
4423 #define mmCP_RB1_WPTR_BASE_IDX                                                                         0
4424 #define mmCP_RB1_WPTR_HI                                                                               0x1df7
4425 #define mmCP_RB1_WPTR_HI_BASE_IDX                                                                      0
4426 #define mmCP_RB2_WPTR                                                                                  0x1df8
4427 #define mmCP_RB2_WPTR_BASE_IDX                                                                         0
4428 #define mmCP_PROCESS_QUANTUM                                                                           0x1df9
4429 #define mmCP_PROCESS_QUANTUM_BASE_IDX                                                                  0
4430 #define mmCP_RB_DOORBELL_RANGE_LOWER                                                                   0x1dfa
4431 #define mmCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX                                                          0
4432 #define mmCP_RB_DOORBELL_RANGE_UPPER                                                                   0x1dfb
4433 #define mmCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX                                                          0
4434 #define mmCP_MEC_DOORBELL_RANGE_LOWER                                                                  0x1dfc
4435 #define mmCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX                                                         0
4436 #define mmCP_MEC_DOORBELL_RANGE_UPPER                                                                  0x1dfd
4437 #define mmCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX                                                         0
4438 #define mmCPG_UTCL1_ERROR                                                                              0x1dfe
4439 #define mmCPG_UTCL1_ERROR_BASE_IDX                                                                     0
4440 #define mmCPC_UTCL1_ERROR                                                                              0x1dff
4441 #define mmCPC_UTCL1_ERROR_BASE_IDX                                                                     0
4442 #define mmCP_RB1_BASE                                                                                  0x1e00
4443 #define mmCP_RB1_BASE_BASE_IDX                                                                         0
4444 #define mmCP_RB1_CNTL                                                                                  0x1e01
4445 #define mmCP_RB1_CNTL_BASE_IDX                                                                         0
4446 #define mmCP_RB1_RPTR_ADDR                                                                             0x1e02
4447 #define mmCP_RB1_RPTR_ADDR_BASE_IDX                                                                    0
4448 #define mmCP_RB1_RPTR_ADDR_HI                                                                          0x1e03
4449 #define mmCP_RB1_RPTR_ADDR_HI_BASE_IDX                                                                 0
4450 #define mmCP_RB1_BUFSZ_MASK                                                                            0x1e04
4451 #define mmCP_RB1_BUFSZ_MASK_BASE_IDX                                                                   0
4452 #define mmCP_RB2_BASE                                                                                  0x1e05
4453 #define mmCP_RB2_BASE_BASE_IDX                                                                         0
4454 #define mmCP_RB2_CNTL                                                                                  0x1e06
4455 #define mmCP_RB2_CNTL_BASE_IDX                                                                         0
4456 #define mmCP_RB2_RPTR_ADDR                                                                             0x1e07
4457 #define mmCP_RB2_RPTR_ADDR_BASE_IDX                                                                    0
4458 #define mmCP_RB2_RPTR_ADDR_HI                                                                          0x1e08
4459 #define mmCP_RB2_RPTR_ADDR_HI_BASE_IDX                                                                 0
4460 #define mmCP_INT_CNTL_RING0                                                                            0x1e0a
4461 #define mmCP_INT_CNTL_RING0_BASE_IDX                                                                   0
4462 #define mmCP_INT_CNTL_RING1                                                                            0x1e0b
4463 #define mmCP_INT_CNTL_RING1_BASE_IDX                                                                   0
4464 #define mmCP_INT_CNTL_RING2                                                                            0x1e0c
4465 #define mmCP_INT_CNTL_RING2_BASE_IDX                                                                   0
4466 #define mmCP_INT_STATUS_RING0                                                                          0x1e0d
4467 #define mmCP_INT_STATUS_RING0_BASE_IDX                                                                 0
4468 #define mmCP_INT_STATUS_RING1                                                                          0x1e0e
4469 #define mmCP_INT_STATUS_RING1_BASE_IDX                                                                 0
4470 #define mmCP_INT_STATUS_RING2                                                                          0x1e0f
4471 #define mmCP_INT_STATUS_RING2_BASE_IDX                                                                 0
4472 #define mmCP_ME_F32_INTERRUPT                                                                          0x1e13
4473 #define mmCP_ME_F32_INTERRUPT_BASE_IDX                                                                 0
4474 #define mmCP_PFP_F32_INTERRUPT                                                                         0x1e14
4475 #define mmCP_PFP_F32_INTERRUPT_BASE_IDX                                                                0
4476 #define mmCP_CE_F32_INTERRUPT                                                                          0x1e15
4477 #define mmCP_CE_F32_INTERRUPT_BASE_IDX                                                                 0
4478 #define mmCP_MEC1_F32_INTERRUPT                                                                        0x1e16
4479 #define mmCP_MEC1_F32_INTERRUPT_BASE_IDX                                                               0
4480 #define mmCP_MEC2_F32_INTERRUPT                                                                        0x1e17
4481 #define mmCP_MEC2_F32_INTERRUPT_BASE_IDX                                                               0
4482 #define mmCP_PWR_CNTL                                                                                  0x1e18
4483 #define mmCP_PWR_CNTL_BASE_IDX                                                                         0
4484 #define mmCP_MEM_SLP_CNTL                                                                              0x1e19
4485 #define mmCP_MEM_SLP_CNTL_BASE_IDX                                                                     0
4486 #define mmCP_ECC_FIRSTOCCURRENCE                                                                       0x1e1a
4487 #define mmCP_ECC_FIRSTOCCURRENCE_BASE_IDX                                                              0
4488 #define mmCP_ECC_FIRSTOCCURRENCE_RING0                                                                 0x1e1b
4489 #define mmCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX                                                        0
4490 #define mmCP_ECC_FIRSTOCCURRENCE_RING1                                                                 0x1e1c
4491 #define mmCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX                                                        0
4492 #define mmCP_ECC_FIRSTOCCURRENCE_RING2                                                                 0x1e1d
4493 #define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX                                                        0
4494 #define mmGB_EDC_MODE                                                                                  0x1e1e
4495 #define mmGB_EDC_MODE_BASE_IDX                                                                         0
4496 #define mmCP_PQ_WPTR_POLL_CNTL                                                                         0x1e23
4497 #define mmCP_PQ_WPTR_POLL_CNTL_BASE_IDX                                                                0
4498 #define mmCP_PQ_WPTR_POLL_CNTL1                                                                        0x1e24
4499 #define mmCP_PQ_WPTR_POLL_CNTL1_BASE_IDX                                                               0
4500 #define mmCP_ME1_PIPE0_INT_CNTL                                                                        0x1e25
4501 #define mmCP_ME1_PIPE0_INT_CNTL_BASE_IDX                                                               0
4502 #define mmCP_ME1_PIPE1_INT_CNTL                                                                        0x1e26
4503 #define mmCP_ME1_PIPE1_INT_CNTL_BASE_IDX                                                               0
4504 #define mmCP_ME1_PIPE2_INT_CNTL                                                                        0x1e27
4505 #define mmCP_ME1_PIPE2_INT_CNTL_BASE_IDX                                                               0
4506 #define mmCP_ME1_PIPE3_INT_CNTL                                                                        0x1e28
4507 #define mmCP_ME1_PIPE3_INT_CNTL_BASE_IDX                                                               0
4508 #define mmCP_ME2_PIPE0_INT_CNTL                                                                        0x1e29
4509 #define mmCP_ME2_PIPE0_INT_CNTL_BASE_IDX                                                               0
4510 #define mmCP_ME2_PIPE1_INT_CNTL                                                                        0x1e2a
4511 #define mmCP_ME2_PIPE1_INT_CNTL_BASE_IDX                                                               0
4512 #define mmCP_ME2_PIPE2_INT_CNTL                                                                        0x1e2b
4513 #define mmCP_ME2_PIPE2_INT_CNTL_BASE_IDX                                                               0
4514 #define mmCP_ME2_PIPE3_INT_CNTL                                                                        0x1e2c
4515 #define mmCP_ME2_PIPE3_INT_CNTL_BASE_IDX                                                               0
4516 #define mmCP_ME1_PIPE0_INT_STATUS                                                                      0x1e2d
4517 #define mmCP_ME1_PIPE0_INT_STATUS_BASE_IDX                                                             0
4518 #define mmCP_ME1_PIPE1_INT_STATUS                                                                      0x1e2e
4519 #define mmCP_ME1_PIPE1_INT_STATUS_BASE_IDX                                                             0
4520 #define mmCP_ME1_PIPE2_INT_STATUS                                                                      0x1e2f
4521 #define mmCP_ME1_PIPE2_INT_STATUS_BASE_IDX                                                             0
4522 #define mmCP_ME1_PIPE3_INT_STATUS                                                                      0x1e30
4523 #define mmCP_ME1_PIPE3_INT_STATUS_BASE_IDX                                                             0
4524 #define mmCP_ME2_PIPE0_INT_STATUS                                                                      0x1e31
4525 #define mmCP_ME2_PIPE0_INT_STATUS_BASE_IDX                                                             0
4526 #define mmCP_ME2_PIPE1_INT_STATUS                                                                      0x1e32
4527 #define mmCP_ME2_PIPE1_INT_STATUS_BASE_IDX                                                             0
4528 #define mmCP_ME2_PIPE2_INT_STATUS                                                                      0x1e33
4529 #define mmCP_ME2_PIPE2_INT_STATUS_BASE_IDX                                                             0
4530 #define mmCP_ME2_PIPE3_INT_STATUS                                                                      0x1e34
4531 #define mmCP_ME2_PIPE3_INT_STATUS_BASE_IDX                                                             0
4532 #define mmCP_GFX_QUEUE_INDEX                                                                           0x1e37
4533 #define mmCP_GFX_QUEUE_INDEX_BASE_IDX                                                                  0
4534 #define mmCC_GC_EDC_CONFIG                                                                             0x1e38
4535 #define mmCC_GC_EDC_CONFIG_BASE_IDX                                                                    0
4536 #define mmCP_ME1_INT_STAT_DEBUG                                                                        0x1e35
4537 #define mmCP_ME1_INT_STAT_DEBUG_BASE_IDX                                                               0
4538 #define mmCP_ME2_INT_STAT_DEBUG                                                                        0x1e36
4539 #define mmCP_ME2_INT_STAT_DEBUG_BASE_IDX                                                               0
4540 #define mmCP_ME1_PIPE_PRIORITY_CNTS                                                                    0x1e39
4541 #define mmCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX                                                           0
4542 #define mmCP_ME1_PIPE0_PRIORITY                                                                        0x1e3a
4543 #define mmCP_ME1_PIPE0_PRIORITY_BASE_IDX                                                               0
4544 #define mmCP_ME1_PIPE1_PRIORITY                                                                        0x1e3b
4545 #define mmCP_ME1_PIPE1_PRIORITY_BASE_IDX                                                               0
4546 #define mmCP_ME1_PIPE2_PRIORITY                                                                        0x1e3c
4547 #define mmCP_ME1_PIPE2_PRIORITY_BASE_IDX                                                               0
4548 #define mmCP_ME1_PIPE3_PRIORITY                                                                        0x1e3d
4549 #define mmCP_ME1_PIPE3_PRIORITY_BASE_IDX                                                               0
4550 #define mmCP_ME2_PIPE_PRIORITY_CNTS                                                                    0x1e3e
4551 #define mmCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX                                                           0
4552 #define mmCP_ME2_PIPE0_PRIORITY                                                                        0x1e3f
4553 #define mmCP_ME2_PIPE0_PRIORITY_BASE_IDX                                                               0
4554 #define mmCP_ME2_PIPE1_PRIORITY                                                                        0x1e40
4555 #define mmCP_ME2_PIPE1_PRIORITY_BASE_IDX                                                               0
4556 #define mmCP_ME2_PIPE2_PRIORITY                                                                        0x1e41
4557 #define mmCP_ME2_PIPE2_PRIORITY_BASE_IDX                                                               0
4558 #define mmCP_ME2_PIPE3_PRIORITY                                                                        0x1e42
4559 #define mmCP_ME2_PIPE3_PRIORITY_BASE_IDX                                                               0
4560 #define mmCP_CE_PRGRM_CNTR_START                                                                       0x1e43
4561 #define mmCP_CE_PRGRM_CNTR_START_BASE_IDX                                                              0
4562 #define mmCP_PFP_PRGRM_CNTR_START                                                                      0x1e44
4563 #define mmCP_PFP_PRGRM_CNTR_START_BASE_IDX                                                             0
4564 #define mmCP_ME_PRGRM_CNTR_START                                                                       0x1e45
4565 #define mmCP_ME_PRGRM_CNTR_START_BASE_IDX                                                              0
4566 #define mmCP_MEC1_PRGRM_CNTR_START                                                                     0x1e46
4567 #define mmCP_MEC1_PRGRM_CNTR_START_BASE_IDX                                                            0
4568 #define mmCP_MEC2_PRGRM_CNTR_START                                                                     0x1e47
4569 #define mmCP_MEC2_PRGRM_CNTR_START_BASE_IDX                                                            0
4570 #define mmCP_CE_INTR_ROUTINE_START                                                                     0x1e48
4571 #define mmCP_CE_INTR_ROUTINE_START_BASE_IDX                                                            0
4572 #define mmCP_PFP_INTR_ROUTINE_START                                                                    0x1e49
4573 #define mmCP_PFP_INTR_ROUTINE_START_BASE_IDX                                                           0
4574 #define mmCP_ME_INTR_ROUTINE_START                                                                     0x1e4a
4575 #define mmCP_ME_INTR_ROUTINE_START_BASE_IDX                                                            0
4576 #define mmCP_MEC1_INTR_ROUTINE_START                                                                   0x1e4b
4577 #define mmCP_MEC1_INTR_ROUTINE_START_BASE_IDX                                                          0
4578 #define mmCP_MEC2_INTR_ROUTINE_START                                                                   0x1e4c
4579 #define mmCP_MEC2_INTR_ROUTINE_START_BASE_IDX                                                          0
4580 #define mmCP_CONTEXT_CNTL                                                                              0x1e4d
4581 #define mmCP_CONTEXT_CNTL_BASE_IDX                                                                     0
4582 #define mmCP_MAX_CONTEXT                                                                               0x1e4e
4583 #define mmCP_MAX_CONTEXT_BASE_IDX                                                                      0
4584 #define mmCP_IQ_WAIT_TIME1                                                                             0x1e4f
4585 #define mmCP_IQ_WAIT_TIME1_BASE_IDX                                                                    0
4586 #define mmCP_IQ_WAIT_TIME2                                                                             0x1e50
4587 #define mmCP_IQ_WAIT_TIME2_BASE_IDX                                                                    0
4588 #define mmCP_RB0_BASE_HI                                                                               0x1e51
4589 #define mmCP_RB0_BASE_HI_BASE_IDX                                                                      0
4590 #define mmCP_RB1_BASE_HI                                                                               0x1e52
4591 #define mmCP_RB1_BASE_HI_BASE_IDX                                                                      0
4592 #define mmCP_VMID_RESET                                                                                0x1e53
4593 #define mmCP_VMID_RESET_BASE_IDX                                                                       0
4594 #define mmCPC_INT_CNTL                                                                                 0x1e54
4595 #define mmCPC_INT_CNTL_BASE_IDX                                                                        0
4596 #define mmCPC_INT_STATUS                                                                               0x1e55
4597 #define mmCPC_INT_STATUS_BASE_IDX                                                                      0
4598 #define mmCP_VMID_PREEMPT                                                                              0x1e56
4599 #define mmCP_VMID_PREEMPT_BASE_IDX                                                                     0
4600 #define mmCPC_INT_CNTX_ID                                                                              0x1e57
4601 #define mmCPC_INT_CNTX_ID_BASE_IDX                                                                     0
4602 #define mmCP_PQ_STATUS                                                                                 0x1e58
4603 #define mmCP_PQ_STATUS_BASE_IDX                                                                        0
4604 #define mmCP_MEC1_F32_INT_DIS                                                                          0x1e5d
4605 #define mmCP_MEC1_F32_INT_DIS_BASE_IDX                                                                 0
4606 #define mmCP_MEC2_F32_INT_DIS                                                                          0x1e5e
4607 #define mmCP_MEC2_F32_INT_DIS_BASE_IDX                                                                 0
4608 #define mmCP_VMID_STATUS                                                                               0x1e5f
4609 #define mmCP_VMID_STATUS_BASE_IDX                                                                      0
4610 #define mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO                                                            0x1e60
4611 #define mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX                                                   0
4612 #define mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI                                                            0x1e61
4613 #define mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX                                                   0
4614 #define mmCPC_SUSPEND_CTX_SAVE_CONTROL                                                                 0x1e62
4615 #define mmCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX                                                        0
4616 #define mmCPC_SUSPEND_CNTL_STACK_OFFSET                                                                0x1e63
4617 #define mmCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX                                                       0
4618 #define mmCPC_SUSPEND_CNTL_STACK_SIZE                                                                  0x1e64
4619 #define mmCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX                                                         0
4620 #define mmCPC_SUSPEND_WG_STATE_OFFSET                                                                  0x1e65
4621 #define mmCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX                                                         0
4622 #define mmCPC_SUSPEND_CTX_SAVE_SIZE                                                                    0x1e66
4623 #define mmCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX                                                           0
4624 #define mmCPC_OS_PIPES                                                                                 0x1e67
4625 #define mmCPC_OS_PIPES_BASE_IDX                                                                        0
4626 #define mmCP_SUSPEND_RESUME_REQ                                                                        0x1e68
4627 #define mmCP_SUSPEND_RESUME_REQ_BASE_IDX                                                               0
4628 #define mmCP_SUSPEND_CNTL                                                                              0x1e69
4629 #define mmCP_SUSPEND_CNTL_BASE_IDX                                                                     0
4630 #define mmCP_IQ_WAIT_TIME3                                                                             0x1e6a
4631 #define mmCP_IQ_WAIT_TIME3_BASE_IDX                                                                    0
4632 #define mmCPC_DDID_BASE_ADDR_LO                                                                        0x1e6b
4633 #define mmCPC_DDID_BASE_ADDR_LO_BASE_IDX                                                               0
4634 #define mmCP_DDID_BASE_ADDR_LO                                                                         0x1e6b
4635 #define mmCP_DDID_BASE_ADDR_LO_BASE_IDX                                                                0
4636 #define mmCPC_DDID_BASE_ADDR_HI                                                                        0x1e6c
4637 #define mmCPC_DDID_BASE_ADDR_HI_BASE_IDX                                                               0
4638 #define mmCP_DDID_BASE_ADDR_HI                                                                         0x1e6c
4639 #define mmCP_DDID_BASE_ADDR_HI_BASE_IDX                                                                0
4640 #define mmCPC_DDID_CNTL                                                                                0x1e6d
4641 #define mmCPC_DDID_CNTL_BASE_IDX                                                                       0
4642 #define mmCP_DDID_CNTL                                                                                 0x1e6d
4643 #define mmCP_DDID_CNTL_BASE_IDX                                                                        0
4644 #define mmCP_GFX_DDID_INFLIGHT_COUNT                                                                   0x1e6e
4645 #define mmCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX                                                          0
4646 #define mmCP_GFX_DDID_WPTR                                                                             0x1e6f
4647 #define mmCP_GFX_DDID_WPTR_BASE_IDX                                                                    0
4648 #define mmCP_GFX_DDID_RPTR                                                                             0x1e70
4649 #define mmCP_GFX_DDID_RPTR_BASE_IDX                                                                    0
4650 #define mmCP_GFX_DDID_DELTA_RPT_COUNT                                                                  0x1e71
4651 #define mmCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX                                                         0
4652 #define mmCP_GFX_HPD_STATUS0                                                                           0x1e72
4653 #define mmCP_GFX_HPD_STATUS0_BASE_IDX                                                                  0
4654 #define mmCP_GFX_HPD_CONTROL0                                                                          0x1e73
4655 #define mmCP_GFX_HPD_CONTROL0_BASE_IDX                                                                 0
4656 #define mmCP_GFX_HPD_OSPRE_FENCE_ADDR_LO                                                               0x1e74
4657 #define mmCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX                                                      0
4658 #define mmCP_GFX_HPD_OSPRE_FENCE_ADDR_HI                                                               0x1e75
4659 #define mmCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX                                                      0
4660 #define mmCP_GFX_HPD_OSPRE_FENCE_DATA_LO                                                               0x1e76
4661 #define mmCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX                                                      0
4662 #define mmCP_GFX_HPD_OSPRE_FENCE_DATA_HI                                                               0x1e77
4663 #define mmCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX                                                      0
4664 #define mmCP_GFX_INDEX_MUTEX                                                                           0x1e78
4665 #define mmCP_GFX_INDEX_MUTEX_BASE_IDX                                                                  0
4666 #define mmCP_GFX_MQD_BASE_ADDR                                                                         0x1e7e
4667 #define mmCP_GFX_MQD_BASE_ADDR_BASE_IDX                                                                0
4668 #define mmCP_GFX_MQD_BASE_ADDR_HI                                                                      0x1e7f
4669 #define mmCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX                                                             0
4670 #define mmCP_GFX_HQD_ACTIVE                                                                            0x1e80
4671 #define mmCP_GFX_HQD_ACTIVE_BASE_IDX                                                                   0
4672 #define mmCP_GFX_HQD_VMID                                                                              0x1e81
4673 #define mmCP_GFX_HQD_VMID_BASE_IDX                                                                     0
4674 #define mmCP_GFX_HQD_QUEUE_PRIORITY                                                                    0x1e84
4675 #define mmCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX                                                           0
4676 #define mmCP_GFX_HQD_QUANTUM                                                                           0x1e85
4677 #define mmCP_GFX_HQD_QUANTUM_BASE_IDX                                                                  0
4678 #define mmCP_GFX_HQD_BASE                                                                              0x1e86
4679 #define mmCP_GFX_HQD_BASE_BASE_IDX                                                                     0
4680 #define mmCP_GFX_HQD_BASE_HI                                                                           0x1e87
4681 #define mmCP_GFX_HQD_BASE_HI_BASE_IDX                                                                  0
4682 #define mmCP_GFX_HQD_RPTR                                                                              0x1e88
4683 #define mmCP_GFX_HQD_RPTR_BASE_IDX                                                                     0
4684 #define mmCP_GFX_HQD_RPTR_ADDR                                                                         0x1e89
4685 #define mmCP_GFX_HQD_RPTR_ADDR_BASE_IDX                                                                0
4686 #define mmCP_GFX_HQD_RPTR_ADDR_HI                                                                      0x1e8a
4687 #define mmCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX                                                             0
4688 #define mmCP_RB_WPTR_POLL_ADDR_LO                                                                      0x1e8b
4689 #define mmCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                             0
4690 #define mmCP_RB_WPTR_POLL_ADDR_HI                                                                      0x1e8c
4691 #define mmCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                             0
4692 #define mmCP_RB_DOORBELL_CONTROL                                                                       0x1e8d
4693 #define mmCP_RB_DOORBELL_CONTROL_BASE_IDX                                                              0
4694 #define mmCP_GFX_HQD_OFFSET                                                                            0x1e8e
4695 #define mmCP_GFX_HQD_OFFSET_BASE_IDX                                                                   0
4696 #define mmCP_GFX_HQD_CNTL                                                                              0x1e8f
4697 #define mmCP_GFX_HQD_CNTL_BASE_IDX                                                                     0
4698 #define mmCP_GFX_HQD_CSMD_RPTR                                                                         0x1e90
4699 #define mmCP_GFX_HQD_CSMD_RPTR_BASE_IDX                                                                0
4700 #define mmCP_GFX_HQD_WPTR                                                                              0x1e91
4701 #define mmCP_GFX_HQD_WPTR_BASE_IDX                                                                     0
4702 #define mmCP_GFX_HQD_WPTR_HI                                                                           0x1e92
4703 #define mmCP_GFX_HQD_WPTR_HI_BASE_IDX                                                                  0
4704 #define mmCP_GFX_HQD_DEQUEUE_REQUEST                                                                   0x1e93
4705 #define mmCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX                                                          0
4706 #define mmCP_GFX_HQD_MAPPED                                                                            0x1e94
4707 #define mmCP_GFX_HQD_MAPPED_BASE_IDX                                                                   0
4708 #define mmCP_GFX_HQD_QUE_MGR_CONTROL                                                                   0x1e95
4709 #define mmCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX                                                          0
4710 #define mmCP_GFX_HQD_HQ_STATUS0                                                                        0x1e98
4711 #define mmCP_GFX_HQD_HQ_STATUS0_BASE_IDX                                                               0
4712 #define mmCP_GFX_HQD_HQ_CONTROL0                                                                       0x1e99
4713 #define mmCP_GFX_HQD_HQ_CONTROL0_BASE_IDX                                                              0
4714 #define mmCP_GFX_MQD_CONTROL                                                                           0x1e9a
4715 #define mmCP_GFX_MQD_CONTROL_BASE_IDX                                                                  0
4716 #define mmCP_HQD_GFX_CONTROL                                                                           0x1e9f
4717 #define mmCP_HQD_GFX_CONTROL_BASE_IDX                                                                  0
4718 #define mmCP_HQD_GFX_STATUS                                                                            0x1ea0
4719 #define mmCP_HQD_GFX_STATUS_BASE_IDX                                                                   0
4720 #define mmCP_GFX_HQD_CE_RPTR_WR                                                                        0x1ea1
4721 #define mmCP_GFX_HQD_CE_RPTR_WR_BASE_IDX                                                               0
4722 #define mmCP_GFX_HQD_CE_BASE                                                                           0x1ea2
4723 #define mmCP_GFX_HQD_CE_BASE_BASE_IDX                                                                  0
4724 #define mmCP_GFX_HQD_CE_BASE_HI                                                                        0x1ea3
4725 #define mmCP_GFX_HQD_CE_BASE_HI_BASE_IDX                                                               0
4726 #define mmCP_GFX_HQD_CE_RPTR                                                                           0x1ea4
4727 #define mmCP_GFX_HQD_CE_RPTR_BASE_IDX                                                                  0
4728 #define mmCP_GFX_HQD_CE_RPTR_ADDR                                                                      0x1ea5
4729 #define mmCP_GFX_HQD_CE_RPTR_ADDR_BASE_IDX                                                             0
4730 #define mmCP_GFX_HQD_CE_RPTR_ADDR_HI                                                                   0x1ea6
4731 #define mmCP_GFX_HQD_CE_RPTR_ADDR_HI_BASE_IDX                                                          0
4732 #define mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO                                                              0x1ea7
4733 #define mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
4734 #define mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI                                                              0x1ea8
4735 #define mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
4736 #define mmCP_GFX_HQD_CE_OFFSET                                                                         0x1ea9
4737 #define mmCP_GFX_HQD_CE_OFFSET_BASE_IDX                                                                0
4738 #define mmCP_GFX_HQD_CE_CNTL                                                                           0x1eaa
4739 #define mmCP_GFX_HQD_CE_CNTL_BASE_IDX                                                                  0
4740 #define mmCP_GFX_HQD_CE_CSMD_RPTR                                                                      0x1eab
4741 #define mmCP_GFX_HQD_CE_CSMD_RPTR_BASE_IDX                                                             0
4742 #define mmCP_GFX_HQD_CE_WPTR                                                                           0x1eac
4743 #define mmCP_GFX_HQD_CE_WPTR_BASE_IDX                                                                  0
4744 #define mmCP_GFX_HQD_CE_WPTR_HI                                                                        0x1ead
4745 #define mmCP_GFX_HQD_CE_WPTR_HI_BASE_IDX                                                               0
4746 #define mmCP_CE_DOORBELL_CONTROL                                                                       0x1eae
4747 #define mmCP_CE_DOORBELL_CONTROL_BASE_IDX                                                              0
4748 #define mmCP_DMA_WATCH0_ADDR_LO                                                                        0x1ec0
4749 #define mmCP_DMA_WATCH0_ADDR_LO_BASE_IDX                                                               0
4750 #define mmCP_DMA_WATCH0_ADDR_HI                                                                        0x1ec1
4751 #define mmCP_DMA_WATCH0_ADDR_HI_BASE_IDX                                                               0
4752 #define mmCP_DMA_WATCH0_MASK                                                                           0x1ec2
4753 #define mmCP_DMA_WATCH0_MASK_BASE_IDX                                                                  0
4754 #define mmCP_DMA_WATCH0_CNTL                                                                           0x1ec3
4755 #define mmCP_DMA_WATCH0_CNTL_BASE_IDX                                                                  0
4756 #define mmCP_DMA_WATCH1_ADDR_LO                                                                        0x1ec4
4757 #define mmCP_DMA_WATCH1_ADDR_LO_BASE_IDX                                                               0
4758 #define mmCP_DMA_WATCH1_ADDR_HI                                                                        0x1ec5
4759 #define mmCP_DMA_WATCH1_ADDR_HI_BASE_IDX                                                               0
4760 #define mmCP_DMA_WATCH1_MASK                                                                           0x1ec6
4761 #define mmCP_DMA_WATCH1_MASK_BASE_IDX                                                                  0
4762 #define mmCP_DMA_WATCH1_CNTL                                                                           0x1ec7
4763 #define mmCP_DMA_WATCH1_CNTL_BASE_IDX                                                                  0
4764 #define mmCP_DMA_WATCH2_ADDR_LO                                                                        0x1ec8
4765 #define mmCP_DMA_WATCH2_ADDR_LO_BASE_IDX                                                               0
4766 #define mmCP_DMA_WATCH2_ADDR_HI                                                                        0x1ec9
4767 #define mmCP_DMA_WATCH2_ADDR_HI_BASE_IDX                                                               0
4768 #define mmCP_DMA_WATCH2_MASK                                                                           0x1eca
4769 #define mmCP_DMA_WATCH2_MASK_BASE_IDX                                                                  0
4770 #define mmCP_DMA_WATCH2_CNTL                                                                           0x1ecb
4771 #define mmCP_DMA_WATCH2_CNTL_BASE_IDX                                                                  0
4772 #define mmCP_DMA_WATCH3_ADDR_LO                                                                        0x1ecc
4773 #define mmCP_DMA_WATCH3_ADDR_LO_BASE_IDX                                                               0
4774 #define mmCP_DMA_WATCH3_ADDR_HI                                                                        0x1ecd
4775 #define mmCP_DMA_WATCH3_ADDR_HI_BASE_IDX                                                               0
4776 #define mmCP_DMA_WATCH3_MASK                                                                           0x1ece
4777 #define mmCP_DMA_WATCH3_MASK_BASE_IDX                                                                  0
4778 #define mmCP_DMA_WATCH3_CNTL                                                                           0x1ecf
4779 #define mmCP_DMA_WATCH3_CNTL_BASE_IDX                                                                  0
4780 #define mmCP_DMA_WATCH_STAT_ADDR_LO                                                                    0x1ed0
4781 #define mmCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX                                                           0
4782 #define mmCP_DMA_WATCH_STAT_ADDR_HI                                                                    0x1ed1
4783 #define mmCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX                                                           0
4784 #define mmCP_DMA_WATCH_STAT                                                                            0x1ed2
4785 #define mmCP_DMA_WATCH_STAT_BASE_IDX                                                                   0
4786 #define mmCP_PFP_JT_STAT                                                                               0x1ed3
4787 #define mmCP_PFP_JT_STAT_BASE_IDX                                                                      0
4788 #define mmCP_CE_JT_STAT                                                                                0x1ed4
4789 #define mmCP_CE_JT_STAT_BASE_IDX                                                                       0
4790 #define mmCP_MEC_JT_STAT                                                                               0x1ed5
4791 #define mmCP_MEC_JT_STAT_BASE_IDX                                                                      0
4792 #define mmCP_FETCHER_SOURCE                                                                            0x1f1e
4793 #define mmCP_FETCHER_SOURCE_BASE_IDX                                                                   0
4794 #define mmCP_CE_CS_PARTITION_INDEX                                                                     0x1f1f
4795 #define mmCP_CE_CS_PARTITION_INDEX_BASE_IDX                                                            0
4796 #define mmCP_RB_DOORBELL_CLEAR                                                                         0x1f28
4797 #define mmCP_RB_DOORBELL_CLEAR_BASE_IDX                                                                0
4798 #define mmCP_RB0_ACTIVE                                                                                0x1f40
4799 #define mmCP_RB0_ACTIVE_BASE_IDX                                                                       0
4800 #define mmCP_RB_ACTIVE                                                                                 0x1f40
4801 #define mmCP_RB_ACTIVE_BASE_IDX                                                                        0
4802 #define mmCP_RB1_ACTIVE                                                                                0x1f41
4803 #define mmCP_RB1_ACTIVE_BASE_IDX                                                                       0
4804 #define mmCP_RB_STATUS                                                                                 0x1f43
4805 #define mmCP_RB_STATUS_BASE_IDX                                                                        0
4806 #define mmCPG_RCIU_CAM_INDEX                                                                           0x1f44
4807 #define mmCPG_RCIU_CAM_INDEX_BASE_IDX                                                                  0
4808 #define mmCPG_RCIU_CAM_DATA                                                                            0x1f45
4809 #define mmCPG_RCIU_CAM_DATA_BASE_IDX                                                                   0
4810 #define mmCPG_RCIU_CAM_DATA_PHASE0                                                                     0x1f45
4811 #define mmCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX                                                            0
4812 #define mmCPG_RCIU_CAM_DATA_PHASE1                                                                     0x1f45
4813 #define mmCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX                                                            0
4814 #define mmCPG_RCIU_CAM_DATA_PHASE2                                                                     0x1f45
4815 #define mmCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX                                                            0
4816 #define mmCP_GPU_TIMESTAMP_OFFSET_LO                                                                   0x1f4c
4817 #define mmCP_GPU_TIMESTAMP_OFFSET_LO_BASE_IDX                                                          0
4818 #define mmCP_GPU_TIMESTAMP_OFFSET_HI                                                                   0x1f4d
4819 #define mmCP_GPU_TIMESTAMP_OFFSET_HI_BASE_IDX                                                          0
4820 #define mmCPF_GCR_CNTL                                                                                 0x1f53
4821 #define mmCPF_GCR_CNTL_BASE_IDX                                                                        0
4822 #define mmCPG_UTCL1_STATUS                                                                             0x1f54
4823 #define mmCPG_UTCL1_STATUS_BASE_IDX                                                                    0
4824 #define mmCPC_UTCL1_STATUS                                                                             0x1f55
4825 #define mmCPC_UTCL1_STATUS_BASE_IDX                                                                    0
4826 #define mmCPF_UTCL1_STATUS                                                                             0x1f56
4827 #define mmCPF_UTCL1_STATUS_BASE_IDX                                                                    0
4828 #define mmCP_SD_CNTL                                                                                   0x1f57
4829 #define mmCP_SD_CNTL_BASE_IDX                                                                          0
4830 #define mmCP_SOFT_RESET_CNTL                                                                           0x1f59
4831 #define mmCP_SOFT_RESET_CNTL_BASE_IDX                                                                  0
4832 #define mmCP_CPC_GFX_CNTL                                                                              0x1f5a
4833 #define mmCP_CPC_GFX_CNTL_BASE_IDX                                                                     0
4834 
4835 
4836 // addressBlock: gc_spipdec
4837 // base address: 0xc700
4838 #define mmSPI_ARB_PRIORITY                                                                             0x1f60
4839 #define mmSPI_ARB_PRIORITY_BASE_IDX                                                                    0
4840 #define mmSPI_ARB_CYCLES_0                                                                             0x1f61
4841 #define mmSPI_ARB_CYCLES_0_BASE_IDX                                                                    0
4842 #define mmSPI_ARB_CYCLES_1                                                                             0x1f62
4843 #define mmSPI_ARB_CYCLES_1_BASE_IDX                                                                    0
4844 #define mmSPI_WCL_PIPE_PERCENT_GFX                                                                     0x1f67
4845 #define mmSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX                                                            0
4846 #define mmSPI_WCL_PIPE_PERCENT_HP3D                                                                    0x1f68
4847 #define mmSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX                                                           0
4848 #define mmSPI_WCL_PIPE_PERCENT_CS0                                                                     0x1f69
4849 #define mmSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX                                                            0
4850 #define mmSPI_WCL_PIPE_PERCENT_CS1                                                                     0x1f6a
4851 #define mmSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX                                                            0
4852 #define mmSPI_WCL_PIPE_PERCENT_CS2                                                                     0x1f6b
4853 #define mmSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX                                                            0
4854 #define mmSPI_WCL_PIPE_PERCENT_CS3                                                                     0x1f6c
4855 #define mmSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX                                                            0
4856 #define mmSPI_GDBG_WAVE_CNTL                                                                           0x1f71
4857 #define mmSPI_GDBG_WAVE_CNTL_BASE_IDX                                                                  0
4858 #define mmSPI_GDBG_TRAP_CONFIG                                                                         0x1f72
4859 #define mmSPI_GDBG_TRAP_CONFIG_BASE_IDX                                                                0
4860 #define mmSPI_GDBG_TRAP_MASK                                                                           0x1f73
4861 #define mmSPI_GDBG_TRAP_MASK_BASE_IDX                                                                  0
4862 #define mmSPI_GDBG_WAVE_CNTL2                                                                          0x1f74
4863 #define mmSPI_GDBG_WAVE_CNTL2_BASE_IDX                                                                 0
4864 #define mmSPI_GDBG_WAVE_CNTL3                                                                          0x1f75
4865 #define mmSPI_GDBG_WAVE_CNTL3_BASE_IDX                                                                 0
4866 #define mmSPI_GDBG_TRAP_DATA0                                                                          0x1f78
4867 #define mmSPI_GDBG_TRAP_DATA0_BASE_IDX                                                                 0
4868 #define mmSPI_GDBG_TRAP_DATA1                                                                          0x1f79
4869 #define mmSPI_GDBG_TRAP_DATA1_BASE_IDX                                                                 0
4870 #define mmSPI_COMPUTE_QUEUE_RESET                                                                      0x1f7b
4871 #define mmSPI_COMPUTE_QUEUE_RESET_BASE_IDX                                                             0
4872 #define mmSPI_RESOURCE_RESERVE_CU_0                                                                    0x1f7c
4873 #define mmSPI_RESOURCE_RESERVE_CU_0_BASE_IDX                                                           0
4874 #define mmSPI_RESOURCE_RESERVE_CU_1                                                                    0x1f7d
4875 #define mmSPI_RESOURCE_RESERVE_CU_1_BASE_IDX                                                           0
4876 #define mmSPI_RESOURCE_RESERVE_CU_2                                                                    0x1f7e
4877 #define mmSPI_RESOURCE_RESERVE_CU_2_BASE_IDX                                                           0
4878 #define mmSPI_RESOURCE_RESERVE_CU_3                                                                    0x1f7f
4879 #define mmSPI_RESOURCE_RESERVE_CU_3_BASE_IDX                                                           0
4880 #define mmSPI_RESOURCE_RESERVE_CU_4                                                                    0x1f80
4881 #define mmSPI_RESOURCE_RESERVE_CU_4_BASE_IDX                                                           0
4882 #define mmSPI_RESOURCE_RESERVE_CU_5                                                                    0x1f81
4883 #define mmSPI_RESOURCE_RESERVE_CU_5_BASE_IDX                                                           0
4884 #define mmSPI_RESOURCE_RESERVE_CU_6                                                                    0x1f82
4885 #define mmSPI_RESOURCE_RESERVE_CU_6_BASE_IDX                                                           0
4886 #define mmSPI_RESOURCE_RESERVE_CU_7                                                                    0x1f83
4887 #define mmSPI_RESOURCE_RESERVE_CU_7_BASE_IDX                                                           0
4888 #define mmSPI_RESOURCE_RESERVE_CU_8                                                                    0x1f84
4889 #define mmSPI_RESOURCE_RESERVE_CU_8_BASE_IDX                                                           0
4890 #define mmSPI_RESOURCE_RESERVE_CU_9                                                                    0x1f85
4891 #define mmSPI_RESOURCE_RESERVE_CU_9_BASE_IDX                                                           0
4892 #define mmSPI_RESOURCE_RESERVE_EN_CU_0                                                                 0x1f86
4893 #define mmSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX                                                        0
4894 #define mmSPI_RESOURCE_RESERVE_EN_CU_1                                                                 0x1f87
4895 #define mmSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX                                                        0
4896 #define mmSPI_RESOURCE_RESERVE_EN_CU_2                                                                 0x1f88
4897 #define mmSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX                                                        0
4898 #define mmSPI_RESOURCE_RESERVE_EN_CU_3                                                                 0x1f89
4899 #define mmSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX                                                        0
4900 #define mmSPI_RESOURCE_RESERVE_EN_CU_4                                                                 0x1f8a
4901 #define mmSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX                                                        0
4902 #define mmSPI_RESOURCE_RESERVE_EN_CU_5                                                                 0x1f8b
4903 #define mmSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX                                                        0
4904 #define mmSPI_RESOURCE_RESERVE_EN_CU_6                                                                 0x1f8c
4905 #define mmSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX                                                        0
4906 #define mmSPI_RESOURCE_RESERVE_EN_CU_7                                                                 0x1f8d
4907 #define mmSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX                                                        0
4908 #define mmSPI_RESOURCE_RESERVE_EN_CU_8                                                                 0x1f8e
4909 #define mmSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX                                                        0
4910 #define mmSPI_RESOURCE_RESERVE_EN_CU_9                                                                 0x1f8f
4911 #define mmSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX                                                        0
4912 #define mmSPI_COMPUTE_WF_CTX_SAVE                                                                      0x1f9c
4913 #define mmSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX                                                             0
4914 #define mmSPI_ARB_CNTL_0                                                                               0x1f9d
4915 #define mmSPI_ARB_CNTL_0_BASE_IDX                                                                      0
4916 #define mmSPI_FEATURE_CTRL                                                                             0x1f9e
4917 #define mmSPI_FEATURE_CTRL_BASE_IDX                                                                    0
4918 #define mmSPI_SHADER_RSRC_LIMIT_CTRL                                                                   0x1f9f
4919 #define mmSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX                                                          0
4920 
4921 
4922 // addressBlock: gc_cpphqddec
4923 // base address: 0xc800
4924 #define mmCP_HPD_MES_ROQ_OFFSETS                                                                       0x1fa4
4925 #define mmCP_HPD_MES_ROQ_OFFSETS_BASE_IDX                                                              0
4926 #define mmCP_HPD_ROQ_OFFSETS                                                                           0x1fa4
4927 #define mmCP_HPD_ROQ_OFFSETS_BASE_IDX                                                                  0
4928 #define mmCP_HPD_STATUS0                                                                               0x1fa5
4929 #define mmCP_HPD_STATUS0_BASE_IDX                                                                      0
4930 #define mmCP_HPD_UTCL1_CNTL                                                                            0x1fa6
4931 #define mmCP_HPD_UTCL1_CNTL_BASE_IDX                                                                   0
4932 #define mmCP_HPD_UTCL1_ERROR                                                                           0x1fa7
4933 #define mmCP_HPD_UTCL1_ERROR_BASE_IDX                                                                  0
4934 #define mmCP_HPD_UTCL1_ERROR_ADDR                                                                      0x1fa8
4935 #define mmCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX                                                             0
4936 #define mmCP_MQD_BASE_ADDR                                                                             0x1fa9
4937 #define mmCP_MQD_BASE_ADDR_BASE_IDX                                                                    0
4938 #define mmCP_MQD_BASE_ADDR_HI                                                                          0x1faa
4939 #define mmCP_MQD_BASE_ADDR_HI_BASE_IDX                                                                 0
4940 #define mmCP_HQD_ACTIVE                                                                                0x1fab
4941 #define mmCP_HQD_ACTIVE_BASE_IDX                                                                       0
4942 #define mmCP_HQD_VMID                                                                                  0x1fac
4943 #define mmCP_HQD_VMID_BASE_IDX                                                                         0
4944 #define mmCP_HQD_PERSISTENT_STATE                                                                      0x1fad
4945 #define mmCP_HQD_PERSISTENT_STATE_BASE_IDX                                                             0
4946 #define mmCP_HQD_PIPE_PRIORITY                                                                         0x1fae
4947 #define mmCP_HQD_PIPE_PRIORITY_BASE_IDX                                                                0
4948 #define mmCP_HQD_QUEUE_PRIORITY                                                                        0x1faf
4949 #define mmCP_HQD_QUEUE_PRIORITY_BASE_IDX                                                               0
4950 #define mmCP_HQD_QUANTUM                                                                               0x1fb0
4951 #define mmCP_HQD_QUANTUM_BASE_IDX                                                                      0
4952 #define mmCP_HQD_PQ_BASE                                                                               0x1fb1
4953 #define mmCP_HQD_PQ_BASE_BASE_IDX                                                                      0
4954 #define mmCP_HQD_PQ_BASE_HI                                                                            0x1fb2
4955 #define mmCP_HQD_PQ_BASE_HI_BASE_IDX                                                                   0
4956 #define mmCP_HQD_PQ_RPTR                                                                               0x1fb3
4957 #define mmCP_HQD_PQ_RPTR_BASE_IDX                                                                      0
4958 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR                                                                   0x1fb4
4959 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX                                                          0
4960 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI                                                                0x1fb5
4961 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX                                                       0
4962 #define mmCP_HQD_PQ_WPTR_POLL_ADDR                                                                     0x1fb6
4963 #define mmCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX                                                            0
4964 #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI                                                                  0x1fb7
4965 #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX                                                         0
4966 #define mmCP_HQD_PQ_DOORBELL_CONTROL                                                                   0x1fb8
4967 #define mmCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX                                                          0
4968 #define mmCP_HQD_PQ_CONTROL                                                                            0x1fba
4969 #define mmCP_HQD_PQ_CONTROL_BASE_IDX                                                                   0
4970 #define mmCP_HQD_IB_BASE_ADDR                                                                          0x1fbb
4971 #define mmCP_HQD_IB_BASE_ADDR_BASE_IDX                                                                 0
4972 #define mmCP_HQD_IB_BASE_ADDR_HI                                                                       0x1fbc
4973 #define mmCP_HQD_IB_BASE_ADDR_HI_BASE_IDX                                                              0
4974 #define mmCP_HQD_IB_RPTR                                                                               0x1fbd
4975 #define mmCP_HQD_IB_RPTR_BASE_IDX                                                                      0
4976 #define mmCP_HQD_IB_CONTROL                                                                            0x1fbe
4977 #define mmCP_HQD_IB_CONTROL_BASE_IDX                                                                   0
4978 #define mmCP_HQD_IQ_TIMER                                                                              0x1fbf
4979 #define mmCP_HQD_IQ_TIMER_BASE_IDX                                                                     0
4980 #define mmCP_HQD_IQ_RPTR                                                                               0x1fc0
4981 #define mmCP_HQD_IQ_RPTR_BASE_IDX                                                                      0
4982 #define mmCP_HQD_DEQUEUE_REQUEST                                                                       0x1fc1
4983 #define mmCP_HQD_DEQUEUE_REQUEST_BASE_IDX                                                              0
4984 #define mmCP_HQD_DMA_OFFLOAD                                                                           0x1fc2
4985 #define mmCP_HQD_DMA_OFFLOAD_BASE_IDX                                                                  0
4986 #define mmCP_HQD_OFFLOAD                                                                               0x1fc2
4987 #define mmCP_HQD_OFFLOAD_BASE_IDX                                                                      0
4988 #define mmCP_HQD_SEMA_CMD                                                                              0x1fc3
4989 #define mmCP_HQD_SEMA_CMD_BASE_IDX                                                                     0
4990 #define mmCP_HQD_MSG_TYPE                                                                              0x1fc4
4991 #define mmCP_HQD_MSG_TYPE_BASE_IDX                                                                     0
4992 #define mmCP_HQD_ATOMIC0_PREOP_LO                                                                      0x1fc5
4993 #define mmCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX                                                             0
4994 #define mmCP_HQD_ATOMIC0_PREOP_HI                                                                      0x1fc6
4995 #define mmCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX                                                             0
4996 #define mmCP_HQD_ATOMIC1_PREOP_LO                                                                      0x1fc7
4997 #define mmCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX                                                             0
4998 #define mmCP_HQD_ATOMIC1_PREOP_HI                                                                      0x1fc8
4999 #define mmCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX                                                             0
5000 #define mmCP_HQD_HQ_SCHEDULER0                                                                         0x1fc9
5001 #define mmCP_HQD_HQ_SCHEDULER0_BASE_IDX                                                                0
5002 #define mmCP_HQD_HQ_STATUS0                                                                            0x1fc9
5003 #define mmCP_HQD_HQ_STATUS0_BASE_IDX                                                                   0
5004 #define mmCP_HQD_HQ_CONTROL0                                                                           0x1fca
5005 #define mmCP_HQD_HQ_CONTROL0_BASE_IDX                                                                  0
5006 #define mmCP_HQD_HQ_SCHEDULER1                                                                         0x1fca
5007 #define mmCP_HQD_HQ_SCHEDULER1_BASE_IDX                                                                0
5008 #define mmCP_MQD_CONTROL                                                                               0x1fcb
5009 #define mmCP_MQD_CONTROL_BASE_IDX                                                                      0
5010 #define mmCP_HQD_HQ_STATUS1                                                                            0x1fcc
5011 #define mmCP_HQD_HQ_STATUS1_BASE_IDX                                                                   0
5012 #define mmCP_HQD_HQ_CONTROL1                                                                           0x1fcd
5013 #define mmCP_HQD_HQ_CONTROL1_BASE_IDX                                                                  0
5014 #define mmCP_HQD_EOP_BASE_ADDR                                                                         0x1fce
5015 #define mmCP_HQD_EOP_BASE_ADDR_BASE_IDX                                                                0
5016 #define mmCP_HQD_EOP_BASE_ADDR_HI                                                                      0x1fcf
5017 #define mmCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX                                                             0
5018 #define mmCP_HQD_EOP_CONTROL                                                                           0x1fd0
5019 #define mmCP_HQD_EOP_CONTROL_BASE_IDX                                                                  0
5020 #define mmCP_HQD_EOP_RPTR                                                                              0x1fd1
5021 #define mmCP_HQD_EOP_RPTR_BASE_IDX                                                                     0
5022 #define mmCP_HQD_EOP_WPTR                                                                              0x1fd2
5023 #define mmCP_HQD_EOP_WPTR_BASE_IDX                                                                     0
5024 #define mmCP_HQD_EOP_EVENTS                                                                            0x1fd3
5025 #define mmCP_HQD_EOP_EVENTS_BASE_IDX                                                                   0
5026 #define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO                                                                 0x1fd4
5027 #define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX                                                        0
5028 #define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI                                                                 0x1fd5
5029 #define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX                                                        0
5030 #define mmCP_HQD_CTX_SAVE_CONTROL                                                                      0x1fd6
5031 #define mmCP_HQD_CTX_SAVE_CONTROL_BASE_IDX                                                             0
5032 #define mmCP_HQD_CNTL_STACK_OFFSET                                                                     0x1fd7
5033 #define mmCP_HQD_CNTL_STACK_OFFSET_BASE_IDX                                                            0
5034 #define mmCP_HQD_CNTL_STACK_SIZE                                                                       0x1fd8
5035 #define mmCP_HQD_CNTL_STACK_SIZE_BASE_IDX                                                              0
5036 #define mmCP_HQD_WG_STATE_OFFSET                                                                       0x1fd9
5037 #define mmCP_HQD_WG_STATE_OFFSET_BASE_IDX                                                              0
5038 #define mmCP_HQD_CTX_SAVE_SIZE                                                                         0x1fda
5039 #define mmCP_HQD_CTX_SAVE_SIZE_BASE_IDX                                                                0
5040 #define mmCP_HQD_GDS_RESOURCE_STATE                                                                    0x1fdb
5041 #define mmCP_HQD_GDS_RESOURCE_STATE_BASE_IDX                                                           0
5042 #define mmCP_HQD_ERROR                                                                                 0x1fdc
5043 #define mmCP_HQD_ERROR_BASE_IDX                                                                        0
5044 #define mmCP_HQD_EOP_WPTR_MEM                                                                          0x1fdd
5045 #define mmCP_HQD_EOP_WPTR_MEM_BASE_IDX                                                                 0
5046 #define mmCP_HQD_AQL_CONTROL                                                                           0x1fde
5047 #define mmCP_HQD_AQL_CONTROL_BASE_IDX                                                                  0
5048 #define mmCP_HQD_PQ_WPTR_LO                                                                            0x1fdf
5049 #define mmCP_HQD_PQ_WPTR_LO_BASE_IDX                                                                   0
5050 #define mmCP_HQD_PQ_WPTR_HI                                                                            0x1fe0
5051 #define mmCP_HQD_PQ_WPTR_HI_BASE_IDX                                                                   0
5052 #define mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET                                                             0x1fe1
5053 #define mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX                                                    0
5054 #define mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT                                                             0x1fe2
5055 #define mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX                                                    0
5056 #define mmCP_HQD_SUSPEND_WG_STATE_OFFSET                                                               0x1fe3
5057 #define mmCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX                                                      0
5058 #define mmCP_HQD_DDID_RPTR                                                                             0x1fe4
5059 #define mmCP_HQD_DDID_RPTR_BASE_IDX                                                                    0
5060 #define mmCP_HQD_DDID_WPTR                                                                             0x1fe5
5061 #define mmCP_HQD_DDID_WPTR_BASE_IDX                                                                    0
5062 #define mmCP_HQD_DDID_INFLIGHT_COUNT                                                                   0x1fe6
5063 #define mmCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX                                                          0
5064 #define mmCP_HQD_DDID_DELTA_RPT_COUNT                                                                  0x1fe7
5065 #define mmCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX                                                         0
5066 #define mmCP_HQD_DEQUEUE_STATUS                                                                        0x1fe8
5067 #define mmCP_HQD_DEQUEUE_STATUS_BASE_IDX                                                               0
5068 
5069 
5070 // addressBlock: gc_didtdec
5071 // base address: 0xca00
5072 #define mmDIDT_IND_INDEX                                                                               0x2020
5073 #define mmDIDT_IND_INDEX_BASE_IDX                                                                      0
5074 #define mmDIDT_IND_DATA                                                                                0x2021
5075 #define mmDIDT_IND_DATA_BASE_IDX                                                                       0
5076 #define mmDIDT_INDEX_AUTO_INCR_EN                                                                      0x2022
5077 #define mmDIDT_INDEX_AUTO_INCR_EN_BASE_IDX                                                             0
5078 
5079 
5080 // addressBlock: gc_gccacdec
5081 // base address: 0xca10
5082 #define mmGC_CAC_CTRL_1                                                                                0x2024
5083 #define mmGC_CAC_CTRL_1_BASE_IDX                                                                       0
5084 #define mmGC_CAC_CTRL_2                                                                                0x2025
5085 #define mmGC_CAC_CTRL_2_BASE_IDX                                                                       0
5086 #define mmGC_CAC_AGGR_LOWER                                                                            0x2026
5087 #define mmGC_CAC_AGGR_LOWER_BASE_IDX                                                                   0
5088 #define mmGC_CAC_AGGR_UPPER                                                                            0x2027
5089 #define mmGC_CAC_AGGR_UPPER_BASE_IDX                                                                   0
5090 #define mmGC_CAC_SOFT_CTRL                                                                             0x202a
5091 #define mmGC_CAC_SOFT_CTRL_BASE_IDX                                                                    0
5092 #define mmGC_EDC_CTRL                                                                                  0x202b
5093 #define mmGC_EDC_CTRL_BASE_IDX                                                                         0
5094 #define mmGC_EDC_THRESHOLD                                                                             0x202c
5095 #define mmGC_EDC_THRESHOLD_BASE_IDX                                                                    0
5096 #define mmGC_EDC_STATUS                                                                                0x202d
5097 #define mmGC_EDC_STATUS_BASE_IDX                                                                       0
5098 #define mmGC_EDC_OVERFLOW                                                                              0x202e
5099 #define mmGC_EDC_OVERFLOW_BASE_IDX                                                                     0
5100 #define mmGC_EDC_ROLLING_POWER_DELTA                                                                   0x202f
5101 #define mmGC_EDC_ROLLING_POWER_DELTA_BASE_IDX                                                          0
5102 #define mmGC_THROTTLE_CTRL                                                                             0x2030
5103 #define mmGC_THROTTLE_CTRL_BASE_IDX                                                                    0
5104 #define mmGC_THROTTLE_CTRL1                                                                            0x2031
5105 #define mmGC_THROTTLE_CTRL1_BASE_IDX                                                                   0
5106 #define mmGC_THROTTLE_STATUS                                                                           0x2032
5107 #define mmGC_THROTTLE_STATUS_BASE_IDX                                                                  0
5108 #define mmEDC_PERF_COUNTER                                                                             0x2033
5109 #define mmEDC_PERF_COUNTER_BASE_IDX                                                                    0
5110 #define mmPCC_PERF_COUNTER                                                                             0x2034
5111 #define mmPCC_PERF_COUNTER_BASE_IDX                                                                    0
5112 #define mmPWRBRK_PERF_COUNTER                                                                          0x2035
5113 #define mmPWRBRK_PERF_COUNTER_BASE_IDX                                                                 0
5114 #define mmGC_EDC_STRETCH_CTRL                                                                          0x2036
5115 #define mmGC_EDC_STRETCH_CTRL_BASE_IDX                                                                 0
5116 #define mmGC_EDC_STRETCH_THRESHOLD                                                                     0x2037
5117 #define mmGC_EDC_STRETCH_THRESHOLD_BASE_IDX                                                            0
5118 #define mmEDC_HYSTERESIS_CNTL                                                                          0x2038
5119 #define mmEDC_HYSTERESIS_CNTL_BASE_IDX                                                                 0
5120 #define mmEDC_HYSTERESIS_STAT                                                                          0x2039
5121 #define mmEDC_HYSTERESIS_STAT_BASE_IDX                                                                 0
5122 #define mmGC_CAC_IND_INDEX                                                                             0x203c
5123 #define mmGC_CAC_IND_INDEX_BASE_IDX                                                                    0
5124 #define mmGC_CAC_IND_DATA                                                                              0x203d
5125 #define mmGC_CAC_IND_DATA_BASE_IDX                                                                     0
5126 #define mmSE_CAC_IND_INDEX                                                                             0x203e
5127 #define mmSE_CAC_IND_INDEX_BASE_IDX                                                                    0
5128 #define mmSE_CAC_IND_DATA                                                                              0x203f
5129 #define mmSE_CAC_IND_DATA_BASE_IDX                                                                     0
5130 
5131 
5132 // addressBlock: gc_tcpdec
5133 // base address: 0xca80
5134 #define mmTCP_WATCH0_ADDR_H                                                                            0x2040
5135 #define mmTCP_WATCH0_ADDR_H_BASE_IDX                                                                   0
5136 #define mmTCP_WATCH0_ADDR_L                                                                            0x2041
5137 #define mmTCP_WATCH0_ADDR_L_BASE_IDX                                                                   0
5138 #define mmTCP_WATCH0_CNTL                                                                              0x2042
5139 #define mmTCP_WATCH0_CNTL_BASE_IDX                                                                     0
5140 #define mmTCP_WATCH1_ADDR_H                                                                            0x2043
5141 #define mmTCP_WATCH1_ADDR_H_BASE_IDX                                                                   0
5142 #define mmTCP_WATCH1_ADDR_L                                                                            0x2044
5143 #define mmTCP_WATCH1_ADDR_L_BASE_IDX                                                                   0
5144 #define mmTCP_WATCH1_CNTL                                                                              0x2045
5145 #define mmTCP_WATCH1_CNTL_BASE_IDX                                                                     0
5146 #define mmTCP_WATCH2_ADDR_H                                                                            0x2046
5147 #define mmTCP_WATCH2_ADDR_H_BASE_IDX                                                                   0
5148 #define mmTCP_WATCH2_ADDR_L                                                                            0x2047
5149 #define mmTCP_WATCH2_ADDR_L_BASE_IDX                                                                   0
5150 #define mmTCP_WATCH2_CNTL                                                                              0x2048
5151 #define mmTCP_WATCH2_CNTL_BASE_IDX                                                                     0
5152 #define mmTCP_WATCH3_ADDR_H                                                                            0x2049
5153 #define mmTCP_WATCH3_ADDR_H_BASE_IDX                                                                   0
5154 #define mmTCP_WATCH3_ADDR_L                                                                            0x204a
5155 #define mmTCP_WATCH3_ADDR_L_BASE_IDX                                                                   0
5156 #define mmTCP_WATCH3_CNTL                                                                              0x204b
5157 #define mmTCP_WATCH3_CNTL_BASE_IDX                                                                     0
5158 #define mmTCP_PERFCOUNTER_FILTER                                                                       0x2059
5159 #define mmTCP_PERFCOUNTER_FILTER_BASE_IDX                                                              0
5160 #define mmTCP_PERFCOUNTER_FILTER_EN                                                                    0x205a
5161 #define mmTCP_PERFCOUNTER_FILTER_EN_BASE_IDX                                                           0
5162 #define mmTCP_PERFCOUNTER_FILTER2                                                                      0x205b
5163 #define mmTCP_PERFCOUNTER_FILTER2_BASE_IDX                                                             0
5164 
5165 
5166 // addressBlock: gc_gdspdec
5167 // base address: 0xcc00
5168 #define mmGDS_VMID0_BASE                                                                               0x20a0
5169 #define mmGDS_VMID0_BASE_BASE_IDX                                                                      0
5170 #define mmGDS_VMID0_SIZE                                                                               0x20a1
5171 #define mmGDS_VMID0_SIZE_BASE_IDX                                                                      0
5172 #define mmGDS_VMID1_BASE                                                                               0x20a2
5173 #define mmGDS_VMID1_BASE_BASE_IDX                                                                      0
5174 #define mmGDS_VMID1_SIZE                                                                               0x20a3
5175 #define mmGDS_VMID1_SIZE_BASE_IDX                                                                      0
5176 #define mmGDS_VMID2_BASE                                                                               0x20a4
5177 #define mmGDS_VMID2_BASE_BASE_IDX                                                                      0
5178 #define mmGDS_VMID2_SIZE                                                                               0x20a5
5179 #define mmGDS_VMID2_SIZE_BASE_IDX                                                                      0
5180 #define mmGDS_VMID3_BASE                                                                               0x20a6
5181 #define mmGDS_VMID3_BASE_BASE_IDX                                                                      0
5182 #define mmGDS_VMID3_SIZE                                                                               0x20a7
5183 #define mmGDS_VMID3_SIZE_BASE_IDX                                                                      0
5184 #define mmGDS_VMID4_BASE                                                                               0x20a8
5185 #define mmGDS_VMID4_BASE_BASE_IDX                                                                      0
5186 #define mmGDS_VMID4_SIZE                                                                               0x20a9
5187 #define mmGDS_VMID4_SIZE_BASE_IDX                                                                      0
5188 #define mmGDS_VMID5_BASE                                                                               0x20aa
5189 #define mmGDS_VMID5_BASE_BASE_IDX                                                                      0
5190 #define mmGDS_VMID5_SIZE                                                                               0x20ab
5191 #define mmGDS_VMID5_SIZE_BASE_IDX                                                                      0
5192 #define mmGDS_VMID6_BASE                                                                               0x20ac
5193 #define mmGDS_VMID6_BASE_BASE_IDX                                                                      0
5194 #define mmGDS_VMID6_SIZE                                                                               0x20ad
5195 #define mmGDS_VMID6_SIZE_BASE_IDX                                                                      0
5196 #define mmGDS_VMID7_BASE                                                                               0x20ae
5197 #define mmGDS_VMID7_BASE_BASE_IDX                                                                      0
5198 #define mmGDS_VMID7_SIZE                                                                               0x20af
5199 #define mmGDS_VMID7_SIZE_BASE_IDX                                                                      0
5200 #define mmGDS_VMID8_BASE                                                                               0x20b0
5201 #define mmGDS_VMID8_BASE_BASE_IDX                                                                      0
5202 #define mmGDS_VMID8_SIZE                                                                               0x20b1
5203 #define mmGDS_VMID8_SIZE_BASE_IDX                                                                      0
5204 #define mmGDS_VMID9_BASE                                                                               0x20b2
5205 #define mmGDS_VMID9_BASE_BASE_IDX                                                                      0
5206 #define mmGDS_VMID9_SIZE                                                                               0x20b3
5207 #define mmGDS_VMID9_SIZE_BASE_IDX                                                                      0
5208 #define mmGDS_VMID10_BASE                                                                              0x20b4
5209 #define mmGDS_VMID10_BASE_BASE_IDX                                                                     0
5210 #define mmGDS_VMID10_SIZE                                                                              0x20b5
5211 #define mmGDS_VMID10_SIZE_BASE_IDX                                                                     0
5212 #define mmGDS_VMID11_BASE                                                                              0x20b6
5213 #define mmGDS_VMID11_BASE_BASE_IDX                                                                     0
5214 #define mmGDS_VMID11_SIZE                                                                              0x20b7
5215 #define mmGDS_VMID11_SIZE_BASE_IDX                                                                     0
5216 #define mmGDS_VMID12_BASE                                                                              0x20b8
5217 #define mmGDS_VMID12_BASE_BASE_IDX                                                                     0
5218 #define mmGDS_VMID12_SIZE                                                                              0x20b9
5219 #define mmGDS_VMID12_SIZE_BASE_IDX                                                                     0
5220 #define mmGDS_VMID13_BASE                                                                              0x20ba
5221 #define mmGDS_VMID13_BASE_BASE_IDX                                                                     0
5222 #define mmGDS_VMID13_SIZE                                                                              0x20bb
5223 #define mmGDS_VMID13_SIZE_BASE_IDX                                                                     0
5224 #define mmGDS_VMID14_BASE                                                                              0x20bc
5225 #define mmGDS_VMID14_BASE_BASE_IDX                                                                     0
5226 #define mmGDS_VMID14_SIZE                                                                              0x20bd
5227 #define mmGDS_VMID14_SIZE_BASE_IDX                                                                     0
5228 #define mmGDS_VMID15_BASE                                                                              0x20be
5229 #define mmGDS_VMID15_BASE_BASE_IDX                                                                     0
5230 #define mmGDS_VMID15_SIZE                                                                              0x20bf
5231 #define mmGDS_VMID15_SIZE_BASE_IDX                                                                     0
5232 #define mmGDS_GWS_VMID0                                                                                0x20c0
5233 #define mmGDS_GWS_VMID0_BASE_IDX                                                                       0
5234 #define mmGDS_GWS_VMID1                                                                                0x20c1
5235 #define mmGDS_GWS_VMID1_BASE_IDX                                                                       0
5236 #define mmGDS_GWS_VMID2                                                                                0x20c2
5237 #define mmGDS_GWS_VMID2_BASE_IDX                                                                       0
5238 #define mmGDS_GWS_VMID3                                                                                0x20c3
5239 #define mmGDS_GWS_VMID3_BASE_IDX                                                                       0
5240 #define mmGDS_GWS_VMID4                                                                                0x20c4
5241 #define mmGDS_GWS_VMID4_BASE_IDX                                                                       0
5242 #define mmGDS_GWS_VMID5                                                                                0x20c5
5243 #define mmGDS_GWS_VMID5_BASE_IDX                                                                       0
5244 #define mmGDS_GWS_VMID6                                                                                0x20c6
5245 #define mmGDS_GWS_VMID6_BASE_IDX                                                                       0
5246 #define mmGDS_GWS_VMID7                                                                                0x20c7
5247 #define mmGDS_GWS_VMID7_BASE_IDX                                                                       0
5248 #define mmGDS_GWS_VMID8                                                                                0x20c8
5249 #define mmGDS_GWS_VMID8_BASE_IDX                                                                       0
5250 #define mmGDS_GWS_VMID9                                                                                0x20c9
5251 #define mmGDS_GWS_VMID9_BASE_IDX                                                                       0
5252 #define mmGDS_GWS_VMID10                                                                               0x20ca
5253 #define mmGDS_GWS_VMID10_BASE_IDX                                                                      0
5254 #define mmGDS_GWS_VMID11                                                                               0x20cb
5255 #define mmGDS_GWS_VMID11_BASE_IDX                                                                      0
5256 #define mmGDS_GWS_VMID12                                                                               0x20cc
5257 #define mmGDS_GWS_VMID12_BASE_IDX                                                                      0
5258 #define mmGDS_GWS_VMID13                                                                               0x20cd
5259 #define mmGDS_GWS_VMID13_BASE_IDX                                                                      0
5260 #define mmGDS_GWS_VMID14                                                                               0x20ce
5261 #define mmGDS_GWS_VMID14_BASE_IDX                                                                      0
5262 #define mmGDS_GWS_VMID15                                                                               0x20cf
5263 #define mmGDS_GWS_VMID15_BASE_IDX                                                                      0
5264 #define mmGDS_OA_VMID0                                                                                 0x20d0
5265 #define mmGDS_OA_VMID0_BASE_IDX                                                                        0
5266 #define mmGDS_OA_VMID1                                                                                 0x20d1
5267 #define mmGDS_OA_VMID1_BASE_IDX                                                                        0
5268 #define mmGDS_OA_VMID2                                                                                 0x20d2
5269 #define mmGDS_OA_VMID2_BASE_IDX                                                                        0
5270 #define mmGDS_OA_VMID3                                                                                 0x20d3
5271 #define mmGDS_OA_VMID3_BASE_IDX                                                                        0
5272 #define mmGDS_OA_VMID4                                                                                 0x20d4
5273 #define mmGDS_OA_VMID4_BASE_IDX                                                                        0
5274 #define mmGDS_OA_VMID5                                                                                 0x20d5
5275 #define mmGDS_OA_VMID5_BASE_IDX                                                                        0
5276 #define mmGDS_OA_VMID6                                                                                 0x20d6
5277 #define mmGDS_OA_VMID6_BASE_IDX                                                                        0
5278 #define mmGDS_OA_VMID7                                                                                 0x20d7
5279 #define mmGDS_OA_VMID7_BASE_IDX                                                                        0
5280 #define mmGDS_OA_VMID8                                                                                 0x20d8
5281 #define mmGDS_OA_VMID8_BASE_IDX                                                                        0
5282 #define mmGDS_OA_VMID9                                                                                 0x20d9
5283 #define mmGDS_OA_VMID9_BASE_IDX                                                                        0
5284 #define mmGDS_OA_VMID10                                                                                0x20da
5285 #define mmGDS_OA_VMID10_BASE_IDX                                                                       0
5286 #define mmGDS_OA_VMID11                                                                                0x20db
5287 #define mmGDS_OA_VMID11_BASE_IDX                                                                       0
5288 #define mmGDS_OA_VMID12                                                                                0x20dc
5289 #define mmGDS_OA_VMID12_BASE_IDX                                                                       0
5290 #define mmGDS_OA_VMID13                                                                                0x20dd
5291 #define mmGDS_OA_VMID13_BASE_IDX                                                                       0
5292 #define mmGDS_OA_VMID14                                                                                0x20de
5293 #define mmGDS_OA_VMID14_BASE_IDX                                                                       0
5294 #define mmGDS_OA_VMID15                                                                                0x20df
5295 #define mmGDS_OA_VMID15_BASE_IDX                                                                       0
5296 #define mmGDS_GWS_RESET0                                                                               0x20e4
5297 #define mmGDS_GWS_RESET0_BASE_IDX                                                                      0
5298 #define mmGDS_GWS_RESET1                                                                               0x20e5
5299 #define mmGDS_GWS_RESET1_BASE_IDX                                                                      0
5300 #define mmGDS_GWS_RESOURCE_RESET                                                                       0x20e6
5301 #define mmGDS_GWS_RESOURCE_RESET_BASE_IDX                                                              0
5302 #define mmGDS_COMPUTE_MAX_WAVE_ID                                                                      0x20e8
5303 #define mmGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX                                                             0
5304 #define mmGDS_OA_RESET_MASK                                                                            0x20e9
5305 #define mmGDS_OA_RESET_MASK_BASE_IDX                                                                   0
5306 #define mmGDS_OA_RESET                                                                                 0x20ea
5307 #define mmGDS_OA_RESET_BASE_IDX                                                                        0
5308 #define mmGDS_ENHANCE2                                                                                 0x20eb
5309 #define mmGDS_ENHANCE2_BASE_IDX                                                                        0
5310 #define mmGDS_OA_CGPG_RESTORE                                                                          0x20ec
5311 #define mmGDS_OA_CGPG_RESTORE_BASE_IDX                                                                 0
5312 #define mmGDS_CS_CTXSW_STATUS                                                                          0x20ed
5313 #define mmGDS_CS_CTXSW_STATUS_BASE_IDX                                                                 0
5314 #define mmGDS_CS_CTXSW_CNT0                                                                            0x20ee
5315 #define mmGDS_CS_CTXSW_CNT0_BASE_IDX                                                                   0
5316 #define mmGDS_CS_CTXSW_CNT1                                                                            0x20ef
5317 #define mmGDS_CS_CTXSW_CNT1_BASE_IDX                                                                   0
5318 #define mmGDS_CS_CTXSW_CNT2                                                                            0x20f0
5319 #define mmGDS_CS_CTXSW_CNT2_BASE_IDX                                                                   0
5320 #define mmGDS_CS_CTXSW_CNT3                                                                            0x20f1
5321 #define mmGDS_CS_CTXSW_CNT3_BASE_IDX                                                                   0
5322 #define mmGDS_GFX_CTXSW_STATUS                                                                         0x20f2
5323 #define mmGDS_GFX_CTXSW_STATUS_BASE_IDX                                                                0
5324 #define mmGDS_VS_CTXSW_CNT0                                                                            0x20f3
5325 #define mmGDS_VS_CTXSW_CNT0_BASE_IDX                                                                   0
5326 #define mmGDS_VS_CTXSW_CNT1                                                                            0x20f4
5327 #define mmGDS_VS_CTXSW_CNT1_BASE_IDX                                                                   0
5328 #define mmGDS_VS_CTXSW_CNT2                                                                            0x20f5
5329 #define mmGDS_VS_CTXSW_CNT2_BASE_IDX                                                                   0
5330 #define mmGDS_VS_CTXSW_CNT3                                                                            0x20f6
5331 #define mmGDS_VS_CTXSW_CNT3_BASE_IDX                                                                   0
5332 #define mmGDS_PS_CTXSW_CNT0                                                                            0x20f7
5333 #define mmGDS_PS_CTXSW_CNT0_BASE_IDX                                                                   0
5334 #define mmGDS_PS_CTXSW_CNT1                                                                            0x20f8
5335 #define mmGDS_PS_CTXSW_CNT1_BASE_IDX                                                                   0
5336 #define mmGDS_PS_CTXSW_CNT2                                                                            0x20f9
5337 #define mmGDS_PS_CTXSW_CNT2_BASE_IDX                                                                   0
5338 #define mmGDS_PS_CTXSW_CNT3                                                                            0x20fa
5339 #define mmGDS_PS_CTXSW_CNT3_BASE_IDX                                                                   0
5340 #define mmGDS_PS_CTXSW_IDX                                                                             0x20fb
5341 #define mmGDS_PS_CTXSW_IDX_BASE_IDX                                                                    0
5342 #define mmGDS_GS_CTXSW_CNT0                                                                            0x2117
5343 #define mmGDS_GS_CTXSW_CNT0_BASE_IDX                                                                   0
5344 #define mmGDS_GS_CTXSW_CNT1                                                                            0x2118
5345 #define mmGDS_GS_CTXSW_CNT1_BASE_IDX                                                                   0
5346 #define mmGDS_GS_CTXSW_CNT2                                                                            0x2119
5347 #define mmGDS_GS_CTXSW_CNT2_BASE_IDX                                                                   0
5348 #define mmGDS_GS_CTXSW_CNT3                                                                            0x211a
5349 #define mmGDS_GS_CTXSW_CNT3_BASE_IDX                                                                   0
5350 #define mmGDS_MEMORY_CLEAN                                                                             0x211f
5351 #define mmGDS_MEMORY_CLEAN_BASE_IDX                                                                    0
5352 
5353 
5354 // addressBlock: gc_gfxdec0
5355 // base address: 0x28000
5356 #define mmDB_RENDER_CONTROL                                                                            0x0000
5357 #define mmDB_RENDER_CONTROL_BASE_IDX                                                                   1
5358 #define mmDB_COUNT_CONTROL                                                                             0x0001
5359 #define mmDB_COUNT_CONTROL_BASE_IDX                                                                    1
5360 #define mmDB_DEPTH_VIEW                                                                                0x0002
5361 #define mmDB_DEPTH_VIEW_BASE_IDX                                                                       1
5362 #define mmDB_RENDER_OVERRIDE                                                                           0x0003
5363 #define mmDB_RENDER_OVERRIDE_BASE_IDX                                                                  1
5364 #define mmDB_RENDER_OVERRIDE2                                                                          0x0004
5365 #define mmDB_RENDER_OVERRIDE2_BASE_IDX                                                                 1
5366 #define mmDB_HTILE_DATA_BASE                                                                           0x0005
5367 #define mmDB_HTILE_DATA_BASE_BASE_IDX                                                                  1
5368 #define mmDB_DEPTH_SIZE_XY                                                                             0x0007
5369 #define mmDB_DEPTH_SIZE_XY_BASE_IDX                                                                    1
5370 #define mmDB_DEPTH_BOUNDS_MIN                                                                          0x0008
5371 #define mmDB_DEPTH_BOUNDS_MIN_BASE_IDX                                                                 1
5372 #define mmDB_DEPTH_BOUNDS_MAX                                                                          0x0009
5373 #define mmDB_DEPTH_BOUNDS_MAX_BASE_IDX                                                                 1
5374 #define mmDB_STENCIL_CLEAR                                                                             0x000a
5375 #define mmDB_STENCIL_CLEAR_BASE_IDX                                                                    1
5376 #define mmDB_DEPTH_CLEAR                                                                               0x000b
5377 #define mmDB_DEPTH_CLEAR_BASE_IDX                                                                      1
5378 #define mmPA_SC_SCREEN_SCISSOR_TL                                                                      0x000c
5379 #define mmPA_SC_SCREEN_SCISSOR_TL_BASE_IDX                                                             1
5380 #define mmPA_SC_SCREEN_SCISSOR_BR                                                                      0x000d
5381 #define mmPA_SC_SCREEN_SCISSOR_BR_BASE_IDX                                                             1
5382 #define mmDB_DFSM_CONTROL                                                                              0x000e
5383 #define mmDB_DFSM_CONTROL_BASE_IDX                                                                     1
5384 #define mmDB_RESERVED_REG_2                                                                            0x000f
5385 #define mmDB_RESERVED_REG_2_BASE_IDX                                                                   1
5386 #define mmDB_Z_INFO                                                                                    0x0010
5387 #define mmDB_Z_INFO_BASE_IDX                                                                           1
5388 #define mmDB_STENCIL_INFO                                                                              0x0011
5389 #define mmDB_STENCIL_INFO_BASE_IDX                                                                     1
5390 #define mmDB_Z_READ_BASE                                                                               0x0012
5391 #define mmDB_Z_READ_BASE_BASE_IDX                                                                      1
5392 #define mmDB_STENCIL_READ_BASE                                                                         0x0013
5393 #define mmDB_STENCIL_READ_BASE_BASE_IDX                                                                1
5394 #define mmDB_Z_WRITE_BASE                                                                              0x0014
5395 #define mmDB_Z_WRITE_BASE_BASE_IDX                                                                     1
5396 #define mmDB_STENCIL_WRITE_BASE                                                                        0x0015
5397 #define mmDB_STENCIL_WRITE_BASE_BASE_IDX                                                               1
5398 #define mmDB_RESERVED_REG_1                                                                            0x0016
5399 #define mmDB_RESERVED_REG_1_BASE_IDX                                                                   1
5400 #define mmDB_RESERVED_REG_3                                                                            0x0017
5401 #define mmDB_RESERVED_REG_3_BASE_IDX                                                                   1
5402 #define mmDB_VRS_OVERRIDE_CNTL                                                                         0x0019
5403 #define mmDB_VRS_OVERRIDE_CNTL_BASE_IDX                                                                1
5404 #define mmDB_Z_READ_BASE_HI                                                                            0x001a
5405 #define mmDB_Z_READ_BASE_HI_BASE_IDX                                                                   1
5406 #define mmDB_STENCIL_READ_BASE_HI                                                                      0x001b
5407 #define mmDB_STENCIL_READ_BASE_HI_BASE_IDX                                                             1
5408 #define mmDB_Z_WRITE_BASE_HI                                                                           0x001c
5409 #define mmDB_Z_WRITE_BASE_HI_BASE_IDX                                                                  1
5410 #define mmDB_STENCIL_WRITE_BASE_HI                                                                     0x001d
5411 #define mmDB_STENCIL_WRITE_BASE_HI_BASE_IDX                                                            1
5412 #define mmDB_HTILE_DATA_BASE_HI                                                                        0x001e
5413 #define mmDB_HTILE_DATA_BASE_HI_BASE_IDX                                                               1
5414 #define mmDB_RMI_L2_CACHE_CONTROL                                                                      0x001f
5415 #define mmDB_RMI_L2_CACHE_CONTROL_BASE_IDX                                                             1
5416 #define mmTA_BC_BASE_ADDR                                                                              0x0020
5417 #define mmTA_BC_BASE_ADDR_BASE_IDX                                                                     1
5418 #define mmTA_BC_BASE_ADDR_HI                                                                           0x0021
5419 #define mmTA_BC_BASE_ADDR_HI_BASE_IDX                                                                  1
5420 #define mmCOHER_DEST_BASE_HI_0                                                                         0x007a
5421 #define mmCOHER_DEST_BASE_HI_0_BASE_IDX                                                                1
5422 #define mmCOHER_DEST_BASE_HI_1                                                                         0x007b
5423 #define mmCOHER_DEST_BASE_HI_1_BASE_IDX                                                                1
5424 #define mmCOHER_DEST_BASE_HI_2                                                                         0x007c
5425 #define mmCOHER_DEST_BASE_HI_2_BASE_IDX                                                                1
5426 #define mmCOHER_DEST_BASE_HI_3                                                                         0x007d
5427 #define mmCOHER_DEST_BASE_HI_3_BASE_IDX                                                                1
5428 #define mmCOHER_DEST_BASE_2                                                                            0x007e
5429 #define mmCOHER_DEST_BASE_2_BASE_IDX                                                                   1
5430 #define mmCOHER_DEST_BASE_3                                                                            0x007f
5431 #define mmCOHER_DEST_BASE_3_BASE_IDX                                                                   1
5432 #define mmPA_SC_WINDOW_OFFSET                                                                          0x0080
5433 #define mmPA_SC_WINDOW_OFFSET_BASE_IDX                                                                 1
5434 #define mmPA_SC_WINDOW_SCISSOR_TL                                                                      0x0081
5435 #define mmPA_SC_WINDOW_SCISSOR_TL_BASE_IDX                                                             1
5436 #define mmPA_SC_WINDOW_SCISSOR_BR                                                                      0x0082
5437 #define mmPA_SC_WINDOW_SCISSOR_BR_BASE_IDX                                                             1
5438 #define mmPA_SC_CLIPRECT_RULE                                                                          0x0083
5439 #define mmPA_SC_CLIPRECT_RULE_BASE_IDX                                                                 1
5440 #define mmPA_SC_CLIPRECT_0_TL                                                                          0x0084
5441 #define mmPA_SC_CLIPRECT_0_TL_BASE_IDX                                                                 1
5442 #define mmPA_SC_CLIPRECT_0_BR                                                                          0x0085
5443 #define mmPA_SC_CLIPRECT_0_BR_BASE_IDX                                                                 1
5444 #define mmPA_SC_CLIPRECT_1_TL                                                                          0x0086
5445 #define mmPA_SC_CLIPRECT_1_TL_BASE_IDX                                                                 1
5446 #define mmPA_SC_CLIPRECT_1_BR                                                                          0x0087
5447 #define mmPA_SC_CLIPRECT_1_BR_BASE_IDX                                                                 1
5448 #define mmPA_SC_CLIPRECT_2_TL                                                                          0x0088
5449 #define mmPA_SC_CLIPRECT_2_TL_BASE_IDX                                                                 1
5450 #define mmPA_SC_CLIPRECT_2_BR                                                                          0x0089
5451 #define mmPA_SC_CLIPRECT_2_BR_BASE_IDX                                                                 1
5452 #define mmPA_SC_CLIPRECT_3_TL                                                                          0x008a
5453 #define mmPA_SC_CLIPRECT_3_TL_BASE_IDX                                                                 1
5454 #define mmPA_SC_CLIPRECT_3_BR                                                                          0x008b
5455 #define mmPA_SC_CLIPRECT_3_BR_BASE_IDX                                                                 1
5456 #define mmPA_SC_EDGERULE                                                                               0x008c
5457 #define mmPA_SC_EDGERULE_BASE_IDX                                                                      1
5458 #define mmPA_SU_HARDWARE_SCREEN_OFFSET                                                                 0x008d
5459 #define mmPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX                                                        1
5460 #define mmCB_TARGET_MASK                                                                               0x008e
5461 #define mmCB_TARGET_MASK_BASE_IDX                                                                      1
5462 #define mmCB_SHADER_MASK                                                                               0x008f
5463 #define mmCB_SHADER_MASK_BASE_IDX                                                                      1
5464 #define mmPA_SC_GENERIC_SCISSOR_TL                                                                     0x0090
5465 #define mmPA_SC_GENERIC_SCISSOR_TL_BASE_IDX                                                            1
5466 #define mmPA_SC_GENERIC_SCISSOR_BR                                                                     0x0091
5467 #define mmPA_SC_GENERIC_SCISSOR_BR_BASE_IDX                                                            1
5468 #define mmCOHER_DEST_BASE_0                                                                            0x0092
5469 #define mmCOHER_DEST_BASE_0_BASE_IDX                                                                   1
5470 #define mmCOHER_DEST_BASE_1                                                                            0x0093
5471 #define mmCOHER_DEST_BASE_1_BASE_IDX                                                                   1
5472 #define mmPA_SC_VPORT_SCISSOR_0_TL                                                                     0x0094
5473 #define mmPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX                                                            1
5474 #define mmPA_SC_VPORT_SCISSOR_0_BR                                                                     0x0095
5475 #define mmPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX                                                            1
5476 #define mmPA_SC_VPORT_SCISSOR_1_TL                                                                     0x0096
5477 #define mmPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX                                                            1
5478 #define mmPA_SC_VPORT_SCISSOR_1_BR                                                                     0x0097
5479 #define mmPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX                                                            1
5480 #define mmPA_SC_VPORT_SCISSOR_2_TL                                                                     0x0098
5481 #define mmPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX                                                            1
5482 #define mmPA_SC_VPORT_SCISSOR_2_BR                                                                     0x0099
5483 #define mmPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX                                                            1
5484 #define mmPA_SC_VPORT_SCISSOR_3_TL                                                                     0x009a
5485 #define mmPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX                                                            1
5486 #define mmPA_SC_VPORT_SCISSOR_3_BR                                                                     0x009b
5487 #define mmPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX                                                            1
5488 #define mmPA_SC_VPORT_SCISSOR_4_TL                                                                     0x009c
5489 #define mmPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX                                                            1
5490 #define mmPA_SC_VPORT_SCISSOR_4_BR                                                                     0x009d
5491 #define mmPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX                                                            1
5492 #define mmPA_SC_VPORT_SCISSOR_5_TL                                                                     0x009e
5493 #define mmPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX                                                            1
5494 #define mmPA_SC_VPORT_SCISSOR_5_BR                                                                     0x009f
5495 #define mmPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX                                                            1
5496 #define mmPA_SC_VPORT_SCISSOR_6_TL                                                                     0x00a0
5497 #define mmPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX                                                            1
5498 #define mmPA_SC_VPORT_SCISSOR_6_BR                                                                     0x00a1
5499 #define mmPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX                                                            1
5500 #define mmPA_SC_VPORT_SCISSOR_7_TL                                                                     0x00a2
5501 #define mmPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX                                                            1
5502 #define mmPA_SC_VPORT_SCISSOR_7_BR                                                                     0x00a3
5503 #define mmPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX                                                            1
5504 #define mmPA_SC_VPORT_SCISSOR_8_TL                                                                     0x00a4
5505 #define mmPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX                                                            1
5506 #define mmPA_SC_VPORT_SCISSOR_8_BR                                                                     0x00a5
5507 #define mmPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX                                                            1
5508 #define mmPA_SC_VPORT_SCISSOR_9_TL                                                                     0x00a6
5509 #define mmPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX                                                            1
5510 #define mmPA_SC_VPORT_SCISSOR_9_BR                                                                     0x00a7
5511 #define mmPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX                                                            1
5512 #define mmPA_SC_VPORT_SCISSOR_10_TL                                                                    0x00a8
5513 #define mmPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX                                                           1
5514 #define mmPA_SC_VPORT_SCISSOR_10_BR                                                                    0x00a9
5515 #define mmPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX                                                           1
5516 #define mmPA_SC_VPORT_SCISSOR_11_TL                                                                    0x00aa
5517 #define mmPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX                                                           1
5518 #define mmPA_SC_VPORT_SCISSOR_11_BR                                                                    0x00ab
5519 #define mmPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX                                                           1
5520 #define mmPA_SC_VPORT_SCISSOR_12_TL                                                                    0x00ac
5521 #define mmPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX                                                           1
5522 #define mmPA_SC_VPORT_SCISSOR_12_BR                                                                    0x00ad
5523 #define mmPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX                                                           1
5524 #define mmPA_SC_VPORT_SCISSOR_13_TL                                                                    0x00ae
5525 #define mmPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX                                                           1
5526 #define mmPA_SC_VPORT_SCISSOR_13_BR                                                                    0x00af
5527 #define mmPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX                                                           1
5528 #define mmPA_SC_VPORT_SCISSOR_14_TL                                                                    0x00b0
5529 #define mmPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX                                                           1
5530 #define mmPA_SC_VPORT_SCISSOR_14_BR                                                                    0x00b1
5531 #define mmPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX                                                           1
5532 #define mmPA_SC_VPORT_SCISSOR_15_TL                                                                    0x00b2
5533 #define mmPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX                                                           1
5534 #define mmPA_SC_VPORT_SCISSOR_15_BR                                                                    0x00b3
5535 #define mmPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX                                                           1
5536 #define mmPA_SC_VPORT_ZMIN_0                                                                           0x00b4
5537 #define mmPA_SC_VPORT_ZMIN_0_BASE_IDX                                                                  1
5538 #define mmPA_SC_VPORT_ZMAX_0                                                                           0x00b5
5539 #define mmPA_SC_VPORT_ZMAX_0_BASE_IDX                                                                  1
5540 #define mmPA_SC_VPORT_ZMIN_1                                                                           0x00b6
5541 #define mmPA_SC_VPORT_ZMIN_1_BASE_IDX                                                                  1
5542 #define mmPA_SC_VPORT_ZMAX_1                                                                           0x00b7
5543 #define mmPA_SC_VPORT_ZMAX_1_BASE_IDX                                                                  1
5544 #define mmPA_SC_VPORT_ZMIN_2                                                                           0x00b8
5545 #define mmPA_SC_VPORT_ZMIN_2_BASE_IDX                                                                  1
5546 #define mmPA_SC_VPORT_ZMAX_2                                                                           0x00b9
5547 #define mmPA_SC_VPORT_ZMAX_2_BASE_IDX                                                                  1
5548 #define mmPA_SC_VPORT_ZMIN_3                                                                           0x00ba
5549 #define mmPA_SC_VPORT_ZMIN_3_BASE_IDX                                                                  1
5550 #define mmPA_SC_VPORT_ZMAX_3                                                                           0x00bb
5551 #define mmPA_SC_VPORT_ZMAX_3_BASE_IDX                                                                  1
5552 #define mmPA_SC_VPORT_ZMIN_4                                                                           0x00bc
5553 #define mmPA_SC_VPORT_ZMIN_4_BASE_IDX                                                                  1
5554 #define mmPA_SC_VPORT_ZMAX_4                                                                           0x00bd
5555 #define mmPA_SC_VPORT_ZMAX_4_BASE_IDX                                                                  1
5556 #define mmPA_SC_VPORT_ZMIN_5                                                                           0x00be
5557 #define mmPA_SC_VPORT_ZMIN_5_BASE_IDX                                                                  1
5558 #define mmPA_SC_VPORT_ZMAX_5                                                                           0x00bf
5559 #define mmPA_SC_VPORT_ZMAX_5_BASE_IDX                                                                  1
5560 #define mmPA_SC_VPORT_ZMIN_6                                                                           0x00c0
5561 #define mmPA_SC_VPORT_ZMIN_6_BASE_IDX                                                                  1
5562 #define mmPA_SC_VPORT_ZMAX_6                                                                           0x00c1
5563 #define mmPA_SC_VPORT_ZMAX_6_BASE_IDX                                                                  1
5564 #define mmPA_SC_VPORT_ZMIN_7                                                                           0x00c2
5565 #define mmPA_SC_VPORT_ZMIN_7_BASE_IDX                                                                  1
5566 #define mmPA_SC_VPORT_ZMAX_7                                                                           0x00c3
5567 #define mmPA_SC_VPORT_ZMAX_7_BASE_IDX                                                                  1
5568 #define mmPA_SC_VPORT_ZMIN_8                                                                           0x00c4
5569 #define mmPA_SC_VPORT_ZMIN_8_BASE_IDX                                                                  1
5570 #define mmPA_SC_VPORT_ZMAX_8                                                                           0x00c5
5571 #define mmPA_SC_VPORT_ZMAX_8_BASE_IDX                                                                  1
5572 #define mmPA_SC_VPORT_ZMIN_9                                                                           0x00c6
5573 #define mmPA_SC_VPORT_ZMIN_9_BASE_IDX                                                                  1
5574 #define mmPA_SC_VPORT_ZMAX_9                                                                           0x00c7
5575 #define mmPA_SC_VPORT_ZMAX_9_BASE_IDX                                                                  1
5576 #define mmPA_SC_VPORT_ZMIN_10                                                                          0x00c8
5577 #define mmPA_SC_VPORT_ZMIN_10_BASE_IDX                                                                 1
5578 #define mmPA_SC_VPORT_ZMAX_10                                                                          0x00c9
5579 #define mmPA_SC_VPORT_ZMAX_10_BASE_IDX                                                                 1
5580 #define mmPA_SC_VPORT_ZMIN_11                                                                          0x00ca
5581 #define mmPA_SC_VPORT_ZMIN_11_BASE_IDX                                                                 1
5582 #define mmPA_SC_VPORT_ZMAX_11                                                                          0x00cb
5583 #define mmPA_SC_VPORT_ZMAX_11_BASE_IDX                                                                 1
5584 #define mmPA_SC_VPORT_ZMIN_12                                                                          0x00cc
5585 #define mmPA_SC_VPORT_ZMIN_12_BASE_IDX                                                                 1
5586 #define mmPA_SC_VPORT_ZMAX_12                                                                          0x00cd
5587 #define mmPA_SC_VPORT_ZMAX_12_BASE_IDX                                                                 1
5588 #define mmPA_SC_VPORT_ZMIN_13                                                                          0x00ce
5589 #define mmPA_SC_VPORT_ZMIN_13_BASE_IDX                                                                 1
5590 #define mmPA_SC_VPORT_ZMAX_13                                                                          0x00cf
5591 #define mmPA_SC_VPORT_ZMAX_13_BASE_IDX                                                                 1
5592 #define mmPA_SC_VPORT_ZMIN_14                                                                          0x00d0
5593 #define mmPA_SC_VPORT_ZMIN_14_BASE_IDX                                                                 1
5594 #define mmPA_SC_VPORT_ZMAX_14                                                                          0x00d1
5595 #define mmPA_SC_VPORT_ZMAX_14_BASE_IDX                                                                 1
5596 #define mmPA_SC_VPORT_ZMIN_15                                                                          0x00d2
5597 #define mmPA_SC_VPORT_ZMIN_15_BASE_IDX                                                                 1
5598 #define mmPA_SC_VPORT_ZMAX_15                                                                          0x00d3
5599 #define mmPA_SC_VPORT_ZMAX_15_BASE_IDX                                                                 1
5600 #define mmPA_SC_RASTER_CONFIG                                                                          0x00d4
5601 #define mmPA_SC_RASTER_CONFIG_BASE_IDX                                                                 1
5602 #define mmPA_SC_RASTER_CONFIG_1                                                                        0x00d5
5603 #define mmPA_SC_RASTER_CONFIG_1_BASE_IDX                                                               1
5604 #define mmPA_SC_SCREEN_EXTENT_CONTROL                                                                  0x00d6
5605 #define mmPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX                                                         1
5606 #define mmPA_SC_TILE_STEERING_OVERRIDE                                                                 0x00d7
5607 #define mmPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX                                                        1
5608 #define mmCP_PERFMON_CNTX_CNTL                                                                         0x00d8
5609 #define mmCP_PERFMON_CNTX_CNTL_BASE_IDX                                                                1
5610 #define mmCP_PIPEID                                                                                    0x00d9
5611 #define mmCP_PIPEID_BASE_IDX                                                                           1
5612 #define mmCP_RINGID                                                                                    0x00d9
5613 #define mmCP_RINGID_BASE_IDX                                                                           1
5614 #define mmCP_VMID                                                                                      0x00da
5615 #define mmCP_VMID_BASE_IDX                                                                             1
5616 #define mmCONTEXT_RESERVED_REG0                                                                        0x00db
5617 #define mmCONTEXT_RESERVED_REG0_BASE_IDX                                                               1
5618 #define mmCONTEXT_RESERVED_REG1                                                                        0x00dc
5619 #define mmCONTEXT_RESERVED_REG1_BASE_IDX                                                               1
5620 #define mmVGT_MAX_VTX_INDX                                                                             0x0100
5621 #define mmVGT_MAX_VTX_INDX_BASE_IDX                                                                    1
5622 #define mmVGT_MIN_VTX_INDX                                                                             0x0101
5623 #define mmVGT_MIN_VTX_INDX_BASE_IDX                                                                    1
5624 #define mmVGT_INDX_OFFSET                                                                              0x0102
5625 #define mmVGT_INDX_OFFSET_BASE_IDX                                                                     1
5626 #define mmVGT_MULTI_PRIM_IB_RESET_INDX                                                                 0x0103
5627 #define mmVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX                                                        1
5628 #define mmCB_RMI_GL2_CACHE_CONTROL                                                                     0x0104
5629 #define mmCB_RMI_GL2_CACHE_CONTROL_BASE_IDX                                                            1
5630 #define mmCB_BLEND_RED                                                                                 0x0105
5631 #define mmCB_BLEND_RED_BASE_IDX                                                                        1
5632 #define mmCB_BLEND_GREEN                                                                               0x0106
5633 #define mmCB_BLEND_GREEN_BASE_IDX                                                                      1
5634 #define mmCB_BLEND_BLUE                                                                                0x0107
5635 #define mmCB_BLEND_BLUE_BASE_IDX                                                                       1
5636 #define mmCB_BLEND_ALPHA                                                                               0x0108
5637 #define mmCB_BLEND_ALPHA_BASE_IDX                                                                      1
5638 #define mmCB_DCC_CONTROL                                                                               0x0109
5639 #define mmCB_DCC_CONTROL_BASE_IDX                                                                      1
5640 #define mmCB_COVERAGE_OUT_CONTROL                                                                      0x010a
5641 #define mmCB_COVERAGE_OUT_CONTROL_BASE_IDX                                                             1
5642 #define mmDB_STENCIL_CONTROL                                                                           0x010b
5643 #define mmDB_STENCIL_CONTROL_BASE_IDX                                                                  1
5644 #define mmDB_STENCILREFMASK                                                                            0x010c
5645 #define mmDB_STENCILREFMASK_BASE_IDX                                                                   1
5646 #define mmDB_STENCILREFMASK_BF                                                                         0x010d
5647 #define mmDB_STENCILREFMASK_BF_BASE_IDX                                                                1
5648 #define mmPA_CL_VPORT_XSCALE                                                                           0x010f
5649 #define mmPA_CL_VPORT_XSCALE_BASE_IDX                                                                  1
5650 #define mmPA_CL_VPORT_XOFFSET                                                                          0x0110
5651 #define mmPA_CL_VPORT_XOFFSET_BASE_IDX                                                                 1
5652 #define mmPA_CL_VPORT_YSCALE                                                                           0x0111
5653 #define mmPA_CL_VPORT_YSCALE_BASE_IDX                                                                  1
5654 #define mmPA_CL_VPORT_YOFFSET                                                                          0x0112
5655 #define mmPA_CL_VPORT_YOFFSET_BASE_IDX                                                                 1
5656 #define mmPA_CL_VPORT_ZSCALE                                                                           0x0113
5657 #define mmPA_CL_VPORT_ZSCALE_BASE_IDX                                                                  1
5658 #define mmPA_CL_VPORT_ZOFFSET                                                                          0x0114
5659 #define mmPA_CL_VPORT_ZOFFSET_BASE_IDX                                                                 1
5660 #define mmPA_CL_VPORT_XSCALE_1                                                                         0x0115
5661 #define mmPA_CL_VPORT_XSCALE_1_BASE_IDX                                                                1
5662 #define mmPA_CL_VPORT_XOFFSET_1                                                                        0x0116
5663 #define mmPA_CL_VPORT_XOFFSET_1_BASE_IDX                                                               1
5664 #define mmPA_CL_VPORT_YSCALE_1                                                                         0x0117
5665 #define mmPA_CL_VPORT_YSCALE_1_BASE_IDX                                                                1
5666 #define mmPA_CL_VPORT_YOFFSET_1                                                                        0x0118
5667 #define mmPA_CL_VPORT_YOFFSET_1_BASE_IDX                                                               1
5668 #define mmPA_CL_VPORT_ZSCALE_1                                                                         0x0119
5669 #define mmPA_CL_VPORT_ZSCALE_1_BASE_IDX                                                                1
5670 #define mmPA_CL_VPORT_ZOFFSET_1                                                                        0x011a
5671 #define mmPA_CL_VPORT_ZOFFSET_1_BASE_IDX                                                               1
5672 #define mmPA_CL_VPORT_XSCALE_2                                                                         0x011b
5673 #define mmPA_CL_VPORT_XSCALE_2_BASE_IDX                                                                1
5674 #define mmPA_CL_VPORT_XOFFSET_2                                                                        0x011c
5675 #define mmPA_CL_VPORT_XOFFSET_2_BASE_IDX                                                               1
5676 #define mmPA_CL_VPORT_YSCALE_2                                                                         0x011d
5677 #define mmPA_CL_VPORT_YSCALE_2_BASE_IDX                                                                1
5678 #define mmPA_CL_VPORT_YOFFSET_2                                                                        0x011e
5679 #define mmPA_CL_VPORT_YOFFSET_2_BASE_IDX                                                               1
5680 #define mmPA_CL_VPORT_ZSCALE_2                                                                         0x011f
5681 #define mmPA_CL_VPORT_ZSCALE_2_BASE_IDX                                                                1
5682 #define mmPA_CL_VPORT_ZOFFSET_2                                                                        0x0120
5683 #define mmPA_CL_VPORT_ZOFFSET_2_BASE_IDX                                                               1
5684 #define mmPA_CL_VPORT_XSCALE_3                                                                         0x0121
5685 #define mmPA_CL_VPORT_XSCALE_3_BASE_IDX                                                                1
5686 #define mmPA_CL_VPORT_XOFFSET_3                                                                        0x0122
5687 #define mmPA_CL_VPORT_XOFFSET_3_BASE_IDX                                                               1
5688 #define mmPA_CL_VPORT_YSCALE_3                                                                         0x0123
5689 #define mmPA_CL_VPORT_YSCALE_3_BASE_IDX                                                                1
5690 #define mmPA_CL_VPORT_YOFFSET_3                                                                        0x0124
5691 #define mmPA_CL_VPORT_YOFFSET_3_BASE_IDX                                                               1
5692 #define mmPA_CL_VPORT_ZSCALE_3                                                                         0x0125
5693 #define mmPA_CL_VPORT_ZSCALE_3_BASE_IDX                                                                1
5694 #define mmPA_CL_VPORT_ZOFFSET_3                                                                        0x0126
5695 #define mmPA_CL_VPORT_ZOFFSET_3_BASE_IDX                                                               1
5696 #define mmPA_CL_VPORT_XSCALE_4                                                                         0x0127
5697 #define mmPA_CL_VPORT_XSCALE_4_BASE_IDX                                                                1
5698 #define mmPA_CL_VPORT_XOFFSET_4                                                                        0x0128
5699 #define mmPA_CL_VPORT_XOFFSET_4_BASE_IDX                                                               1
5700 #define mmPA_CL_VPORT_YSCALE_4                                                                         0x0129
5701 #define mmPA_CL_VPORT_YSCALE_4_BASE_IDX                                                                1
5702 #define mmPA_CL_VPORT_YOFFSET_4                                                                        0x012a
5703 #define mmPA_CL_VPORT_YOFFSET_4_BASE_IDX                                                               1
5704 #define mmPA_CL_VPORT_ZSCALE_4                                                                         0x012b
5705 #define mmPA_CL_VPORT_ZSCALE_4_BASE_IDX                                                                1
5706 #define mmPA_CL_VPORT_ZOFFSET_4                                                                        0x012c
5707 #define mmPA_CL_VPORT_ZOFFSET_4_BASE_IDX                                                               1
5708 #define mmPA_CL_VPORT_XSCALE_5                                                                         0x012d
5709 #define mmPA_CL_VPORT_XSCALE_5_BASE_IDX                                                                1
5710 #define mmPA_CL_VPORT_XOFFSET_5                                                                        0x012e
5711 #define mmPA_CL_VPORT_XOFFSET_5_BASE_IDX                                                               1
5712 #define mmPA_CL_VPORT_YSCALE_5                                                                         0x012f
5713 #define mmPA_CL_VPORT_YSCALE_5_BASE_IDX                                                                1
5714 #define mmPA_CL_VPORT_YOFFSET_5                                                                        0x0130
5715 #define mmPA_CL_VPORT_YOFFSET_5_BASE_IDX                                                               1
5716 #define mmPA_CL_VPORT_ZSCALE_5                                                                         0x0131
5717 #define mmPA_CL_VPORT_ZSCALE_5_BASE_IDX                                                                1
5718 #define mmPA_CL_VPORT_ZOFFSET_5                                                                        0x0132
5719 #define mmPA_CL_VPORT_ZOFFSET_5_BASE_IDX                                                               1
5720 #define mmPA_CL_VPORT_XSCALE_6                                                                         0x0133
5721 #define mmPA_CL_VPORT_XSCALE_6_BASE_IDX                                                                1
5722 #define mmPA_CL_VPORT_XOFFSET_6                                                                        0x0134
5723 #define mmPA_CL_VPORT_XOFFSET_6_BASE_IDX                                                               1
5724 #define mmPA_CL_VPORT_YSCALE_6                                                                         0x0135
5725 #define mmPA_CL_VPORT_YSCALE_6_BASE_IDX                                                                1
5726 #define mmPA_CL_VPORT_YOFFSET_6                                                                        0x0136
5727 #define mmPA_CL_VPORT_YOFFSET_6_BASE_IDX                                                               1
5728 #define mmPA_CL_VPORT_ZSCALE_6                                                                         0x0137
5729 #define mmPA_CL_VPORT_ZSCALE_6_BASE_IDX                                                                1
5730 #define mmPA_CL_VPORT_ZOFFSET_6                                                                        0x0138
5731 #define mmPA_CL_VPORT_ZOFFSET_6_BASE_IDX                                                               1
5732 #define mmPA_CL_VPORT_XSCALE_7                                                                         0x0139
5733 #define mmPA_CL_VPORT_XSCALE_7_BASE_IDX                                                                1
5734 #define mmPA_CL_VPORT_XOFFSET_7                                                                        0x013a
5735 #define mmPA_CL_VPORT_XOFFSET_7_BASE_IDX                                                               1
5736 #define mmPA_CL_VPORT_YSCALE_7                                                                         0x013b
5737 #define mmPA_CL_VPORT_YSCALE_7_BASE_IDX                                                                1
5738 #define mmPA_CL_VPORT_YOFFSET_7                                                                        0x013c
5739 #define mmPA_CL_VPORT_YOFFSET_7_BASE_IDX                                                               1
5740 #define mmPA_CL_VPORT_ZSCALE_7                                                                         0x013d
5741 #define mmPA_CL_VPORT_ZSCALE_7_BASE_IDX                                                                1
5742 #define mmPA_CL_VPORT_ZOFFSET_7                                                                        0x013e
5743 #define mmPA_CL_VPORT_ZOFFSET_7_BASE_IDX                                                               1
5744 #define mmPA_CL_VPORT_XSCALE_8                                                                         0x013f
5745 #define mmPA_CL_VPORT_XSCALE_8_BASE_IDX                                                                1
5746 #define mmPA_CL_VPORT_XOFFSET_8                                                                        0x0140
5747 #define mmPA_CL_VPORT_XOFFSET_8_BASE_IDX                                                               1
5748 #define mmPA_CL_VPORT_YSCALE_8                                                                         0x0141
5749 #define mmPA_CL_VPORT_YSCALE_8_BASE_IDX                                                                1
5750 #define mmPA_CL_VPORT_YOFFSET_8                                                                        0x0142
5751 #define mmPA_CL_VPORT_YOFFSET_8_BASE_IDX                                                               1
5752 #define mmPA_CL_VPORT_ZSCALE_8                                                                         0x0143
5753 #define mmPA_CL_VPORT_ZSCALE_8_BASE_IDX                                                                1
5754 #define mmPA_CL_VPORT_ZOFFSET_8                                                                        0x0144
5755 #define mmPA_CL_VPORT_ZOFFSET_8_BASE_IDX                                                               1
5756 #define mmPA_CL_VPORT_XSCALE_9                                                                         0x0145
5757 #define mmPA_CL_VPORT_XSCALE_9_BASE_IDX                                                                1
5758 #define mmPA_CL_VPORT_XOFFSET_9                                                                        0x0146
5759 #define mmPA_CL_VPORT_XOFFSET_9_BASE_IDX                                                               1
5760 #define mmPA_CL_VPORT_YSCALE_9                                                                         0x0147
5761 #define mmPA_CL_VPORT_YSCALE_9_BASE_IDX                                                                1
5762 #define mmPA_CL_VPORT_YOFFSET_9                                                                        0x0148
5763 #define mmPA_CL_VPORT_YOFFSET_9_BASE_IDX                                                               1
5764 #define mmPA_CL_VPORT_ZSCALE_9                                                                         0x0149
5765 #define mmPA_CL_VPORT_ZSCALE_9_BASE_IDX                                                                1
5766 #define mmPA_CL_VPORT_ZOFFSET_9                                                                        0x014a
5767 #define mmPA_CL_VPORT_ZOFFSET_9_BASE_IDX                                                               1
5768 #define mmPA_CL_VPORT_XSCALE_10                                                                        0x014b
5769 #define mmPA_CL_VPORT_XSCALE_10_BASE_IDX                                                               1
5770 #define mmPA_CL_VPORT_XOFFSET_10                                                                       0x014c
5771 #define mmPA_CL_VPORT_XOFFSET_10_BASE_IDX                                                              1
5772 #define mmPA_CL_VPORT_YSCALE_10                                                                        0x014d
5773 #define mmPA_CL_VPORT_YSCALE_10_BASE_IDX                                                               1
5774 #define mmPA_CL_VPORT_YOFFSET_10                                                                       0x014e
5775 #define mmPA_CL_VPORT_YOFFSET_10_BASE_IDX                                                              1
5776 #define mmPA_CL_VPORT_ZSCALE_10                                                                        0x014f
5777 #define mmPA_CL_VPORT_ZSCALE_10_BASE_IDX                                                               1
5778 #define mmPA_CL_VPORT_ZOFFSET_10                                                                       0x0150
5779 #define mmPA_CL_VPORT_ZOFFSET_10_BASE_IDX                                                              1
5780 #define mmPA_CL_VPORT_XSCALE_11                                                                        0x0151
5781 #define mmPA_CL_VPORT_XSCALE_11_BASE_IDX                                                               1
5782 #define mmPA_CL_VPORT_XOFFSET_11                                                                       0x0152
5783 #define mmPA_CL_VPORT_XOFFSET_11_BASE_IDX                                                              1
5784 #define mmPA_CL_VPORT_YSCALE_11                                                                        0x0153
5785 #define mmPA_CL_VPORT_YSCALE_11_BASE_IDX                                                               1
5786 #define mmPA_CL_VPORT_YOFFSET_11                                                                       0x0154
5787 #define mmPA_CL_VPORT_YOFFSET_11_BASE_IDX                                                              1
5788 #define mmPA_CL_VPORT_ZSCALE_11                                                                        0x0155
5789 #define mmPA_CL_VPORT_ZSCALE_11_BASE_IDX                                                               1
5790 #define mmPA_CL_VPORT_ZOFFSET_11                                                                       0x0156
5791 #define mmPA_CL_VPORT_ZOFFSET_11_BASE_IDX                                                              1
5792 #define mmPA_CL_VPORT_XSCALE_12                                                                        0x0157
5793 #define mmPA_CL_VPORT_XSCALE_12_BASE_IDX                                                               1
5794 #define mmPA_CL_VPORT_XOFFSET_12                                                                       0x0158
5795 #define mmPA_CL_VPORT_XOFFSET_12_BASE_IDX                                                              1
5796 #define mmPA_CL_VPORT_YSCALE_12                                                                        0x0159
5797 #define mmPA_CL_VPORT_YSCALE_12_BASE_IDX                                                               1
5798 #define mmPA_CL_VPORT_YOFFSET_12                                                                       0x015a
5799 #define mmPA_CL_VPORT_YOFFSET_12_BASE_IDX                                                              1
5800 #define mmPA_CL_VPORT_ZSCALE_12                                                                        0x015b
5801 #define mmPA_CL_VPORT_ZSCALE_12_BASE_IDX                                                               1
5802 #define mmPA_CL_VPORT_ZOFFSET_12                                                                       0x015c
5803 #define mmPA_CL_VPORT_ZOFFSET_12_BASE_IDX                                                              1
5804 #define mmPA_CL_VPORT_XSCALE_13                                                                        0x015d
5805 #define mmPA_CL_VPORT_XSCALE_13_BASE_IDX                                                               1
5806 #define mmPA_CL_VPORT_XOFFSET_13                                                                       0x015e
5807 #define mmPA_CL_VPORT_XOFFSET_13_BASE_IDX                                                              1
5808 #define mmPA_CL_VPORT_YSCALE_13                                                                        0x015f
5809 #define mmPA_CL_VPORT_YSCALE_13_BASE_IDX                                                               1
5810 #define mmPA_CL_VPORT_YOFFSET_13                                                                       0x0160
5811 #define mmPA_CL_VPORT_YOFFSET_13_BASE_IDX                                                              1
5812 #define mmPA_CL_VPORT_ZSCALE_13                                                                        0x0161
5813 #define mmPA_CL_VPORT_ZSCALE_13_BASE_IDX                                                               1
5814 #define mmPA_CL_VPORT_ZOFFSET_13                                                                       0x0162
5815 #define mmPA_CL_VPORT_ZOFFSET_13_BASE_IDX                                                              1
5816 #define mmPA_CL_VPORT_XSCALE_14                                                                        0x0163
5817 #define mmPA_CL_VPORT_XSCALE_14_BASE_IDX                                                               1
5818 #define mmPA_CL_VPORT_XOFFSET_14                                                                       0x0164
5819 #define mmPA_CL_VPORT_XOFFSET_14_BASE_IDX                                                              1
5820 #define mmPA_CL_VPORT_YSCALE_14                                                                        0x0165
5821 #define mmPA_CL_VPORT_YSCALE_14_BASE_IDX                                                               1
5822 #define mmPA_CL_VPORT_YOFFSET_14                                                                       0x0166
5823 #define mmPA_CL_VPORT_YOFFSET_14_BASE_IDX                                                              1
5824 #define mmPA_CL_VPORT_ZSCALE_14                                                                        0x0167
5825 #define mmPA_CL_VPORT_ZSCALE_14_BASE_IDX                                                               1
5826 #define mmPA_CL_VPORT_ZOFFSET_14                                                                       0x0168
5827 #define mmPA_CL_VPORT_ZOFFSET_14_BASE_IDX                                                              1
5828 #define mmPA_CL_VPORT_XSCALE_15                                                                        0x0169
5829 #define mmPA_CL_VPORT_XSCALE_15_BASE_IDX                                                               1
5830 #define mmPA_CL_VPORT_XOFFSET_15                                                                       0x016a
5831 #define mmPA_CL_VPORT_XOFFSET_15_BASE_IDX                                                              1
5832 #define mmPA_CL_VPORT_YSCALE_15                                                                        0x016b
5833 #define mmPA_CL_VPORT_YSCALE_15_BASE_IDX                                                               1
5834 #define mmPA_CL_VPORT_YOFFSET_15                                                                       0x016c
5835 #define mmPA_CL_VPORT_YOFFSET_15_BASE_IDX                                                              1
5836 #define mmPA_CL_VPORT_ZSCALE_15                                                                        0x016d
5837 #define mmPA_CL_VPORT_ZSCALE_15_BASE_IDX                                                               1
5838 #define mmPA_CL_VPORT_ZOFFSET_15                                                                       0x016e
5839 #define mmPA_CL_VPORT_ZOFFSET_15_BASE_IDX                                                              1
5840 #define mmPA_CL_UCP_0_X                                                                                0x016f
5841 #define mmPA_CL_UCP_0_X_BASE_IDX                                                                       1
5842 #define mmPA_CL_UCP_0_Y                                                                                0x0170
5843 #define mmPA_CL_UCP_0_Y_BASE_IDX                                                                       1
5844 #define mmPA_CL_UCP_0_Z                                                                                0x0171
5845 #define mmPA_CL_UCP_0_Z_BASE_IDX                                                                       1
5846 #define mmPA_CL_UCP_0_W                                                                                0x0172
5847 #define mmPA_CL_UCP_0_W_BASE_IDX                                                                       1
5848 #define mmPA_CL_UCP_1_X                                                                                0x0173
5849 #define mmPA_CL_UCP_1_X_BASE_IDX                                                                       1
5850 #define mmPA_CL_UCP_1_Y                                                                                0x0174
5851 #define mmPA_CL_UCP_1_Y_BASE_IDX                                                                       1
5852 #define mmPA_CL_UCP_1_Z                                                                                0x0175
5853 #define mmPA_CL_UCP_1_Z_BASE_IDX                                                                       1
5854 #define mmPA_CL_UCP_1_W                                                                                0x0176
5855 #define mmPA_CL_UCP_1_W_BASE_IDX                                                                       1
5856 #define mmPA_CL_UCP_2_X                                                                                0x0177
5857 #define mmPA_CL_UCP_2_X_BASE_IDX                                                                       1
5858 #define mmPA_CL_UCP_2_Y                                                                                0x0178
5859 #define mmPA_CL_UCP_2_Y_BASE_IDX                                                                       1
5860 #define mmPA_CL_UCP_2_Z                                                                                0x0179
5861 #define mmPA_CL_UCP_2_Z_BASE_IDX                                                                       1
5862 #define mmPA_CL_UCP_2_W                                                                                0x017a
5863 #define mmPA_CL_UCP_2_W_BASE_IDX                                                                       1
5864 #define mmPA_CL_UCP_3_X                                                                                0x017b
5865 #define mmPA_CL_UCP_3_X_BASE_IDX                                                                       1
5866 #define mmPA_CL_UCP_3_Y                                                                                0x017c
5867 #define mmPA_CL_UCP_3_Y_BASE_IDX                                                                       1
5868 #define mmPA_CL_UCP_3_Z                                                                                0x017d
5869 #define mmPA_CL_UCP_3_Z_BASE_IDX                                                                       1
5870 #define mmPA_CL_UCP_3_W                                                                                0x017e
5871 #define mmPA_CL_UCP_3_W_BASE_IDX                                                                       1
5872 #define mmPA_CL_UCP_4_X                                                                                0x017f
5873 #define mmPA_CL_UCP_4_X_BASE_IDX                                                                       1
5874 #define mmPA_CL_UCP_4_Y                                                                                0x0180
5875 #define mmPA_CL_UCP_4_Y_BASE_IDX                                                                       1
5876 #define mmPA_CL_UCP_4_Z                                                                                0x0181
5877 #define mmPA_CL_UCP_4_Z_BASE_IDX                                                                       1
5878 #define mmPA_CL_UCP_4_W                                                                                0x0182
5879 #define mmPA_CL_UCP_4_W_BASE_IDX                                                                       1
5880 #define mmPA_CL_UCP_5_X                                                                                0x0183
5881 #define mmPA_CL_UCP_5_X_BASE_IDX                                                                       1
5882 #define mmPA_CL_UCP_5_Y                                                                                0x0184
5883 #define mmPA_CL_UCP_5_Y_BASE_IDX                                                                       1
5884 #define mmPA_CL_UCP_5_Z                                                                                0x0185
5885 #define mmPA_CL_UCP_5_Z_BASE_IDX                                                                       1
5886 #define mmPA_CL_UCP_5_W                                                                                0x0186
5887 #define mmPA_CL_UCP_5_W_BASE_IDX                                                                       1
5888 #define mmPA_CL_PROG_NEAR_CLIP_Z                                                                       0x0187
5889 #define mmPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX                                                              1
5890 #define mmSPI_PS_INPUT_CNTL_0                                                                          0x0191
5891 #define mmSPI_PS_INPUT_CNTL_0_BASE_IDX                                                                 1
5892 #define mmSPI_PS_INPUT_CNTL_1                                                                          0x0192
5893 #define mmSPI_PS_INPUT_CNTL_1_BASE_IDX                                                                 1
5894 #define mmSPI_PS_INPUT_CNTL_2                                                                          0x0193
5895 #define mmSPI_PS_INPUT_CNTL_2_BASE_IDX                                                                 1
5896 #define mmSPI_PS_INPUT_CNTL_3                                                                          0x0194
5897 #define mmSPI_PS_INPUT_CNTL_3_BASE_IDX                                                                 1
5898 #define mmSPI_PS_INPUT_CNTL_4                                                                          0x0195
5899 #define mmSPI_PS_INPUT_CNTL_4_BASE_IDX                                                                 1
5900 #define mmSPI_PS_INPUT_CNTL_5                                                                          0x0196
5901 #define mmSPI_PS_INPUT_CNTL_5_BASE_IDX                                                                 1
5902 #define mmSPI_PS_INPUT_CNTL_6                                                                          0x0197
5903 #define mmSPI_PS_INPUT_CNTL_6_BASE_IDX                                                                 1
5904 #define mmSPI_PS_INPUT_CNTL_7                                                                          0x0198
5905 #define mmSPI_PS_INPUT_CNTL_7_BASE_IDX                                                                 1
5906 #define mmSPI_PS_INPUT_CNTL_8                                                                          0x0199
5907 #define mmSPI_PS_INPUT_CNTL_8_BASE_IDX                                                                 1
5908 #define mmSPI_PS_INPUT_CNTL_9                                                                          0x019a
5909 #define mmSPI_PS_INPUT_CNTL_9_BASE_IDX                                                                 1
5910 #define mmSPI_PS_INPUT_CNTL_10                                                                         0x019b
5911 #define mmSPI_PS_INPUT_CNTL_10_BASE_IDX                                                                1
5912 #define mmSPI_PS_INPUT_CNTL_11                                                                         0x019c
5913 #define mmSPI_PS_INPUT_CNTL_11_BASE_IDX                                                                1
5914 #define mmSPI_PS_INPUT_CNTL_12                                                                         0x019d
5915 #define mmSPI_PS_INPUT_CNTL_12_BASE_IDX                                                                1
5916 #define mmSPI_PS_INPUT_CNTL_13                                                                         0x019e
5917 #define mmSPI_PS_INPUT_CNTL_13_BASE_IDX                                                                1
5918 #define mmSPI_PS_INPUT_CNTL_14                                                                         0x019f
5919 #define mmSPI_PS_INPUT_CNTL_14_BASE_IDX                                                                1
5920 #define mmSPI_PS_INPUT_CNTL_15                                                                         0x01a0
5921 #define mmSPI_PS_INPUT_CNTL_15_BASE_IDX                                                                1
5922 #define mmSPI_PS_INPUT_CNTL_16                                                                         0x01a1
5923 #define mmSPI_PS_INPUT_CNTL_16_BASE_IDX                                                                1
5924 #define mmSPI_PS_INPUT_CNTL_17                                                                         0x01a2
5925 #define mmSPI_PS_INPUT_CNTL_17_BASE_IDX                                                                1
5926 #define mmSPI_PS_INPUT_CNTL_18                                                                         0x01a3
5927 #define mmSPI_PS_INPUT_CNTL_18_BASE_IDX                                                                1
5928 #define mmSPI_PS_INPUT_CNTL_19                                                                         0x01a4
5929 #define mmSPI_PS_INPUT_CNTL_19_BASE_IDX                                                                1
5930 #define mmSPI_PS_INPUT_CNTL_20                                                                         0x01a5
5931 #define mmSPI_PS_INPUT_CNTL_20_BASE_IDX                                                                1
5932 #define mmSPI_PS_INPUT_CNTL_21                                                                         0x01a6
5933 #define mmSPI_PS_INPUT_CNTL_21_BASE_IDX                                                                1
5934 #define mmSPI_PS_INPUT_CNTL_22                                                                         0x01a7
5935 #define mmSPI_PS_INPUT_CNTL_22_BASE_IDX                                                                1
5936 #define mmSPI_PS_INPUT_CNTL_23                                                                         0x01a8
5937 #define mmSPI_PS_INPUT_CNTL_23_BASE_IDX                                                                1
5938 #define mmSPI_PS_INPUT_CNTL_24                                                                         0x01a9
5939 #define mmSPI_PS_INPUT_CNTL_24_BASE_IDX                                                                1
5940 #define mmSPI_PS_INPUT_CNTL_25                                                                         0x01aa
5941 #define mmSPI_PS_INPUT_CNTL_25_BASE_IDX                                                                1
5942 #define mmSPI_PS_INPUT_CNTL_26                                                                         0x01ab
5943 #define mmSPI_PS_INPUT_CNTL_26_BASE_IDX                                                                1
5944 #define mmSPI_PS_INPUT_CNTL_27                                                                         0x01ac
5945 #define mmSPI_PS_INPUT_CNTL_27_BASE_IDX                                                                1
5946 #define mmSPI_PS_INPUT_CNTL_28                                                                         0x01ad
5947 #define mmSPI_PS_INPUT_CNTL_28_BASE_IDX                                                                1
5948 #define mmSPI_PS_INPUT_CNTL_29                                                                         0x01ae
5949 #define mmSPI_PS_INPUT_CNTL_29_BASE_IDX                                                                1
5950 #define mmSPI_PS_INPUT_CNTL_30                                                                         0x01af
5951 #define mmSPI_PS_INPUT_CNTL_30_BASE_IDX                                                                1
5952 #define mmSPI_PS_INPUT_CNTL_31                                                                         0x01b0
5953 #define mmSPI_PS_INPUT_CNTL_31_BASE_IDX                                                                1
5954 #define mmSPI_VS_OUT_CONFIG                                                                            0x01b1
5955 #define mmSPI_VS_OUT_CONFIG_BASE_IDX                                                                   1
5956 #define mmSPI_PS_INPUT_ENA                                                                             0x01b3
5957 #define mmSPI_PS_INPUT_ENA_BASE_IDX                                                                    1
5958 #define mmSPI_PS_INPUT_ADDR                                                                            0x01b4
5959 #define mmSPI_PS_INPUT_ADDR_BASE_IDX                                                                   1
5960 #define mmSPI_INTERP_CONTROL_0                                                                         0x01b5
5961 #define mmSPI_INTERP_CONTROL_0_BASE_IDX                                                                1
5962 #define mmSPI_PS_IN_CONTROL                                                                            0x01b6
5963 #define mmSPI_PS_IN_CONTROL_BASE_IDX                                                                   1
5964 #define mmSPI_BARYC_CNTL                                                                               0x01b8
5965 #define mmSPI_BARYC_CNTL_BASE_IDX                                                                      1
5966 #define mmSPI_TMPRING_SIZE                                                                             0x01ba
5967 #define mmSPI_TMPRING_SIZE_BASE_IDX                                                                    1
5968 #define mmSPI_SHADER_IDX_FORMAT                                                                        0x01c2
5969 #define mmSPI_SHADER_IDX_FORMAT_BASE_IDX                                                               1
5970 #define mmSPI_SHADER_POS_FORMAT                                                                        0x01c3
5971 #define mmSPI_SHADER_POS_FORMAT_BASE_IDX                                                               1
5972 #define mmSPI_SHADER_Z_FORMAT                                                                          0x01c4
5973 #define mmSPI_SHADER_Z_FORMAT_BASE_IDX                                                                 1
5974 #define mmSPI_SHADER_COL_FORMAT                                                                        0x01c5
5975 #define mmSPI_SHADER_COL_FORMAT_BASE_IDX                                                               1
5976 #define mmSX_PS_DOWNCONVERT_CONTROL                                                                    0x01d4
5977 #define mmSX_PS_DOWNCONVERT_CONTROL_BASE_IDX                                                           1
5978 #define mmSX_PS_DOWNCONVERT                                                                            0x01d5
5979 #define mmSX_PS_DOWNCONVERT_BASE_IDX                                                                   1
5980 #define mmSX_BLEND_OPT_EPSILON                                                                         0x01d6
5981 #define mmSX_BLEND_OPT_EPSILON_BASE_IDX                                                                1
5982 #define mmSX_BLEND_OPT_CONTROL                                                                         0x01d7
5983 #define mmSX_BLEND_OPT_CONTROL_BASE_IDX                                                                1
5984 #define mmSX_MRT0_BLEND_OPT                                                                            0x01d8
5985 #define mmSX_MRT0_BLEND_OPT_BASE_IDX                                                                   1
5986 #define mmSX_MRT1_BLEND_OPT                                                                            0x01d9
5987 #define mmSX_MRT1_BLEND_OPT_BASE_IDX                                                                   1
5988 #define mmSX_MRT2_BLEND_OPT                                                                            0x01da
5989 #define mmSX_MRT2_BLEND_OPT_BASE_IDX                                                                   1
5990 #define mmSX_MRT3_BLEND_OPT                                                                            0x01db
5991 #define mmSX_MRT3_BLEND_OPT_BASE_IDX                                                                   1
5992 #define mmSX_MRT4_BLEND_OPT                                                                            0x01dc
5993 #define mmSX_MRT4_BLEND_OPT_BASE_IDX                                                                   1
5994 #define mmSX_MRT5_BLEND_OPT                                                                            0x01dd
5995 #define mmSX_MRT5_BLEND_OPT_BASE_IDX                                                                   1
5996 #define mmSX_MRT6_BLEND_OPT                                                                            0x01de
5997 #define mmSX_MRT6_BLEND_OPT_BASE_IDX                                                                   1
5998 #define mmSX_MRT7_BLEND_OPT                                                                            0x01df
5999 #define mmSX_MRT7_BLEND_OPT_BASE_IDX                                                                   1
6000 #define mmCB_BLEND0_CONTROL                                                                            0x01e0
6001 #define mmCB_BLEND0_CONTROL_BASE_IDX                                                                   1
6002 #define mmCB_BLEND1_CONTROL                                                                            0x01e1
6003 #define mmCB_BLEND1_CONTROL_BASE_IDX                                                                   1
6004 #define mmCB_BLEND2_CONTROL                                                                            0x01e2
6005 #define mmCB_BLEND2_CONTROL_BASE_IDX                                                                   1
6006 #define mmCB_BLEND3_CONTROL                                                                            0x01e3
6007 #define mmCB_BLEND3_CONTROL_BASE_IDX                                                                   1
6008 #define mmCB_BLEND4_CONTROL                                                                            0x01e4
6009 #define mmCB_BLEND4_CONTROL_BASE_IDX                                                                   1
6010 #define mmCB_BLEND5_CONTROL                                                                            0x01e5
6011 #define mmCB_BLEND5_CONTROL_BASE_IDX                                                                   1
6012 #define mmCB_BLEND6_CONTROL                                                                            0x01e6
6013 #define mmCB_BLEND6_CONTROL_BASE_IDX                                                                   1
6014 #define mmCB_BLEND7_CONTROL                                                                            0x01e7
6015 #define mmCB_BLEND7_CONTROL_BASE_IDX                                                                   1
6016 #define mmCS_COPY_STATE                                                                                0x01f3
6017 #define mmCS_COPY_STATE_BASE_IDX                                                                       1
6018 #define mmGFX_COPY_STATE                                                                               0x01f4
6019 #define mmGFX_COPY_STATE_BASE_IDX                                                                      1
6020 #define mmPA_CL_POINT_X_RAD                                                                            0x01f5
6021 #define mmPA_CL_POINT_X_RAD_BASE_IDX                                                                   1
6022 #define mmPA_CL_POINT_Y_RAD                                                                            0x01f6
6023 #define mmPA_CL_POINT_Y_RAD_BASE_IDX                                                                   1
6024 #define mmPA_CL_POINT_SIZE                                                                             0x01f7
6025 #define mmPA_CL_POINT_SIZE_BASE_IDX                                                                    1
6026 #define mmPA_CL_POINT_CULL_RAD                                                                         0x01f8
6027 #define mmPA_CL_POINT_CULL_RAD_BASE_IDX                                                                1
6028 #define mmVGT_DMA_BASE_HI                                                                              0x01f9
6029 #define mmVGT_DMA_BASE_HI_BASE_IDX                                                                     1
6030 #define mmVGT_DMA_BASE                                                                                 0x01fa
6031 #define mmVGT_DMA_BASE_BASE_IDX                                                                        1
6032 #define mmVGT_DRAW_INITIATOR                                                                           0x01fc
6033 #define mmVGT_DRAW_INITIATOR_BASE_IDX                                                                  1
6034 #define mmVGT_IMMED_DATA                                                                               0x01fd
6035 #define mmVGT_IMMED_DATA_BASE_IDX                                                                      1
6036 #define mmVGT_EVENT_ADDRESS_REG                                                                        0x01fe
6037 #define mmVGT_EVENT_ADDRESS_REG_BASE_IDX                                                               1
6038 #define mmGE_MAX_OUTPUT_PER_SUBGROUP                                                                   0x01ff
6039 #define mmGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX                                                          1
6040 #define mmDB_DEPTH_CONTROL                                                                             0x0200
6041 #define mmDB_DEPTH_CONTROL_BASE_IDX                                                                    1
6042 #define mmDB_EQAA                                                                                      0x0201
6043 #define mmDB_EQAA_BASE_IDX                                                                             1
6044 #define mmCB_COLOR_CONTROL                                                                             0x0202
6045 #define mmCB_COLOR_CONTROL_BASE_IDX                                                                    1
6046 #define mmDB_SHADER_CONTROL                                                                            0x0203
6047 #define mmDB_SHADER_CONTROL_BASE_IDX                                                                   1
6048 #define mmPA_CL_CLIP_CNTL                                                                              0x0204
6049 #define mmPA_CL_CLIP_CNTL_BASE_IDX                                                                     1
6050 #define mmPA_SU_SC_MODE_CNTL                                                                           0x0205
6051 #define mmPA_SU_SC_MODE_CNTL_BASE_IDX                                                                  1
6052 #define mmPA_CL_VTE_CNTL                                                                               0x0206
6053 #define mmPA_CL_VTE_CNTL_BASE_IDX                                                                      1
6054 #define mmPA_CL_VS_OUT_CNTL                                                                            0x0207
6055 #define mmPA_CL_VS_OUT_CNTL_BASE_IDX                                                                   1
6056 #define mmPA_CL_NANINF_CNTL                                                                            0x0208
6057 #define mmPA_CL_NANINF_CNTL_BASE_IDX                                                                   1
6058 #define mmPA_SU_LINE_STIPPLE_CNTL                                                                      0x0209
6059 #define mmPA_SU_LINE_STIPPLE_CNTL_BASE_IDX                                                             1
6060 #define mmPA_SU_LINE_STIPPLE_SCALE                                                                     0x020a
6061 #define mmPA_SU_LINE_STIPPLE_SCALE_BASE_IDX                                                            1
6062 #define mmPA_SU_PRIM_FILTER_CNTL                                                                       0x020b
6063 #define mmPA_SU_PRIM_FILTER_CNTL_BASE_IDX                                                              1
6064 #define mmPA_SU_SMALL_PRIM_FILTER_CNTL                                                                 0x020c
6065 #define mmPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX                                                        1
6066 #define mmPA_CL_NGG_CNTL                                                                               0x020e
6067 #define mmPA_CL_NGG_CNTL_BASE_IDX                                                                      1
6068 #define mmPA_SU_OVER_RASTERIZATION_CNTL                                                                0x020f
6069 #define mmPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX                                                       1
6070 #define mmPA_STEREO_CNTL                                                                               0x0210
6071 #define mmPA_STEREO_CNTL_BASE_IDX                                                                      1
6072 #define mmPA_STATE_STEREO_X                                                                            0x0211
6073 #define mmPA_STATE_STEREO_X_BASE_IDX                                                                   1
6074 #define mmPA_CL_VRS_CNTL                                                                               0x0212
6075 #define mmPA_CL_VRS_CNTL_BASE_IDX                                                                      1
6076 #define mmPA_SU_POINT_SIZE                                                                             0x0280
6077 #define mmPA_SU_POINT_SIZE_BASE_IDX                                                                    1
6078 #define mmPA_SU_POINT_MINMAX                                                                           0x0281
6079 #define mmPA_SU_POINT_MINMAX_BASE_IDX                                                                  1
6080 #define mmPA_SU_LINE_CNTL                                                                              0x0282
6081 #define mmPA_SU_LINE_CNTL_BASE_IDX                                                                     1
6082 #define mmPA_SC_LINE_STIPPLE                                                                           0x0283
6083 #define mmPA_SC_LINE_STIPPLE_BASE_IDX                                                                  1
6084 #define mmVGT_OUTPUT_PATH_CNTL                                                                         0x0284
6085 #define mmVGT_OUTPUT_PATH_CNTL_BASE_IDX                                                                1
6086 #define mmVGT_HOS_CNTL                                                                                 0x0285
6087 #define mmVGT_HOS_CNTL_BASE_IDX                                                                        1
6088 #define mmVGT_HOS_MAX_TESS_LEVEL                                                                       0x0286
6089 #define mmVGT_HOS_MAX_TESS_LEVEL_BASE_IDX                                                              1
6090 #define mmVGT_HOS_MIN_TESS_LEVEL                                                                       0x0287
6091 #define mmVGT_HOS_MIN_TESS_LEVEL_BASE_IDX                                                              1
6092 #define mmVGT_HOS_REUSE_DEPTH                                                                          0x0288
6093 #define mmVGT_HOS_REUSE_DEPTH_BASE_IDX                                                                 1
6094 #define mmVGT_GROUP_PRIM_TYPE                                                                          0x0289
6095 #define mmVGT_GROUP_PRIM_TYPE_BASE_IDX                                                                 1
6096 #define mmVGT_GROUP_FIRST_DECR                                                                         0x028a
6097 #define mmVGT_GROUP_FIRST_DECR_BASE_IDX                                                                1
6098 #define mmVGT_GROUP_DECR                                                                               0x028b
6099 #define mmVGT_GROUP_DECR_BASE_IDX                                                                      1
6100 #define mmVGT_GROUP_VECT_0_CNTL                                                                        0x028c
6101 #define mmVGT_GROUP_VECT_0_CNTL_BASE_IDX                                                               1
6102 #define mmVGT_GROUP_VECT_1_CNTL                                                                        0x028d
6103 #define mmVGT_GROUP_VECT_1_CNTL_BASE_IDX                                                               1
6104 #define mmVGT_GROUP_VECT_0_FMT_CNTL                                                                    0x028e
6105 #define mmVGT_GROUP_VECT_0_FMT_CNTL_BASE_IDX                                                           1
6106 #define mmVGT_GROUP_VECT_1_FMT_CNTL                                                                    0x028f
6107 #define mmVGT_GROUP_VECT_1_FMT_CNTL_BASE_IDX                                                           1
6108 #define mmVGT_GS_MODE                                                                                  0x0290
6109 #define mmVGT_GS_MODE_BASE_IDX                                                                         1
6110 #define mmVGT_GS_ONCHIP_CNTL                                                                           0x0291
6111 #define mmVGT_GS_ONCHIP_CNTL_BASE_IDX                                                                  1
6112 #define mmPA_SC_MODE_CNTL_0                                                                            0x0292
6113 #define mmPA_SC_MODE_CNTL_0_BASE_IDX                                                                   1
6114 #define mmPA_SC_MODE_CNTL_1                                                                            0x0293
6115 #define mmPA_SC_MODE_CNTL_1_BASE_IDX                                                                   1
6116 #define mmVGT_ENHANCE                                                                                  0x0294
6117 #define mmVGT_ENHANCE_BASE_IDX                                                                         1
6118 #define mmVGT_GS_PER_ES                                                                                0x0295
6119 #define mmVGT_GS_PER_ES_BASE_IDX                                                                       1
6120 #define mmVGT_ES_PER_GS                                                                                0x0296
6121 #define mmVGT_ES_PER_GS_BASE_IDX                                                                       1
6122 #define mmVGT_GS_PER_VS                                                                                0x0297
6123 #define mmVGT_GS_PER_VS_BASE_IDX                                                                       1
6124 #define mmVGT_GSVS_RING_OFFSET_1                                                                       0x0298
6125 #define mmVGT_GSVS_RING_OFFSET_1_BASE_IDX                                                              1
6126 #define mmVGT_GSVS_RING_OFFSET_2                                                                       0x0299
6127 #define mmVGT_GSVS_RING_OFFSET_2_BASE_IDX                                                              1
6128 #define mmVGT_GSVS_RING_OFFSET_3                                                                       0x029a
6129 #define mmVGT_GSVS_RING_OFFSET_3_BASE_IDX                                                              1
6130 #define mmVGT_GS_OUT_PRIM_TYPE                                                                         0x029b
6131 #define mmVGT_GS_OUT_PRIM_TYPE_BASE_IDX                                                                1
6132 #define mmIA_ENHANCE                                                                                   0x029c
6133 #define mmIA_ENHANCE_BASE_IDX                                                                          1
6134 #define mmVGT_DMA_SIZE                                                                                 0x029d
6135 #define mmVGT_DMA_SIZE_BASE_IDX                                                                        1
6136 #define mmVGT_DMA_MAX_SIZE                                                                             0x029e
6137 #define mmVGT_DMA_MAX_SIZE_BASE_IDX                                                                    1
6138 #define mmVGT_DMA_INDEX_TYPE                                                                           0x029f
6139 #define mmVGT_DMA_INDEX_TYPE_BASE_IDX                                                                  1
6140 #define mmWD_ENHANCE                                                                                   0x02a0
6141 #define mmWD_ENHANCE_BASE_IDX                                                                          1
6142 #define mmVGT_PRIMITIVEID_EN                                                                           0x02a1
6143 #define mmVGT_PRIMITIVEID_EN_BASE_IDX                                                                  1
6144 #define mmVGT_DMA_NUM_INSTANCES                                                                        0x02a2
6145 #define mmVGT_DMA_NUM_INSTANCES_BASE_IDX                                                               1
6146 #define mmVGT_PRIMITIVEID_RESET                                                                        0x02a3
6147 #define mmVGT_PRIMITIVEID_RESET_BASE_IDX                                                               1
6148 #define mmVGT_EVENT_INITIATOR                                                                          0x02a4
6149 #define mmVGT_EVENT_INITIATOR_BASE_IDX                                                                 1
6150 #define mmVGT_MULTI_PRIM_IB_RESET_EN                                                                   0x02a5
6151 #define mmVGT_MULTI_PRIM_IB_RESET_EN_BASE_IDX                                                          1
6152 #define mmVGT_DRAW_PAYLOAD_CNTL                                                                        0x02a6
6153 #define mmVGT_DRAW_PAYLOAD_CNTL_BASE_IDX                                                               1
6154 #define mmVGT_INSTANCE_STEP_RATE_0                                                                     0x02a8
6155 #define mmVGT_INSTANCE_STEP_RATE_0_BASE_IDX                                                            1
6156 #define mmVGT_INSTANCE_STEP_RATE_1                                                                     0x02a9
6157 #define mmVGT_INSTANCE_STEP_RATE_1_BASE_IDX                                                            1
6158 #define mmIA_MULTI_VGT_PARAM                                                                           0x02aa
6159 #define mmIA_MULTI_VGT_PARAM_BASE_IDX                                                                  1
6160 #define mmVGT_ESGS_RING_ITEMSIZE                                                                       0x02ab
6161 #define mmVGT_ESGS_RING_ITEMSIZE_BASE_IDX                                                              1
6162 #define mmVGT_GSVS_RING_ITEMSIZE                                                                       0x02ac
6163 #define mmVGT_GSVS_RING_ITEMSIZE_BASE_IDX                                                              1
6164 #define mmVGT_REUSE_OFF                                                                                0x02ad
6165 #define mmVGT_REUSE_OFF_BASE_IDX                                                                       1
6166 #define mmVGT_VTX_CNT_EN                                                                               0x02ae
6167 #define mmVGT_VTX_CNT_EN_BASE_IDX                                                                      1
6168 #define mmDB_HTILE_SURFACE                                                                             0x02af
6169 #define mmDB_HTILE_SURFACE_BASE_IDX                                                                    1
6170 #define mmDB_SRESULTS_COMPARE_STATE0                                                                   0x02b0
6171 #define mmDB_SRESULTS_COMPARE_STATE0_BASE_IDX                                                          1
6172 #define mmDB_SRESULTS_COMPARE_STATE1                                                                   0x02b1
6173 #define mmDB_SRESULTS_COMPARE_STATE1_BASE_IDX                                                          1
6174 #define mmDB_PRELOAD_CONTROL                                                                           0x02b2
6175 #define mmDB_PRELOAD_CONTROL_BASE_IDX                                                                  1
6176 #define mmVGT_STRMOUT_BUFFER_SIZE_0                                                                    0x02b4
6177 #define mmVGT_STRMOUT_BUFFER_SIZE_0_BASE_IDX                                                           1
6178 #define mmVGT_STRMOUT_VTX_STRIDE_0                                                                     0x02b5
6179 #define mmVGT_STRMOUT_VTX_STRIDE_0_BASE_IDX                                                            1
6180 #define mmVGT_STRMOUT_BUFFER_OFFSET_0                                                                  0x02b7
6181 #define mmVGT_STRMOUT_BUFFER_OFFSET_0_BASE_IDX                                                         1
6182 #define mmVGT_STRMOUT_BUFFER_SIZE_1                                                                    0x02b8
6183 #define mmVGT_STRMOUT_BUFFER_SIZE_1_BASE_IDX                                                           1
6184 #define mmVGT_STRMOUT_VTX_STRIDE_1                                                                     0x02b9
6185 #define mmVGT_STRMOUT_VTX_STRIDE_1_BASE_IDX                                                            1
6186 #define mmVGT_STRMOUT_BUFFER_OFFSET_1                                                                  0x02bb
6187 #define mmVGT_STRMOUT_BUFFER_OFFSET_1_BASE_IDX                                                         1
6188 #define mmVGT_STRMOUT_BUFFER_SIZE_2                                                                    0x02bc
6189 #define mmVGT_STRMOUT_BUFFER_SIZE_2_BASE_IDX                                                           1
6190 #define mmVGT_STRMOUT_VTX_STRIDE_2                                                                     0x02bd
6191 #define mmVGT_STRMOUT_VTX_STRIDE_2_BASE_IDX                                                            1
6192 #define mmVGT_STRMOUT_BUFFER_OFFSET_2                                                                  0x02bf
6193 #define mmVGT_STRMOUT_BUFFER_OFFSET_2_BASE_IDX                                                         1
6194 #define mmVGT_STRMOUT_BUFFER_SIZE_3                                                                    0x02c0
6195 #define mmVGT_STRMOUT_BUFFER_SIZE_3_BASE_IDX                                                           1
6196 #define mmVGT_STRMOUT_VTX_STRIDE_3                                                                     0x02c1
6197 #define mmVGT_STRMOUT_VTX_STRIDE_3_BASE_IDX                                                            1
6198 #define mmVGT_STRMOUT_BUFFER_OFFSET_3                                                                  0x02c3
6199 #define mmVGT_STRMOUT_BUFFER_OFFSET_3_BASE_IDX                                                         1
6200 #define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET                                                               0x02ca
6201 #define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX                                                      1
6202 #define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE                                                   0x02cb
6203 #define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX                                          1
6204 #define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE                                                        0x02cc
6205 #define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX                                               1
6206 #define mmVGT_GS_MAX_VERT_OUT                                                                          0x02ce
6207 #define mmVGT_GS_MAX_VERT_OUT_BASE_IDX                                                                 1
6208 #define mmGE_NGG_SUBGRP_CNTL                                                                           0x02d3
6209 #define mmGE_NGG_SUBGRP_CNTL_BASE_IDX                                                                  1
6210 #define mmVGT_TESS_DISTRIBUTION                                                                        0x02d4
6211 #define mmVGT_TESS_DISTRIBUTION_BASE_IDX                                                               1
6212 #define mmVGT_SHADER_STAGES_EN                                                                         0x02d5
6213 #define mmVGT_SHADER_STAGES_EN_BASE_IDX                                                                1
6214 #define mmVGT_LS_HS_CONFIG                                                                             0x02d6
6215 #define mmVGT_LS_HS_CONFIG_BASE_IDX                                                                    1
6216 #define mmVGT_GS_VERT_ITEMSIZE                                                                         0x02d7
6217 #define mmVGT_GS_VERT_ITEMSIZE_BASE_IDX                                                                1
6218 #define mmVGT_GS_VERT_ITEMSIZE_1                                                                       0x02d8
6219 #define mmVGT_GS_VERT_ITEMSIZE_1_BASE_IDX                                                              1
6220 #define mmVGT_GS_VERT_ITEMSIZE_2                                                                       0x02d9
6221 #define mmVGT_GS_VERT_ITEMSIZE_2_BASE_IDX                                                              1
6222 #define mmVGT_GS_VERT_ITEMSIZE_3                                                                       0x02da
6223 #define mmVGT_GS_VERT_ITEMSIZE_3_BASE_IDX                                                              1
6224 #define mmVGT_TF_PARAM                                                                                 0x02db
6225 #define mmVGT_TF_PARAM_BASE_IDX                                                                        1
6226 #define mmDB_ALPHA_TO_MASK                                                                             0x02dc
6227 #define mmDB_ALPHA_TO_MASK_BASE_IDX                                                                    1
6228 #define mmVGT_DISPATCH_DRAW_INDEX                                                                      0x02dd
6229 #define mmVGT_DISPATCH_DRAW_INDEX_BASE_IDX                                                             1
6230 #define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL                                                                0x02de
6231 #define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX                                                       1
6232 #define mmPA_SU_POLY_OFFSET_CLAMP                                                                      0x02df
6233 #define mmPA_SU_POLY_OFFSET_CLAMP_BASE_IDX                                                             1
6234 #define mmPA_SU_POLY_OFFSET_FRONT_SCALE                                                                0x02e0
6235 #define mmPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX                                                       1
6236 #define mmPA_SU_POLY_OFFSET_FRONT_OFFSET                                                               0x02e1
6237 #define mmPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX                                                      1
6238 #define mmPA_SU_POLY_OFFSET_BACK_SCALE                                                                 0x02e2
6239 #define mmPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX                                                        1
6240 #define mmPA_SU_POLY_OFFSET_BACK_OFFSET                                                                0x02e3
6241 #define mmPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX                                                       1
6242 #define mmVGT_GS_INSTANCE_CNT                                                                          0x02e4
6243 #define mmVGT_GS_INSTANCE_CNT_BASE_IDX                                                                 1
6244 #define mmVGT_STRMOUT_CONFIG                                                                           0x02e5
6245 #define mmVGT_STRMOUT_CONFIG_BASE_IDX                                                                  1
6246 #define mmVGT_STRMOUT_BUFFER_CONFIG                                                                    0x02e6
6247 #define mmVGT_STRMOUT_BUFFER_CONFIG_BASE_IDX                                                           1
6248 #define mmVGT_DMA_EVENT_INITIATOR                                                                      0x02e7
6249 #define mmVGT_DMA_EVENT_INITIATOR_BASE_IDX                                                             1
6250 #define mmPA_SC_CENTROID_PRIORITY_0                                                                    0x02f5
6251 #define mmPA_SC_CENTROID_PRIORITY_0_BASE_IDX                                                           1
6252 #define mmPA_SC_CENTROID_PRIORITY_1                                                                    0x02f6
6253 #define mmPA_SC_CENTROID_PRIORITY_1_BASE_IDX                                                           1
6254 #define mmPA_SC_LINE_CNTL                                                                              0x02f7
6255 #define mmPA_SC_LINE_CNTL_BASE_IDX                                                                     1
6256 #define mmPA_SC_AA_CONFIG                                                                              0x02f8
6257 #define mmPA_SC_AA_CONFIG_BASE_IDX                                                                     1
6258 #define mmPA_SU_VTX_CNTL                                                                               0x02f9
6259 #define mmPA_SU_VTX_CNTL_BASE_IDX                                                                      1
6260 #define mmPA_CL_GB_VERT_CLIP_ADJ                                                                       0x02fa
6261 #define mmPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX                                                              1
6262 #define mmPA_CL_GB_VERT_DISC_ADJ                                                                       0x02fb
6263 #define mmPA_CL_GB_VERT_DISC_ADJ_BASE_IDX                                                              1
6264 #define mmPA_CL_GB_HORZ_CLIP_ADJ                                                                       0x02fc
6265 #define mmPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX                                                              1
6266 #define mmPA_CL_GB_HORZ_DISC_ADJ                                                                       0x02fd
6267 #define mmPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX                                                              1
6268 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0                                                            0x02fe
6269 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX                                                   1
6270 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1                                                            0x02ff
6271 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX                                                   1
6272 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2                                                            0x0300
6273 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX                                                   1
6274 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3                                                            0x0301
6275 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX                                                   1
6276 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0                                                            0x0302
6277 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX                                                   1
6278 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1                                                            0x0303
6279 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX                                                   1
6280 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2                                                            0x0304
6281 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX                                                   1
6282 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3                                                            0x0305
6283 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX                                                   1
6284 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0                                                            0x0306
6285 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX                                                   1
6286 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1                                                            0x0307
6287 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX                                                   1
6288 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2                                                            0x0308
6289 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX                                                   1
6290 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3                                                            0x0309
6291 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX                                                   1
6292 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0                                                            0x030a
6293 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX                                                   1
6294 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1                                                            0x030b
6295 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX                                                   1
6296 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2                                                            0x030c
6297 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX                                                   1
6298 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3                                                            0x030d
6299 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX                                                   1
6300 #define mmPA_SC_AA_MASK_X0Y0_X1Y0                                                                      0x030e
6301 #define mmPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX                                                             1
6302 #define mmPA_SC_AA_MASK_X0Y1_X1Y1                                                                      0x030f
6303 #define mmPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX                                                             1
6304 #define mmPA_SC_SHADER_CONTROL                                                                         0x0310
6305 #define mmPA_SC_SHADER_CONTROL_BASE_IDX                                                                1
6306 #define mmPA_SC_BINNER_CNTL_0                                                                          0x0311
6307 #define mmPA_SC_BINNER_CNTL_0_BASE_IDX                                                                 1
6308 #define mmPA_SC_BINNER_CNTL_1                                                                          0x0312
6309 #define mmPA_SC_BINNER_CNTL_1_BASE_IDX                                                                 1
6310 #define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL                                                        0x0313
6311 #define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX                                               1
6312 #define mmPA_SC_NGG_MODE_CNTL                                                                          0x0314
6313 #define mmPA_SC_NGG_MODE_CNTL_BASE_IDX                                                                 1
6314 #define mmVGT_VERTEX_REUSE_BLOCK_CNTL                                                                  0x0316
6315 #define mmVGT_VERTEX_REUSE_BLOCK_CNTL_BASE_IDX                                                         1
6316 #define mmVGT_OUT_DEALLOC_CNTL                                                                         0x0317
6317 #define mmVGT_OUT_DEALLOC_CNTL_BASE_IDX                                                                1
6318 #define mmCB_COLOR0_BASE                                                                               0x0318
6319 #define mmCB_COLOR0_BASE_BASE_IDX                                                                      1
6320 #define mmCB_COLOR0_PITCH                                                                              0x0319
6321 #define mmCB_COLOR0_PITCH_BASE_IDX                                                                     1
6322 #define mmCB_COLOR0_SLICE                                                                              0x031a
6323 #define mmCB_COLOR0_SLICE_BASE_IDX                                                                     1
6324 #define mmCB_COLOR0_VIEW                                                                               0x031b
6325 #define mmCB_COLOR0_VIEW_BASE_IDX                                                                      1
6326 #define mmCB_COLOR0_INFO                                                                               0x031c
6327 #define mmCB_COLOR0_INFO_BASE_IDX                                                                      1
6328 #define mmCB_COLOR0_ATTRIB                                                                             0x031d
6329 #define mmCB_COLOR0_ATTRIB_BASE_IDX                                                                    1
6330 #define mmCB_COLOR0_DCC_CONTROL                                                                        0x031e
6331 #define mmCB_COLOR0_DCC_CONTROL_BASE_IDX                                                               1
6332 #define mmCB_COLOR0_CMASK                                                                              0x031f
6333 #define mmCB_COLOR0_CMASK_BASE_IDX                                                                     1
6334 #define mmCB_COLOR0_CMASK_SLICE                                                                        0x0320
6335 #define mmCB_COLOR0_CMASK_SLICE_BASE_IDX                                                               1
6336 #define mmCB_COLOR0_FMASK                                                                              0x0321
6337 #define mmCB_COLOR0_FMASK_BASE_IDX                                                                     1
6338 #define mmCB_COLOR0_FMASK_SLICE                                                                        0x0322
6339 #define mmCB_COLOR0_FMASK_SLICE_BASE_IDX                                                               1
6340 #define mmCB_COLOR0_CLEAR_WORD0                                                                        0x0323
6341 #define mmCB_COLOR0_CLEAR_WORD0_BASE_IDX                                                               1
6342 #define mmCB_COLOR0_CLEAR_WORD1                                                                        0x0324
6343 #define mmCB_COLOR0_CLEAR_WORD1_BASE_IDX                                                               1
6344 #define mmCB_COLOR0_DCC_BASE                                                                           0x0325
6345 #define mmCB_COLOR0_DCC_BASE_BASE_IDX                                                                  1
6346 #define mmCB_COLOR1_BASE                                                                               0x0327
6347 #define mmCB_COLOR1_BASE_BASE_IDX                                                                      1
6348 #define mmCB_COLOR1_PITCH                                                                              0x0328
6349 #define mmCB_COLOR1_PITCH_BASE_IDX                                                                     1
6350 #define mmCB_COLOR1_SLICE                                                                              0x0329
6351 #define mmCB_COLOR1_SLICE_BASE_IDX                                                                     1
6352 #define mmCB_COLOR1_VIEW                                                                               0x032a
6353 #define mmCB_COLOR1_VIEW_BASE_IDX                                                                      1
6354 #define mmCB_COLOR1_INFO                                                                               0x032b
6355 #define mmCB_COLOR1_INFO_BASE_IDX                                                                      1
6356 #define mmCB_COLOR1_ATTRIB                                                                             0x032c
6357 #define mmCB_COLOR1_ATTRIB_BASE_IDX                                                                    1
6358 #define mmCB_COLOR1_DCC_CONTROL                                                                        0x032d
6359 #define mmCB_COLOR1_DCC_CONTROL_BASE_IDX                                                               1
6360 #define mmCB_COLOR1_CMASK                                                                              0x032e
6361 #define mmCB_COLOR1_CMASK_BASE_IDX                                                                     1
6362 #define mmCB_COLOR1_CMASK_SLICE                                                                        0x032f
6363 #define mmCB_COLOR1_CMASK_SLICE_BASE_IDX                                                               1
6364 #define mmCB_COLOR1_FMASK                                                                              0x0330
6365 #define mmCB_COLOR1_FMASK_BASE_IDX                                                                     1
6366 #define mmCB_COLOR1_FMASK_SLICE                                                                        0x0331
6367 #define mmCB_COLOR1_FMASK_SLICE_BASE_IDX                                                               1
6368 #define mmCB_COLOR1_CLEAR_WORD0                                                                        0x0332
6369 #define mmCB_COLOR1_CLEAR_WORD0_BASE_IDX                                                               1
6370 #define mmCB_COLOR1_CLEAR_WORD1                                                                        0x0333
6371 #define mmCB_COLOR1_CLEAR_WORD1_BASE_IDX                                                               1
6372 #define mmCB_COLOR1_DCC_BASE                                                                           0x0334
6373 #define mmCB_COLOR1_DCC_BASE_BASE_IDX                                                                  1
6374 #define mmCB_COLOR2_BASE                                                                               0x0336
6375 #define mmCB_COLOR2_BASE_BASE_IDX                                                                      1
6376 #define mmCB_COLOR2_PITCH                                                                              0x0337
6377 #define mmCB_COLOR2_PITCH_BASE_IDX                                                                     1
6378 #define mmCB_COLOR2_SLICE                                                                              0x0338
6379 #define mmCB_COLOR2_SLICE_BASE_IDX                                                                     1
6380 #define mmCB_COLOR2_VIEW                                                                               0x0339
6381 #define mmCB_COLOR2_VIEW_BASE_IDX                                                                      1
6382 #define mmCB_COLOR2_INFO                                                                               0x033a
6383 #define mmCB_COLOR2_INFO_BASE_IDX                                                                      1
6384 #define mmCB_COLOR2_ATTRIB                                                                             0x033b
6385 #define mmCB_COLOR2_ATTRIB_BASE_IDX                                                                    1
6386 #define mmCB_COLOR2_DCC_CONTROL                                                                        0x033c
6387 #define mmCB_COLOR2_DCC_CONTROL_BASE_IDX                                                               1
6388 #define mmCB_COLOR2_CMASK                                                                              0x033d
6389 #define mmCB_COLOR2_CMASK_BASE_IDX                                                                     1
6390 #define mmCB_COLOR2_CMASK_SLICE                                                                        0x033e
6391 #define mmCB_COLOR2_CMASK_SLICE_BASE_IDX                                                               1
6392 #define mmCB_COLOR2_FMASK                                                                              0x033f
6393 #define mmCB_COLOR2_FMASK_BASE_IDX                                                                     1
6394 #define mmCB_COLOR2_FMASK_SLICE                                                                        0x0340
6395 #define mmCB_COLOR2_FMASK_SLICE_BASE_IDX                                                               1
6396 #define mmCB_COLOR2_CLEAR_WORD0                                                                        0x0341
6397 #define mmCB_COLOR2_CLEAR_WORD0_BASE_IDX                                                               1
6398 #define mmCB_COLOR2_CLEAR_WORD1                                                                        0x0342
6399 #define mmCB_COLOR2_CLEAR_WORD1_BASE_IDX                                                               1
6400 #define mmCB_COLOR2_DCC_BASE                                                                           0x0343
6401 #define mmCB_COLOR2_DCC_BASE_BASE_IDX                                                                  1
6402 #define mmCB_COLOR3_BASE                                                                               0x0345
6403 #define mmCB_COLOR3_BASE_BASE_IDX                                                                      1
6404 #define mmCB_COLOR3_PITCH                                                                              0x0346
6405 #define mmCB_COLOR3_PITCH_BASE_IDX                                                                     1
6406 #define mmCB_COLOR3_SLICE                                                                              0x0347
6407 #define mmCB_COLOR3_SLICE_BASE_IDX                                                                     1
6408 #define mmCB_COLOR3_VIEW                                                                               0x0348
6409 #define mmCB_COLOR3_VIEW_BASE_IDX                                                                      1
6410 #define mmCB_COLOR3_INFO                                                                               0x0349
6411 #define mmCB_COLOR3_INFO_BASE_IDX                                                                      1
6412 #define mmCB_COLOR3_ATTRIB                                                                             0x034a
6413 #define mmCB_COLOR3_ATTRIB_BASE_IDX                                                                    1
6414 #define mmCB_COLOR3_DCC_CONTROL                                                                        0x034b
6415 #define mmCB_COLOR3_DCC_CONTROL_BASE_IDX                                                               1
6416 #define mmCB_COLOR3_CMASK                                                                              0x034c
6417 #define mmCB_COLOR3_CMASK_BASE_IDX                                                                     1
6418 #define mmCB_COLOR3_CMASK_SLICE                                                                        0x034d
6419 #define mmCB_COLOR3_CMASK_SLICE_BASE_IDX                                                               1
6420 #define mmCB_COLOR3_FMASK                                                                              0x034e
6421 #define mmCB_COLOR3_FMASK_BASE_IDX                                                                     1
6422 #define mmCB_COLOR3_FMASK_SLICE                                                                        0x034f
6423 #define mmCB_COLOR3_FMASK_SLICE_BASE_IDX                                                               1
6424 #define mmCB_COLOR3_CLEAR_WORD0                                                                        0x0350
6425 #define mmCB_COLOR3_CLEAR_WORD0_BASE_IDX                                                               1
6426 #define mmCB_COLOR3_CLEAR_WORD1                                                                        0x0351
6427 #define mmCB_COLOR3_CLEAR_WORD1_BASE_IDX                                                               1
6428 #define mmCB_COLOR3_DCC_BASE                                                                           0x0352
6429 #define mmCB_COLOR3_DCC_BASE_BASE_IDX                                                                  1
6430 #define mmCB_COLOR4_BASE                                                                               0x0354
6431 #define mmCB_COLOR4_BASE_BASE_IDX                                                                      1
6432 #define mmCB_COLOR4_PITCH                                                                              0x0355
6433 #define mmCB_COLOR4_PITCH_BASE_IDX                                                                     1
6434 #define mmCB_COLOR4_SLICE                                                                              0x0356
6435 #define mmCB_COLOR4_SLICE_BASE_IDX                                                                     1
6436 #define mmCB_COLOR4_VIEW                                                                               0x0357
6437 #define mmCB_COLOR4_VIEW_BASE_IDX                                                                      1
6438 #define mmCB_COLOR4_INFO                                                                               0x0358
6439 #define mmCB_COLOR4_INFO_BASE_IDX                                                                      1
6440 #define mmCB_COLOR4_ATTRIB                                                                             0x0359
6441 #define mmCB_COLOR4_ATTRIB_BASE_IDX                                                                    1
6442 #define mmCB_COLOR4_DCC_CONTROL                                                                        0x035a
6443 #define mmCB_COLOR4_DCC_CONTROL_BASE_IDX                                                               1
6444 #define mmCB_COLOR4_CMASK                                                                              0x035b
6445 #define mmCB_COLOR4_CMASK_BASE_IDX                                                                     1
6446 #define mmCB_COLOR4_CMASK_SLICE                                                                        0x035c
6447 #define mmCB_COLOR4_CMASK_SLICE_BASE_IDX                                                               1
6448 #define mmCB_COLOR4_FMASK                                                                              0x035d
6449 #define mmCB_COLOR4_FMASK_BASE_IDX                                                                     1
6450 #define mmCB_COLOR4_FMASK_SLICE                                                                        0x035e
6451 #define mmCB_COLOR4_FMASK_SLICE_BASE_IDX                                                               1
6452 #define mmCB_COLOR4_CLEAR_WORD0                                                                        0x035f
6453 #define mmCB_COLOR4_CLEAR_WORD0_BASE_IDX                                                               1
6454 #define mmCB_COLOR4_CLEAR_WORD1                                                                        0x0360
6455 #define mmCB_COLOR4_CLEAR_WORD1_BASE_IDX                                                               1
6456 #define mmCB_COLOR4_DCC_BASE                                                                           0x0361
6457 #define mmCB_COLOR4_DCC_BASE_BASE_IDX                                                                  1
6458 #define mmCB_COLOR5_BASE                                                                               0x0363
6459 #define mmCB_COLOR5_BASE_BASE_IDX                                                                      1
6460 #define mmCB_COLOR5_PITCH                                                                              0x0364
6461 #define mmCB_COLOR5_PITCH_BASE_IDX                                                                     1
6462 #define mmCB_COLOR5_SLICE                                                                              0x0365
6463 #define mmCB_COLOR5_SLICE_BASE_IDX                                                                     1
6464 #define mmCB_COLOR5_VIEW                                                                               0x0366
6465 #define mmCB_COLOR5_VIEW_BASE_IDX                                                                      1
6466 #define mmCB_COLOR5_INFO                                                                               0x0367
6467 #define mmCB_COLOR5_INFO_BASE_IDX                                                                      1
6468 #define mmCB_COLOR5_ATTRIB                                                                             0x0368
6469 #define mmCB_COLOR5_ATTRIB_BASE_IDX                                                                    1
6470 #define mmCB_COLOR5_DCC_CONTROL                                                                        0x0369
6471 #define mmCB_COLOR5_DCC_CONTROL_BASE_IDX                                                               1
6472 #define mmCB_COLOR5_CMASK                                                                              0x036a
6473 #define mmCB_COLOR5_CMASK_BASE_IDX                                                                     1
6474 #define mmCB_COLOR5_CMASK_SLICE                                                                        0x036b
6475 #define mmCB_COLOR5_CMASK_SLICE_BASE_IDX                                                               1
6476 #define mmCB_COLOR5_FMASK                                                                              0x036c
6477 #define mmCB_COLOR5_FMASK_BASE_IDX                                                                     1
6478 #define mmCB_COLOR5_FMASK_SLICE                                                                        0x036d
6479 #define mmCB_COLOR5_FMASK_SLICE_BASE_IDX                                                               1
6480 #define mmCB_COLOR5_CLEAR_WORD0                                                                        0x036e
6481 #define mmCB_COLOR5_CLEAR_WORD0_BASE_IDX                                                               1
6482 #define mmCB_COLOR5_CLEAR_WORD1                                                                        0x036f
6483 #define mmCB_COLOR5_CLEAR_WORD1_BASE_IDX                                                               1
6484 #define mmCB_COLOR5_DCC_BASE                                                                           0x0370
6485 #define mmCB_COLOR5_DCC_BASE_BASE_IDX                                                                  1
6486 #define mmCB_COLOR6_BASE                                                                               0x0372
6487 #define mmCB_COLOR6_BASE_BASE_IDX                                                                      1
6488 #define mmCB_COLOR6_PITCH                                                                              0x0373
6489 #define mmCB_COLOR6_PITCH_BASE_IDX                                                                     1
6490 #define mmCB_COLOR6_SLICE                                                                              0x0374
6491 #define mmCB_COLOR6_SLICE_BASE_IDX                                                                     1
6492 #define mmCB_COLOR6_VIEW                                                                               0x0375
6493 #define mmCB_COLOR6_VIEW_BASE_IDX                                                                      1
6494 #define mmCB_COLOR6_INFO                                                                               0x0376
6495 #define mmCB_COLOR6_INFO_BASE_IDX                                                                      1
6496 #define mmCB_COLOR6_ATTRIB                                                                             0x0377
6497 #define mmCB_COLOR6_ATTRIB_BASE_IDX                                                                    1
6498 #define mmCB_COLOR6_DCC_CONTROL                                                                        0x0378
6499 #define mmCB_COLOR6_DCC_CONTROL_BASE_IDX                                                               1
6500 #define mmCB_COLOR6_CMASK                                                                              0x0379
6501 #define mmCB_COLOR6_CMASK_BASE_IDX                                                                     1
6502 #define mmCB_COLOR6_CMASK_SLICE                                                                        0x037a
6503 #define mmCB_COLOR6_CMASK_SLICE_BASE_IDX                                                               1
6504 #define mmCB_COLOR6_FMASK                                                                              0x037b
6505 #define mmCB_COLOR6_FMASK_BASE_IDX                                                                     1
6506 #define mmCB_COLOR6_FMASK_SLICE                                                                        0x037c
6507 #define mmCB_COLOR6_FMASK_SLICE_BASE_IDX                                                               1
6508 #define mmCB_COLOR6_CLEAR_WORD0                                                                        0x037d
6509 #define mmCB_COLOR6_CLEAR_WORD0_BASE_IDX                                                               1
6510 #define mmCB_COLOR6_CLEAR_WORD1                                                                        0x037e
6511 #define mmCB_COLOR6_CLEAR_WORD1_BASE_IDX                                                               1
6512 #define mmCB_COLOR6_DCC_BASE                                                                           0x037f
6513 #define mmCB_COLOR6_DCC_BASE_BASE_IDX                                                                  1
6514 #define mmCB_COLOR7_BASE                                                                               0x0381
6515 #define mmCB_COLOR7_BASE_BASE_IDX                                                                      1
6516 #define mmCB_COLOR7_PITCH                                                                              0x0382
6517 #define mmCB_COLOR7_PITCH_BASE_IDX                                                                     1
6518 #define mmCB_COLOR7_SLICE                                                                              0x0383
6519 #define mmCB_COLOR7_SLICE_BASE_IDX                                                                     1
6520 #define mmCB_COLOR7_VIEW                                                                               0x0384
6521 #define mmCB_COLOR7_VIEW_BASE_IDX                                                                      1
6522 #define mmCB_COLOR7_INFO                                                                               0x0385
6523 #define mmCB_COLOR7_INFO_BASE_IDX                                                                      1
6524 #define mmCB_COLOR7_ATTRIB                                                                             0x0386
6525 #define mmCB_COLOR7_ATTRIB_BASE_IDX                                                                    1
6526 #define mmCB_COLOR7_DCC_CONTROL                                                                        0x0387
6527 #define mmCB_COLOR7_DCC_CONTROL_BASE_IDX                                                               1
6528 #define mmCB_COLOR7_CMASK                                                                              0x0388
6529 #define mmCB_COLOR7_CMASK_BASE_IDX                                                                     1
6530 #define mmCB_COLOR7_CMASK_SLICE                                                                        0x0389
6531 #define mmCB_COLOR7_CMASK_SLICE_BASE_IDX                                                               1
6532 #define mmCB_COLOR7_FMASK                                                                              0x038a
6533 #define mmCB_COLOR7_FMASK_BASE_IDX                                                                     1
6534 #define mmCB_COLOR7_FMASK_SLICE                                                                        0x038b
6535 #define mmCB_COLOR7_FMASK_SLICE_BASE_IDX                                                               1
6536 #define mmCB_COLOR7_CLEAR_WORD0                                                                        0x038c
6537 #define mmCB_COLOR7_CLEAR_WORD0_BASE_IDX                                                               1
6538 #define mmCB_COLOR7_CLEAR_WORD1                                                                        0x038d
6539 #define mmCB_COLOR7_CLEAR_WORD1_BASE_IDX                                                               1
6540 #define mmCB_COLOR7_DCC_BASE                                                                           0x038e
6541 #define mmCB_COLOR7_DCC_BASE_BASE_IDX                                                                  1
6542 #define mmCB_COLOR0_BASE_EXT                                                                           0x0390
6543 #define mmCB_COLOR0_BASE_EXT_BASE_IDX                                                                  1
6544 #define mmCB_COLOR1_BASE_EXT                                                                           0x0391
6545 #define mmCB_COLOR1_BASE_EXT_BASE_IDX                                                                  1
6546 #define mmCB_COLOR2_BASE_EXT                                                                           0x0392
6547 #define mmCB_COLOR2_BASE_EXT_BASE_IDX                                                                  1
6548 #define mmCB_COLOR3_BASE_EXT                                                                           0x0393
6549 #define mmCB_COLOR3_BASE_EXT_BASE_IDX                                                                  1
6550 #define mmCB_COLOR4_BASE_EXT                                                                           0x0394
6551 #define mmCB_COLOR4_BASE_EXT_BASE_IDX                                                                  1
6552 #define mmCB_COLOR5_BASE_EXT                                                                           0x0395
6553 #define mmCB_COLOR5_BASE_EXT_BASE_IDX                                                                  1
6554 #define mmCB_COLOR6_BASE_EXT                                                                           0x0396
6555 #define mmCB_COLOR6_BASE_EXT_BASE_IDX                                                                  1
6556 #define mmCB_COLOR7_BASE_EXT                                                                           0x0397
6557 #define mmCB_COLOR7_BASE_EXT_BASE_IDX                                                                  1
6558 #define mmCB_COLOR0_CMASK_BASE_EXT                                                                     0x0398
6559 #define mmCB_COLOR0_CMASK_BASE_EXT_BASE_IDX                                                            1
6560 #define mmCB_COLOR1_CMASK_BASE_EXT                                                                     0x0399
6561 #define mmCB_COLOR1_CMASK_BASE_EXT_BASE_IDX                                                            1
6562 #define mmCB_COLOR2_CMASK_BASE_EXT                                                                     0x039a
6563 #define mmCB_COLOR2_CMASK_BASE_EXT_BASE_IDX                                                            1
6564 #define mmCB_COLOR3_CMASK_BASE_EXT                                                                     0x039b
6565 #define mmCB_COLOR3_CMASK_BASE_EXT_BASE_IDX                                                            1
6566 #define mmCB_COLOR4_CMASK_BASE_EXT                                                                     0x039c
6567 #define mmCB_COLOR4_CMASK_BASE_EXT_BASE_IDX                                                            1
6568 #define mmCB_COLOR5_CMASK_BASE_EXT                                                                     0x039d
6569 #define mmCB_COLOR5_CMASK_BASE_EXT_BASE_IDX                                                            1
6570 #define mmCB_COLOR6_CMASK_BASE_EXT                                                                     0x039e
6571 #define mmCB_COLOR6_CMASK_BASE_EXT_BASE_IDX                                                            1
6572 #define mmCB_COLOR7_CMASK_BASE_EXT                                                                     0x039f
6573 #define mmCB_COLOR7_CMASK_BASE_EXT_BASE_IDX                                                            1
6574 #define mmCB_COLOR0_FMASK_BASE_EXT                                                                     0x03a0
6575 #define mmCB_COLOR0_FMASK_BASE_EXT_BASE_IDX                                                            1
6576 #define mmCB_COLOR1_FMASK_BASE_EXT                                                                     0x03a1
6577 #define mmCB_COLOR1_FMASK_BASE_EXT_BASE_IDX                                                            1
6578 #define mmCB_COLOR2_FMASK_BASE_EXT                                                                     0x03a2
6579 #define mmCB_COLOR2_FMASK_BASE_EXT_BASE_IDX                                                            1
6580 #define mmCB_COLOR3_FMASK_BASE_EXT                                                                     0x03a3
6581 #define mmCB_COLOR3_FMASK_BASE_EXT_BASE_IDX                                                            1
6582 #define mmCB_COLOR4_FMASK_BASE_EXT                                                                     0x03a4
6583 #define mmCB_COLOR4_FMASK_BASE_EXT_BASE_IDX                                                            1
6584 #define mmCB_COLOR5_FMASK_BASE_EXT                                                                     0x03a5
6585 #define mmCB_COLOR5_FMASK_BASE_EXT_BASE_IDX                                                            1
6586 #define mmCB_COLOR6_FMASK_BASE_EXT                                                                     0x03a6
6587 #define mmCB_COLOR6_FMASK_BASE_EXT_BASE_IDX                                                            1
6588 #define mmCB_COLOR7_FMASK_BASE_EXT                                                                     0x03a7
6589 #define mmCB_COLOR7_FMASK_BASE_EXT_BASE_IDX                                                            1
6590 #define mmCB_COLOR0_DCC_BASE_EXT                                                                       0x03a8
6591 #define mmCB_COLOR0_DCC_BASE_EXT_BASE_IDX                                                              1
6592 #define mmCB_COLOR1_DCC_BASE_EXT                                                                       0x03a9
6593 #define mmCB_COLOR1_DCC_BASE_EXT_BASE_IDX                                                              1
6594 #define mmCB_COLOR2_DCC_BASE_EXT                                                                       0x03aa
6595 #define mmCB_COLOR2_DCC_BASE_EXT_BASE_IDX                                                              1
6596 #define mmCB_COLOR3_DCC_BASE_EXT                                                                       0x03ab
6597 #define mmCB_COLOR3_DCC_BASE_EXT_BASE_IDX                                                              1
6598 #define mmCB_COLOR4_DCC_BASE_EXT                                                                       0x03ac
6599 #define mmCB_COLOR4_DCC_BASE_EXT_BASE_IDX                                                              1
6600 #define mmCB_COLOR5_DCC_BASE_EXT                                                                       0x03ad
6601 #define mmCB_COLOR5_DCC_BASE_EXT_BASE_IDX                                                              1
6602 #define mmCB_COLOR6_DCC_BASE_EXT                                                                       0x03ae
6603 #define mmCB_COLOR6_DCC_BASE_EXT_BASE_IDX                                                              1
6604 #define mmCB_COLOR7_DCC_BASE_EXT                                                                       0x03af
6605 #define mmCB_COLOR7_DCC_BASE_EXT_BASE_IDX                                                              1
6606 #define mmCB_COLOR0_ATTRIB2                                                                            0x03b0
6607 #define mmCB_COLOR0_ATTRIB2_BASE_IDX                                                                   1
6608 #define mmCB_COLOR1_ATTRIB2                                                                            0x03b1
6609 #define mmCB_COLOR1_ATTRIB2_BASE_IDX                                                                   1
6610 #define mmCB_COLOR2_ATTRIB2                                                                            0x03b2
6611 #define mmCB_COLOR2_ATTRIB2_BASE_IDX                                                                   1
6612 #define mmCB_COLOR3_ATTRIB2                                                                            0x03b3
6613 #define mmCB_COLOR3_ATTRIB2_BASE_IDX                                                                   1
6614 #define mmCB_COLOR4_ATTRIB2                                                                            0x03b4
6615 #define mmCB_COLOR4_ATTRIB2_BASE_IDX                                                                   1
6616 #define mmCB_COLOR5_ATTRIB2                                                                            0x03b5
6617 #define mmCB_COLOR5_ATTRIB2_BASE_IDX                                                                   1
6618 #define mmCB_COLOR6_ATTRIB2                                                                            0x03b6
6619 #define mmCB_COLOR6_ATTRIB2_BASE_IDX                                                                   1
6620 #define mmCB_COLOR7_ATTRIB2                                                                            0x03b7
6621 #define mmCB_COLOR7_ATTRIB2_BASE_IDX                                                                   1
6622 #define mmCB_COLOR0_ATTRIB3                                                                            0x03b8
6623 #define mmCB_COLOR0_ATTRIB3_BASE_IDX                                                                   1
6624 #define mmCB_COLOR1_ATTRIB3                                                                            0x03b9
6625 #define mmCB_COLOR1_ATTRIB3_BASE_IDX                                                                   1
6626 #define mmCB_COLOR2_ATTRIB3                                                                            0x03ba
6627 #define mmCB_COLOR2_ATTRIB3_BASE_IDX                                                                   1
6628 #define mmCB_COLOR3_ATTRIB3                                                                            0x03bb
6629 #define mmCB_COLOR3_ATTRIB3_BASE_IDX                                                                   1
6630 #define mmCB_COLOR4_ATTRIB3                                                                            0x03bc
6631 #define mmCB_COLOR4_ATTRIB3_BASE_IDX                                                                   1
6632 #define mmCB_COLOR5_ATTRIB3                                                                            0x03bd
6633 #define mmCB_COLOR5_ATTRIB3_BASE_IDX                                                                   1
6634 #define mmCB_COLOR6_ATTRIB3                                                                            0x03be
6635 #define mmCB_COLOR6_ATTRIB3_BASE_IDX                                                                   1
6636 #define mmCB_COLOR7_ATTRIB3                                                                            0x03bf
6637 #define mmCB_COLOR7_ATTRIB3_BASE_IDX                                                                   1
6638 
6639 
6640 // addressBlock: gc_gfxudec
6641 // base address: 0x30000
6642 #define mmCP_EOP_DONE_ADDR_LO                                                                          0x2000
6643 #define mmCP_EOP_DONE_ADDR_LO_BASE_IDX                                                                 1
6644 #define mmCP_EOP_DONE_ADDR_HI                                                                          0x2001
6645 #define mmCP_EOP_DONE_ADDR_HI_BASE_IDX                                                                 1
6646 #define mmCP_EOP_DONE_DATA_LO                                                                          0x2002
6647 #define mmCP_EOP_DONE_DATA_LO_BASE_IDX                                                                 1
6648 #define mmCP_EOP_DONE_DATA_HI                                                                          0x2003
6649 #define mmCP_EOP_DONE_DATA_HI_BASE_IDX                                                                 1
6650 #define mmCP_EOP_LAST_FENCE_LO                                                                         0x2004
6651 #define mmCP_EOP_LAST_FENCE_LO_BASE_IDX                                                                1
6652 #define mmCP_EOP_LAST_FENCE_HI                                                                         0x2005
6653 #define mmCP_EOP_LAST_FENCE_HI_BASE_IDX                                                                1
6654 #define mmCP_STREAM_OUT_ADDR_LO                                                                        0x2006
6655 #define mmCP_STREAM_OUT_ADDR_LO_BASE_IDX                                                               1
6656 #define mmCP_STREAM_OUT_ADDR_HI                                                                        0x2007
6657 #define mmCP_STREAM_OUT_ADDR_HI_BASE_IDX                                                               1
6658 #define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO                                                                0x2008
6659 #define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO_BASE_IDX                                                       1
6660 #define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI                                                                0x2009
6661 #define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI_BASE_IDX                                                       1
6662 #define mmCP_NUM_PRIM_NEEDED_COUNT0_LO                                                                 0x200a
6663 #define mmCP_NUM_PRIM_NEEDED_COUNT0_LO_BASE_IDX                                                        1
6664 #define mmCP_NUM_PRIM_NEEDED_COUNT0_HI                                                                 0x200b
6665 #define mmCP_NUM_PRIM_NEEDED_COUNT0_HI_BASE_IDX                                                        1
6666 #define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO                                                                0x200c
6667 #define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO_BASE_IDX                                                       1
6668 #define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI                                                                0x200d
6669 #define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI_BASE_IDX                                                       1
6670 #define mmCP_NUM_PRIM_NEEDED_COUNT1_LO                                                                 0x200e
6671 #define mmCP_NUM_PRIM_NEEDED_COUNT1_LO_BASE_IDX                                                        1
6672 #define mmCP_NUM_PRIM_NEEDED_COUNT1_HI                                                                 0x200f
6673 #define mmCP_NUM_PRIM_NEEDED_COUNT1_HI_BASE_IDX                                                        1
6674 #define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO                                                                0x2010
6675 #define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO_BASE_IDX                                                       1
6676 #define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI                                                                0x2011
6677 #define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI_BASE_IDX                                                       1
6678 #define mmCP_NUM_PRIM_NEEDED_COUNT2_LO                                                                 0x2012
6679 #define mmCP_NUM_PRIM_NEEDED_COUNT2_LO_BASE_IDX                                                        1
6680 #define mmCP_NUM_PRIM_NEEDED_COUNT2_HI                                                                 0x2013
6681 #define mmCP_NUM_PRIM_NEEDED_COUNT2_HI_BASE_IDX                                                        1
6682 #define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO                                                                0x2014
6683 #define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX                                                       1
6684 #define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI                                                                0x2015
6685 #define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI_BASE_IDX                                                       1
6686 #define mmCP_NUM_PRIM_NEEDED_COUNT3_LO                                                                 0x2016
6687 #define mmCP_NUM_PRIM_NEEDED_COUNT3_LO_BASE_IDX                                                        1
6688 #define mmCP_NUM_PRIM_NEEDED_COUNT3_HI                                                                 0x2017
6689 #define mmCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX                                                        1
6690 #define mmCP_PIPE_STATS_ADDR_LO                                                                        0x2018
6691 #define mmCP_PIPE_STATS_ADDR_LO_BASE_IDX                                                               1
6692 #define mmCP_PIPE_STATS_ADDR_HI                                                                        0x2019
6693 #define mmCP_PIPE_STATS_ADDR_HI_BASE_IDX                                                               1
6694 #define mmCP_VGT_IAVERT_COUNT_LO                                                                       0x201a
6695 #define mmCP_VGT_IAVERT_COUNT_LO_BASE_IDX                                                              1
6696 #define mmCP_VGT_IAVERT_COUNT_HI                                                                       0x201b
6697 #define mmCP_VGT_IAVERT_COUNT_HI_BASE_IDX                                                              1
6698 #define mmCP_VGT_IAPRIM_COUNT_LO                                                                       0x201c
6699 #define mmCP_VGT_IAPRIM_COUNT_LO_BASE_IDX                                                              1
6700 #define mmCP_VGT_IAPRIM_COUNT_HI                                                                       0x201d
6701 #define mmCP_VGT_IAPRIM_COUNT_HI_BASE_IDX                                                              1
6702 #define mmCP_VGT_GSPRIM_COUNT_LO                                                                       0x201e
6703 #define mmCP_VGT_GSPRIM_COUNT_LO_BASE_IDX                                                              1
6704 #define mmCP_VGT_GSPRIM_COUNT_HI                                                                       0x201f
6705 #define mmCP_VGT_GSPRIM_COUNT_HI_BASE_IDX                                                              1
6706 #define mmCP_VGT_VSINVOC_COUNT_LO                                                                      0x2020
6707 #define mmCP_VGT_VSINVOC_COUNT_LO_BASE_IDX                                                             1
6708 #define mmCP_VGT_VSINVOC_COUNT_HI                                                                      0x2021
6709 #define mmCP_VGT_VSINVOC_COUNT_HI_BASE_IDX                                                             1
6710 #define mmCP_VGT_GSINVOC_COUNT_LO                                                                      0x2022
6711 #define mmCP_VGT_GSINVOC_COUNT_LO_BASE_IDX                                                             1
6712 #define mmCP_VGT_GSINVOC_COUNT_HI                                                                      0x2023
6713 #define mmCP_VGT_GSINVOC_COUNT_HI_BASE_IDX                                                             1
6714 #define mmCP_VGT_HSINVOC_COUNT_LO                                                                      0x2024
6715 #define mmCP_VGT_HSINVOC_COUNT_LO_BASE_IDX                                                             1
6716 #define mmCP_VGT_HSINVOC_COUNT_HI                                                                      0x2025
6717 #define mmCP_VGT_HSINVOC_COUNT_HI_BASE_IDX                                                             1
6718 #define mmCP_VGT_DSINVOC_COUNT_LO                                                                      0x2026
6719 #define mmCP_VGT_DSINVOC_COUNT_LO_BASE_IDX                                                             1
6720 #define mmCP_VGT_DSINVOC_COUNT_HI                                                                      0x2027
6721 #define mmCP_VGT_DSINVOC_COUNT_HI_BASE_IDX                                                             1
6722 #define mmCP_PA_CINVOC_COUNT_LO                                                                        0x2028
6723 #define mmCP_PA_CINVOC_COUNT_LO_BASE_IDX                                                               1
6724 #define mmCP_PA_CINVOC_COUNT_HI                                                                        0x2029
6725 #define mmCP_PA_CINVOC_COUNT_HI_BASE_IDX                                                               1
6726 #define mmCP_PA_CPRIM_COUNT_LO                                                                         0x202a
6727 #define mmCP_PA_CPRIM_COUNT_LO_BASE_IDX                                                                1
6728 #define mmCP_PA_CPRIM_COUNT_HI                                                                         0x202b
6729 #define mmCP_PA_CPRIM_COUNT_HI_BASE_IDX                                                                1
6730 #define mmCP_SC_PSINVOC_COUNT0_LO                                                                      0x202c
6731 #define mmCP_SC_PSINVOC_COUNT0_LO_BASE_IDX                                                             1
6732 #define mmCP_SC_PSINVOC_COUNT0_HI                                                                      0x202d
6733 #define mmCP_SC_PSINVOC_COUNT0_HI_BASE_IDX                                                             1
6734 #define mmCP_SC_PSINVOC_COUNT1_LO                                                                      0x202e
6735 #define mmCP_SC_PSINVOC_COUNT1_LO_BASE_IDX                                                             1
6736 #define mmCP_SC_PSINVOC_COUNT1_HI                                                                      0x202f
6737 #define mmCP_SC_PSINVOC_COUNT1_HI_BASE_IDX                                                             1
6738 #define mmCP_VGT_CSINVOC_COUNT_LO                                                                      0x2030
6739 #define mmCP_VGT_CSINVOC_COUNT_LO_BASE_IDX                                                             1
6740 #define mmCP_VGT_CSINVOC_COUNT_HI                                                                      0x2031
6741 #define mmCP_VGT_CSINVOC_COUNT_HI_BASE_IDX                                                             1
6742 #define mmCP_PIPE_STATS_CONTROL                                                                        0x203d
6743 #define mmCP_PIPE_STATS_CONTROL_BASE_IDX                                                               1
6744 #define mmCP_STREAM_OUT_CONTROL                                                                        0x203e
6745 #define mmCP_STREAM_OUT_CONTROL_BASE_IDX                                                               1
6746 #define mmCP_STRMOUT_CNTL                                                                              0x203f
6747 #define mmCP_STRMOUT_CNTL_BASE_IDX                                                                     1
6748 #define mmSCRATCH_REG0                                                                                 0x2040
6749 #define mmSCRATCH_REG0_BASE_IDX                                                                        1
6750 #define mmSCRATCH_REG1                                                                                 0x2041
6751 #define mmSCRATCH_REG1_BASE_IDX                                                                        1
6752 #define mmSCRATCH_REG2                                                                                 0x2042
6753 #define mmSCRATCH_REG2_BASE_IDX                                                                        1
6754 #define mmSCRATCH_REG3                                                                                 0x2043
6755 #define mmSCRATCH_REG3_BASE_IDX                                                                        1
6756 #define mmSCRATCH_REG4                                                                                 0x2044
6757 #define mmSCRATCH_REG4_BASE_IDX                                                                        1
6758 #define mmSCRATCH_REG5                                                                                 0x2045
6759 #define mmSCRATCH_REG5_BASE_IDX                                                                        1
6760 #define mmSCRATCH_REG6                                                                                 0x2046
6761 #define mmSCRATCH_REG6_BASE_IDX                                                                        1
6762 #define mmSCRATCH_REG7                                                                                 0x2047
6763 #define mmSCRATCH_REG7_BASE_IDX                                                                        1
6764 #define mmSCRATCH_REG_ATOMIC                                                                           0x2048
6765 #define mmSCRATCH_REG_ATOMIC_BASE_IDX                                                                  1
6766 #define mmSCRATCH_REG_CMPSWAP_ATOMIC                                                                   0x2048
6767 #define mmSCRATCH_REG_CMPSWAP_ATOMIC_BASE_IDX                                                          1
6768 #define mmCP_APPEND_DDID_CNT                                                                           0x204b
6769 #define mmCP_APPEND_DDID_CNT_BASE_IDX                                                                  1
6770 #define mmCP_APPEND_DATA_HI                                                                            0x204c
6771 #define mmCP_APPEND_DATA_HI_BASE_IDX                                                                   1
6772 #define mmCP_APPEND_LAST_CS_FENCE_HI                                                                   0x204d
6773 #define mmCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX                                                          1
6774 #define mmCP_APPEND_LAST_PS_FENCE_HI                                                                   0x204e
6775 #define mmCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX                                                          1
6776 #define mmSCRATCH_UMSK                                                                                 0x2050
6777 #define mmSCRATCH_UMSK_BASE_IDX                                                                        1
6778 #define mmSCRATCH_ADDR                                                                                 0x2051
6779 #define mmSCRATCH_ADDR_BASE_IDX                                                                        1
6780 #define mmCP_PFP_ATOMIC_PREOP_LO                                                                       0x2052
6781 #define mmCP_PFP_ATOMIC_PREOP_LO_BASE_IDX                                                              1
6782 #define mmCP_PFP_ATOMIC_PREOP_HI                                                                       0x2053
6783 #define mmCP_PFP_ATOMIC_PREOP_HI_BASE_IDX                                                              1
6784 #define mmCP_PFP_GDS_ATOMIC0_PREOP_LO                                                                  0x2054
6785 #define mmCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX                                                         1
6786 #define mmCP_PFP_GDS_ATOMIC0_PREOP_HI                                                                  0x2055
6787 #define mmCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX                                                         1
6788 #define mmCP_PFP_GDS_ATOMIC1_PREOP_LO                                                                  0x2056
6789 #define mmCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX                                                         1
6790 #define mmCP_PFP_GDS_ATOMIC1_PREOP_HI                                                                  0x2057
6791 #define mmCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX                                                         1
6792 #define mmCP_APPEND_ADDR_LO                                                                            0x2058
6793 #define mmCP_APPEND_ADDR_LO_BASE_IDX                                                                   1
6794 #define mmCP_APPEND_ADDR_HI                                                                            0x2059
6795 #define mmCP_APPEND_ADDR_HI_BASE_IDX                                                                   1
6796 #define mmCP_APPEND_DATA                                                                               0x205a
6797 #define mmCP_APPEND_DATA_BASE_IDX                                                                      1
6798 #define mmCP_APPEND_DATA_LO                                                                            0x205a
6799 #define mmCP_APPEND_DATA_LO_BASE_IDX                                                                   1
6800 #define mmCP_APPEND_LAST_CS_FENCE                                                                      0x205b
6801 #define mmCP_APPEND_LAST_CS_FENCE_BASE_IDX                                                             1
6802 #define mmCP_APPEND_LAST_CS_FENCE_LO                                                                   0x205b
6803 #define mmCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX                                                          1
6804 #define mmCP_APPEND_LAST_PS_FENCE                                                                      0x205c
6805 #define mmCP_APPEND_LAST_PS_FENCE_BASE_IDX                                                             1
6806 #define mmCP_APPEND_LAST_PS_FENCE_LO                                                                   0x205c
6807 #define mmCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX                                                          1
6808 #define mmCP_ATOMIC_PREOP_LO                                                                           0x205d
6809 #define mmCP_ATOMIC_PREOP_LO_BASE_IDX                                                                  1
6810 #define mmCP_ME_ATOMIC_PREOP_LO                                                                        0x205d
6811 #define mmCP_ME_ATOMIC_PREOP_LO_BASE_IDX                                                               1
6812 #define mmCP_ATOMIC_PREOP_HI                                                                           0x205e
6813 #define mmCP_ATOMIC_PREOP_HI_BASE_IDX                                                                  1
6814 #define mmCP_ME_ATOMIC_PREOP_HI                                                                        0x205e
6815 #define mmCP_ME_ATOMIC_PREOP_HI_BASE_IDX                                                               1
6816 #define mmCP_GDS_ATOMIC0_PREOP_LO                                                                      0x205f
6817 #define mmCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX                                                             1
6818 #define mmCP_ME_GDS_ATOMIC0_PREOP_LO                                                                   0x205f
6819 #define mmCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX                                                          1
6820 #define mmCP_GDS_ATOMIC0_PREOP_HI                                                                      0x2060
6821 #define mmCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX                                                             1
6822 #define mmCP_ME_GDS_ATOMIC0_PREOP_HI                                                                   0x2060
6823 #define mmCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX                                                          1
6824 #define mmCP_GDS_ATOMIC1_PREOP_LO                                                                      0x2061
6825 #define mmCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX                                                             1
6826 #define mmCP_ME_GDS_ATOMIC1_PREOP_LO                                                                   0x2061
6827 #define mmCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX                                                          1
6828 #define mmCP_GDS_ATOMIC1_PREOP_HI                                                                      0x2062
6829 #define mmCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX                                                             1
6830 #define mmCP_ME_GDS_ATOMIC1_PREOP_HI                                                                   0x2062
6831 #define mmCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX                                                          1
6832 #define mmCP_ME_MC_WADDR_LO                                                                            0x2069
6833 #define mmCP_ME_MC_WADDR_LO_BASE_IDX                                                                   1
6834 #define mmCP_ME_MC_WADDR_HI                                                                            0x206a
6835 #define mmCP_ME_MC_WADDR_HI_BASE_IDX                                                                   1
6836 #define mmCP_ME_MC_WDATA_LO                                                                            0x206b
6837 #define mmCP_ME_MC_WDATA_LO_BASE_IDX                                                                   1
6838 #define mmCP_ME_MC_WDATA_HI                                                                            0x206c
6839 #define mmCP_ME_MC_WDATA_HI_BASE_IDX                                                                   1
6840 #define mmCP_ME_MC_RADDR_LO                                                                            0x206d
6841 #define mmCP_ME_MC_RADDR_LO_BASE_IDX                                                                   1
6842 #define mmCP_ME_MC_RADDR_HI                                                                            0x206e
6843 #define mmCP_ME_MC_RADDR_HI_BASE_IDX                                                                   1
6844 #define mmCP_SEM_WAIT_TIMER                                                                            0x206f
6845 #define mmCP_SEM_WAIT_TIMER_BASE_IDX                                                                   1
6846 #define mmCP_SIG_SEM_ADDR_LO                                                                           0x2070
6847 #define mmCP_SIG_SEM_ADDR_LO_BASE_IDX                                                                  1
6848 #define mmCP_SIG_SEM_ADDR_HI                                                                           0x2071
6849 #define mmCP_SIG_SEM_ADDR_HI_BASE_IDX                                                                  1
6850 #define mmCP_WAIT_REG_MEM_TIMEOUT                                                                      0x2074
6851 #define mmCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX                                                             1
6852 #define mmCP_WAIT_SEM_ADDR_LO                                                                          0x2075
6853 #define mmCP_WAIT_SEM_ADDR_LO_BASE_IDX                                                                 1
6854 #define mmCP_WAIT_SEM_ADDR_HI                                                                          0x2076
6855 #define mmCP_WAIT_SEM_ADDR_HI_BASE_IDX                                                                 1
6856 #define mmCP_DMA_PFP_CONTROL                                                                           0x2077
6857 #define mmCP_DMA_PFP_CONTROL_BASE_IDX                                                                  1
6858 #define mmCP_DMA_ME_CONTROL                                                                            0x2078
6859 #define mmCP_DMA_ME_CONTROL_BASE_IDX                                                                   1
6860 #define mmCP_COHER_BASE_HI                                                                             0x2079
6861 #define mmCP_COHER_BASE_HI_BASE_IDX                                                                    1
6862 #define mmCP_COHER_START_DELAY                                                                         0x207b
6863 #define mmCP_COHER_START_DELAY_BASE_IDX                                                                1
6864 #define mmCP_COHER_CNTL                                                                                0x207c
6865 #define mmCP_COHER_CNTL_BASE_IDX                                                                       1
6866 #define mmCP_COHER_SIZE                                                                                0x207d
6867 #define mmCP_COHER_SIZE_BASE_IDX                                                                       1
6868 #define mmCP_COHER_BASE                                                                                0x207e
6869 #define mmCP_COHER_BASE_BASE_IDX                                                                       1
6870 #define mmCP_COHER_STATUS                                                                              0x207f
6871 #define mmCP_COHER_STATUS_BASE_IDX                                                                     1
6872 #define mmCP_DMA_ME_SRC_ADDR                                                                           0x2080
6873 #define mmCP_DMA_ME_SRC_ADDR_BASE_IDX                                                                  1
6874 #define mmCP_DMA_ME_SRC_ADDR_HI                                                                        0x2081
6875 #define mmCP_DMA_ME_SRC_ADDR_HI_BASE_IDX                                                               1
6876 #define mmCP_DMA_ME_DST_ADDR                                                                           0x2082
6877 #define mmCP_DMA_ME_DST_ADDR_BASE_IDX                                                                  1
6878 #define mmCP_DMA_ME_DST_ADDR_HI                                                                        0x2083
6879 #define mmCP_DMA_ME_DST_ADDR_HI_BASE_IDX                                                               1
6880 #define mmCP_DMA_ME_COMMAND                                                                            0x2084
6881 #define mmCP_DMA_ME_COMMAND_BASE_IDX                                                                   1
6882 #define mmCP_DMA_PFP_SRC_ADDR                                                                          0x2085
6883 #define mmCP_DMA_PFP_SRC_ADDR_BASE_IDX                                                                 1
6884 #define mmCP_DMA_PFP_SRC_ADDR_HI                                                                       0x2086
6885 #define mmCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX                                                              1
6886 #define mmCP_DMA_PFP_DST_ADDR                                                                          0x2087
6887 #define mmCP_DMA_PFP_DST_ADDR_BASE_IDX                                                                 1
6888 #define mmCP_DMA_PFP_DST_ADDR_HI                                                                       0x2088
6889 #define mmCP_DMA_PFP_DST_ADDR_HI_BASE_IDX                                                              1
6890 #define mmCP_DMA_PFP_COMMAND                                                                           0x2089
6891 #define mmCP_DMA_PFP_COMMAND_BASE_IDX                                                                  1
6892 #define mmCP_DMA_CNTL                                                                                  0x208a
6893 #define mmCP_DMA_CNTL_BASE_IDX                                                                         1
6894 #define mmCP_DMA_READ_TAGS                                                                             0x208b
6895 #define mmCP_DMA_READ_TAGS_BASE_IDX                                                                    1
6896 #define mmCP_COHER_SIZE_HI                                                                             0x208c
6897 #define mmCP_COHER_SIZE_HI_BASE_IDX                                                                    1
6898 #define mmCP_PFP_IB_CONTROL                                                                            0x208d
6899 #define mmCP_PFP_IB_CONTROL_BASE_IDX                                                                   1
6900 #define mmCP_PFP_LOAD_CONTROL                                                                          0x208e
6901 #define mmCP_PFP_LOAD_CONTROL_BASE_IDX                                                                 1
6902 #define mmCP_SCRATCH_INDEX                                                                             0x208f
6903 #define mmCP_SCRATCH_INDEX_BASE_IDX                                                                    1
6904 #define mmCP_SCRATCH_DATA                                                                              0x2090
6905 #define mmCP_SCRATCH_DATA_BASE_IDX                                                                     1
6906 #define mmCP_RB_OFFSET                                                                                 0x2091
6907 #define mmCP_RB_OFFSET_BASE_IDX                                                                        1
6908 #define mmCP_IB2_OFFSET                                                                                0x2093
6909 #define mmCP_IB2_OFFSET_BASE_IDX                                                                       1
6910 #define mmCP_IB2_PREAMBLE_BEGIN                                                                        0x2096
6911 #define mmCP_IB2_PREAMBLE_BEGIN_BASE_IDX                                                               1
6912 #define mmCP_IB2_PREAMBLE_END                                                                          0x2097
6913 #define mmCP_IB2_PREAMBLE_END_BASE_IDX                                                                 1
6914 #define mmCP_CE_IB1_OFFSET                                                                             0x2098
6915 #define mmCP_CE_IB1_OFFSET_BASE_IDX                                                                    1
6916 #define mmCP_CE_IB2_OFFSET                                                                             0x2099
6917 #define mmCP_CE_IB2_OFFSET_BASE_IDX                                                                    1
6918 #define mmCP_CE_COUNTER                                                                                0x209a
6919 #define mmCP_CE_COUNTER_BASE_IDX                                                                       1
6920 #define mmCP_DMA_ME_CMD_ADDR_LO                                                                        0x209c
6921 #define mmCP_DMA_ME_CMD_ADDR_LO_BASE_IDX                                                               1
6922 #define mmCP_DMA_ME_CMD_ADDR_HI                                                                        0x209d
6923 #define mmCP_DMA_ME_CMD_ADDR_HI_BASE_IDX                                                               1
6924 #define mmCP_DMA_PFP_CMD_ADDR_LO                                                                       0x209e
6925 #define mmCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX                                                              1
6926 #define mmCP_DMA_PFP_CMD_ADDR_HI                                                                       0x209f
6927 #define mmCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX                                                              1
6928 #define mmCP_APPEND_CMD_ADDR_LO                                                                        0x20a0
6929 #define mmCP_APPEND_CMD_ADDR_LO_BASE_IDX                                                               1
6930 #define mmCP_APPEND_CMD_ADDR_HI                                                                        0x20a1
6931 #define mmCP_APPEND_CMD_ADDR_HI_BASE_IDX                                                               1
6932 #define mmUCONFIG_RESERVED_REG0                                                                        0x20a2
6933 #define mmUCONFIG_RESERVED_REG0_BASE_IDX                                                               1
6934 #define mmUCONFIG_RESERVED_REG1                                                                        0x20a3
6935 #define mmUCONFIG_RESERVED_REG1_BASE_IDX                                                               1
6936 #define mmCP_CE_ATOMIC_PREOP_LO                                                                        0x20a8
6937 #define mmCP_CE_ATOMIC_PREOP_LO_BASE_IDX                                                               1
6938 #define mmCP_CE_ATOMIC_PREOP_HI                                                                        0x20a9
6939 #define mmCP_CE_ATOMIC_PREOP_HI_BASE_IDX                                                               1
6940 #define mmCP_CE_GDS_ATOMIC0_PREOP_LO                                                                   0x20aa
6941 #define mmCP_CE_GDS_ATOMIC0_PREOP_LO_BASE_IDX                                                          1
6942 #define mmCP_CE_GDS_ATOMIC0_PREOP_HI                                                                   0x20ab
6943 #define mmCP_CE_GDS_ATOMIC0_PREOP_HI_BASE_IDX                                                          1
6944 #define mmCP_CE_GDS_ATOMIC1_PREOP_LO                                                                   0x20ac
6945 #define mmCP_CE_GDS_ATOMIC1_PREOP_LO_BASE_IDX                                                          1
6946 #define mmCP_CE_GDS_ATOMIC1_PREOP_HI                                                                   0x20ad
6947 #define mmCP_CE_GDS_ATOMIC1_PREOP_HI_BASE_IDX                                                          1
6948 #define mmCP_CE_INIT_CMD_BUFSZ                                                                         0x20bd
6949 #define mmCP_CE_INIT_CMD_BUFSZ_BASE_IDX                                                                1
6950 #define mmCP_CE_IB1_CMD_BUFSZ                                                                          0x20be
6951 #define mmCP_CE_IB1_CMD_BUFSZ_BASE_IDX                                                                 1
6952 #define mmCP_CE_IB2_CMD_BUFSZ                                                                          0x20bf
6953 #define mmCP_CE_IB2_CMD_BUFSZ_BASE_IDX                                                                 1
6954 #define mmCP_IB2_CMD_BUFSZ                                                                             0x20c1
6955 #define mmCP_IB2_CMD_BUFSZ_BASE_IDX                                                                    1
6956 #define mmCP_ST_CMD_BUFSZ                                                                              0x20c2
6957 #define mmCP_ST_CMD_BUFSZ_BASE_IDX                                                                     1
6958 #define mmCP_CE_INIT_BASE_LO                                                                           0x20c3
6959 #define mmCP_CE_INIT_BASE_LO_BASE_IDX                                                                  1
6960 #define mmCP_CE_INIT_BASE_HI                                                                           0x20c4
6961 #define mmCP_CE_INIT_BASE_HI_BASE_IDX                                                                  1
6962 #define mmCP_CE_INIT_BUFSZ                                                                             0x20c5
6963 #define mmCP_CE_INIT_BUFSZ_BASE_IDX                                                                    1
6964 #define mmCP_CE_IB1_BASE_LO                                                                            0x20c6
6965 #define mmCP_CE_IB1_BASE_LO_BASE_IDX                                                                   1
6966 #define mmCP_CE_IB1_BASE_HI                                                                            0x20c7
6967 #define mmCP_CE_IB1_BASE_HI_BASE_IDX                                                                   1
6968 #define mmCP_CE_IB1_BUFSZ                                                                              0x20c8
6969 #define mmCP_CE_IB1_BUFSZ_BASE_IDX                                                                     1
6970 #define mmCP_CE_IB2_BASE_LO                                                                            0x20c9
6971 #define mmCP_CE_IB2_BASE_LO_BASE_IDX                                                                   1
6972 #define mmCP_CE_IB2_BASE_HI                                                                            0x20ca
6973 #define mmCP_CE_IB2_BASE_HI_BASE_IDX                                                                   1
6974 #define mmCP_CE_IB2_BUFSZ                                                                              0x20cb
6975 #define mmCP_CE_IB2_BUFSZ_BASE_IDX                                                                     1
6976 #define mmCP_IB1_BASE_LO                                                                               0x20cc
6977 #define mmCP_IB1_BASE_LO_BASE_IDX                                                                      1
6978 #define mmCP_IB1_BASE_HI                                                                               0x20cd
6979 #define mmCP_IB1_BASE_HI_BASE_IDX                                                                      1
6980 #define mmCP_IB1_BUFSZ                                                                                 0x20ce
6981 #define mmCP_IB1_BUFSZ_BASE_IDX                                                                        1
6982 #define mmCP_IB2_BASE_LO                                                                               0x20cf
6983 #define mmCP_IB2_BASE_LO_BASE_IDX                                                                      1
6984 #define mmCP_IB2_BASE_HI                                                                               0x20d0
6985 #define mmCP_IB2_BASE_HI_BASE_IDX                                                                      1
6986 #define mmCP_IB2_BUFSZ                                                                                 0x20d1
6987 #define mmCP_IB2_BUFSZ_BASE_IDX                                                                        1
6988 #define mmCP_ST_BASE_LO                                                                                0x20d2
6989 #define mmCP_ST_BASE_LO_BASE_IDX                                                                       1
6990 #define mmCP_ST_BASE_HI                                                                                0x20d3
6991 #define mmCP_ST_BASE_HI_BASE_IDX                                                                       1
6992 #define mmCP_ST_BUFSZ                                                                                  0x20d4
6993 #define mmCP_ST_BUFSZ_BASE_IDX                                                                         1
6994 #define mmCP_EOP_DONE_EVENT_CNTL                                                                       0x20d5
6995 #define mmCP_EOP_DONE_EVENT_CNTL_BASE_IDX                                                              1
6996 #define mmCP_EOP_DONE_DATA_CNTL                                                                        0x20d6
6997 #define mmCP_EOP_DONE_DATA_CNTL_BASE_IDX                                                               1
6998 #define mmCP_EOP_DONE_CNTX_ID                                                                          0x20d7
6999 #define mmCP_EOP_DONE_CNTX_ID_BASE_IDX                                                                 1
7000 #define mmCP_DB_BASE_LO                                                                                0x20d8
7001 #define mmCP_DB_BASE_LO_BASE_IDX                                                                       1
7002 #define mmCP_DB_BASE_HI                                                                                0x20d9
7003 #define mmCP_DB_BASE_HI_BASE_IDX                                                                       1
7004 #define mmCP_DB_BUFSZ                                                                                  0x20da
7005 #define mmCP_DB_BUFSZ_BASE_IDX                                                                         1
7006 #define mmCP_DB_CMD_BUFSZ                                                                              0x20db
7007 #define mmCP_DB_CMD_BUFSZ_BASE_IDX                                                                     1
7008 #define mmCP_CE_DB_BASE_LO                                                                             0x20dc
7009 #define mmCP_CE_DB_BASE_LO_BASE_IDX                                                                    1
7010 #define mmCP_CE_DB_BASE_HI                                                                             0x20dd
7011 #define mmCP_CE_DB_BASE_HI_BASE_IDX                                                                    1
7012 #define mmCP_CE_DB_BUFSZ                                                                               0x20de
7013 #define mmCP_CE_DB_BUFSZ_BASE_IDX                                                                      1
7014 #define mmCP_CE_DB_CMD_BUFSZ                                                                           0x20df
7015 #define mmCP_CE_DB_CMD_BUFSZ_BASE_IDX                                                                  1
7016 #define mmCP_PFP_COMPLETION_STATUS                                                                     0x20ec
7017 #define mmCP_PFP_COMPLETION_STATUS_BASE_IDX                                                            1
7018 #define mmCP_CE_COMPLETION_STATUS                                                                      0x20ed
7019 #define mmCP_CE_COMPLETION_STATUS_BASE_IDX                                                             1
7020 #define mmCP_PRED_NOT_VISIBLE                                                                          0x20ee
7021 #define mmCP_PRED_NOT_VISIBLE_BASE_IDX                                                                 1
7022 #define mmCP_PFP_METADATA_BASE_ADDR                                                                    0x20f0
7023 #define mmCP_PFP_METADATA_BASE_ADDR_BASE_IDX                                                           1
7024 #define mmCP_PFP_METADATA_BASE_ADDR_HI                                                                 0x20f1
7025 #define mmCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX                                                        1
7026 #define mmCP_CE_METADATA_BASE_ADDR                                                                     0x20f2
7027 #define mmCP_CE_METADATA_BASE_ADDR_BASE_IDX                                                            1
7028 #define mmCP_CE_METADATA_BASE_ADDR_HI                                                                  0x20f3
7029 #define mmCP_CE_METADATA_BASE_ADDR_HI_BASE_IDX                                                         1
7030 #define mmCP_DRAW_INDX_INDR_ADDR                                                                       0x20f4
7031 #define mmCP_DRAW_INDX_INDR_ADDR_BASE_IDX                                                              1
7032 #define mmCP_DRAW_INDX_INDR_ADDR_HI                                                                    0x20f5
7033 #define mmCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX                                                           1
7034 #define mmCP_DISPATCH_INDR_ADDR                                                                        0x20f6
7035 #define mmCP_DISPATCH_INDR_ADDR_BASE_IDX                                                               1
7036 #define mmCP_DISPATCH_INDR_ADDR_HI                                                                     0x20f7
7037 #define mmCP_DISPATCH_INDR_ADDR_HI_BASE_IDX                                                            1
7038 #define mmCP_INDEX_BASE_ADDR                                                                           0x20f8
7039 #define mmCP_INDEX_BASE_ADDR_BASE_IDX                                                                  1
7040 #define mmCP_INDEX_BASE_ADDR_HI                                                                        0x20f9
7041 #define mmCP_INDEX_BASE_ADDR_HI_BASE_IDX                                                               1
7042 #define mmCP_INDEX_TYPE                                                                                0x20fa
7043 #define mmCP_INDEX_TYPE_BASE_IDX                                                                       1
7044 #define mmCP_GDS_BKUP_ADDR                                                                             0x20fb
7045 #define mmCP_GDS_BKUP_ADDR_BASE_IDX                                                                    1
7046 #define mmCP_GDS_BKUP_ADDR_HI                                                                          0x20fc
7047 #define mmCP_GDS_BKUP_ADDR_HI_BASE_IDX                                                                 1
7048 #define mmCP_SAMPLE_STATUS                                                                             0x20fd
7049 #define mmCP_SAMPLE_STATUS_BASE_IDX                                                                    1
7050 #define mmCP_ME_COHER_CNTL                                                                             0x20fe
7051 #define mmCP_ME_COHER_CNTL_BASE_IDX                                                                    1
7052 #define mmCP_ME_COHER_SIZE                                                                             0x20ff
7053 #define mmCP_ME_COHER_SIZE_BASE_IDX                                                                    1
7054 #define mmCP_ME_COHER_SIZE_HI                                                                          0x2100
7055 #define mmCP_ME_COHER_SIZE_HI_BASE_IDX                                                                 1
7056 #define mmCP_ME_COHER_BASE                                                                             0x2101
7057 #define mmCP_ME_COHER_BASE_BASE_IDX                                                                    1
7058 #define mmCP_ME_COHER_BASE_HI                                                                          0x2102
7059 #define mmCP_ME_COHER_BASE_HI_BASE_IDX                                                                 1
7060 #define mmCP_ME_COHER_STATUS                                                                           0x2103
7061 #define mmCP_ME_COHER_STATUS_BASE_IDX                                                                  1
7062 #define mmRLC_GPM_PERF_COUNT_0                                                                         0x2140
7063 #define mmRLC_GPM_PERF_COUNT_0_BASE_IDX                                                                1
7064 #define mmRLC_GPM_PERF_COUNT_1                                                                         0x2141
7065 #define mmRLC_GPM_PERF_COUNT_1_BASE_IDX                                                                1
7066 #define mmGRBM_GFX_INDEX                                                                               0x2200
7067 #define mmGRBM_GFX_INDEX_BASE_IDX                                                                      1
7068 #define mmVGT_ESGS_RING_SIZE_UMD                                                                       0x2240
7069 #define mmVGT_ESGS_RING_SIZE_UMD_BASE_IDX                                                              1
7070 #define mmVGT_GSVS_RING_SIZE_UMD                                                                       0x2241
7071 #define mmVGT_GSVS_RING_SIZE_UMD_BASE_IDX                                                              1
7072 #define mmVGT_PRIMITIVE_TYPE                                                                           0x2242
7073 #define mmVGT_PRIMITIVE_TYPE_BASE_IDX                                                                  1
7074 #define mmVGT_INDEX_TYPE                                                                               0x2243
7075 #define mmVGT_INDEX_TYPE_BASE_IDX                                                                      1
7076 #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0                                                             0x2244
7077 #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0_BASE_IDX                                                    1
7078 #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1                                                             0x2245
7079 #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1_BASE_IDX                                                    1
7080 #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2                                                             0x2246
7081 #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2_BASE_IDX                                                    1
7082 #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3                                                             0x2247
7083 #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3_BASE_IDX                                                    1
7084 #define mmGE_MIN_VTX_INDX                                                                              0x2249
7085 #define mmGE_MIN_VTX_INDX_BASE_IDX                                                                     1
7086 #define mmGE_INDX_OFFSET                                                                               0x224a
7087 #define mmGE_INDX_OFFSET_BASE_IDX                                                                      1
7088 #define mmGE_MULTI_PRIM_IB_RESET_EN                                                                    0x224b
7089 #define mmGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX                                                           1
7090 #define mmVGT_NUM_INDICES                                                                              0x224c
7091 #define mmVGT_NUM_INDICES_BASE_IDX                                                                     1
7092 #define mmVGT_NUM_INSTANCES                                                                            0x224d
7093 #define mmVGT_NUM_INSTANCES_BASE_IDX                                                                   1
7094 #define mmVGT_TF_RING_SIZE_UMD                                                                         0x224e
7095 #define mmVGT_TF_RING_SIZE_UMD_BASE_IDX                                                                1
7096 #define mmVGT_HS_OFFCHIP_PARAM_UMD                                                                     0x224f
7097 #define mmVGT_HS_OFFCHIP_PARAM_UMD_BASE_IDX                                                            1
7098 #define mmVGT_TF_MEMORY_BASE_UMD                                                                       0x2250
7099 #define mmVGT_TF_MEMORY_BASE_UMD_BASE_IDX                                                              1
7100 #define mmGE_DMA_FIRST_INDEX                                                                           0x2251
7101 #define mmGE_DMA_FIRST_INDEX_BASE_IDX                                                                  1
7102 #define mmWD_POS_BUF_BASE                                                                              0x2252
7103 #define mmWD_POS_BUF_BASE_BASE_IDX                                                                     1
7104 #define mmWD_POS_BUF_BASE_HI                                                                           0x2253
7105 #define mmWD_POS_BUF_BASE_HI_BASE_IDX                                                                  1
7106 #define mmWD_CNTL_SB_BUF_BASE                                                                          0x2254
7107 #define mmWD_CNTL_SB_BUF_BASE_BASE_IDX                                                                 1
7108 #define mmWD_CNTL_SB_BUF_BASE_HI                                                                       0x2255
7109 #define mmWD_CNTL_SB_BUF_BASE_HI_BASE_IDX                                                              1
7110 #define mmWD_INDEX_BUF_BASE                                                                            0x2256
7111 #define mmWD_INDEX_BUF_BASE_BASE_IDX                                                                   1
7112 #define mmWD_INDEX_BUF_BASE_HI                                                                         0x2257
7113 #define mmWD_INDEX_BUF_BASE_HI_BASE_IDX                                                                1
7114 #define mmIA_MULTI_VGT_PARAM_PIPED                                                                     0x2258
7115 #define mmIA_MULTI_VGT_PARAM_PIPED_BASE_IDX                                                            1
7116 #define mmGE_MAX_VTX_INDX                                                                              0x2259
7117 #define mmGE_MAX_VTX_INDX_BASE_IDX                                                                     1
7118 #define mmVGT_INSTANCE_BASE_ID                                                                         0x225a
7119 #define mmVGT_INSTANCE_BASE_ID_BASE_IDX                                                                1
7120 #define mmGE_CNTL                                                                                      0x225b
7121 #define mmGE_CNTL_BASE_IDX                                                                             1
7122 #define mmGE_USER_VGPR1                                                                                0x225c
7123 #define mmGE_USER_VGPR1_BASE_IDX                                                                       1
7124 #define mmGE_USER_VGPR2                                                                                0x225d
7125 #define mmGE_USER_VGPR2_BASE_IDX                                                                       1
7126 #define mmGE_USER_VGPR3                                                                                0x225e
7127 #define mmGE_USER_VGPR3_BASE_IDX                                                                       1
7128 #define mmGE_STEREO_CNTL                                                                               0x225f
7129 #define mmGE_STEREO_CNTL_BASE_IDX                                                                      1
7130 #define mmGE_PC_ALLOC                                                                                  0x2260
7131 #define mmGE_PC_ALLOC_BASE_IDX                                                                         1
7132 #define mmVGT_TF_MEMORY_BASE_HI_UMD                                                                    0x2261
7133 #define mmVGT_TF_MEMORY_BASE_HI_UMD_BASE_IDX                                                           1
7134 #define mmGE_USER_VGPR_EN                                                                              0x2262
7135 #define mmGE_USER_VGPR_EN_BASE_IDX                                                                     1
7136 #define mmPA_SU_LINE_STIPPLE_VALUE                                                                     0x2280
7137 #define mmPA_SU_LINE_STIPPLE_VALUE_BASE_IDX                                                            1
7138 #define mmPA_SC_LINE_STIPPLE_STATE                                                                     0x2281
7139 #define mmPA_SC_LINE_STIPPLE_STATE_BASE_IDX                                                            1
7140 #define mmPA_SC_SCREEN_EXTENT_MIN_0                                                                    0x2284
7141 #define mmPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX                                                           1
7142 #define mmPA_SC_SCREEN_EXTENT_MAX_0                                                                    0x2285
7143 #define mmPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX                                                           1
7144 #define mmPA_SC_SCREEN_EXTENT_MIN_1                                                                    0x2286
7145 #define mmPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX                                                           1
7146 #define mmPA_SC_SCREEN_EXTENT_MAX_1                                                                    0x228b
7147 #define mmPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX                                                           1
7148 #define mmPA_SC_P3D_TRAP_SCREEN_HV_EN                                                                  0x22a0
7149 #define mmPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX                                                         1
7150 #define mmPA_SC_P3D_TRAP_SCREEN_H                                                                      0x22a1
7151 #define mmPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX                                                             1
7152 #define mmPA_SC_P3D_TRAP_SCREEN_V                                                                      0x22a2
7153 #define mmPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX                                                             1
7154 #define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE                                                             0x22a3
7155 #define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX                                                    1
7156 #define mmPA_SC_P3D_TRAP_SCREEN_COUNT                                                                  0x22a4
7157 #define mmPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX                                                         1
7158 #define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN                                                                 0x22a8
7159 #define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX                                                        1
7160 #define mmPA_SC_HP3D_TRAP_SCREEN_H                                                                     0x22a9
7161 #define mmPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX                                                            1
7162 #define mmPA_SC_HP3D_TRAP_SCREEN_V                                                                     0x22aa
7163 #define mmPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX                                                            1
7164 #define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE                                                            0x22ab
7165 #define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX                                                   1
7166 #define mmPA_SC_HP3D_TRAP_SCREEN_COUNT                                                                 0x22ac
7167 #define mmPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX                                                        1
7168 #define mmPA_SC_TRAP_SCREEN_HV_EN                                                                      0x22b0
7169 #define mmPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX                                                             1
7170 #define mmPA_SC_TRAP_SCREEN_H                                                                          0x22b1
7171 #define mmPA_SC_TRAP_SCREEN_H_BASE_IDX                                                                 1
7172 #define mmPA_SC_TRAP_SCREEN_V                                                                          0x22b2
7173 #define mmPA_SC_TRAP_SCREEN_V_BASE_IDX                                                                 1
7174 #define mmPA_SC_TRAP_SCREEN_OCCURRENCE                                                                 0x22b3
7175 #define mmPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX                                                        1
7176 #define mmPA_SC_TRAP_SCREEN_COUNT                                                                      0x22b4
7177 #define mmPA_SC_TRAP_SCREEN_COUNT_BASE_IDX                                                             1
7178 #define mmSQ_THREAD_TRACE_USERDATA_0                                                                   0x2340
7179 #define mmSQ_THREAD_TRACE_USERDATA_0_BASE_IDX                                                          1
7180 #define mmSQ_THREAD_TRACE_USERDATA_1                                                                   0x2341
7181 #define mmSQ_THREAD_TRACE_USERDATA_1_BASE_IDX                                                          1
7182 #define mmSQ_THREAD_TRACE_USERDATA_2                                                                   0x2342
7183 #define mmSQ_THREAD_TRACE_USERDATA_2_BASE_IDX                                                          1
7184 #define mmSQ_THREAD_TRACE_USERDATA_3                                                                   0x2343
7185 #define mmSQ_THREAD_TRACE_USERDATA_3_BASE_IDX                                                          1
7186 #define mmSQ_THREAD_TRACE_USERDATA_4                                                                   0x2344
7187 #define mmSQ_THREAD_TRACE_USERDATA_4_BASE_IDX                                                          1
7188 #define mmSQ_THREAD_TRACE_USERDATA_5                                                                   0x2345
7189 #define mmSQ_THREAD_TRACE_USERDATA_5_BASE_IDX                                                          1
7190 #define mmSQ_THREAD_TRACE_USERDATA_6                                                                   0x2346
7191 #define mmSQ_THREAD_TRACE_USERDATA_6_BASE_IDX                                                          1
7192 #define mmSQ_THREAD_TRACE_USERDATA_7                                                                   0x2347
7193 #define mmSQ_THREAD_TRACE_USERDATA_7_BASE_IDX                                                          1
7194 #define mmSQC_CACHES                                                                                   0x2348
7195 #define mmSQC_CACHES_BASE_IDX                                                                          1
7196 #define mmTA_CS_BC_BASE_ADDR                                                                           0x2380
7197 #define mmTA_CS_BC_BASE_ADDR_BASE_IDX                                                                  1
7198 #define mmTA_CS_BC_BASE_ADDR_HI                                                                        0x2381
7199 #define mmTA_CS_BC_BASE_ADDR_HI_BASE_IDX                                                               1
7200 #define mmDB_OCCLUSION_COUNT0_LOW                                                                      0x23c0
7201 #define mmDB_OCCLUSION_COUNT0_LOW_BASE_IDX                                                             1
7202 #define mmDB_OCCLUSION_COUNT0_HI                                                                       0x23c1
7203 #define mmDB_OCCLUSION_COUNT0_HI_BASE_IDX                                                              1
7204 #define mmDB_OCCLUSION_COUNT1_LOW                                                                      0x23c2
7205 #define mmDB_OCCLUSION_COUNT1_LOW_BASE_IDX                                                             1
7206 #define mmDB_OCCLUSION_COUNT1_HI                                                                       0x23c3
7207 #define mmDB_OCCLUSION_COUNT1_HI_BASE_IDX                                                              1
7208 #define mmDB_OCCLUSION_COUNT2_LOW                                                                      0x23c4
7209 #define mmDB_OCCLUSION_COUNT2_LOW_BASE_IDX                                                             1
7210 #define mmDB_OCCLUSION_COUNT2_HI                                                                       0x23c5
7211 #define mmDB_OCCLUSION_COUNT2_HI_BASE_IDX                                                              1
7212 #define mmDB_OCCLUSION_COUNT3_LOW                                                                      0x23c6
7213 #define mmDB_OCCLUSION_COUNT3_LOW_BASE_IDX                                                             1
7214 #define mmDB_OCCLUSION_COUNT3_HI                                                                       0x23c7
7215 #define mmDB_OCCLUSION_COUNT3_HI_BASE_IDX                                                              1
7216 #define mmDB_ZPASS_COUNT_LOW                                                                           0x23fe
7217 #define mmDB_ZPASS_COUNT_LOW_BASE_IDX                                                                  1
7218 #define mmDB_ZPASS_COUNT_HI                                                                            0x23ff
7219 #define mmDB_ZPASS_COUNT_HI_BASE_IDX                                                                   1
7220 #define mmGDS_RD_ADDR                                                                                  0x2400
7221 #define mmGDS_RD_ADDR_BASE_IDX                                                                         1
7222 #define mmGDS_RD_DATA                                                                                  0x2401
7223 #define mmGDS_RD_DATA_BASE_IDX                                                                         1
7224 #define mmGDS_RD_BURST_ADDR                                                                            0x2402
7225 #define mmGDS_RD_BURST_ADDR_BASE_IDX                                                                   1
7226 #define mmGDS_RD_BURST_COUNT                                                                           0x2403
7227 #define mmGDS_RD_BURST_COUNT_BASE_IDX                                                                  1
7228 #define mmGDS_RD_BURST_DATA                                                                            0x2404
7229 #define mmGDS_RD_BURST_DATA_BASE_IDX                                                                   1
7230 #define mmGDS_WR_ADDR                                                                                  0x2405
7231 #define mmGDS_WR_ADDR_BASE_IDX                                                                         1
7232 #define mmGDS_WR_DATA                                                                                  0x2406
7233 #define mmGDS_WR_DATA_BASE_IDX                                                                         1
7234 #define mmGDS_WR_BURST_ADDR                                                                            0x2407
7235 #define mmGDS_WR_BURST_ADDR_BASE_IDX                                                                   1
7236 #define mmGDS_WR_BURST_DATA                                                                            0x2408
7237 #define mmGDS_WR_BURST_DATA_BASE_IDX                                                                   1
7238 #define mmGDS_WRITE_COMPLETE                                                                           0x2409
7239 #define mmGDS_WRITE_COMPLETE_BASE_IDX                                                                  1
7240 #define mmGDS_ATOM_CNTL                                                                                0x240a
7241 #define mmGDS_ATOM_CNTL_BASE_IDX                                                                       1
7242 #define mmGDS_ATOM_COMPLETE                                                                            0x240b
7243 #define mmGDS_ATOM_COMPLETE_BASE_IDX                                                                   1
7244 #define mmGDS_ATOM_BASE                                                                                0x240c
7245 #define mmGDS_ATOM_BASE_BASE_IDX                                                                       1
7246 #define mmGDS_ATOM_SIZE                                                                                0x240d
7247 #define mmGDS_ATOM_SIZE_BASE_IDX                                                                       1
7248 #define mmGDS_ATOM_OFFSET0                                                                             0x240e
7249 #define mmGDS_ATOM_OFFSET0_BASE_IDX                                                                    1
7250 #define mmGDS_ATOM_OFFSET1                                                                             0x240f
7251 #define mmGDS_ATOM_OFFSET1_BASE_IDX                                                                    1
7252 #define mmGDS_ATOM_DST                                                                                 0x2410
7253 #define mmGDS_ATOM_DST_BASE_IDX                                                                        1
7254 #define mmGDS_ATOM_OP                                                                                  0x2411
7255 #define mmGDS_ATOM_OP_BASE_IDX                                                                         1
7256 #define mmGDS_ATOM_SRC0                                                                                0x2412
7257 #define mmGDS_ATOM_SRC0_BASE_IDX                                                                       1
7258 #define mmGDS_ATOM_SRC0_U                                                                              0x2413
7259 #define mmGDS_ATOM_SRC0_U_BASE_IDX                                                                     1
7260 #define mmGDS_ATOM_SRC1                                                                                0x2414
7261 #define mmGDS_ATOM_SRC1_BASE_IDX                                                                       1
7262 #define mmGDS_ATOM_SRC1_U                                                                              0x2415
7263 #define mmGDS_ATOM_SRC1_U_BASE_IDX                                                                     1
7264 #define mmGDS_ATOM_READ0                                                                               0x2416
7265 #define mmGDS_ATOM_READ0_BASE_IDX                                                                      1
7266 #define mmGDS_ATOM_READ0_U                                                                             0x2417
7267 #define mmGDS_ATOM_READ0_U_BASE_IDX                                                                    1
7268 #define mmGDS_ATOM_READ1                                                                               0x2418
7269 #define mmGDS_ATOM_READ1_BASE_IDX                                                                      1
7270 #define mmGDS_ATOM_READ1_U                                                                             0x2419
7271 #define mmGDS_ATOM_READ1_U_BASE_IDX                                                                    1
7272 #define mmGDS_GWS_RESOURCE_CNTL                                                                        0x241a
7273 #define mmGDS_GWS_RESOURCE_CNTL_BASE_IDX                                                               1
7274 #define mmGDS_GWS_RESOURCE                                                                             0x241b
7275 #define mmGDS_GWS_RESOURCE_BASE_IDX                                                                    1
7276 #define mmGDS_GWS_RESOURCE_CNT                                                                         0x241c
7277 #define mmGDS_GWS_RESOURCE_CNT_BASE_IDX                                                                1
7278 #define mmGDS_OA_CNTL                                                                                  0x241d
7279 #define mmGDS_OA_CNTL_BASE_IDX                                                                         1
7280 #define mmGDS_OA_COUNTER                                                                               0x241e
7281 #define mmGDS_OA_COUNTER_BASE_IDX                                                                      1
7282 #define mmGDS_OA_ADDRESS                                                                               0x241f
7283 #define mmGDS_OA_ADDRESS_BASE_IDX                                                                      1
7284 #define mmGDS_OA_INCDEC                                                                                0x2420
7285 #define mmGDS_OA_INCDEC_BASE_IDX                                                                       1
7286 #define mmGDS_OA_RING_SIZE                                                                             0x2421
7287 #define mmGDS_OA_RING_SIZE_BASE_IDX                                                                    1
7288 #define mmSPI_CONFIG_CNTL_REMAP                                                                        0x2440
7289 #define mmSPI_CONFIG_CNTL_REMAP_BASE_IDX                                                               1
7290 #define mmSPI_CONFIG_CNTL_1_REMAP                                                                      0x2441
7291 #define mmSPI_CONFIG_CNTL_1_REMAP_BASE_IDX                                                             1
7292 #define mmSPI_CONFIG_CNTL_2_REMAP                                                                      0x2442
7293 #define mmSPI_CONFIG_CNTL_2_REMAP_BASE_IDX                                                             1
7294 #define mmSPI_WAVE_LIMIT_CNTL_REMAP                                                                    0x2443
7295 #define mmSPI_WAVE_LIMIT_CNTL_REMAP_BASE_IDX                                                           1
7296 
7297 
7298 // addressBlock: gc_cprs64dec
7299 // base address: 0x32000
7300 #define mmCP_MES_PRGRM_CNTR_START                                                                      0x2800
7301 #define mmCP_MES_PRGRM_CNTR_START_BASE_IDX                                                             1
7302 #define mmCP_MES_INTR_ROUTINE_START                                                                    0x2801
7303 #define mmCP_MES_INTR_ROUTINE_START_BASE_IDX                                                           1
7304 #define mmCP_MES_MTVEC_LO                                                                              0x2801
7305 #define mmCP_MES_MTVEC_LO_BASE_IDX                                                                     1
7306 #define mmCP_MES_MTVEC_HI                                                                              0x2802
7307 #define mmCP_MES_MTVEC_HI_BASE_IDX                                                                     1
7308 #define mmCP_MES_CNTL                                                                                  0x2807
7309 #define mmCP_MES_CNTL_BASE_IDX                                                                         1
7310 #define mmCP_MES_PIPE_PRIORITY_CNTS                                                                    0x2808
7311 #define mmCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX                                                           1
7312 #define mmCP_MES_PIPE0_PRIORITY                                                                        0x2809
7313 #define mmCP_MES_PIPE0_PRIORITY_BASE_IDX                                                               1
7314 #define mmCP_MES_PIPE1_PRIORITY                                                                        0x280a
7315 #define mmCP_MES_PIPE1_PRIORITY_BASE_IDX                                                               1
7316 #define mmCP_MES_PIPE2_PRIORITY                                                                        0x280b
7317 #define mmCP_MES_PIPE2_PRIORITY_BASE_IDX                                                               1
7318 #define mmCP_MES_PIPE3_PRIORITY                                                                        0x280c
7319 #define mmCP_MES_PIPE3_PRIORITY_BASE_IDX                                                               1
7320 #define mmCP_MES_HEADER_DUMP                                                                           0x280d
7321 #define mmCP_MES_HEADER_DUMP_BASE_IDX                                                                  1
7322 #define mmCP_MES_MIE_LO                                                                                0x280e
7323 #define mmCP_MES_MIE_LO_BASE_IDX                                                                       1
7324 #define mmCP_MES_MIE_HI                                                                                0x280f
7325 #define mmCP_MES_MIE_HI_BASE_IDX                                                                       1
7326 #define mmCP_MES_INTERRUPT                                                                             0x2810
7327 #define mmCP_MES_INTERRUPT_BASE_IDX                                                                    1
7328 #define mmCP_MES_SCRATCH_INDEX                                                                         0x2811
7329 #define mmCP_MES_SCRATCH_INDEX_BASE_IDX                                                                1
7330 #define mmCP_MES_SCRATCH_DATA                                                                          0x2812
7331 #define mmCP_MES_SCRATCH_DATA_BASE_IDX                                                                 1
7332 #define mmCP_MES_INSTR_PNTR                                                                            0x2813
7333 #define mmCP_MES_INSTR_PNTR_BASE_IDX                                                                   1
7334 #define mmCP_MES_MSCRATCH_HI                                                                           0x2814
7335 #define mmCP_MES_MSCRATCH_HI_BASE_IDX                                                                  1
7336 #define mmCP_MES_MSCRATCH_LO                                                                           0x2815
7337 #define mmCP_MES_MSCRATCH_LO_BASE_IDX                                                                  1
7338 #define mmCP_MES_MSTATUS_LO                                                                            0x2816
7339 #define mmCP_MES_MSTATUS_LO_BASE_IDX                                                                   1
7340 #define mmCP_MES_MSTATUS_HI                                                                            0x2817
7341 #define mmCP_MES_MSTATUS_HI_BASE_IDX                                                                   1
7342 #define mmCP_MES_MEPC_LO                                                                               0x2818
7343 #define mmCP_MES_MEPC_LO_BASE_IDX                                                                      1
7344 #define mmCP_MES_MEPC_HI                                                                               0x2819
7345 #define mmCP_MES_MEPC_HI_BASE_IDX                                                                      1
7346 #define mmCP_MES_MCAUSE_LO                                                                             0x281a
7347 #define mmCP_MES_MCAUSE_LO_BASE_IDX                                                                    1
7348 #define mmCP_MES_MCAUSE_HI                                                                             0x281b
7349 #define mmCP_MES_MCAUSE_HI_BASE_IDX                                                                    1
7350 #define mmCP_MES_MBADADDR_LO                                                                           0x281c
7351 #define mmCP_MES_MBADADDR_LO_BASE_IDX                                                                  1
7352 #define mmCP_MES_MBADADDR_HI                                                                           0x281d
7353 #define mmCP_MES_MBADADDR_HI_BASE_IDX                                                                  1
7354 #define mmCP_MES_MIP_LO                                                                                0x281e
7355 #define mmCP_MES_MIP_LO_BASE_IDX                                                                       1
7356 #define mmCP_MES_MIP_HI                                                                                0x281f
7357 #define mmCP_MES_MIP_HI_BASE_IDX                                                                       1
7358 #define mmCP_MES_IC_OP_CNTL                                                                            0x2820
7359 #define mmCP_MES_IC_OP_CNTL_BASE_IDX                                                                   1
7360 #define mmCP_MES_MCYCLE_LO                                                                             0x2826
7361 #define mmCP_MES_MCYCLE_LO_BASE_IDX                                                                    1
7362 #define mmCP_MES_MCYCLE_HI                                                                             0x2827
7363 #define mmCP_MES_MCYCLE_HI_BASE_IDX                                                                    1
7364 #define mmCP_MES_MTIME_LO                                                                              0x2828
7365 #define mmCP_MES_MTIME_LO_BASE_IDX                                                                     1
7366 #define mmCP_MES_MTIME_HI                                                                              0x2829
7367 #define mmCP_MES_MTIME_HI_BASE_IDX                                                                     1
7368 #define mmCP_MES_MINSTRET_LO                                                                           0x282a
7369 #define mmCP_MES_MINSTRET_LO_BASE_IDX                                                                  1
7370 #define mmCP_MES_MINSTRET_HI                                                                           0x282b
7371 #define mmCP_MES_MINSTRET_HI_BASE_IDX                                                                  1
7372 #define mmCP_MES_MISA_LO                                                                               0x282c
7373 #define mmCP_MES_MISA_LO_BASE_IDX                                                                      1
7374 #define mmCP_MES_MISA_HI                                                                               0x282d
7375 #define mmCP_MES_MISA_HI_BASE_IDX                                                                      1
7376 #define mmCP_MES_MVENDORID_LO                                                                          0x282e
7377 #define mmCP_MES_MVENDORID_LO_BASE_IDX                                                                 1
7378 #define mmCP_MES_MVENDORID_HI                                                                          0x282f
7379 #define mmCP_MES_MVENDORID_HI_BASE_IDX                                                                 1
7380 #define mmCP_MES_MARCHID_LO                                                                            0x2830
7381 #define mmCP_MES_MARCHID_LO_BASE_IDX                                                                   1
7382 #define mmCP_MES_MARCHID_HI                                                                            0x2831
7383 #define mmCP_MES_MARCHID_HI_BASE_IDX                                                                   1
7384 #define mmCP_MES_MIMPID_LO                                                                             0x2832
7385 #define mmCP_MES_MIMPID_LO_BASE_IDX                                                                    1
7386 #define mmCP_MES_MIMPID_HI                                                                             0x2833
7387 #define mmCP_MES_MIMPID_HI_BASE_IDX                                                                    1
7388 #define mmCP_MES_MHARTID_LO                                                                            0x2834
7389 #define mmCP_MES_MHARTID_LO_BASE_IDX                                                                   1
7390 #define mmCP_MES_MHARTID_HI                                                                            0x2835
7391 #define mmCP_MES_MHARTID_HI_BASE_IDX                                                                   1
7392 #define mmCP_MES_DC_BASE_CNTL                                                                          0x2836
7393 #define mmCP_MES_DC_BASE_CNTL_BASE_IDX                                                                 1
7394 #define mmCP_MES_DC_OP_CNTL                                                                            0x2837
7395 #define mmCP_MES_DC_OP_CNTL_BASE_IDX                                                                   1
7396 #define mmCP_MES_MTIMECMP_LO                                                                           0x2838
7397 #define mmCP_MES_MTIMECMP_LO_BASE_IDX                                                                  1
7398 #define mmCP_MES_MTIMECMP_HI                                                                           0x2839
7399 #define mmCP_MES_MTIMECMP_HI_BASE_IDX                                                                  1
7400 #define mmCP_MES_PROCESS_QUANTUM_PIPE0                                                                 0x283a
7401 #define mmCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX                                                        1
7402 #define mmCP_MES_PROCESS_QUANTUM_PIPE1                                                                 0x283b
7403 #define mmCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX                                                        1
7404 #define mmCP_MES_DOORBELL_CONTROL1                                                                     0x283c
7405 #define mmCP_MES_DOORBELL_CONTROL1_BASE_IDX                                                            1
7406 #define mmCP_MES_DOORBELL_CONTROL2                                                                     0x283d
7407 #define mmCP_MES_DOORBELL_CONTROL2_BASE_IDX                                                            1
7408 #define mmCP_MES_DOORBELL_CONTROL3                                                                     0x283e
7409 #define mmCP_MES_DOORBELL_CONTROL3_BASE_IDX                                                            1
7410 #define mmCP_MES_DOORBELL_CONTROL4                                                                     0x283f
7411 #define mmCP_MES_DOORBELL_CONTROL4_BASE_IDX                                                            1
7412 #define mmCP_MES_DOORBELL_CONTROL5                                                                     0x2840
7413 #define mmCP_MES_DOORBELL_CONTROL5_BASE_IDX                                                            1
7414 #define mmCP_MES_DOORBELL_CONTROL6                                                                     0x2841
7415 #define mmCP_MES_DOORBELL_CONTROL6_BASE_IDX                                                            1
7416 #define mmCP_MES_GP0_LO                                                                                0x2843
7417 #define mmCP_MES_GP0_LO_BASE_IDX                                                                       1
7418 #define mmCP_MES_GP0_HI                                                                                0x2844
7419 #define mmCP_MES_GP0_HI_BASE_IDX                                                                       1
7420 #define mmCP_MES_GP1_LO                                                                                0x2845
7421 #define mmCP_MES_GP1_LO_BASE_IDX                                                                       1
7422 #define mmCP_MES_GP1_HI                                                                                0x2846
7423 #define mmCP_MES_GP1_HI_BASE_IDX                                                                       1
7424 #define mmCP_MES_GP2_LO                                                                                0x2847
7425 #define mmCP_MES_GP2_LO_BASE_IDX                                                                       1
7426 #define mmCP_MES_GP2_HI                                                                                0x2848
7427 #define mmCP_MES_GP2_HI_BASE_IDX                                                                       1
7428 #define mmCP_MES_GP3_LO                                                                                0x2849
7429 #define mmCP_MES_GP3_LO_BASE_IDX                                                                       1
7430 #define mmCP_MES_GP3_HI                                                                                0x284a
7431 #define mmCP_MES_GP3_HI_BASE_IDX                                                                       1
7432 #define mmCP_MES_GP4_LO                                                                                0x284b
7433 #define mmCP_MES_GP4_LO_BASE_IDX                                                                       1
7434 #define mmCP_MES_GP4_HI                                                                                0x284c
7435 #define mmCP_MES_GP4_HI_BASE_IDX                                                                       1
7436 #define mmCP_MES_GP5_LO                                                                                0x284d
7437 #define mmCP_MES_GP5_LO_BASE_IDX                                                                       1
7438 #define mmCP_MES_GP5_HI                                                                                0x284e
7439 #define mmCP_MES_GP5_HI_BASE_IDX                                                                       1
7440 #define mmCP_MES_GP6_LO                                                                                0x284f
7441 #define mmCP_MES_GP6_LO_BASE_IDX                                                                       1
7442 #define mmCP_MES_GP6_HI                                                                                0x2850
7443 #define mmCP_MES_GP6_HI_BASE_IDX                                                                       1
7444 #define mmCP_MES_GP7_LO                                                                                0x2851
7445 #define mmCP_MES_GP7_LO_BASE_IDX                                                                       1
7446 #define mmCP_MES_GP7_HI                                                                                0x2852
7447 #define mmCP_MES_GP7_HI_BASE_IDX                                                                       1
7448 #define mmCP_MES_GP8_LO                                                                                0x2853
7449 #define mmCP_MES_GP8_LO_BASE_IDX                                                                       1
7450 #define mmCP_MES_GP8_HI                                                                                0x2854
7451 #define mmCP_MES_GP8_HI_BASE_IDX                                                                       1
7452 #define mmCP_MES_GP9_LO                                                                                0x2855
7453 #define mmCP_MES_GP9_LO_BASE_IDX                                                                       1
7454 #define mmCP_MES_GP9_HI                                                                                0x2856
7455 #define mmCP_MES_GP9_HI_BASE_IDX                                                                       1
7456 #define mmCP_MES_DM_INDEX_ADDR                                                                         0x2880
7457 #define mmCP_MES_DM_INDEX_ADDR_BASE_IDX                                                                1
7458 #define mmCP_MES_DM_INDEX_DATA                                                                         0x2881
7459 #define mmCP_MES_DM_INDEX_DATA_BASE_IDX                                                                1
7460 #define mmCP_MES_PERFCOUNT_CNTL                                                                        0x2899
7461 #define mmCP_MES_PERFCOUNT_CNTL_BASE_IDX                                                               1
7462 #define mmCP_MES_PENDING_INTERRUPT                                                                     0x289a
7463 #define mmCP_MES_PENDING_INTERRUPT_BASE_IDX                                                            1
7464 
7465 
7466 // addressBlock: gc_gusdec
7467 // base address: 0x33000
7468 #define mmGUS_IO_RD_COMBINE_FLUSH                                                                      0x2c00
7469 #define mmGUS_IO_RD_COMBINE_FLUSH_BASE_IDX                                                             1
7470 #define mmGUS_IO_WR_COMBINE_FLUSH                                                                      0x2c01
7471 #define mmGUS_IO_WR_COMBINE_FLUSH_BASE_IDX                                                             1
7472 #define mmGUS_IO_RD_PRI_AGE_RATE                                                                       0x2c02
7473 #define mmGUS_IO_RD_PRI_AGE_RATE_BASE_IDX                                                              1
7474 #define mmGUS_IO_WR_PRI_AGE_RATE                                                                       0x2c03
7475 #define mmGUS_IO_WR_PRI_AGE_RATE_BASE_IDX                                                              1
7476 #define mmGUS_IO_RD_PRI_AGE_COEFF                                                                      0x2c04
7477 #define mmGUS_IO_RD_PRI_AGE_COEFF_BASE_IDX                                                             1
7478 #define mmGUS_IO_WR_PRI_AGE_COEFF                                                                      0x2c05
7479 #define mmGUS_IO_WR_PRI_AGE_COEFF_BASE_IDX                                                             1
7480 #define mmGUS_IO_RD_PRI_QUEUING                                                                        0x2c06
7481 #define mmGUS_IO_RD_PRI_QUEUING_BASE_IDX                                                               1
7482 #define mmGUS_IO_WR_PRI_QUEUING                                                                        0x2c07
7483 #define mmGUS_IO_WR_PRI_QUEUING_BASE_IDX                                                               1
7484 #define mmGUS_IO_RD_PRI_FIXED                                                                          0x2c08
7485 #define mmGUS_IO_RD_PRI_FIXED_BASE_IDX                                                                 1
7486 #define mmGUS_IO_WR_PRI_FIXED                                                                          0x2c09
7487 #define mmGUS_IO_WR_PRI_FIXED_BASE_IDX                                                                 1
7488 #define mmGUS_IO_RD_PRI_URGENCY_COEFF                                                                  0x2c0a
7489 #define mmGUS_IO_RD_PRI_URGENCY_COEFF_BASE_IDX                                                         1
7490 #define mmGUS_IO_WR_PRI_URGENCY_COEFF                                                                  0x2c0b
7491 #define mmGUS_IO_WR_PRI_URGENCY_COEFF_BASE_IDX                                                         1
7492 #define mmGUS_IO_RD_PRI_URGENCY_MODE                                                                   0x2c0c
7493 #define mmGUS_IO_RD_PRI_URGENCY_MODE_BASE_IDX                                                          1
7494 #define mmGUS_IO_WR_PRI_URGENCY_MODE                                                                   0x2c0d
7495 #define mmGUS_IO_WR_PRI_URGENCY_MODE_BASE_IDX                                                          1
7496 #define mmGUS_IO_RD_PRI_QUANT_PRI1                                                                     0x2c0e
7497 #define mmGUS_IO_RD_PRI_QUANT_PRI1_BASE_IDX                                                            1
7498 #define mmGUS_IO_RD_PRI_QUANT_PRI2                                                                     0x2c0f
7499 #define mmGUS_IO_RD_PRI_QUANT_PRI2_BASE_IDX                                                            1
7500 #define mmGUS_IO_RD_PRI_QUANT_PRI3                                                                     0x2c10
7501 #define mmGUS_IO_RD_PRI_QUANT_PRI3_BASE_IDX                                                            1
7502 #define mmGUS_IO_RD_PRI_QUANT_PRI4                                                                     0x2c11
7503 #define mmGUS_IO_RD_PRI_QUANT_PRI4_BASE_IDX                                                            1
7504 #define mmGUS_IO_WR_PRI_QUANT_PRI1                                                                     0x2c12
7505 #define mmGUS_IO_WR_PRI_QUANT_PRI1_BASE_IDX                                                            1
7506 #define mmGUS_IO_WR_PRI_QUANT_PRI2                                                                     0x2c13
7507 #define mmGUS_IO_WR_PRI_QUANT_PRI2_BASE_IDX                                                            1
7508 #define mmGUS_IO_WR_PRI_QUANT_PRI3                                                                     0x2c14
7509 #define mmGUS_IO_WR_PRI_QUANT_PRI3_BASE_IDX                                                            1
7510 #define mmGUS_IO_WR_PRI_QUANT_PRI4                                                                     0x2c15
7511 #define mmGUS_IO_WR_PRI_QUANT_PRI4_BASE_IDX                                                            1
7512 #define mmGUS_IO_RD_PRI_QUANT1_PRI1                                                                    0x2c16
7513 #define mmGUS_IO_RD_PRI_QUANT1_PRI1_BASE_IDX                                                           1
7514 #define mmGUS_IO_RD_PRI_QUANT1_PRI2                                                                    0x2c17
7515 #define mmGUS_IO_RD_PRI_QUANT1_PRI2_BASE_IDX                                                           1
7516 #define mmGUS_IO_RD_PRI_QUANT1_PRI3                                                                    0x2c18
7517 #define mmGUS_IO_RD_PRI_QUANT1_PRI3_BASE_IDX                                                           1
7518 #define mmGUS_IO_RD_PRI_QUANT1_PRI4                                                                    0x2c19
7519 #define mmGUS_IO_RD_PRI_QUANT1_PRI4_BASE_IDX                                                           1
7520 #define mmGUS_IO_WR_PRI_QUANT1_PRI1                                                                    0x2c1a
7521 #define mmGUS_IO_WR_PRI_QUANT1_PRI1_BASE_IDX                                                           1
7522 #define mmGUS_IO_WR_PRI_QUANT1_PRI2                                                                    0x2c1b
7523 #define mmGUS_IO_WR_PRI_QUANT1_PRI2_BASE_IDX                                                           1
7524 #define mmGUS_IO_WR_PRI_QUANT1_PRI3                                                                    0x2c1c
7525 #define mmGUS_IO_WR_PRI_QUANT1_PRI3_BASE_IDX                                                           1
7526 #define mmGUS_IO_WR_PRI_QUANT1_PRI4                                                                    0x2c1d
7527 #define mmGUS_IO_WR_PRI_QUANT1_PRI4_BASE_IDX                                                           1
7528 #define mmGUS_DRAM_COMBINE_FLUSH                                                                       0x2c1e
7529 #define mmGUS_DRAM_COMBINE_FLUSH_BASE_IDX                                                              1
7530 #define mmGUS_DRAM_COMBINE_RD_WR_EN                                                                    0x2c1f
7531 #define mmGUS_DRAM_COMBINE_RD_WR_EN_BASE_IDX                                                           1
7532 #define mmGUS_DRAM_PRI_AGE_RATE                                                                        0x2c20
7533 #define mmGUS_DRAM_PRI_AGE_RATE_BASE_IDX                                                               1
7534 #define mmGUS_DRAM_PRI_AGE_COEFF                                                                       0x2c21
7535 #define mmGUS_DRAM_PRI_AGE_COEFF_BASE_IDX                                                              1
7536 #define mmGUS_DRAM_PRI_QUEUING                                                                         0x2c22
7537 #define mmGUS_DRAM_PRI_QUEUING_BASE_IDX                                                                1
7538 #define mmGUS_DRAM_PRI_FIXED                                                                           0x2c23
7539 #define mmGUS_DRAM_PRI_FIXED_BASE_IDX                                                                  1
7540 #define mmGUS_DRAM_PRI_URGENCY_COEFF                                                                   0x2c24
7541 #define mmGUS_DRAM_PRI_URGENCY_COEFF_BASE_IDX                                                          1
7542 #define mmGUS_DRAM_PRI_URGENCY_MODE                                                                    0x2c25
7543 #define mmGUS_DRAM_PRI_URGENCY_MODE_BASE_IDX                                                           1
7544 #define mmGUS_DRAM_PRI_QUANT_PRI1                                                                      0x2c26
7545 #define mmGUS_DRAM_PRI_QUANT_PRI1_BASE_IDX                                                             1
7546 #define mmGUS_DRAM_PRI_QUANT_PRI2                                                                      0x2c27
7547 #define mmGUS_DRAM_PRI_QUANT_PRI2_BASE_IDX                                                             1
7548 #define mmGUS_DRAM_PRI_QUANT_PRI3                                                                      0x2c28
7549 #define mmGUS_DRAM_PRI_QUANT_PRI3_BASE_IDX                                                             1
7550 #define mmGUS_DRAM_PRI_QUANT_PRI4                                                                      0x2c29
7551 #define mmGUS_DRAM_PRI_QUANT_PRI4_BASE_IDX                                                             1
7552 #define mmGUS_DRAM_PRI_QUANT_PRI5                                                                      0x2c2a
7553 #define mmGUS_DRAM_PRI_QUANT_PRI5_BASE_IDX                                                             1
7554 #define mmGUS_DRAM_PRI_QUANT1_PRI1                                                                     0x2c2b
7555 #define mmGUS_DRAM_PRI_QUANT1_PRI1_BASE_IDX                                                            1
7556 #define mmGUS_DRAM_PRI_QUANT1_PRI2                                                                     0x2c2c
7557 #define mmGUS_DRAM_PRI_QUANT1_PRI2_BASE_IDX                                                            1
7558 #define mmGUS_DRAM_PRI_QUANT1_PRI3                                                                     0x2c2d
7559 #define mmGUS_DRAM_PRI_QUANT1_PRI3_BASE_IDX                                                            1
7560 #define mmGUS_DRAM_PRI_QUANT1_PRI4                                                                     0x2c2e
7561 #define mmGUS_DRAM_PRI_QUANT1_PRI4_BASE_IDX                                                            1
7562 #define mmGUS_DRAM_PRI_QUANT1_PRI5                                                                     0x2c2f
7563 #define mmGUS_DRAM_PRI_QUANT1_PRI5_BASE_IDX                                                            1
7564 #define mmGUS_IO_GROUP_BURST                                                                           0x2c30
7565 #define mmGUS_IO_GROUP_BURST_BASE_IDX                                                                  1
7566 #define mmGUS_DRAM_GROUP_BURST                                                                         0x2c31
7567 #define mmGUS_DRAM_GROUP_BURST_BASE_IDX                                                                1
7568 #define mmGUS_SDP_ARB_FINAL                                                                            0x2c32
7569 #define mmGUS_SDP_ARB_FINAL_BASE_IDX                                                                   1
7570 #define mmGUS_SDP_QOS_VC_PRIORITY                                                                      0x2c33
7571 #define mmGUS_SDP_QOS_VC_PRIORITY_BASE_IDX                                                             1
7572 #define mmGUS_SDP_CREDITS                                                                              0x2c34
7573 #define mmGUS_SDP_CREDITS_BASE_IDX                                                                     1
7574 #define mmGUS_SDP_TAG_RESERVE0                                                                         0x2c35
7575 #define mmGUS_SDP_TAG_RESERVE0_BASE_IDX                                                                1
7576 #define mmGUS_SDP_TAG_RESERVE1                                                                         0x2c36
7577 #define mmGUS_SDP_TAG_RESERVE1_BASE_IDX                                                                1
7578 #define mmGUS_SDP_VCC_RESERVE0                                                                         0x2c37
7579 #define mmGUS_SDP_VCC_RESERVE0_BASE_IDX                                                                1
7580 #define mmGUS_SDP_VCC_RESERVE1                                                                         0x2c38
7581 #define mmGUS_SDP_VCC_RESERVE1_BASE_IDX                                                                1
7582 #define mmGUS_SDP_VCD_RESERVE0                                                                         0x2c39
7583 #define mmGUS_SDP_VCD_RESERVE0_BASE_IDX                                                                1
7584 #define mmGUS_SDP_VCD_RESERVE1                                                                         0x2c3a
7585 #define mmGUS_SDP_VCD_RESERVE1_BASE_IDX                                                                1
7586 #define mmGUS_SDP_REQ_CNTL                                                                             0x2c3b
7587 #define mmGUS_SDP_REQ_CNTL_BASE_IDX                                                                    1
7588 #define mmGUS_MISC                                                                                     0x2c3c
7589 #define mmGUS_MISC_BASE_IDX                                                                            1
7590 #define mmGUS_LATENCY_SAMPLING                                                                         0x2c3d
7591 #define mmGUS_LATENCY_SAMPLING_BASE_IDX                                                                1
7592 #define mmGUS_ERR_STATUS                                                                               0x2c3e
7593 #define mmGUS_ERR_STATUS_BASE_IDX                                                                      1
7594 #define mmGUS_MISC2                                                                                    0x2c3f
7595 #define mmGUS_MISC2_BASE_IDX                                                                           1
7596 #define mmGUS_SDP_ENABLE                                                                               0x2c45
7597 #define mmGUS_SDP_ENABLE_BASE_IDX                                                                      1
7598 #define mmGUS_L1_CH0_CMD_IN                                                                            0x2c46
7599 #define mmGUS_L1_CH0_CMD_IN_BASE_IDX                                                                   1
7600 #define mmGUS_L1_CH0_CMD_OUT                                                                           0x2c47
7601 #define mmGUS_L1_CH0_CMD_OUT_BASE_IDX                                                                  1
7602 #define mmGUS_L1_CH0_DATA_IN                                                                           0x2c48
7603 #define mmGUS_L1_CH0_DATA_IN_BASE_IDX                                                                  1
7604 #define mmGUS_L1_CH0_DATA_OUT                                                                          0x2c49
7605 #define mmGUS_L1_CH0_DATA_OUT_BASE_IDX                                                                 1
7606 #define mmGUS_L1_CH0_DATA_U_IN                                                                         0x2c4a
7607 #define mmGUS_L1_CH0_DATA_U_IN_BASE_IDX                                                                1
7608 #define mmGUS_L1_CH0_DATA_U_OUT                                                                        0x2c4b
7609 #define mmGUS_L1_CH0_DATA_U_OUT_BASE_IDX                                                               1
7610 #define mmGUS_L1_CH1_CMD_IN                                                                            0x2c4c
7611 #define mmGUS_L1_CH1_CMD_IN_BASE_IDX                                                                   1
7612 #define mmGUS_L1_CH1_CMD_OUT                                                                           0x2c4d
7613 #define mmGUS_L1_CH1_CMD_OUT_BASE_IDX                                                                  1
7614 #define mmGUS_L1_CH1_DATA_IN                                                                           0x2c4e
7615 #define mmGUS_L1_CH1_DATA_IN_BASE_IDX                                                                  1
7616 #define mmGUS_L1_CH1_DATA_OUT                                                                          0x2c4f
7617 #define mmGUS_L1_CH1_DATA_OUT_BASE_IDX                                                                 1
7618 #define mmGUS_L1_CH1_DATA_U_IN                                                                         0x2c50
7619 #define mmGUS_L1_CH1_DATA_U_IN_BASE_IDX                                                                1
7620 #define mmGUS_L1_CH1_DATA_U_OUT                                                                        0x2c51
7621 #define mmGUS_L1_CH1_DATA_U_OUT_BASE_IDX                                                               1
7622 #define mmGUS_L1_SA0_CMD_IN                                                                            0x2c52
7623 #define mmGUS_L1_SA0_CMD_IN_BASE_IDX                                                                   1
7624 #define mmGUS_L1_SA0_CMD_OUT                                                                           0x2c53
7625 #define mmGUS_L1_SA0_CMD_OUT_BASE_IDX                                                                  1
7626 #define mmGUS_L1_SA0_DATA_IN                                                                           0x2c54
7627 #define mmGUS_L1_SA0_DATA_IN_BASE_IDX                                                                  1
7628 #define mmGUS_L1_SA0_DATA_OUT                                                                          0x2c55
7629 #define mmGUS_L1_SA0_DATA_OUT_BASE_IDX                                                                 1
7630 #define mmGUS_L1_SA0_DATA_U_IN                                                                         0x2c56
7631 #define mmGUS_L1_SA0_DATA_U_IN_BASE_IDX                                                                1
7632 #define mmGUS_L1_SA0_DATA_U_OUT                                                                        0x2c57
7633 #define mmGUS_L1_SA0_DATA_U_OUT_BASE_IDX                                                               1
7634 #define mmGUS_L1_SA1_CMD_IN                                                                            0x2c58
7635 #define mmGUS_L1_SA1_CMD_IN_BASE_IDX                                                                   1
7636 #define mmGUS_L1_SA1_CMD_OUT                                                                           0x2c59
7637 #define mmGUS_L1_SA1_CMD_OUT_BASE_IDX                                                                  1
7638 #define mmGUS_L1_SA1_DATA_IN                                                                           0x2c5a
7639 #define mmGUS_L1_SA1_DATA_IN_BASE_IDX                                                                  1
7640 #define mmGUS_L1_SA1_DATA_OUT                                                                          0x2c5b
7641 #define mmGUS_L1_SA1_DATA_OUT_BASE_IDX                                                                 1
7642 #define mmGUS_L1_SA1_DATA_U_IN                                                                         0x2c5c
7643 #define mmGUS_L1_SA1_DATA_U_IN_BASE_IDX                                                                1
7644 #define mmGUS_L1_SA1_DATA_U_OUT                                                                        0x2c5d
7645 #define mmGUS_L1_SA1_DATA_U_OUT_BASE_IDX                                                               1
7646 #define mmGUS_L1_SA2_CMD_IN                                                                            0x2c5e
7647 #define mmGUS_L1_SA2_CMD_IN_BASE_IDX                                                                   1
7648 #define mmGUS_L1_SA2_CMD_OUT                                                                           0x2c5f
7649 #define mmGUS_L1_SA2_CMD_OUT_BASE_IDX                                                                  1
7650 #define mmGUS_L1_SA2_DATA_IN                                                                           0x2c60
7651 #define mmGUS_L1_SA2_DATA_IN_BASE_IDX                                                                  1
7652 #define mmGUS_L1_SA2_DATA_OUT                                                                          0x2c61
7653 #define mmGUS_L1_SA2_DATA_OUT_BASE_IDX                                                                 1
7654 #define mmGUS_L1_SA2_DATA_U_IN                                                                         0x2c62
7655 #define mmGUS_L1_SA2_DATA_U_IN_BASE_IDX                                                                1
7656 #define mmGUS_L1_SA2_DATA_U_OUT                                                                        0x2c63
7657 #define mmGUS_L1_SA2_DATA_U_OUT_BASE_IDX                                                               1
7658 #define mmGUS_L1_SA3_CMD_IN                                                                            0x2c64
7659 #define mmGUS_L1_SA3_CMD_IN_BASE_IDX                                                                   1
7660 #define mmGUS_L1_SA3_CMD_OUT                                                                           0x2c65
7661 #define mmGUS_L1_SA3_CMD_OUT_BASE_IDX                                                                  1
7662 #define mmGUS_L1_SA3_DATA_IN                                                                           0x2c66
7663 #define mmGUS_L1_SA3_DATA_IN_BASE_IDX                                                                  1
7664 #define mmGUS_L1_SA3_DATA_OUT                                                                          0x2c67
7665 #define mmGUS_L1_SA3_DATA_OUT_BASE_IDX                                                                 1
7666 #define mmGUS_L1_SA3_DATA_U_IN                                                                         0x2c68
7667 #define mmGUS_L1_SA3_DATA_U_IN_BASE_IDX                                                                1
7668 #define mmGUS_L1_SA3_DATA_U_OUT                                                                        0x2c69
7669 #define mmGUS_L1_SA3_DATA_U_OUT_BASE_IDX                                                               1
7670 #define mmGUS_MISC3                                                                                    0x2c6a
7671 #define mmGUS_MISC3_BASE_IDX                                                                           1
7672 #define mmGUS_WRRSP_FIFO_CNTL                                                                          0x2c6b
7673 #define mmGUS_WRRSP_FIFO_CNTL_BASE_IDX                                                                 1
7674 
7675 
7676 // addressBlock: gc_gl1dec
7677 // base address: 0x33400
7678 #define mmGL1_DRAM_BURST_MASK                                                                          0x2d02
7679 #define mmGL1_DRAM_BURST_MASK_BASE_IDX                                                                 1
7680 #define mmGL1_ARB_STATUS                                                                               0x2d03
7681 #define mmGL1_ARB_STATUS_BASE_IDX                                                                      1
7682 #define mmGL1_PIPE_STEER                                                                               0x2d10
7683 #define mmGL1_PIPE_STEER_BASE_IDX                                                                      1
7684 #define mmGL1C_STATUS                                                                                  0x2d41
7685 #define mmGL1C_STATUS_BASE_IDX                                                                         1
7686 #define mmGL1C_UTCL0_CNTL2                                                                             0x2d43
7687 #define mmGL1C_UTCL0_CNTL2_BASE_IDX                                                                    1
7688 #define mmGL1C_UTCL0_STATUS                                                                            0x2d44
7689 #define mmGL1C_UTCL0_STATUS_BASE_IDX                                                                   1
7690 #define mmGL1C_UTCL0_RETRY                                                                             0x2d45
7691 #define mmGL1C_UTCL0_RETRY_BASE_IDX                                                                    1
7692 
7693 
7694 // addressBlock: gc_chdec
7695 // base address: 0x33600
7696 #define mmCH_ARB_CTRL                                                                                  0x2d80
7697 #define mmCH_ARB_CTRL_BASE_IDX                                                                         1
7698 #define mmCH_DRAM_BURST_MASK                                                                           0x2d82
7699 #define mmCH_DRAM_BURST_MASK_BASE_IDX                                                                  1
7700 #define mmCH_ARB_STATUS                                                                                0x2d83
7701 #define mmCH_ARB_STATUS_BASE_IDX                                                                       1
7702 #define mmCH_DRAM_BURST_CTRL                                                                           0x2d84
7703 #define mmCH_DRAM_BURST_CTRL_BASE_IDX                                                                  1
7704 #define mmCHA_CHC_CREDITS                                                                              0x2d88
7705 #define mmCHA_CHC_CREDITS_BASE_IDX                                                                     1
7706 #define mmCHA_CLIENT_FREE_DELAY                                                                        0x2d89
7707 #define mmCHA_CLIENT_FREE_DELAY_BASE_IDX                                                               1
7708 #define mmCH_PIPE_STEER                                                                                0x2d90
7709 #define mmCH_PIPE_STEER_BASE_IDX                                                                       1
7710 #define mmCH_VC5_ENABLE                                                                                0x2d94
7711 #define mmCH_VC5_ENABLE_BASE_IDX                                                                       1
7712 #define mmCHC_CTRL                                                                                     0x2dc0
7713 #define mmCHC_CTRL_BASE_IDX                                                                            1
7714 #define mmCHC_STATUS                                                                                   0x2dc1
7715 #define mmCHC_STATUS_BASE_IDX                                                                          1
7716 #define mmCHCG_CTRL                                                                                    0x2dc2
7717 #define mmCHCG_CTRL_BASE_IDX                                                                           1
7718 #define mmCHCG_STATUS                                                                                  0x2dc3
7719 #define mmCHCG_STATUS_BASE_IDX                                                                         1
7720 
7721 
7722 // addressBlock: gc_gl2dec
7723 // base address: 0x33800
7724 #define mmGL2C_CTRL                                                                                    0x2e00
7725 #define mmGL2C_CTRL_BASE_IDX                                                                           1
7726 #define mmGL2C_CTRL2                                                                                   0x2e01
7727 #define mmGL2C_CTRL2_BASE_IDX                                                                          1
7728 #define mmGL2C_ADDR_MATCH_MASK                                                                         0x2e03
7729 #define mmGL2C_ADDR_MATCH_MASK_BASE_IDX                                                                1
7730 #define mmGL2C_ADDR_MATCH_SIZE                                                                         0x2e04
7731 #define mmGL2C_ADDR_MATCH_SIZE_BASE_IDX                                                                1
7732 #define mmGL2C_WBINVL2                                                                                 0x2e05
7733 #define mmGL2C_WBINVL2_BASE_IDX                                                                        1
7734 #define mmGL2C_SOFT_RESET                                                                              0x2e06
7735 #define mmGL2C_SOFT_RESET_BASE_IDX                                                                     1
7736 #define mmGL2C_CM_CTRL0                                                                                0x2e07
7737 #define mmGL2C_CM_CTRL0_BASE_IDX                                                                       1
7738 #define mmGL2C_CM_CTRL1                                                                                0x2e08
7739 #define mmGL2C_CM_CTRL1_BASE_IDX                                                                       1
7740 #define mmGL2C_CM_STALL                                                                                0x2e09
7741 #define mmGL2C_CM_STALL_BASE_IDX                                                                       1
7742 #define mmGL2C_MDC_PF_FLAG_CTRL                                                                        0x2e0a
7743 #define mmGL2C_MDC_PF_FLAG_CTRL_BASE_IDX                                                               1
7744 #define mmGL2C_LB_CTR_CTRL                                                                             0x2e0d
7745 #define mmGL2C_LB_CTR_CTRL_BASE_IDX                                                                    1
7746 #define mmGL2C_LB_DATA0                                                                                0x2e0e
7747 #define mmGL2C_LB_DATA0_BASE_IDX                                                                       1
7748 #define mmGL2C_LB_DATA1                                                                                0x2e0f
7749 #define mmGL2C_LB_DATA1_BASE_IDX                                                                       1
7750 #define mmGL2C_LB_DATA2                                                                                0x2e10
7751 #define mmGL2C_LB_DATA2_BASE_IDX                                                                       1
7752 #define mmGL2C_LB_DATA3                                                                                0x2e11
7753 #define mmGL2C_LB_DATA3_BASE_IDX                                                                       1
7754 #define mmGL2C_LB_CTR_SEL0                                                                             0x2e12
7755 #define mmGL2C_LB_CTR_SEL0_BASE_IDX                                                                    1
7756 #define mmGL2C_LB_CTR_SEL1                                                                             0x2e13
7757 #define mmGL2C_LB_CTR_SEL1_BASE_IDX                                                                    1
7758 #define mmGL2A_ADDR_MATCH_CTRL                                                                         0x2e20
7759 #define mmGL2A_ADDR_MATCH_CTRL_BASE_IDX                                                                1
7760 #define mmGL2A_ADDR_MATCH_MASK                                                                         0x2e21
7761 #define mmGL2A_ADDR_MATCH_MASK_BASE_IDX                                                                1
7762 #define mmGL2A_ADDR_MATCH_SIZE                                                                         0x2e22
7763 #define mmGL2A_ADDR_MATCH_SIZE_BASE_IDX                                                                1
7764 #define mmGL2A_PRIORITY_CTRL                                                                           0x2e23
7765 #define mmGL2A_PRIORITY_CTRL_BASE_IDX                                                                  1
7766 #define mmGL2_PIPE_STEER_0                                                                             0x2e25
7767 #define mmGL2_PIPE_STEER_0_BASE_IDX                                                                    1
7768 #define mmGL2_PIPE_STEER_1                                                                             0x2e26
7769 #define mmGL2_PIPE_STEER_1_BASE_IDX                                                                    1
7770 
7771 
7772 // addressBlock: gc_perfddec
7773 // base address: 0x34000
7774 #define mmCPG_PERFCOUNTER1_LO                                                                          0x3000
7775 #define mmCPG_PERFCOUNTER1_LO_BASE_IDX                                                                 1
7776 #define mmCPG_PERFCOUNTER1_HI                                                                          0x3001
7777 #define mmCPG_PERFCOUNTER1_HI_BASE_IDX                                                                 1
7778 #define mmCPG_PERFCOUNTER0_LO                                                                          0x3002
7779 #define mmCPG_PERFCOUNTER0_LO_BASE_IDX                                                                 1
7780 #define mmCPG_PERFCOUNTER0_HI                                                                          0x3003
7781 #define mmCPG_PERFCOUNTER0_HI_BASE_IDX                                                                 1
7782 #define mmCPC_PERFCOUNTER1_LO                                                                          0x3004
7783 #define mmCPC_PERFCOUNTER1_LO_BASE_IDX                                                                 1
7784 #define mmCPC_PERFCOUNTER1_HI                                                                          0x3005
7785 #define mmCPC_PERFCOUNTER1_HI_BASE_IDX                                                                 1
7786 #define mmCPC_PERFCOUNTER0_LO                                                                          0x3006
7787 #define mmCPC_PERFCOUNTER0_LO_BASE_IDX                                                                 1
7788 #define mmCPC_PERFCOUNTER0_HI                                                                          0x3007
7789 #define mmCPC_PERFCOUNTER0_HI_BASE_IDX                                                                 1
7790 #define mmCPF_PERFCOUNTER1_LO                                                                          0x3008
7791 #define mmCPF_PERFCOUNTER1_LO_BASE_IDX                                                                 1
7792 #define mmCPF_PERFCOUNTER1_HI                                                                          0x3009
7793 #define mmCPF_PERFCOUNTER1_HI_BASE_IDX                                                                 1
7794 #define mmCPF_PERFCOUNTER0_LO                                                                          0x300a
7795 #define mmCPF_PERFCOUNTER0_LO_BASE_IDX                                                                 1
7796 #define mmCPF_PERFCOUNTER0_HI                                                                          0x300b
7797 #define mmCPF_PERFCOUNTER0_HI_BASE_IDX                                                                 1
7798 #define mmCPF_LATENCY_STATS_DATA                                                                       0x300c
7799 #define mmCPF_LATENCY_STATS_DATA_BASE_IDX                                                              1
7800 #define mmCPG_LATENCY_STATS_DATA                                                                       0x300d
7801 #define mmCPG_LATENCY_STATS_DATA_BASE_IDX                                                              1
7802 #define mmCPC_LATENCY_STATS_DATA                                                                       0x300e
7803 #define mmCPC_LATENCY_STATS_DATA_BASE_IDX                                                              1
7804 #define mmGRBM_PERFCOUNTER0_LO                                                                         0x3040
7805 #define mmGRBM_PERFCOUNTER0_LO_BASE_IDX                                                                1
7806 #define mmGRBM_PERFCOUNTER0_HI                                                                         0x3041
7807 #define mmGRBM_PERFCOUNTER0_HI_BASE_IDX                                                                1
7808 #define mmGRBM_PERFCOUNTER1_LO                                                                         0x3043
7809 #define mmGRBM_PERFCOUNTER1_LO_BASE_IDX                                                                1
7810 #define mmGRBM_PERFCOUNTER1_HI                                                                         0x3044
7811 #define mmGRBM_PERFCOUNTER1_HI_BASE_IDX                                                                1
7812 #define mmGRBM_SE0_PERFCOUNTER_LO                                                                      0x3045
7813 #define mmGRBM_SE0_PERFCOUNTER_LO_BASE_IDX                                                             1
7814 #define mmGRBM_SE0_PERFCOUNTER_HI                                                                      0x3046
7815 #define mmGRBM_SE0_PERFCOUNTER_HI_BASE_IDX                                                             1
7816 #define mmGRBM_SE1_PERFCOUNTER_LO                                                                      0x3047
7817 #define mmGRBM_SE1_PERFCOUNTER_LO_BASE_IDX                                                             1
7818 #define mmGRBM_SE1_PERFCOUNTER_HI                                                                      0x3048
7819 #define mmGRBM_SE1_PERFCOUNTER_HI_BASE_IDX                                                             1
7820 #define mmGRBM_SE2_PERFCOUNTER_LO                                                                      0x3049
7821 #define mmGRBM_SE2_PERFCOUNTER_LO_BASE_IDX                                                             1
7822 #define mmGRBM_SE2_PERFCOUNTER_HI                                                                      0x304a
7823 #define mmGRBM_SE2_PERFCOUNTER_HI_BASE_IDX                                                             1
7824 #define mmGRBM_SE3_PERFCOUNTER_LO                                                                      0x304b
7825 #define mmGRBM_SE3_PERFCOUNTER_LO_BASE_IDX                                                             1
7826 #define mmGRBM_SE3_PERFCOUNTER_HI                                                                      0x304c
7827 #define mmGRBM_SE3_PERFCOUNTER_HI_BASE_IDX                                                             1
7828 #define mmGE1_PERFCOUNTER0_LO                                                                          0x30a4
7829 #define mmGE1_PERFCOUNTER0_LO_BASE_IDX                                                                 1
7830 #define mmGE1_PERFCOUNTER0_HI                                                                          0x30a5
7831 #define mmGE1_PERFCOUNTER0_HI_BASE_IDX                                                                 1
7832 #define mmGE1_PERFCOUNTER1_LO                                                                          0x30a6
7833 #define mmGE1_PERFCOUNTER1_LO_BASE_IDX                                                                 1
7834 #define mmGE1_PERFCOUNTER1_HI                                                                          0x30a7
7835 #define mmGE1_PERFCOUNTER1_HI_BASE_IDX                                                                 1
7836 #define mmGE1_PERFCOUNTER2_LO                                                                          0x30a8
7837 #define mmGE1_PERFCOUNTER2_LO_BASE_IDX                                                                 1
7838 #define mmGE1_PERFCOUNTER2_HI                                                                          0x30a9
7839 #define mmGE1_PERFCOUNTER2_HI_BASE_IDX                                                                 1
7840 #define mmGE1_PERFCOUNTER3_LO                                                                          0x30aa
7841 #define mmGE1_PERFCOUNTER3_LO_BASE_IDX                                                                 1
7842 #define mmGE1_PERFCOUNTER3_HI                                                                          0x30ab
7843 #define mmGE1_PERFCOUNTER3_HI_BASE_IDX                                                                 1
7844 #define mmGE2_DIST_PERFCOUNTER0_LO                                                                     0x30ac
7845 #define mmGE2_DIST_PERFCOUNTER0_LO_BASE_IDX                                                            1
7846 #define mmGE2_DIST_PERFCOUNTER0_HI                                                                     0x30ad
7847 #define mmGE2_DIST_PERFCOUNTER0_HI_BASE_IDX                                                            1
7848 #define mmGE2_DIST_PERFCOUNTER1_LO                                                                     0x30ae
7849 #define mmGE2_DIST_PERFCOUNTER1_LO_BASE_IDX                                                            1
7850 #define mmGE2_DIST_PERFCOUNTER1_HI                                                                     0x30af
7851 #define mmGE2_DIST_PERFCOUNTER1_HI_BASE_IDX                                                            1
7852 #define mmGE2_DIST_PERFCOUNTER2_LO                                                                     0x30b0
7853 #define mmGE2_DIST_PERFCOUNTER2_LO_BASE_IDX                                                            1
7854 #define mmGE2_DIST_PERFCOUNTER2_HI                                                                     0x30b1
7855 #define mmGE2_DIST_PERFCOUNTER2_HI_BASE_IDX                                                            1
7856 #define mmGE2_DIST_PERFCOUNTER3_LO                                                                     0x30b2
7857 #define mmGE2_DIST_PERFCOUNTER3_LO_BASE_IDX                                                            1
7858 #define mmGE2_DIST_PERFCOUNTER3_HI                                                                     0x30b3
7859 #define mmGE2_DIST_PERFCOUNTER3_HI_BASE_IDX                                                            1
7860 #define mmGE2_SE_PERFCOUNTER0_LO                                                                       0x30b4
7861 #define mmGE2_SE_PERFCOUNTER0_LO_BASE_IDX                                                              1
7862 #define mmGE2_SE_PERFCOUNTER0_HI                                                                       0x30b5
7863 #define mmGE2_SE_PERFCOUNTER0_HI_BASE_IDX                                                              1
7864 #define mmGE2_SE_PERFCOUNTER1_LO                                                                       0x30b6
7865 #define mmGE2_SE_PERFCOUNTER1_LO_BASE_IDX                                                              1
7866 #define mmGE2_SE_PERFCOUNTER1_HI                                                                       0x30b7
7867 #define mmGE2_SE_PERFCOUNTER1_HI_BASE_IDX                                                              1
7868 #define mmGE2_SE_PERFCOUNTER2_LO                                                                       0x30b8
7869 #define mmGE2_SE_PERFCOUNTER2_LO_BASE_IDX                                                              1
7870 #define mmGE2_SE_PERFCOUNTER2_HI                                                                       0x30b9
7871 #define mmGE2_SE_PERFCOUNTER2_HI_BASE_IDX                                                              1
7872 #define mmGE2_SE_PERFCOUNTER3_LO                                                                       0x30ba
7873 #define mmGE2_SE_PERFCOUNTER3_LO_BASE_IDX                                                              1
7874 #define mmGE2_SE_PERFCOUNTER3_HI                                                                       0x30bb
7875 #define mmGE2_SE_PERFCOUNTER3_HI_BASE_IDX                                                              1
7876 #define mmPA_SU_PERFCOUNTER0_LO                                                                        0x3100
7877 #define mmPA_SU_PERFCOUNTER0_LO_BASE_IDX                                                               1
7878 #define mmPA_SU_PERFCOUNTER0_HI                                                                        0x3101
7879 #define mmPA_SU_PERFCOUNTER0_HI_BASE_IDX                                                               1
7880 #define mmPA_SU_PERFCOUNTER1_LO                                                                        0x3102
7881 #define mmPA_SU_PERFCOUNTER1_LO_BASE_IDX                                                               1
7882 #define mmPA_SU_PERFCOUNTER1_HI                                                                        0x3103
7883 #define mmPA_SU_PERFCOUNTER1_HI_BASE_IDX                                                               1
7884 #define mmPA_SU_PERFCOUNTER2_LO                                                                        0x3104
7885 #define mmPA_SU_PERFCOUNTER2_LO_BASE_IDX                                                               1
7886 #define mmPA_SU_PERFCOUNTER2_HI                                                                        0x3105
7887 #define mmPA_SU_PERFCOUNTER2_HI_BASE_IDX                                                               1
7888 #define mmPA_SU_PERFCOUNTER3_LO                                                                        0x3106
7889 #define mmPA_SU_PERFCOUNTER3_LO_BASE_IDX                                                               1
7890 #define mmPA_SU_PERFCOUNTER3_HI                                                                        0x3107
7891 #define mmPA_SU_PERFCOUNTER3_HI_BASE_IDX                                                               1
7892 #define mmPA_SC_PERFCOUNTER0_LO                                                                        0x3140
7893 #define mmPA_SC_PERFCOUNTER0_LO_BASE_IDX                                                               1
7894 #define mmPA_SC_PERFCOUNTER0_HI                                                                        0x3141
7895 #define mmPA_SC_PERFCOUNTER0_HI_BASE_IDX                                                               1
7896 #define mmPA_SC_PERFCOUNTER1_LO                                                                        0x3142
7897 #define mmPA_SC_PERFCOUNTER1_LO_BASE_IDX                                                               1
7898 #define mmPA_SC_PERFCOUNTER1_HI                                                                        0x3143
7899 #define mmPA_SC_PERFCOUNTER1_HI_BASE_IDX                                                               1
7900 #define mmPA_SC_PERFCOUNTER2_LO                                                                        0x3144
7901 #define mmPA_SC_PERFCOUNTER2_LO_BASE_IDX                                                               1
7902 #define mmPA_SC_PERFCOUNTER2_HI                                                                        0x3145
7903 #define mmPA_SC_PERFCOUNTER2_HI_BASE_IDX                                                               1
7904 #define mmPA_SC_PERFCOUNTER3_LO                                                                        0x3146
7905 #define mmPA_SC_PERFCOUNTER3_LO_BASE_IDX                                                               1
7906 #define mmPA_SC_PERFCOUNTER3_HI                                                                        0x3147
7907 #define mmPA_SC_PERFCOUNTER3_HI_BASE_IDX                                                               1
7908 #define mmPA_SC_PERFCOUNTER4_LO                                                                        0x3148
7909 #define mmPA_SC_PERFCOUNTER4_LO_BASE_IDX                                                               1
7910 #define mmPA_SC_PERFCOUNTER4_HI                                                                        0x3149
7911 #define mmPA_SC_PERFCOUNTER4_HI_BASE_IDX                                                               1
7912 #define mmPA_SC_PERFCOUNTER5_LO                                                                        0x314a
7913 #define mmPA_SC_PERFCOUNTER5_LO_BASE_IDX                                                               1
7914 #define mmPA_SC_PERFCOUNTER5_HI                                                                        0x314b
7915 #define mmPA_SC_PERFCOUNTER5_HI_BASE_IDX                                                               1
7916 #define mmPA_SC_PERFCOUNTER6_LO                                                                        0x314c
7917 #define mmPA_SC_PERFCOUNTER6_LO_BASE_IDX                                                               1
7918 #define mmPA_SC_PERFCOUNTER6_HI                                                                        0x314d
7919 #define mmPA_SC_PERFCOUNTER6_HI_BASE_IDX                                                               1
7920 #define mmPA_SC_PERFCOUNTER7_LO                                                                        0x314e
7921 #define mmPA_SC_PERFCOUNTER7_LO_BASE_IDX                                                               1
7922 #define mmPA_SC_PERFCOUNTER7_HI                                                                        0x314f
7923 #define mmPA_SC_PERFCOUNTER7_HI_BASE_IDX                                                               1
7924 #define mmSPI_PERFCOUNTER0_HI                                                                          0x3180
7925 #define mmSPI_PERFCOUNTER0_HI_BASE_IDX                                                                 1
7926 #define mmSPI_PERFCOUNTER0_LO                                                                          0x3181
7927 #define mmSPI_PERFCOUNTER0_LO_BASE_IDX                                                                 1
7928 #define mmSPI_PERFCOUNTER1_HI                                                                          0x3182
7929 #define mmSPI_PERFCOUNTER1_HI_BASE_IDX                                                                 1
7930 #define mmSPI_PERFCOUNTER1_LO                                                                          0x3183
7931 #define mmSPI_PERFCOUNTER1_LO_BASE_IDX                                                                 1
7932 #define mmSPI_PERFCOUNTER2_HI                                                                          0x3184
7933 #define mmSPI_PERFCOUNTER2_HI_BASE_IDX                                                                 1
7934 #define mmSPI_PERFCOUNTER2_LO                                                                          0x3185
7935 #define mmSPI_PERFCOUNTER2_LO_BASE_IDX                                                                 1
7936 #define mmSPI_PERFCOUNTER3_HI                                                                          0x3186
7937 #define mmSPI_PERFCOUNTER3_HI_BASE_IDX                                                                 1
7938 #define mmSPI_PERFCOUNTER3_LO                                                                          0x3187
7939 #define mmSPI_PERFCOUNTER3_LO_BASE_IDX                                                                 1
7940 #define mmSPI_PERFCOUNTER4_HI                                                                          0x3188
7941 #define mmSPI_PERFCOUNTER4_HI_BASE_IDX                                                                 1
7942 #define mmSPI_PERFCOUNTER4_LO                                                                          0x3189
7943 #define mmSPI_PERFCOUNTER4_LO_BASE_IDX                                                                 1
7944 #define mmSPI_PERFCOUNTER5_HI                                                                          0x318a
7945 #define mmSPI_PERFCOUNTER5_HI_BASE_IDX                                                                 1
7946 #define mmSPI_PERFCOUNTER5_LO                                                                          0x318b
7947 #define mmSPI_PERFCOUNTER5_LO_BASE_IDX                                                                 1
7948 #define mmSQ_PERFCOUNTER0_LO                                                                           0x31c0
7949 #define mmSQ_PERFCOUNTER0_LO_BASE_IDX                                                                  1
7950 #define mmSQ_PERFCOUNTER0_HI                                                                           0x31c1
7951 #define mmSQ_PERFCOUNTER0_HI_BASE_IDX                                                                  1
7952 #define mmSQ_PERFCOUNTER1_LO                                                                           0x31c2
7953 #define mmSQ_PERFCOUNTER1_LO_BASE_IDX                                                                  1
7954 #define mmSQ_PERFCOUNTER1_HI                                                                           0x31c3
7955 #define mmSQ_PERFCOUNTER1_HI_BASE_IDX                                                                  1
7956 #define mmSQ_PERFCOUNTER2_LO                                                                           0x31c4
7957 #define mmSQ_PERFCOUNTER2_LO_BASE_IDX                                                                  1
7958 #define mmSQ_PERFCOUNTER2_HI                                                                           0x31c5
7959 #define mmSQ_PERFCOUNTER2_HI_BASE_IDX                                                                  1
7960 #define mmSQ_PERFCOUNTER3_LO                                                                           0x31c6
7961 #define mmSQ_PERFCOUNTER3_LO_BASE_IDX                                                                  1
7962 #define mmSQ_PERFCOUNTER3_HI                                                                           0x31c7
7963 #define mmSQ_PERFCOUNTER3_HI_BASE_IDX                                                                  1
7964 #define mmSQ_PERFCOUNTER4_LO                                                                           0x31c8
7965 #define mmSQ_PERFCOUNTER4_LO_BASE_IDX                                                                  1
7966 #define mmSQ_PERFCOUNTER4_HI                                                                           0x31c9
7967 #define mmSQ_PERFCOUNTER4_HI_BASE_IDX                                                                  1
7968 #define mmSQ_PERFCOUNTER5_LO                                                                           0x31ca
7969 #define mmSQ_PERFCOUNTER5_LO_BASE_IDX                                                                  1
7970 #define mmSQ_PERFCOUNTER5_HI                                                                           0x31cb
7971 #define mmSQ_PERFCOUNTER5_HI_BASE_IDX                                                                  1
7972 #define mmSQ_PERFCOUNTER6_LO                                                                           0x31cc
7973 #define mmSQ_PERFCOUNTER6_LO_BASE_IDX                                                                  1
7974 #define mmSQ_PERFCOUNTER6_HI                                                                           0x31cd
7975 #define mmSQ_PERFCOUNTER6_HI_BASE_IDX                                                                  1
7976 #define mmSQ_PERFCOUNTER7_LO                                                                           0x31ce
7977 #define mmSQ_PERFCOUNTER7_LO_BASE_IDX                                                                  1
7978 #define mmSQ_PERFCOUNTER7_HI                                                                           0x31cf
7979 #define mmSQ_PERFCOUNTER7_HI_BASE_IDX                                                                  1
7980 #define mmSQ_PERFCOUNTER8_LO                                                                           0x31d0
7981 #define mmSQ_PERFCOUNTER8_LO_BASE_IDX                                                                  1
7982 #define mmSQ_PERFCOUNTER8_HI                                                                           0x31d1
7983 #define mmSQ_PERFCOUNTER8_HI_BASE_IDX                                                                  1
7984 #define mmSQ_PERFCOUNTER9_LO                                                                           0x31d2
7985 #define mmSQ_PERFCOUNTER9_LO_BASE_IDX                                                                  1
7986 #define mmSQ_PERFCOUNTER9_HI                                                                           0x31d3
7987 #define mmSQ_PERFCOUNTER9_HI_BASE_IDX                                                                  1
7988 #define mmSQ_PERFCOUNTER10_LO                                                                          0x31d4
7989 #define mmSQ_PERFCOUNTER10_LO_BASE_IDX                                                                 1
7990 #define mmSQ_PERFCOUNTER10_HI                                                                          0x31d5
7991 #define mmSQ_PERFCOUNTER10_HI_BASE_IDX                                                                 1
7992 #define mmSQ_PERFCOUNTER11_LO                                                                          0x31d6
7993 #define mmSQ_PERFCOUNTER11_LO_BASE_IDX                                                                 1
7994 #define mmSQ_PERFCOUNTER11_HI                                                                          0x31d7
7995 #define mmSQ_PERFCOUNTER11_HI_BASE_IDX                                                                 1
7996 #define mmSQ_PERFCOUNTER12_LO                                                                          0x31d8
7997 #define mmSQ_PERFCOUNTER12_LO_BASE_IDX                                                                 1
7998 #define mmSQ_PERFCOUNTER12_HI                                                                          0x31d9
7999 #define mmSQ_PERFCOUNTER12_HI_BASE_IDX                                                                 1
8000 #define mmSQ_PERFCOUNTER13_LO                                                                          0x31da
8001 #define mmSQ_PERFCOUNTER13_LO_BASE_IDX                                                                 1
8002 #define mmSQ_PERFCOUNTER13_HI                                                                          0x31db
8003 #define mmSQ_PERFCOUNTER13_HI_BASE_IDX                                                                 1
8004 #define mmSQ_PERFCOUNTER14_LO                                                                          0x31dc
8005 #define mmSQ_PERFCOUNTER14_LO_BASE_IDX                                                                 1
8006 #define mmSQ_PERFCOUNTER14_HI                                                                          0x31dd
8007 #define mmSQ_PERFCOUNTER14_HI_BASE_IDX                                                                 1
8008 #define mmSQ_PERFCOUNTER15_LO                                                                          0x31de
8009 #define mmSQ_PERFCOUNTER15_LO_BASE_IDX                                                                 1
8010 #define mmSQ_PERFCOUNTER15_HI                                                                          0x31df
8011 #define mmSQ_PERFCOUNTER15_HI_BASE_IDX                                                                 1
8012 #define mmSX_PERFCOUNTER0_LO                                                                           0x3240
8013 #define mmSX_PERFCOUNTER0_LO_BASE_IDX                                                                  1
8014 #define mmSX_PERFCOUNTER0_HI                                                                           0x3241
8015 #define mmSX_PERFCOUNTER0_HI_BASE_IDX                                                                  1
8016 #define mmSX_PERFCOUNTER1_LO                                                                           0x3242
8017 #define mmSX_PERFCOUNTER1_LO_BASE_IDX                                                                  1
8018 #define mmSX_PERFCOUNTER1_HI                                                                           0x3243
8019 #define mmSX_PERFCOUNTER1_HI_BASE_IDX                                                                  1
8020 #define mmSX_PERFCOUNTER2_LO                                                                           0x3244
8021 #define mmSX_PERFCOUNTER2_LO_BASE_IDX                                                                  1
8022 #define mmSX_PERFCOUNTER2_HI                                                                           0x3245
8023 #define mmSX_PERFCOUNTER2_HI_BASE_IDX                                                                  1
8024 #define mmSX_PERFCOUNTER3_LO                                                                           0x3246
8025 #define mmSX_PERFCOUNTER3_LO_BASE_IDX                                                                  1
8026 #define mmSX_PERFCOUNTER3_HI                                                                           0x3247
8027 #define mmSX_PERFCOUNTER3_HI_BASE_IDX                                                                  1
8028 #define mmGCEA_PERFCOUNTER2_LO                                                                         0x3260
8029 #define mmGCEA_PERFCOUNTER2_LO_BASE_IDX                                                                1
8030 #define mmGCEA_PERFCOUNTER2_HI                                                                         0x3261
8031 #define mmGCEA_PERFCOUNTER2_HI_BASE_IDX                                                                1
8032 #define mmGCEA_PERFCOUNTER_LO                                                                          0x3262
8033 #define mmGCEA_PERFCOUNTER_LO_BASE_IDX                                                                 1
8034 #define mmGCEA_PERFCOUNTER_HI                                                                          0x3263
8035 #define mmGCEA_PERFCOUNTER_HI_BASE_IDX                                                                 1
8036 #define mmGDS_PERFCOUNTER0_LO                                                                          0x3280
8037 #define mmGDS_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8038 #define mmGDS_PERFCOUNTER0_HI                                                                          0x3281
8039 #define mmGDS_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8040 #define mmGDS_PERFCOUNTER1_LO                                                                          0x3282
8041 #define mmGDS_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8042 #define mmGDS_PERFCOUNTER1_HI                                                                          0x3283
8043 #define mmGDS_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8044 #define mmGDS_PERFCOUNTER2_LO                                                                          0x3284
8045 #define mmGDS_PERFCOUNTER2_LO_BASE_IDX                                                                 1
8046 #define mmGDS_PERFCOUNTER2_HI                                                                          0x3285
8047 #define mmGDS_PERFCOUNTER2_HI_BASE_IDX                                                                 1
8048 #define mmGDS_PERFCOUNTER3_LO                                                                          0x3286
8049 #define mmGDS_PERFCOUNTER3_LO_BASE_IDX                                                                 1
8050 #define mmGDS_PERFCOUNTER3_HI                                                                          0x3287
8051 #define mmGDS_PERFCOUNTER3_HI_BASE_IDX                                                                 1
8052 #define mmTA_PERFCOUNTER0_LO                                                                           0x32c0
8053 #define mmTA_PERFCOUNTER0_LO_BASE_IDX                                                                  1
8054 #define mmTA_PERFCOUNTER0_HI                                                                           0x32c1
8055 #define mmTA_PERFCOUNTER0_HI_BASE_IDX                                                                  1
8056 #define mmTA_PERFCOUNTER1_LO                                                                           0x32c2
8057 #define mmTA_PERFCOUNTER1_LO_BASE_IDX                                                                  1
8058 #define mmTA_PERFCOUNTER1_HI                                                                           0x32c3
8059 #define mmTA_PERFCOUNTER1_HI_BASE_IDX                                                                  1
8060 #define mmTD_PERFCOUNTER0_LO                                                                           0x3300
8061 #define mmTD_PERFCOUNTER0_LO_BASE_IDX                                                                  1
8062 #define mmTD_PERFCOUNTER0_HI                                                                           0x3301
8063 #define mmTD_PERFCOUNTER0_HI_BASE_IDX                                                                  1
8064 #define mmTD_PERFCOUNTER1_LO                                                                           0x3302
8065 #define mmTD_PERFCOUNTER1_LO_BASE_IDX                                                                  1
8066 #define mmTD_PERFCOUNTER1_HI                                                                           0x3303
8067 #define mmTD_PERFCOUNTER1_HI_BASE_IDX                                                                  1
8068 #define mmTCP_PERFCOUNTER0_LO                                                                          0x3340
8069 #define mmTCP_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8070 #define mmTCP_PERFCOUNTER0_HI                                                                          0x3341
8071 #define mmTCP_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8072 #define mmTCP_PERFCOUNTER1_LO                                                                          0x3342
8073 #define mmTCP_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8074 #define mmTCP_PERFCOUNTER1_HI                                                                          0x3343
8075 #define mmTCP_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8076 #define mmTCP_PERFCOUNTER2_LO                                                                          0x3344
8077 #define mmTCP_PERFCOUNTER2_LO_BASE_IDX                                                                 1
8078 #define mmTCP_PERFCOUNTER2_HI                                                                          0x3345
8079 #define mmTCP_PERFCOUNTER2_HI_BASE_IDX                                                                 1
8080 #define mmTCP_PERFCOUNTER3_LO                                                                          0x3346
8081 #define mmTCP_PERFCOUNTER3_LO_BASE_IDX                                                                 1
8082 #define mmTCP_PERFCOUNTER3_HI                                                                          0x3347
8083 #define mmTCP_PERFCOUNTER3_HI_BASE_IDX                                                                 1
8084 #define mmGL2C_PERFCOUNTER0_LO                                                                         0x3380
8085 #define mmGL2C_PERFCOUNTER0_LO_BASE_IDX                                                                1
8086 #define mmGL2C_PERFCOUNTER0_HI                                                                         0x3381
8087 #define mmGL2C_PERFCOUNTER0_HI_BASE_IDX                                                                1
8088 #define mmGL2C_PERFCOUNTER1_LO                                                                         0x3382
8089 #define mmGL2C_PERFCOUNTER1_LO_BASE_IDX                                                                1
8090 #define mmGL2C_PERFCOUNTER1_HI                                                                         0x3383
8091 #define mmGL2C_PERFCOUNTER1_HI_BASE_IDX                                                                1
8092 #define mmGL2C_PERFCOUNTER2_LO                                                                         0x3384
8093 #define mmGL2C_PERFCOUNTER2_LO_BASE_IDX                                                                1
8094 #define mmGL2C_PERFCOUNTER2_HI                                                                         0x3385
8095 #define mmGL2C_PERFCOUNTER2_HI_BASE_IDX                                                                1
8096 #define mmGL2C_PERFCOUNTER3_LO                                                                         0x3386
8097 #define mmGL2C_PERFCOUNTER3_LO_BASE_IDX                                                                1
8098 #define mmGL2C_PERFCOUNTER3_HI                                                                         0x3387
8099 #define mmGL2C_PERFCOUNTER3_HI_BASE_IDX                                                                1
8100 #define mmGL2A_PERFCOUNTER0_LO                                                                         0x3390
8101 #define mmGL2A_PERFCOUNTER0_LO_BASE_IDX                                                                1
8102 #define mmGL2A_PERFCOUNTER0_HI                                                                         0x3391
8103 #define mmGL2A_PERFCOUNTER0_HI_BASE_IDX                                                                1
8104 #define mmGL2A_PERFCOUNTER1_LO                                                                         0x3392
8105 #define mmGL2A_PERFCOUNTER1_LO_BASE_IDX                                                                1
8106 #define mmGL2A_PERFCOUNTER1_HI                                                                         0x3393
8107 #define mmGL2A_PERFCOUNTER1_HI_BASE_IDX                                                                1
8108 #define mmGL2A_PERFCOUNTER2_LO                                                                         0x3394
8109 #define mmGL2A_PERFCOUNTER2_LO_BASE_IDX                                                                1
8110 #define mmGL2A_PERFCOUNTER2_HI                                                                         0x3395
8111 #define mmGL2A_PERFCOUNTER2_HI_BASE_IDX                                                                1
8112 #define mmGL2A_PERFCOUNTER3_LO                                                                         0x3396
8113 #define mmGL2A_PERFCOUNTER3_LO_BASE_IDX                                                                1
8114 #define mmGL2A_PERFCOUNTER3_HI                                                                         0x3397
8115 #define mmGL2A_PERFCOUNTER3_HI_BASE_IDX                                                                1
8116 #define mmGL1C_PERFCOUNTER0_LO                                                                         0x33a0
8117 #define mmGL1C_PERFCOUNTER0_LO_BASE_IDX                                                                1
8118 #define mmGL1C_PERFCOUNTER0_HI                                                                         0x33a1
8119 #define mmGL1C_PERFCOUNTER0_HI_BASE_IDX                                                                1
8120 #define mmGL1C_PERFCOUNTER1_LO                                                                         0x33a2
8121 #define mmGL1C_PERFCOUNTER1_LO_BASE_IDX                                                                1
8122 #define mmGL1C_PERFCOUNTER1_HI                                                                         0x33a3
8123 #define mmGL1C_PERFCOUNTER1_HI_BASE_IDX                                                                1
8124 #define mmGL1C_PERFCOUNTER2_LO                                                                         0x33a4
8125 #define mmGL1C_PERFCOUNTER2_LO_BASE_IDX                                                                1
8126 #define mmGL1C_PERFCOUNTER2_HI                                                                         0x33a5
8127 #define mmGL1C_PERFCOUNTER2_HI_BASE_IDX                                                                1
8128 #define mmGL1C_PERFCOUNTER3_LO                                                                         0x33a6
8129 #define mmGL1C_PERFCOUNTER3_LO_BASE_IDX                                                                1
8130 #define mmGL1C_PERFCOUNTER3_HI                                                                         0x33a7
8131 #define mmGL1C_PERFCOUNTER3_HI_BASE_IDX                                                                1
8132 #define mmCHC_PERFCOUNTER0_LO                                                                          0x33c0
8133 #define mmCHC_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8134 #define mmCHC_PERFCOUNTER0_HI                                                                          0x33c1
8135 #define mmCHC_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8136 #define mmCHC_PERFCOUNTER1_LO                                                                          0x33c2
8137 #define mmCHC_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8138 #define mmCHC_PERFCOUNTER1_HI                                                                          0x33c3
8139 #define mmCHC_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8140 #define mmCHC_PERFCOUNTER2_LO                                                                          0x33c4
8141 #define mmCHC_PERFCOUNTER2_LO_BASE_IDX                                                                 1
8142 #define mmCHC_PERFCOUNTER2_HI                                                                          0x33c5
8143 #define mmCHC_PERFCOUNTER2_HI_BASE_IDX                                                                 1
8144 #define mmCHC_PERFCOUNTER3_LO                                                                          0x33c6
8145 #define mmCHC_PERFCOUNTER3_LO_BASE_IDX                                                                 1
8146 #define mmCHC_PERFCOUNTER3_HI                                                                          0x33c7
8147 #define mmCHC_PERFCOUNTER3_HI_BASE_IDX                                                                 1
8148 #define mmCHCG_PERFCOUNTER0_LO                                                                         0x33c8
8149 #define mmCHCG_PERFCOUNTER0_LO_BASE_IDX                                                                1
8150 #define mmCHCG_PERFCOUNTER0_HI                                                                         0x33c9
8151 #define mmCHCG_PERFCOUNTER0_HI_BASE_IDX                                                                1
8152 #define mmCHCG_PERFCOUNTER1_LO                                                                         0x33ca
8153 #define mmCHCG_PERFCOUNTER1_LO_BASE_IDX                                                                1
8154 #define mmCHCG_PERFCOUNTER1_HI                                                                         0x33cb
8155 #define mmCHCG_PERFCOUNTER1_HI_BASE_IDX                                                                1
8156 #define mmCHCG_PERFCOUNTER2_LO                                                                         0x33cc
8157 #define mmCHCG_PERFCOUNTER2_LO_BASE_IDX                                                                1
8158 #define mmCHCG_PERFCOUNTER2_HI                                                                         0x33cd
8159 #define mmCHCG_PERFCOUNTER2_HI_BASE_IDX                                                                1
8160 #define mmCHCG_PERFCOUNTER3_LO                                                                         0x33ce
8161 #define mmCHCG_PERFCOUNTER3_LO_BASE_IDX                                                                1
8162 #define mmCHCG_PERFCOUNTER3_HI                                                                         0x33cf
8163 #define mmCHCG_PERFCOUNTER3_HI_BASE_IDX                                                                1
8164 #define mmCB_PERFCOUNTER0_LO                                                                           0x3406
8165 #define mmCB_PERFCOUNTER0_LO_BASE_IDX                                                                  1
8166 #define mmCB_PERFCOUNTER0_HI                                                                           0x3407
8167 #define mmCB_PERFCOUNTER0_HI_BASE_IDX                                                                  1
8168 #define mmCB_PERFCOUNTER1_LO                                                                           0x3408
8169 #define mmCB_PERFCOUNTER1_LO_BASE_IDX                                                                  1
8170 #define mmCB_PERFCOUNTER1_HI                                                                           0x3409
8171 #define mmCB_PERFCOUNTER1_HI_BASE_IDX                                                                  1
8172 #define mmCB_PERFCOUNTER2_LO                                                                           0x340a
8173 #define mmCB_PERFCOUNTER2_LO_BASE_IDX                                                                  1
8174 #define mmCB_PERFCOUNTER2_HI                                                                           0x340b
8175 #define mmCB_PERFCOUNTER2_HI_BASE_IDX                                                                  1
8176 #define mmCB_PERFCOUNTER3_LO                                                                           0x340c
8177 #define mmCB_PERFCOUNTER3_LO_BASE_IDX                                                                  1
8178 #define mmCB_PERFCOUNTER3_HI                                                                           0x340d
8179 #define mmCB_PERFCOUNTER3_HI_BASE_IDX                                                                  1
8180 #define mmDB_PERFCOUNTER0_LO                                                                           0x3440
8181 #define mmDB_PERFCOUNTER0_LO_BASE_IDX                                                                  1
8182 #define mmDB_PERFCOUNTER0_HI                                                                           0x3441
8183 #define mmDB_PERFCOUNTER0_HI_BASE_IDX                                                                  1
8184 #define mmDB_PERFCOUNTER1_LO                                                                           0x3442
8185 #define mmDB_PERFCOUNTER1_LO_BASE_IDX                                                                  1
8186 #define mmDB_PERFCOUNTER1_HI                                                                           0x3443
8187 #define mmDB_PERFCOUNTER1_HI_BASE_IDX                                                                  1
8188 #define mmDB_PERFCOUNTER2_LO                                                                           0x3444
8189 #define mmDB_PERFCOUNTER2_LO_BASE_IDX                                                                  1
8190 #define mmDB_PERFCOUNTER2_HI                                                                           0x3445
8191 #define mmDB_PERFCOUNTER2_HI_BASE_IDX                                                                  1
8192 #define mmDB_PERFCOUNTER3_LO                                                                           0x3446
8193 #define mmDB_PERFCOUNTER3_LO_BASE_IDX                                                                  1
8194 #define mmDB_PERFCOUNTER3_HI                                                                           0x3447
8195 #define mmDB_PERFCOUNTER3_HI_BASE_IDX                                                                  1
8196 #define mmRLC_PERFCOUNTER0_LO                                                                          0x3480
8197 #define mmRLC_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8198 #define mmRLC_PERFCOUNTER0_HI                                                                          0x3481
8199 #define mmRLC_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8200 #define mmRLC_PERFCOUNTER1_LO                                                                          0x3482
8201 #define mmRLC_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8202 #define mmRLC_PERFCOUNTER1_HI                                                                          0x3483
8203 #define mmRLC_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8204 #define mmRMI_PERFCOUNTER0_LO                                                                          0x34c0
8205 #define mmRMI_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8206 #define mmRMI_PERFCOUNTER0_HI                                                                          0x34c1
8207 #define mmRMI_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8208 #define mmRMI_PERFCOUNTER1_LO                                                                          0x34c2
8209 #define mmRMI_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8210 #define mmRMI_PERFCOUNTER1_HI                                                                          0x34c3
8211 #define mmRMI_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8212 #define mmRMI_PERFCOUNTER2_LO                                                                          0x34c4
8213 #define mmRMI_PERFCOUNTER2_LO_BASE_IDX                                                                 1
8214 #define mmRMI_PERFCOUNTER2_HI                                                                          0x34c5
8215 #define mmRMI_PERFCOUNTER2_HI_BASE_IDX                                                                 1
8216 #define mmRMI_PERFCOUNTER3_LO                                                                          0x34c6
8217 #define mmRMI_PERFCOUNTER3_LO_BASE_IDX                                                                 1
8218 #define mmRMI_PERFCOUNTER3_HI                                                                          0x34c7
8219 #define mmRMI_PERFCOUNTER3_HI_BASE_IDX                                                                 1
8220 #define mmUTCL1_PERFCOUNTER0_LO                                                                        0x351c
8221 #define mmUTCL1_PERFCOUNTER0_LO_BASE_IDX                                                               1
8222 #define mmUTCL1_PERFCOUNTER0_HI                                                                        0x351d
8223 #define mmUTCL1_PERFCOUNTER0_HI_BASE_IDX                                                               1
8224 #define mmUTCL1_PERFCOUNTER1_LO                                                                        0x351e
8225 #define mmUTCL1_PERFCOUNTER1_LO_BASE_IDX                                                               1
8226 #define mmUTCL1_PERFCOUNTER1_HI                                                                        0x351f
8227 #define mmUTCL1_PERFCOUNTER1_HI_BASE_IDX                                                               1
8228 #define mmGCR_PERFCOUNTER0_LO                                                                          0x3520
8229 #define mmGCR_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8230 #define mmGCR_PERFCOUNTER0_HI                                                                          0x3521
8231 #define mmGCR_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8232 #define mmGCR_PERFCOUNTER1_LO                                                                          0x3522
8233 #define mmGCR_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8234 #define mmGCR_PERFCOUNTER1_HI                                                                          0x3523
8235 #define mmGCR_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8236 #define mmPA_PH_PERFCOUNTER0_LO                                                                        0x3580
8237 #define mmPA_PH_PERFCOUNTER0_LO_BASE_IDX                                                               1
8238 #define mmPA_PH_PERFCOUNTER0_HI                                                                        0x3581
8239 #define mmPA_PH_PERFCOUNTER0_HI_BASE_IDX                                                               1
8240 #define mmPA_PH_PERFCOUNTER1_LO                                                                        0x3582
8241 #define mmPA_PH_PERFCOUNTER1_LO_BASE_IDX                                                               1
8242 #define mmPA_PH_PERFCOUNTER1_HI                                                                        0x3583
8243 #define mmPA_PH_PERFCOUNTER1_HI_BASE_IDX                                                               1
8244 #define mmPA_PH_PERFCOUNTER2_LO                                                                        0x3584
8245 #define mmPA_PH_PERFCOUNTER2_LO_BASE_IDX                                                               1
8246 #define mmPA_PH_PERFCOUNTER2_HI                                                                        0x3585
8247 #define mmPA_PH_PERFCOUNTER2_HI_BASE_IDX                                                               1
8248 #define mmPA_PH_PERFCOUNTER3_LO                                                                        0x3586
8249 #define mmPA_PH_PERFCOUNTER3_LO_BASE_IDX                                                               1
8250 #define mmPA_PH_PERFCOUNTER3_HI                                                                        0x3587
8251 #define mmPA_PH_PERFCOUNTER3_HI_BASE_IDX                                                               1
8252 #define mmPA_PH_PERFCOUNTER4_LO                                                                        0x3588
8253 #define mmPA_PH_PERFCOUNTER4_LO_BASE_IDX                                                               1
8254 #define mmPA_PH_PERFCOUNTER4_HI                                                                        0x3589
8255 #define mmPA_PH_PERFCOUNTER4_HI_BASE_IDX                                                               1
8256 #define mmPA_PH_PERFCOUNTER5_LO                                                                        0x358a
8257 #define mmPA_PH_PERFCOUNTER5_LO_BASE_IDX                                                               1
8258 #define mmPA_PH_PERFCOUNTER5_HI                                                                        0x358b
8259 #define mmPA_PH_PERFCOUNTER5_HI_BASE_IDX                                                               1
8260 #define mmPA_PH_PERFCOUNTER6_LO                                                                        0x358c
8261 #define mmPA_PH_PERFCOUNTER6_LO_BASE_IDX                                                               1
8262 #define mmPA_PH_PERFCOUNTER6_HI                                                                        0x358d
8263 #define mmPA_PH_PERFCOUNTER6_HI_BASE_IDX                                                               1
8264 #define mmPA_PH_PERFCOUNTER7_LO                                                                        0x358e
8265 #define mmPA_PH_PERFCOUNTER7_LO_BASE_IDX                                                               1
8266 #define mmPA_PH_PERFCOUNTER7_HI                                                                        0x358f
8267 #define mmPA_PH_PERFCOUNTER7_HI_BASE_IDX                                                               1
8268 #define mmGL1A_PERFCOUNTER0_LO                                                                         0x35c0
8269 #define mmGL1A_PERFCOUNTER0_LO_BASE_IDX                                                                1
8270 #define mmGL1A_PERFCOUNTER0_HI                                                                         0x35c1
8271 #define mmGL1A_PERFCOUNTER0_HI_BASE_IDX                                                                1
8272 #define mmGL1A_PERFCOUNTER1_LO                                                                         0x35c2
8273 #define mmGL1A_PERFCOUNTER1_LO_BASE_IDX                                                                1
8274 #define mmGL1A_PERFCOUNTER1_HI                                                                         0x35c3
8275 #define mmGL1A_PERFCOUNTER1_HI_BASE_IDX                                                                1
8276 #define mmGL1A_PERFCOUNTER2_LO                                                                         0x35c4
8277 #define mmGL1A_PERFCOUNTER2_LO_BASE_IDX                                                                1
8278 #define mmGL1A_PERFCOUNTER2_HI                                                                         0x35c5
8279 #define mmGL1A_PERFCOUNTER2_HI_BASE_IDX                                                                1
8280 #define mmGL1A_PERFCOUNTER3_LO                                                                         0x35c6
8281 #define mmGL1A_PERFCOUNTER3_LO_BASE_IDX                                                                1
8282 #define mmGL1A_PERFCOUNTER3_HI                                                                         0x35c7
8283 #define mmGL1A_PERFCOUNTER3_HI_BASE_IDX                                                                1
8284 #define mmCHA_PERFCOUNTER0_LO                                                                          0x3600
8285 #define mmCHA_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8286 #define mmCHA_PERFCOUNTER0_HI                                                                          0x3601
8287 #define mmCHA_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8288 #define mmCHA_PERFCOUNTER1_LO                                                                          0x3602
8289 #define mmCHA_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8290 #define mmCHA_PERFCOUNTER1_HI                                                                          0x3603
8291 #define mmCHA_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8292 #define mmCHA_PERFCOUNTER2_LO                                                                          0x3604
8293 #define mmCHA_PERFCOUNTER2_LO_BASE_IDX                                                                 1
8294 #define mmCHA_PERFCOUNTER2_HI                                                                          0x3605
8295 #define mmCHA_PERFCOUNTER2_HI_BASE_IDX                                                                 1
8296 #define mmCHA_PERFCOUNTER3_LO                                                                          0x3606
8297 #define mmCHA_PERFCOUNTER3_LO_BASE_IDX                                                                 1
8298 #define mmCHA_PERFCOUNTER3_HI                                                                          0x3607
8299 #define mmCHA_PERFCOUNTER3_HI_BASE_IDX                                                                 1
8300 #define mmGUS_PERFCOUNTER2_LO                                                                          0x3640
8301 #define mmGUS_PERFCOUNTER2_LO_BASE_IDX                                                                 1
8302 #define mmGUS_PERFCOUNTER2_HI                                                                          0x3641
8303 #define mmGUS_PERFCOUNTER2_HI_BASE_IDX                                                                 1
8304 #define mmGUS_PERFCOUNTER_LO                                                                           0x3642
8305 #define mmGUS_PERFCOUNTER_LO_BASE_IDX                                                                  1
8306 #define mmGUS_PERFCOUNTER_HI                                                                           0x3643
8307 #define mmGUS_PERFCOUNTER_HI_BASE_IDX                                                                  1
8308 
8309 
8310 // addressBlock: gc_gcvml2prdec
8311 // base address: 0x353a0
8312 #define mmGCMC_VM_L2_PERFCOUNTER_LO                                                                    0x34e8
8313 #define mmGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX                                                           1
8314 #define mmGCMC_VM_L2_PERFCOUNTER_HI                                                                    0x34e9
8315 #define mmGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX                                                           1
8316 #define mmGCUTCL2_PERFCOUNTER_LO                                                                       0x34ea
8317 #define mmGCUTCL2_PERFCOUNTER_LO_BASE_IDX                                                              1
8318 #define mmGCUTCL2_PERFCOUNTER_HI                                                                       0x34eb
8319 #define mmGCUTCL2_PERFCOUNTER_HI_BASE_IDX                                                              1
8320 
8321 
8322 // addressBlock: gc_gcvml2perfddec
8323 // base address: 0x353e0
8324 #define mmGCVML2_PERFCOUNTER2_0_LO                                                                     0x34f8
8325 #define mmGCVML2_PERFCOUNTER2_0_LO_BASE_IDX                                                            1
8326 #define mmGCVML2_PERFCOUNTER2_1_LO                                                                     0x34f9
8327 #define mmGCVML2_PERFCOUNTER2_1_LO_BASE_IDX                                                            1
8328 #define mmGCVML2_PERFCOUNTER2_0_HI                                                                     0x34fa
8329 #define mmGCVML2_PERFCOUNTER2_0_HI_BASE_IDX                                                            1
8330 #define mmGCVML2_PERFCOUNTER2_1_HI                                                                     0x34fb
8331 #define mmGCVML2_PERFCOUNTER2_1_HI_BASE_IDX                                                            1
8332 
8333 
8334 // addressBlock: gc_sdma0_sdma0perfddec
8335 // base address: 0x35980
8336 #define mmSDMA0_PERFCNT_PERFCOUNTER_LO                                                                 0x3660
8337 #define mmSDMA0_PERFCNT_PERFCOUNTER_LO_BASE_IDX                                                        1
8338 #define mmSDMA0_PERFCNT_PERFCOUNTER_HI                                                                 0x3661
8339 #define mmSDMA0_PERFCNT_PERFCOUNTER_HI_BASE_IDX                                                        1
8340 #define mmSDMA0_PERFCOUNTER0_LO                                                                        0x3662
8341 #define mmSDMA0_PERFCOUNTER0_LO_BASE_IDX                                                               1
8342 #define mmSDMA0_PERFCOUNTER0_HI                                                                        0x3663
8343 #define mmSDMA0_PERFCOUNTER0_HI_BASE_IDX                                                               1
8344 #define mmSDMA0_PERFCOUNTER1_LO                                                                        0x3664
8345 #define mmSDMA0_PERFCOUNTER1_LO_BASE_IDX                                                               1
8346 #define mmSDMA0_PERFCOUNTER1_HI                                                                        0x3665
8347 #define mmSDMA0_PERFCOUNTER1_HI_BASE_IDX                                                               1
8348 
8349 
8350 // addressBlock: gc_sdma1_sdma1perfddec
8351 // base address: 0x359b0
8352 #define mmSDMA1_PERFCNT_PERFCOUNTER_LO                                                                 0x366c
8353 #define mmSDMA1_PERFCNT_PERFCOUNTER_LO_BASE_IDX                                                        1
8354 #define mmSDMA1_PERFCNT_PERFCOUNTER_HI                                                                 0x366d
8355 #define mmSDMA1_PERFCNT_PERFCOUNTER_HI_BASE_IDX                                                        1
8356 #define mmSDMA1_PERFCOUNTER0_LO                                                                        0x366e
8357 #define mmSDMA1_PERFCOUNTER0_LO_BASE_IDX                                                               1
8358 #define mmSDMA1_PERFCOUNTER0_HI                                                                        0x366f
8359 #define mmSDMA1_PERFCOUNTER0_HI_BASE_IDX                                                               1
8360 #define mmSDMA1_PERFCOUNTER1_LO                                                                        0x3670
8361 #define mmSDMA1_PERFCOUNTER1_LO_BASE_IDX                                                               1
8362 #define mmSDMA1_PERFCOUNTER1_HI                                                                        0x3671
8363 #define mmSDMA1_PERFCOUNTER1_HI_BASE_IDX                                                               1
8364 
8365 
8366 // addressBlock: gc_sdma2_sdma2perfddec
8367 // base address: 0x359e0
8368 #define mmSDMA2_PERFCNT_PERFCOUNTER_LO                                                                 0x3678
8369 #define mmSDMA2_PERFCNT_PERFCOUNTER_LO_BASE_IDX                                                        1
8370 #define mmSDMA2_PERFCNT_PERFCOUNTER_HI                                                                 0x3679
8371 #define mmSDMA2_PERFCNT_PERFCOUNTER_HI_BASE_IDX                                                        1
8372 #define mmSDMA2_PERFCOUNTER0_LO                                                                        0x367a
8373 #define mmSDMA2_PERFCOUNTER0_LO_BASE_IDX                                                               1
8374 #define mmSDMA2_PERFCOUNTER0_HI                                                                        0x367b
8375 #define mmSDMA2_PERFCOUNTER0_HI_BASE_IDX                                                               1
8376 #define mmSDMA2_PERFCOUNTER1_LO                                                                        0x367c
8377 #define mmSDMA2_PERFCOUNTER1_LO_BASE_IDX                                                               1
8378 #define mmSDMA2_PERFCOUNTER1_HI                                                                        0x367d
8379 #define mmSDMA2_PERFCOUNTER1_HI_BASE_IDX                                                               1
8380 
8381 
8382 // addressBlock: gc_sdma3_sdma3perfddec
8383 // base address: 0x35a10
8384 #define mmSDMA3_PERFCNT_PERFCOUNTER_LO                                                                 0x3684
8385 #define mmSDMA3_PERFCNT_PERFCOUNTER_LO_BASE_IDX                                                        1
8386 #define mmSDMA3_PERFCNT_PERFCOUNTER_HI                                                                 0x3685
8387 #define mmSDMA3_PERFCNT_PERFCOUNTER_HI_BASE_IDX                                                        1
8388 #define mmSDMA3_PERFCOUNTER0_LO                                                                        0x3686
8389 #define mmSDMA3_PERFCOUNTER0_LO_BASE_IDX                                                               1
8390 #define mmSDMA3_PERFCOUNTER0_HI                                                                        0x3687
8391 #define mmSDMA3_PERFCOUNTER0_HI_BASE_IDX                                                               1
8392 #define mmSDMA3_PERFCOUNTER1_LO                                                                        0x3688
8393 #define mmSDMA3_PERFCOUNTER1_LO_BASE_IDX                                                               1
8394 #define mmSDMA3_PERFCOUNTER1_HI                                                                        0x3689
8395 #define mmSDMA3_PERFCOUNTER1_HI_BASE_IDX                                                               1
8396 
8397 
8398 // addressBlock: gc_perfsdec
8399 // base address: 0x36000
8400 #define mmCPG_PERFCOUNTER1_SELECT                                                                      0x3800
8401 #define mmCPG_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
8402 #define mmCPG_PERFCOUNTER0_SELECT1                                                                     0x3801
8403 #define mmCPG_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
8404 #define mmCPG_PERFCOUNTER0_SELECT                                                                      0x3802
8405 #define mmCPG_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
8406 #define mmCPC_PERFCOUNTER1_SELECT                                                                      0x3803
8407 #define mmCPC_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
8408 #define mmCPC_PERFCOUNTER0_SELECT1                                                                     0x3804
8409 #define mmCPC_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
8410 #define mmCPF_PERFCOUNTER1_SELECT                                                                      0x3805
8411 #define mmCPF_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
8412 #define mmCPF_PERFCOUNTER0_SELECT1                                                                     0x3806
8413 #define mmCPF_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
8414 #define mmCPF_PERFCOUNTER0_SELECT                                                                      0x3807
8415 #define mmCPF_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
8416 #define mmCP_PERFMON_CNTL                                                                              0x3808
8417 #define mmCP_PERFMON_CNTL_BASE_IDX                                                                     1
8418 #define mmCPC_PERFCOUNTER0_SELECT                                                                      0x3809
8419 #define mmCPC_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
8420 #define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT                                                            0x380a
8421 #define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX                                                   1
8422 #define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT                                                            0x380b
8423 #define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX                                                   1
8424 #define mmCPF_LATENCY_STATS_SELECT                                                                     0x380c
8425 #define mmCPF_LATENCY_STATS_SELECT_BASE_IDX                                                            1
8426 #define mmCPG_LATENCY_STATS_SELECT                                                                     0x380d
8427 #define mmCPG_LATENCY_STATS_SELECT_BASE_IDX                                                            1
8428 #define mmCPC_LATENCY_STATS_SELECT                                                                     0x380e
8429 #define mmCPC_LATENCY_STATS_SELECT_BASE_IDX                                                            1
8430 #define mmCP_DRAW_OBJECT                                                                               0x3810
8431 #define mmCP_DRAW_OBJECT_BASE_IDX                                                                      1
8432 #define mmCP_DRAW_OBJECT_COUNTER                                                                       0x3811
8433 #define mmCP_DRAW_OBJECT_COUNTER_BASE_IDX                                                              1
8434 #define mmCP_DRAW_WINDOW_MASK_HI                                                                       0x3812
8435 #define mmCP_DRAW_WINDOW_MASK_HI_BASE_IDX                                                              1
8436 #define mmCP_DRAW_WINDOW_HI                                                                            0x3813
8437 #define mmCP_DRAW_WINDOW_HI_BASE_IDX                                                                   1
8438 #define mmCP_DRAW_WINDOW_LO                                                                            0x3814
8439 #define mmCP_DRAW_WINDOW_LO_BASE_IDX                                                                   1
8440 #define mmCP_DRAW_WINDOW_CNTL                                                                          0x3815
8441 #define mmCP_DRAW_WINDOW_CNTL_BASE_IDX                                                                 1
8442 #define mmGRBM_PERFCOUNTER0_SELECT                                                                     0x3840
8443 #define mmGRBM_PERFCOUNTER0_SELECT_BASE_IDX                                                            1
8444 #define mmGRBM_PERFCOUNTER1_SELECT                                                                     0x3841
8445 #define mmGRBM_PERFCOUNTER1_SELECT_BASE_IDX                                                            1
8446 #define mmGRBM_SE0_PERFCOUNTER_SELECT                                                                  0x3842
8447 #define mmGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX                                                         1
8448 #define mmGRBM_SE1_PERFCOUNTER_SELECT                                                                  0x3843
8449 #define mmGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX                                                         1
8450 #define mmGRBM_SE2_PERFCOUNTER_SELECT                                                                  0x3844
8451 #define mmGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX                                                         1
8452 #define mmGRBM_SE3_PERFCOUNTER_SELECT                                                                  0x3845
8453 #define mmGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX                                                         1
8454 #define mmGRBM_PERFCOUNTER0_SELECT_HI                                                                  0x384d
8455 #define mmGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX                                                         1
8456 #define mmGRBM_PERFCOUNTER1_SELECT_HI                                                                  0x384e
8457 #define mmGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX                                                         1
8458 #define mmGE1_PERFCOUNTER0_SELECT                                                                      0x38a4
8459 #define mmGE1_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
8460 #define mmGE1_PERFCOUNTER0_SELECT1                                                                     0x38a5
8461 #define mmGE1_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
8462 #define mmGE1_PERFCOUNTER1_SELECT                                                                      0x38a6
8463 #define mmGE1_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
8464 #define mmGE1_PERFCOUNTER1_SELECT1                                                                     0x38a7
8465 #define mmGE1_PERFCOUNTER1_SELECT1_BASE_IDX                                                            1
8466 #define mmGE1_PERFCOUNTER2_SELECT                                                                      0x38a8
8467 #define mmGE1_PERFCOUNTER2_SELECT_BASE_IDX                                                             1
8468 #define mmGE1_PERFCOUNTER2_SELECT1                                                                     0x38a9
8469 #define mmGE1_PERFCOUNTER2_SELECT1_BASE_IDX                                                            1
8470 #define mmGE1_PERFCOUNTER3_SELECT                                                                      0x38aa
8471 #define mmGE1_PERFCOUNTER3_SELECT_BASE_IDX                                                             1
8472 #define mmGE1_PERFCOUNTER3_SELECT1                                                                     0x38ab
8473 #define mmGE1_PERFCOUNTER3_SELECT1_BASE_IDX                                                            1
8474 #define mmGE2_DIST_PERFCOUNTER0_SELECT                                                                 0x38ac
8475 #define mmGE2_DIST_PERFCOUNTER0_SELECT_BASE_IDX                                                        1
8476 #define mmGE2_DIST_PERFCOUNTER0_SELECT1                                                                0x38ad
8477 #define mmGE2_DIST_PERFCOUNTER0_SELECT1_BASE_IDX                                                       1
8478 #define mmGE2_DIST_PERFCOUNTER1_SELECT                                                                 0x38ae
8479 #define mmGE2_DIST_PERFCOUNTER1_SELECT_BASE_IDX                                                        1
8480 #define mmGE2_DIST_PERFCOUNTER1_SELECT1                                                                0x38af
8481 #define mmGE2_DIST_PERFCOUNTER1_SELECT1_BASE_IDX                                                       1
8482 #define mmGE2_DIST_PERFCOUNTER2_SELECT                                                                 0x38b0
8483 #define mmGE2_DIST_PERFCOUNTER2_SELECT_BASE_IDX                                                        1
8484 #define mmGE2_DIST_PERFCOUNTER2_SELECT1                                                                0x38b1
8485 #define mmGE2_DIST_PERFCOUNTER2_SELECT1_BASE_IDX                                                       1
8486 #define mmGE2_DIST_PERFCOUNTER3_SELECT                                                                 0x38b2
8487 #define mmGE2_DIST_PERFCOUNTER3_SELECT_BASE_IDX                                                        1
8488 #define mmGE2_DIST_PERFCOUNTER3_SELECT1                                                                0x38b3
8489 #define mmGE2_DIST_PERFCOUNTER3_SELECT1_BASE_IDX                                                       1
8490 #define mmGE2_SE_PERFCOUNTER0_SELECT                                                                   0x38b4
8491 #define mmGE2_SE_PERFCOUNTER0_SELECT_BASE_IDX                                                          1
8492 #define mmGE2_SE_PERFCOUNTER0_SELECT1                                                                  0x38b5
8493 #define mmGE2_SE_PERFCOUNTER0_SELECT1_BASE_IDX                                                         1
8494 #define mmGE2_SE_PERFCOUNTER1_SELECT                                                                   0x38b6
8495 #define mmGE2_SE_PERFCOUNTER1_SELECT_BASE_IDX                                                          1
8496 #define mmGE2_SE_PERFCOUNTER1_SELECT1                                                                  0x38b7
8497 #define mmGE2_SE_PERFCOUNTER1_SELECT1_BASE_IDX                                                         1
8498 #define mmGE2_SE_PERFCOUNTER2_SELECT                                                                   0x38b8
8499 #define mmGE2_SE_PERFCOUNTER2_SELECT_BASE_IDX                                                          1
8500 #define mmGE2_SE_PERFCOUNTER2_SELECT1                                                                  0x38b9
8501 #define mmGE2_SE_PERFCOUNTER2_SELECT1_BASE_IDX                                                         1
8502 #define mmGE2_SE_PERFCOUNTER3_SELECT                                                                   0x38ba
8503 #define mmGE2_SE_PERFCOUNTER3_SELECT_BASE_IDX                                                          1
8504 #define mmGE2_SE_PERFCOUNTER3_SELECT1                                                                  0x38bb
8505 #define mmGE2_SE_PERFCOUNTER3_SELECT1_BASE_IDX                                                         1
8506 #define mmPA_SU_PERFCOUNTER0_SELECT                                                                    0x3900
8507 #define mmPA_SU_PERFCOUNTER0_SELECT_BASE_IDX                                                           1
8508 #define mmPA_SU_PERFCOUNTER0_SELECT1                                                                   0x3901
8509 #define mmPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX                                                          1
8510 #define mmPA_SU_PERFCOUNTER1_SELECT                                                                    0x3902
8511 #define mmPA_SU_PERFCOUNTER1_SELECT_BASE_IDX                                                           1
8512 #define mmPA_SU_PERFCOUNTER1_SELECT1                                                                   0x3903
8513 #define mmPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX                                                          1
8514 #define mmPA_SU_PERFCOUNTER2_SELECT                                                                    0x3904
8515 #define mmPA_SU_PERFCOUNTER2_SELECT_BASE_IDX                                                           1
8516 #define mmPA_SU_PERFCOUNTER2_SELECT1                                                                   0x3905
8517 #define mmPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX                                                          1
8518 #define mmPA_SU_PERFCOUNTER3_SELECT                                                                    0x3906
8519 #define mmPA_SU_PERFCOUNTER3_SELECT_BASE_IDX                                                           1
8520 #define mmPA_SU_PERFCOUNTER3_SELECT1                                                                   0x3907
8521 #define mmPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX                                                          1
8522 #define mmPA_SC_PERFCOUNTER0_SELECT                                                                    0x3940
8523 #define mmPA_SC_PERFCOUNTER0_SELECT_BASE_IDX                                                           1
8524 #define mmPA_SC_PERFCOUNTER0_SELECT1                                                                   0x3941
8525 #define mmPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX                                                          1
8526 #define mmPA_SC_PERFCOUNTER1_SELECT                                                                    0x3942
8527 #define mmPA_SC_PERFCOUNTER1_SELECT_BASE_IDX                                                           1
8528 #define mmPA_SC_PERFCOUNTER2_SELECT                                                                    0x3943
8529 #define mmPA_SC_PERFCOUNTER2_SELECT_BASE_IDX                                                           1
8530 #define mmPA_SC_PERFCOUNTER3_SELECT                                                                    0x3944
8531 #define mmPA_SC_PERFCOUNTER3_SELECT_BASE_IDX                                                           1
8532 #define mmPA_SC_PERFCOUNTER4_SELECT                                                                    0x3945
8533 #define mmPA_SC_PERFCOUNTER4_SELECT_BASE_IDX                                                           1
8534 #define mmPA_SC_PERFCOUNTER5_SELECT                                                                    0x3946
8535 #define mmPA_SC_PERFCOUNTER5_SELECT_BASE_IDX                                                           1
8536 #define mmPA_SC_PERFCOUNTER6_SELECT                                                                    0x3947
8537 #define mmPA_SC_PERFCOUNTER6_SELECT_BASE_IDX                                                           1
8538 #define mmPA_SC_PERFCOUNTER7_SELECT                                                                    0x3948
8539 #define mmPA_SC_PERFCOUNTER7_SELECT_BASE_IDX                                                           1
8540 #define mmSPI_PERFCOUNTER0_SELECT                                                                      0x3980
8541 #define mmSPI_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
8542 #define mmSPI_PERFCOUNTER1_SELECT                                                                      0x3981
8543 #define mmSPI_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
8544 #define mmSPI_PERFCOUNTER2_SELECT                                                                      0x3982
8545 #define mmSPI_PERFCOUNTER2_SELECT_BASE_IDX                                                             1
8546 #define mmSPI_PERFCOUNTER3_SELECT                                                                      0x3983
8547 #define mmSPI_PERFCOUNTER3_SELECT_BASE_IDX                                                             1
8548 #define mmSPI_PERFCOUNTER0_SELECT1                                                                     0x3984
8549 #define mmSPI_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
8550 #define mmSPI_PERFCOUNTER1_SELECT1                                                                     0x3985
8551 #define mmSPI_PERFCOUNTER1_SELECT1_BASE_IDX                                                            1
8552 #define mmSPI_PERFCOUNTER2_SELECT1                                                                     0x3986
8553 #define mmSPI_PERFCOUNTER2_SELECT1_BASE_IDX                                                            1
8554 #define mmSPI_PERFCOUNTER3_SELECT1                                                                     0x3987
8555 #define mmSPI_PERFCOUNTER3_SELECT1_BASE_IDX                                                            1
8556 #define mmSPI_PERFCOUNTER4_SELECT                                                                      0x3988
8557 #define mmSPI_PERFCOUNTER4_SELECT_BASE_IDX                                                             1
8558 #define mmSPI_PERFCOUNTER5_SELECT                                                                      0x3989
8559 #define mmSPI_PERFCOUNTER5_SELECT_BASE_IDX                                                             1
8560 #define mmSPI_PERFCOUNTER_BINS                                                                         0x398a
8561 #define mmSPI_PERFCOUNTER_BINS_BASE_IDX                                                                1
8562 #define mmSQ_PERFCOUNTER0_SELECT                                                                       0x39c0
8563 #define mmSQ_PERFCOUNTER0_SELECT_BASE_IDX                                                              1
8564 #define mmSQ_PERFCOUNTER1_SELECT                                                                       0x39c1
8565 #define mmSQ_PERFCOUNTER1_SELECT_BASE_IDX                                                              1
8566 #define mmSQ_PERFCOUNTER2_SELECT                                                                       0x39c2
8567 #define mmSQ_PERFCOUNTER2_SELECT_BASE_IDX                                                              1
8568 #define mmSQ_PERFCOUNTER3_SELECT                                                                       0x39c3
8569 #define mmSQ_PERFCOUNTER3_SELECT_BASE_IDX                                                              1
8570 #define mmSQ_PERFCOUNTER4_SELECT                                                                       0x39c4
8571 #define mmSQ_PERFCOUNTER4_SELECT_BASE_IDX                                                              1
8572 #define mmSQ_PERFCOUNTER5_SELECT                                                                       0x39c5
8573 #define mmSQ_PERFCOUNTER5_SELECT_BASE_IDX                                                              1
8574 #define mmSQ_PERFCOUNTER6_SELECT                                                                       0x39c6
8575 #define mmSQ_PERFCOUNTER6_SELECT_BASE_IDX                                                              1
8576 #define mmSQ_PERFCOUNTER7_SELECT                                                                       0x39c7
8577 #define mmSQ_PERFCOUNTER7_SELECT_BASE_IDX                                                              1
8578 #define mmSQ_PERFCOUNTER8_SELECT                                                                       0x39c8
8579 #define mmSQ_PERFCOUNTER8_SELECT_BASE_IDX                                                              1
8580 #define mmSQ_PERFCOUNTER9_SELECT                                                                       0x39c9
8581 #define mmSQ_PERFCOUNTER9_SELECT_BASE_IDX                                                              1
8582 #define mmSQ_PERFCOUNTER10_SELECT                                                                      0x39ca
8583 #define mmSQ_PERFCOUNTER10_SELECT_BASE_IDX                                                             1
8584 #define mmSQ_PERFCOUNTER11_SELECT                                                                      0x39cb
8585 #define mmSQ_PERFCOUNTER11_SELECT_BASE_IDX                                                             1
8586 #define mmSQ_PERFCOUNTER12_SELECT                                                                      0x39cc
8587 #define mmSQ_PERFCOUNTER12_SELECT_BASE_IDX                                                             1
8588 #define mmSQ_PERFCOUNTER13_SELECT                                                                      0x39cd
8589 #define mmSQ_PERFCOUNTER13_SELECT_BASE_IDX                                                             1
8590 #define mmSQ_PERFCOUNTER14_SELECT                                                                      0x39ce
8591 #define mmSQ_PERFCOUNTER14_SELECT_BASE_IDX                                                             1
8592 #define mmSQ_PERFCOUNTER15_SELECT                                                                      0x39cf
8593 #define mmSQ_PERFCOUNTER15_SELECT_BASE_IDX                                                             1
8594 #define mmSQ_PERFCOUNTER_CTRL                                                                          0x39e0
8595 #define mmSQ_PERFCOUNTER_CTRL_BASE_IDX                                                                 1
8596 #define mmSQ_PERFCOUNTER_CTRL2                                                                         0x39e2
8597 #define mmSQ_PERFCOUNTER_CTRL2_BASE_IDX                                                                1
8598 #define mmGCEA_PERFCOUNTER2_SELECT                                                                     0x3a00
8599 #define mmGCEA_PERFCOUNTER2_SELECT_BASE_IDX                                                            1
8600 #define mmGCEA_PERFCOUNTER2_SELECT1                                                                    0x3a01
8601 #define mmGCEA_PERFCOUNTER2_SELECT1_BASE_IDX                                                           1
8602 #define mmGCEA_PERFCOUNTER2_MODE                                                                       0x3a02
8603 #define mmGCEA_PERFCOUNTER2_MODE_BASE_IDX                                                              1
8604 #define mmGCEA_PERFCOUNTER0_CFG                                                                        0x3a03
8605 #define mmGCEA_PERFCOUNTER0_CFG_BASE_IDX                                                               1
8606 #define mmGCEA_PERFCOUNTER1_CFG                                                                        0x3a04
8607 #define mmGCEA_PERFCOUNTER1_CFG_BASE_IDX                                                               1
8608 #define mmGCEA_PERFCOUNTER_RSLT_CNTL                                                                   0x3a05
8609 #define mmGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                          1
8610 #define mmSX_PERFCOUNTER0_SELECT                                                                       0x3a40
8611 #define mmSX_PERFCOUNTER0_SELECT_BASE_IDX                                                              1
8612 #define mmSX_PERFCOUNTER1_SELECT                                                                       0x3a41
8613 #define mmSX_PERFCOUNTER1_SELECT_BASE_IDX                                                              1
8614 #define mmSX_PERFCOUNTER2_SELECT                                                                       0x3a42
8615 #define mmSX_PERFCOUNTER2_SELECT_BASE_IDX                                                              1
8616 #define mmSX_PERFCOUNTER3_SELECT                                                                       0x3a43
8617 #define mmSX_PERFCOUNTER3_SELECT_BASE_IDX                                                              1
8618 #define mmSX_PERFCOUNTER0_SELECT1                                                                      0x3a44
8619 #define mmSX_PERFCOUNTER0_SELECT1_BASE_IDX                                                             1
8620 #define mmSX_PERFCOUNTER1_SELECT1                                                                      0x3a45
8621 #define mmSX_PERFCOUNTER1_SELECT1_BASE_IDX                                                             1
8622 #define mmGDS_PERFCOUNTER0_SELECT                                                                      0x3a80
8623 #define mmGDS_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
8624 #define mmGDS_PERFCOUNTER1_SELECT                                                                      0x3a81
8625 #define mmGDS_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
8626 #define mmGDS_PERFCOUNTER2_SELECT                                                                      0x3a82
8627 #define mmGDS_PERFCOUNTER2_SELECT_BASE_IDX                                                             1
8628 #define mmGDS_PERFCOUNTER3_SELECT                                                                      0x3a83
8629 #define mmGDS_PERFCOUNTER3_SELECT_BASE_IDX                                                             1
8630 #define mmGDS_PERFCOUNTER0_SELECT1                                                                     0x3a84
8631 #define mmGDS_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
8632 #define mmGDS_PERFCOUNTER1_SELECT1                                                                     0x3a85
8633 #define mmGDS_PERFCOUNTER1_SELECT1_BASE_IDX                                                            1
8634 #define mmGDS_PERFCOUNTER2_SELECT1                                                                     0x3a86
8635 #define mmGDS_PERFCOUNTER2_SELECT1_BASE_IDX                                                            1
8636 #define mmGDS_PERFCOUNTER3_SELECT1                                                                     0x3a87
8637 #define mmGDS_PERFCOUNTER3_SELECT1_BASE_IDX                                                            1
8638 #define mmTA_PERFCOUNTER0_SELECT                                                                       0x3ac0
8639 #define mmTA_PERFCOUNTER0_SELECT_BASE_IDX                                                              1
8640 #define mmTA_PERFCOUNTER0_SELECT1                                                                      0x3ac1
8641 #define mmTA_PERFCOUNTER0_SELECT1_BASE_IDX                                                             1
8642 #define mmTA_PERFCOUNTER1_SELECT                                                                       0x3ac2
8643 #define mmTA_PERFCOUNTER1_SELECT_BASE_IDX                                                              1
8644 #define mmTD_PERFCOUNTER0_SELECT                                                                       0x3b00
8645 #define mmTD_PERFCOUNTER0_SELECT_BASE_IDX                                                              1
8646 #define mmTD_PERFCOUNTER0_SELECT1                                                                      0x3b01
8647 #define mmTD_PERFCOUNTER0_SELECT1_BASE_IDX                                                             1
8648 #define mmTD_PERFCOUNTER1_SELECT                                                                       0x3b02
8649 #define mmTD_PERFCOUNTER1_SELECT_BASE_IDX                                                              1
8650 #define mmTCP_PERFCOUNTER0_SELECT                                                                      0x3b40
8651 #define mmTCP_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
8652 #define mmTCP_PERFCOUNTER0_SELECT1                                                                     0x3b41
8653 #define mmTCP_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
8654 #define mmTCP_PERFCOUNTER1_SELECT                                                                      0x3b42
8655 #define mmTCP_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
8656 #define mmTCP_PERFCOUNTER1_SELECT1                                                                     0x3b43
8657 #define mmTCP_PERFCOUNTER1_SELECT1_BASE_IDX                                                            1
8658 #define mmTCP_PERFCOUNTER2_SELECT                                                                      0x3b44
8659 #define mmTCP_PERFCOUNTER2_SELECT_BASE_IDX                                                             1
8660 #define mmTCP_PERFCOUNTER3_SELECT                                                                      0x3b45
8661 #define mmTCP_PERFCOUNTER3_SELECT_BASE_IDX                                                             1
8662 #define mmGL2C_PERFCOUNTER0_SELECT                                                                     0x3b80
8663 #define mmGL2C_PERFCOUNTER0_SELECT_BASE_IDX                                                            1
8664 #define mmGL2C_PERFCOUNTER0_SELECT1                                                                    0x3b81
8665 #define mmGL2C_PERFCOUNTER0_SELECT1_BASE_IDX                                                           1
8666 #define mmGL2C_PERFCOUNTER1_SELECT                                                                     0x3b82
8667 #define mmGL2C_PERFCOUNTER1_SELECT_BASE_IDX                                                            1
8668 #define mmGL2C_PERFCOUNTER1_SELECT1                                                                    0x3b83
8669 #define mmGL2C_PERFCOUNTER1_SELECT1_BASE_IDX                                                           1
8670 #define mmGL2C_PERFCOUNTER2_SELECT                                                                     0x3b84
8671 #define mmGL2C_PERFCOUNTER2_SELECT_BASE_IDX                                                            1
8672 #define mmGL2C_PERFCOUNTER3_SELECT                                                                     0x3b85
8673 #define mmGL2C_PERFCOUNTER3_SELECT_BASE_IDX                                                            1
8674 #define mmGL2A_PERFCOUNTER0_SELECT                                                                     0x3b90
8675 #define mmGL2A_PERFCOUNTER0_SELECT_BASE_IDX                                                            1
8676 #define mmGL2A_PERFCOUNTER0_SELECT1                                                                    0x3b91
8677 #define mmGL2A_PERFCOUNTER0_SELECT1_BASE_IDX                                                           1
8678 #define mmGL2A_PERFCOUNTER1_SELECT                                                                     0x3b92
8679 #define mmGL2A_PERFCOUNTER1_SELECT_BASE_IDX                                                            1
8680 #define mmGL2A_PERFCOUNTER1_SELECT1                                                                    0x3b93
8681 #define mmGL2A_PERFCOUNTER1_SELECT1_BASE_IDX                                                           1
8682 #define mmGL2A_PERFCOUNTER2_SELECT                                                                     0x3b94
8683 #define mmGL2A_PERFCOUNTER2_SELECT_BASE_IDX                                                            1
8684 #define mmGL2A_PERFCOUNTER3_SELECT                                                                     0x3b95
8685 #define mmGL2A_PERFCOUNTER3_SELECT_BASE_IDX                                                            1
8686 #define mmGL1C_PERFCOUNTER0_SELECT                                                                     0x3ba0
8687 #define mmGL1C_PERFCOUNTER0_SELECT_BASE_IDX                                                            1
8688 #define mmGL1C_PERFCOUNTER0_SELECT1                                                                    0x3ba1
8689 #define mmGL1C_PERFCOUNTER0_SELECT1_BASE_IDX                                                           1
8690 #define mmGL1C_PERFCOUNTER1_SELECT                                                                     0x3ba2
8691 #define mmGL1C_PERFCOUNTER1_SELECT_BASE_IDX                                                            1
8692 #define mmGL1C_PERFCOUNTER2_SELECT                                                                     0x3ba3
8693 #define mmGL1C_PERFCOUNTER2_SELECT_BASE_IDX                                                            1
8694 #define mmGL1C_PERFCOUNTER3_SELECT                                                                     0x3ba4
8695 #define mmGL1C_PERFCOUNTER3_SELECT_BASE_IDX                                                            1
8696 #define mmCHC_PERFCOUNTER0_SELECT                                                                      0x3bc0
8697 #define mmCHC_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
8698 #define mmCHC_PERFCOUNTER0_SELECT1                                                                     0x3bc1
8699 #define mmCHC_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
8700 #define mmCHC_PERFCOUNTER1_SELECT                                                                      0x3bc2
8701 #define mmCHC_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
8702 #define mmCHC_PERFCOUNTER2_SELECT                                                                      0x3bc3
8703 #define mmCHC_PERFCOUNTER2_SELECT_BASE_IDX                                                             1
8704 #define mmCHC_PERFCOUNTER3_SELECT                                                                      0x3bc4
8705 #define mmCHC_PERFCOUNTER3_SELECT_BASE_IDX                                                             1
8706 #define mmCHCG_PERFCOUNTER0_SELECT                                                                     0x3bc6
8707 #define mmCHCG_PERFCOUNTER0_SELECT_BASE_IDX                                                            1
8708 #define mmCHCG_PERFCOUNTER0_SELECT1                                                                    0x3bc7
8709 #define mmCHCG_PERFCOUNTER0_SELECT1_BASE_IDX                                                           1
8710 #define mmCHCG_PERFCOUNTER1_SELECT                                                                     0x3bc8
8711 #define mmCHCG_PERFCOUNTER1_SELECT_BASE_IDX                                                            1
8712 #define mmCHCG_PERFCOUNTER2_SELECT                                                                     0x3bc9
8713 #define mmCHCG_PERFCOUNTER2_SELECT_BASE_IDX                                                            1
8714 #define mmCHCG_PERFCOUNTER3_SELECT                                                                     0x3bca
8715 #define mmCHCG_PERFCOUNTER3_SELECT_BASE_IDX                                                            1
8716 #define mmCB_PERFCOUNTER_FILTER                                                                        0x3c00
8717 #define mmCB_PERFCOUNTER_FILTER_BASE_IDX                                                               1
8718 #define mmCB_PERFCOUNTER0_SELECT                                                                       0x3c01
8719 #define mmCB_PERFCOUNTER0_SELECT_BASE_IDX                                                              1
8720 #define mmCB_PERFCOUNTER0_SELECT1                                                                      0x3c02
8721 #define mmCB_PERFCOUNTER0_SELECT1_BASE_IDX                                                             1
8722 #define mmCB_PERFCOUNTER1_SELECT                                                                       0x3c03
8723 #define mmCB_PERFCOUNTER1_SELECT_BASE_IDX                                                              1
8724 #define mmCB_PERFCOUNTER2_SELECT                                                                       0x3c04
8725 #define mmCB_PERFCOUNTER2_SELECT_BASE_IDX                                                              1
8726 #define mmCB_PERFCOUNTER3_SELECT                                                                       0x3c05
8727 #define mmCB_PERFCOUNTER3_SELECT_BASE_IDX                                                              1
8728 #define mmDB_PERFCOUNTER0_SELECT                                                                       0x3c40
8729 #define mmDB_PERFCOUNTER0_SELECT_BASE_IDX                                                              1
8730 #define mmDB_PERFCOUNTER0_SELECT1                                                                      0x3c41
8731 #define mmDB_PERFCOUNTER0_SELECT1_BASE_IDX                                                             1
8732 #define mmDB_PERFCOUNTER1_SELECT                                                                       0x3c42
8733 #define mmDB_PERFCOUNTER1_SELECT_BASE_IDX                                                              1
8734 #define mmDB_PERFCOUNTER1_SELECT1                                                                      0x3c43
8735 #define mmDB_PERFCOUNTER1_SELECT1_BASE_IDX                                                             1
8736 #define mmDB_PERFCOUNTER2_SELECT                                                                       0x3c44
8737 #define mmDB_PERFCOUNTER2_SELECT_BASE_IDX                                                              1
8738 #define mmDB_PERFCOUNTER3_SELECT                                                                       0x3c46
8739 #define mmDB_PERFCOUNTER3_SELECT_BASE_IDX                                                              1
8740 #define mmRLC_SPM_PERFMON_CNTL                                                                         0x3c80
8741 #define mmRLC_SPM_PERFMON_CNTL_BASE_IDX                                                                1
8742 #define mmRLC_SPM_PERFMON_RING_BASE_LO                                                                 0x3c81
8743 #define mmRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX                                                        1
8744 #define mmRLC_SPM_PERFMON_RING_BASE_HI                                                                 0x3c82
8745 #define mmRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX                                                        1
8746 #define mmRLC_SPM_PERFMON_RING_SIZE                                                                    0x3c83
8747 #define mmRLC_SPM_PERFMON_RING_SIZE_BASE_IDX                                                           1
8748 #define mmRLC_SPM_PERFMON_SEGMENT_SIZE                                                                 0x3c84
8749 #define mmRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX                                                        1
8750 #define mmRLC_SPM_RING_RDPTR                                                                           0x3c85
8751 #define mmRLC_SPM_RING_RDPTR_BASE_IDX                                                                  1
8752 #define mmRLC_SPM_SEGMENT_THRESHOLD                                                                    0x3c86
8753 #define mmRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX                                                           1
8754 #define mmRLC_SPM_SE_MUXSEL_ADDR                                                                       0x3c87
8755 #define mmRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX                                                              1
8756 #define mmRLC_SPM_SE_MUXSEL_DATA                                                                       0x3c88
8757 #define mmRLC_SPM_SE_MUXSEL_DATA_BASE_IDX                                                              1
8758 #define mmRLC_SPM_GLOBAL_MUXSEL_ADDR                                                                   0x3c89
8759 #define mmRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX                                                          1
8760 #define mmRLC_SPM_GLOBAL_MUXSEL_DATA                                                                   0x3c8a
8761 #define mmRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX                                                          1
8762 #define mmRLC_SPM_DESER_START_SKEW                                                                     0x3c8b
8763 #define mmRLC_SPM_DESER_START_SKEW_BASE_IDX                                                            1
8764 #define mmRLC_SPM_GLOBALS_SAMPLE_SKEW                                                                  0x3c8c
8765 #define mmRLC_SPM_GLOBALS_SAMPLE_SKEW_BASE_IDX                                                         1
8766 #define mmRLC_SPM_GLOBALS_MUXSEL_SKEW                                                                  0x3c8d
8767 #define mmRLC_SPM_GLOBALS_MUXSEL_SKEW_BASE_IDX                                                         1
8768 #define mmRLC_SPM_SE_SAMPLE_SKEW                                                                       0x3c8e
8769 #define mmRLC_SPM_SE_SAMPLE_SKEW_BASE_IDX                                                              1
8770 #define mmRLC_SPM_SE_MUXSEL_SKEW                                                                       0x3c8f
8771 #define mmRLC_SPM_SE_MUXSEL_SKEW_BASE_IDX                                                              1
8772 #define mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR                                                             0x3c90
8773 #define mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR_BASE_IDX                                                    1
8774 #define mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA                                                             0x3c91
8775 #define mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA_BASE_IDX                                                    1
8776 #define mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR                                                              0x3c92
8777 #define mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR_BASE_IDX                                                     1
8778 #define mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA                                                              0x3c93
8779 #define mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA_BASE_IDX                                                     1
8780 #define mmRLC_SPM_RING_WRPTR                                                                           0x3c94
8781 #define mmRLC_SPM_RING_WRPTR_BASE_IDX                                                                  1
8782 #define mmRLC_SPM_ACCUM_DATARAM_ADDR                                                                   0x3c95
8783 #define mmRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX                                                          1
8784 #define mmRLC_SPM_ACCUM_DATARAM_DATA                                                                   0x3c96
8785 #define mmRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX                                                          1
8786 #define mmRLC_SPM_ACCUM_CTRLRAM_ADDR                                                                   0x3c97
8787 #define mmRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX                                                          1
8788 #define mmRLC_SPM_ACCUM_CTRLRAM_DATA                                                                   0x3c98
8789 #define mmRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX                                                          1
8790 #define mmRLC_SPM_ACCUM_STATUS                                                                         0x3c99
8791 #define mmRLC_SPM_ACCUM_STATUS_BASE_IDX                                                                1
8792 #define mmRLC_SPM_ACCUM_CTRL                                                                           0x3c9a
8793 #define mmRLC_SPM_ACCUM_CTRL_BASE_IDX                                                                  1
8794 #define mmRLC_SPM_ACCUM_MODE                                                                           0x3c9b
8795 #define mmRLC_SPM_ACCUM_MODE_BASE_IDX                                                                  1
8796 #define mmRLC_SPM_ACCUM_THRESHOLD                                                                      0x3c9c
8797 #define mmRLC_SPM_ACCUM_THRESHOLD_BASE_IDX                                                             1
8798 #define mmRLC_SPM_ACCUM_SAMPLES_REQUESTED                                                              0x3c9d
8799 #define mmRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX                                                     1
8800 #define mmRLC_SPM_ACCUM_DATARAM_WRCOUNT                                                                0x3c9e
8801 #define mmRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX                                                       1
8802 #define mmRLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE                                                          0x3c9f
8803 #define mmRLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE_BASE_IDX                                                 1
8804 #define mmRLC_SPM_PERFMON_GLB_SEGMENT_SIZE                                                             0x3ca0
8805 #define mmRLC_SPM_PERFMON_GLB_SEGMENT_SIZE_BASE_IDX                                                    1
8806 #define mmRLC_SPM_VIRT_CTRL                                                                            0x3ca1
8807 #define mmRLC_SPM_VIRT_CTRL_BASE_IDX                                                                   1
8808 #define mmRLC_SPM_PERFMON_SWA_SEGMENT_SIZE                                                             0x3ca2
8809 #define mmRLC_SPM_PERFMON_SWA_SEGMENT_SIZE_BASE_IDX                                                    1
8810 #define mmRLC_SPM_VIRT_STATUS                                                                          0x3ca3
8811 #define mmRLC_SPM_VIRT_STATUS_BASE_IDX                                                                 1
8812 #define mmRLC_SPM_GFXCLOCK_HIGHCOUNT                                                                   0x3ca4
8813 #define mmRLC_SPM_GFXCLOCK_HIGHCOUNT_BASE_IDX                                                          1
8814 #define mmRLC_SPM_GFXCLOCK_LOWCOUNT                                                                    0x3ca5
8815 #define mmRLC_SPM_GFXCLOCK_LOWCOUNT_BASE_IDX                                                           1
8816 #define mmRLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE                                                      0x3ca6
8817 #define mmRLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE_BASE_IDX                                             1
8818 #define mmRLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET                                                            0x3ca7
8819 #define mmRLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET_BASE_IDX                                                   1
8820 #define mmRLC_SPM_SE_MUXSEL_ADDR_OFFSET                                                                0x3ca8
8821 #define mmRLC_SPM_SE_MUXSEL_ADDR_OFFSET_BASE_IDX                                                       1
8822 #define mmRLC_SPM_ACCUM_SWA_DATARAM_ADDR                                                               0x3ca9
8823 #define mmRLC_SPM_ACCUM_SWA_DATARAM_ADDR_BASE_IDX                                                      1
8824 #define mmRLC_SPM_ACCUM_SWA_DATARAM_DATA                                                               0x3caa
8825 #define mmRLC_SPM_ACCUM_SWA_DATARAM_DATA_BASE_IDX                                                      1
8826 #define mmRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET                                                            0x3cab
8827 #define mmRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET_BASE_IDX                                                   1
8828 #define mmRLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE                                                         0x3cac
8829 #define mmRLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE_BASE_IDX                                                1
8830 #define mmRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS                                                     0x3cad
8831 #define mmRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS_BASE_IDX                                            1
8832 #define mmRLC_PERFMON_CNTL                                                                             0x3cc0
8833 #define mmRLC_PERFMON_CNTL_BASE_IDX                                                                    1
8834 #define mmRLC_PERFCOUNTER0_SELECT                                                                      0x3cc1
8835 #define mmRLC_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
8836 #define mmRLC_PERFCOUNTER1_SELECT                                                                      0x3cc2
8837 #define mmRLC_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
8838 #define mmRLC_GPU_IOV_PERF_CNT_CNTL                                                                    0x3cc3
8839 #define mmRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX                                                           1
8840 #define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR                                                                 0x3cc4
8841 #define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX                                                        1
8842 #define mmRLC_GPU_IOV_PERF_CNT_WR_DATA                                                                 0x3cc5
8843 #define mmRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX                                                        1
8844 #define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR                                                                 0x3cc6
8845 #define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX                                                        1
8846 #define mmRLC_GPU_IOV_PERF_CNT_RD_DATA                                                                 0x3cc7
8847 #define mmRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX                                                        1
8848 #define mmRLC_PERFMON_CLK_CNTL                                                                         0x3ce4
8849 #define mmRLC_PERFMON_CLK_CNTL_BASE_IDX                                                                1
8850 #define mmRMI_PERFCOUNTER0_SELECT                                                                      0x3d00
8851 #define mmRMI_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
8852 #define mmRMI_PERFCOUNTER0_SELECT1                                                                     0x3d01
8853 #define mmRMI_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
8854 #define mmRMI_PERFCOUNTER1_SELECT                                                                      0x3d02
8855 #define mmRMI_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
8856 #define mmRMI_PERFCOUNTER2_SELECT                                                                      0x3d03
8857 #define mmRMI_PERFCOUNTER2_SELECT_BASE_IDX                                                             1
8858 #define mmRMI_PERFCOUNTER2_SELECT1                                                                     0x3d04
8859 #define mmRMI_PERFCOUNTER2_SELECT1_BASE_IDX                                                            1
8860 #define mmRMI_PERFCOUNTER3_SELECT                                                                      0x3d05
8861 #define mmRMI_PERFCOUNTER3_SELECT_BASE_IDX                                                             1
8862 #define mmRMI_PERF_COUNTER_CNTL                                                                        0x3d06
8863 #define mmRMI_PERF_COUNTER_CNTL_BASE_IDX                                                               1
8864 #define mmGCR_PERFCOUNTER0_SELECT                                                                      0x3d60
8865 #define mmGCR_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
8866 #define mmGCR_PERFCOUNTER0_SELECT1                                                                     0x3d61
8867 #define mmGCR_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
8868 #define mmGCR_PERFCOUNTER1_SELECT                                                                      0x3d62
8869 #define mmGCR_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
8870 #define mmUTCL1_PERFCOUNTER0_SELECT                                                                    0x3d63
8871 #define mmUTCL1_PERFCOUNTER0_SELECT_BASE_IDX                                                           1
8872 #define mmUTCL1_PERFCOUNTER1_SELECT                                                                    0x3d64
8873 #define mmUTCL1_PERFCOUNTER1_SELECT_BASE_IDX                                                           1
8874 #define mmPA_PH_PERFCOUNTER0_SELECT                                                                    0x3d80
8875 #define mmPA_PH_PERFCOUNTER0_SELECT_BASE_IDX                                                           1
8876 #define mmPA_PH_PERFCOUNTER0_SELECT1                                                                   0x3d81
8877 #define mmPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX                                                          1
8878 #define mmPA_PH_PERFCOUNTER1_SELECT                                                                    0x3d82
8879 #define mmPA_PH_PERFCOUNTER1_SELECT_BASE_IDX                                                           1
8880 #define mmPA_PH_PERFCOUNTER2_SELECT                                                                    0x3d83
8881 #define mmPA_PH_PERFCOUNTER2_SELECT_BASE_IDX                                                           1
8882 #define mmPA_PH_PERFCOUNTER3_SELECT                                                                    0x3d84
8883 #define mmPA_PH_PERFCOUNTER3_SELECT_BASE_IDX                                                           1
8884 #define mmPA_PH_PERFCOUNTER4_SELECT                                                                    0x3d85
8885 #define mmPA_PH_PERFCOUNTER4_SELECT_BASE_IDX                                                           1
8886 #define mmPA_PH_PERFCOUNTER5_SELECT                                                                    0x3d86
8887 #define mmPA_PH_PERFCOUNTER5_SELECT_BASE_IDX                                                           1
8888 #define mmPA_PH_PERFCOUNTER6_SELECT                                                                    0x3d87
8889 #define mmPA_PH_PERFCOUNTER6_SELECT_BASE_IDX                                                           1
8890 #define mmPA_PH_PERFCOUNTER7_SELECT                                                                    0x3d88
8891 #define mmPA_PH_PERFCOUNTER7_SELECT_BASE_IDX                                                           1
8892 #define mmPA_PH_PERFCOUNTER1_SELECT1                                                                   0x3d90
8893 #define mmPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX                                                          1
8894 #define mmPA_PH_PERFCOUNTER2_SELECT1                                                                   0x3d91
8895 #define mmPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX                                                          1
8896 #define mmPA_PH_PERFCOUNTER3_SELECT1                                                                   0x3d92
8897 #define mmPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX                                                          1
8898 #define mmGL1A_PERFCOUNTER0_SELECT                                                                     0x3dc0
8899 #define mmGL1A_PERFCOUNTER0_SELECT_BASE_IDX                                                            1
8900 #define mmGL1A_PERFCOUNTER0_SELECT1                                                                    0x3dc1
8901 #define mmGL1A_PERFCOUNTER0_SELECT1_BASE_IDX                                                           1
8902 #define mmGL1A_PERFCOUNTER1_SELECT                                                                     0x3dc2
8903 #define mmGL1A_PERFCOUNTER1_SELECT_BASE_IDX                                                            1
8904 #define mmGL1A_PERFCOUNTER2_SELECT                                                                     0x3dc3
8905 #define mmGL1A_PERFCOUNTER2_SELECT_BASE_IDX                                                            1
8906 #define mmGL1A_PERFCOUNTER3_SELECT                                                                     0x3dc4
8907 #define mmGL1A_PERFCOUNTER3_SELECT_BASE_IDX                                                            1
8908 #define mmCHA_PERFCOUNTER0_SELECT                                                                      0x3de0
8909 #define mmCHA_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
8910 #define mmCHA_PERFCOUNTER0_SELECT1                                                                     0x3de1
8911 #define mmCHA_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
8912 #define mmCHA_PERFCOUNTER1_SELECT                                                                      0x3de2
8913 #define mmCHA_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
8914 #define mmCHA_PERFCOUNTER2_SELECT                                                                      0x3de3
8915 #define mmCHA_PERFCOUNTER2_SELECT_BASE_IDX                                                             1
8916 #define mmCHA_PERFCOUNTER3_SELECT                                                                      0x3de4
8917 #define mmCHA_PERFCOUNTER3_SELECT_BASE_IDX                                                             1
8918 #define mmGUS_PERFCOUNTER2_SELECT                                                                      0x3e00
8919 #define mmGUS_PERFCOUNTER2_SELECT_BASE_IDX                                                             1
8920 #define mmGUS_PERFCOUNTER2_SELECT1                                                                     0x3e01
8921 #define mmGUS_PERFCOUNTER2_SELECT1_BASE_IDX                                                            1
8922 #define mmGUS_PERFCOUNTER2_MODE                                                                        0x3e02
8923 #define mmGUS_PERFCOUNTER2_MODE_BASE_IDX                                                               1
8924 #define mmGUS_PERFCOUNTER0_CFG                                                                         0x3e03
8925 #define mmGUS_PERFCOUNTER0_CFG_BASE_IDX                                                                1
8926 #define mmGUS_PERFCOUNTER1_CFG                                                                         0x3e04
8927 #define mmGUS_PERFCOUNTER1_CFG_BASE_IDX                                                                1
8928 #define mmGUS_PERFCOUNTER_RSLT_CNTL                                                                    0x3e05
8929 #define mmGUS_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                           1
8930 
8931 
8932 // addressBlock: gc_gcvml2pldec
8933 // base address: 0x374b0
8934 #define mmGCMC_VM_L2_PERFCOUNTER0_CFG                                                                  0x3d2c
8935 #define mmGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX                                                         1
8936 #define mmGCMC_VM_L2_PERFCOUNTER1_CFG                                                                  0x3d2d
8937 #define mmGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX                                                         1
8938 #define mmGCMC_VM_L2_PERFCOUNTER2_CFG                                                                  0x3d2e
8939 #define mmGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX                                                         1
8940 #define mmGCMC_VM_L2_PERFCOUNTER3_CFG                                                                  0x3d2f
8941 #define mmGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX                                                         1
8942 #define mmGCMC_VM_L2_PERFCOUNTER4_CFG                                                                  0x3d30
8943 #define mmGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX                                                         1
8944 #define mmGCMC_VM_L2_PERFCOUNTER5_CFG                                                                  0x3d31
8945 #define mmGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX                                                         1
8946 #define mmGCMC_VM_L2_PERFCOUNTER6_CFG                                                                  0x3d32
8947 #define mmGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX                                                         1
8948 #define mmGCMC_VM_L2_PERFCOUNTER7_CFG                                                                  0x3d33
8949 #define mmGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX                                                         1
8950 #define mmGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL                                                             0x3d34
8951 #define mmGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                    1
8952 #define mmGCUTCL2_PERFCOUNTER0_CFG                                                                     0x3d35
8953 #define mmGCUTCL2_PERFCOUNTER0_CFG_BASE_IDX                                                            1
8954 #define mmGCUTCL2_PERFCOUNTER1_CFG                                                                     0x3d36
8955 #define mmGCUTCL2_PERFCOUNTER1_CFG_BASE_IDX                                                            1
8956 #define mmGCUTCL2_PERFCOUNTER2_CFG                                                                     0x3d37
8957 #define mmGCUTCL2_PERFCOUNTER2_CFG_BASE_IDX                                                            1
8958 #define mmGCUTCL2_PERFCOUNTER3_CFG                                                                     0x3d38
8959 #define mmGCUTCL2_PERFCOUNTER3_CFG_BASE_IDX                                                            1
8960 #define mmGCUTCL2_PERFCOUNTER_RSLT_CNTL                                                                0x3d39
8961 #define mmGCUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                       1
8962 
8963 
8964 // addressBlock: gc_gcvml2perfsdec
8965 // base address: 0x374f0
8966 #define mmGCVML2_PERFCOUNTER2_0_SELECT                                                                 0x3d3c
8967 #define mmGCVML2_PERFCOUNTER2_0_SELECT_BASE_IDX                                                        1
8968 #define mmGCVML2_PERFCOUNTER2_1_SELECT                                                                 0x3d3d
8969 #define mmGCVML2_PERFCOUNTER2_1_SELECT_BASE_IDX                                                        1
8970 #define mmGCVML2_PERFCOUNTER2_0_SELECT1                                                                0x3d3e
8971 #define mmGCVML2_PERFCOUNTER2_0_SELECT1_BASE_IDX                                                       1
8972 #define mmGCVML2_PERFCOUNTER2_1_SELECT1                                                                0x3d3f
8973 #define mmGCVML2_PERFCOUNTER2_1_SELECT1_BASE_IDX                                                       1
8974 #define mmGCVML2_PERFCOUNTER2_0_MODE                                                                   0x3d40
8975 #define mmGCVML2_PERFCOUNTER2_0_MODE_BASE_IDX                                                          1
8976 #define mmGCVML2_PERFCOUNTER2_1_MODE                                                                   0x3d41
8977 #define mmGCVML2_PERFCOUNTER2_1_MODE_BASE_IDX                                                          1
8978 
8979 
8980 // addressBlock: gc_sdma0_sdma0perfsdec
8981 // base address: 0x37880
8982 #define mmSDMA0_PERFCNT_PERFCOUNTER0_CFG                                                               0x3e20
8983 #define mmSDMA0_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX                                                      1
8984 #define mmSDMA0_PERFCNT_PERFCOUNTER1_CFG                                                               0x3e21
8985 #define mmSDMA0_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX                                                      1
8986 #define mmSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL                                                          0x3e22
8987 #define mmSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                 1
8988 #define mmSDMA0_PERFCNT_MISC_CNTL                                                                      0x3e23
8989 #define mmSDMA0_PERFCNT_MISC_CNTL_BASE_IDX                                                             1
8990 #define mmSDMA0_PERFCOUNTER0_SELECT                                                                    0x3e24
8991 #define mmSDMA0_PERFCOUNTER0_SELECT_BASE_IDX                                                           1
8992 #define mmSDMA0_PERFCOUNTER0_SELECT1                                                                   0x3e25
8993 #define mmSDMA0_PERFCOUNTER0_SELECT1_BASE_IDX                                                          1
8994 #define mmSDMA0_PERFCOUNTER1_SELECT                                                                    0x3e26
8995 #define mmSDMA0_PERFCOUNTER1_SELECT_BASE_IDX                                                           1
8996 #define mmSDMA0_PERFCOUNTER1_SELECT1                                                                   0x3e27
8997 #define mmSDMA0_PERFCOUNTER1_SELECT1_BASE_IDX                                                          1
8998 
8999 
9000 // addressBlock: gc_sdma1_sdma1perfsdec
9001 // base address: 0x378b0
9002 #define mmSDMA1_PERFCNT_PERFCOUNTER0_CFG                                                               0x3e2c
9003 #define mmSDMA1_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX                                                      1
9004 #define mmSDMA1_PERFCNT_PERFCOUNTER1_CFG                                                               0x3e2d
9005 #define mmSDMA1_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX                                                      1
9006 #define mmSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL                                                          0x3e2e
9007 #define mmSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                 1
9008 #define mmSDMA1_PERFCNT_MISC_CNTL                                                                      0x3e2f
9009 #define mmSDMA1_PERFCNT_MISC_CNTL_BASE_IDX                                                             1
9010 #define mmSDMA1_PERFCOUNTER0_SELECT                                                                    0x3e30
9011 #define mmSDMA1_PERFCOUNTER0_SELECT_BASE_IDX                                                           1
9012 #define mmSDMA1_PERFCOUNTER0_SELECT1                                                                   0x3e31
9013 #define mmSDMA1_PERFCOUNTER0_SELECT1_BASE_IDX                                                          1
9014 #define mmSDMA1_PERFCOUNTER1_SELECT                                                                    0x3e32
9015 #define mmSDMA1_PERFCOUNTER1_SELECT_BASE_IDX                                                           1
9016 #define mmSDMA1_PERFCOUNTER1_SELECT1                                                                   0x3e33
9017 #define mmSDMA1_PERFCOUNTER1_SELECT1_BASE_IDX                                                          1
9018 
9019 
9020 // addressBlock: gc_sdma2_sdma2perfsdec
9021 // base address: 0x378e0
9022 #define mmSDMA2_PERFCNT_PERFCOUNTER0_CFG                                                               0x3e38
9023 #define mmSDMA2_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX                                                      1
9024 #define mmSDMA2_PERFCNT_PERFCOUNTER1_CFG                                                               0x3e39
9025 #define mmSDMA2_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX                                                      1
9026 #define mmSDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL                                                          0x3e3a
9027 #define mmSDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                 1
9028 #define mmSDMA2_PERFCNT_MISC_CNTL                                                                      0x3e3b
9029 #define mmSDMA2_PERFCNT_MISC_CNTL_BASE_IDX                                                             1
9030 #define mmSDMA2_PERFCOUNTER0_SELECT                                                                    0x3e3c
9031 #define mmSDMA2_PERFCOUNTER0_SELECT_BASE_IDX                                                           1
9032 #define mmSDMA2_PERFCOUNTER0_SELECT1                                                                   0x3e3d
9033 #define mmSDMA2_PERFCOUNTER0_SELECT1_BASE_IDX                                                          1
9034 #define mmSDMA2_PERFCOUNTER1_SELECT                                                                    0x3e3e
9035 #define mmSDMA2_PERFCOUNTER1_SELECT_BASE_IDX                                                           1
9036 #define mmSDMA2_PERFCOUNTER1_SELECT1                                                                   0x3e3f
9037 #define mmSDMA2_PERFCOUNTER1_SELECT1_BASE_IDX                                                          1
9038 
9039 
9040 // addressBlock: gc_sdma3_sdma3perfsdec
9041 // base address: 0x37910
9042 #define mmSDMA3_PERFCNT_PERFCOUNTER0_CFG                                                               0x3e44
9043 #define mmSDMA3_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX                                                      1
9044 #define mmSDMA3_PERFCNT_PERFCOUNTER1_CFG                                                               0x3e45
9045 #define mmSDMA3_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX                                                      1
9046 #define mmSDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL                                                          0x3e46
9047 #define mmSDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                 1
9048 #define mmSDMA3_PERFCNT_MISC_CNTL                                                                      0x3e47
9049 #define mmSDMA3_PERFCNT_MISC_CNTL_BASE_IDX                                                             1
9050 #define mmSDMA3_PERFCOUNTER0_SELECT                                                                    0x3e48
9051 #define mmSDMA3_PERFCOUNTER0_SELECT_BASE_IDX                                                           1
9052 #define mmSDMA3_PERFCOUNTER0_SELECT1                                                                   0x3e49
9053 #define mmSDMA3_PERFCOUNTER0_SELECT1_BASE_IDX                                                          1
9054 #define mmSDMA3_PERFCOUNTER1_SELECT                                                                    0x3e4a
9055 #define mmSDMA3_PERFCOUNTER1_SELECT_BASE_IDX                                                           1
9056 #define mmSDMA3_PERFCOUNTER1_SELECT1                                                                   0x3e4b
9057 #define mmSDMA3_PERFCOUNTER1_SELECT1_BASE_IDX                                                          1
9058 
9059 
9060 // base address: 0x3a000
9061 
9062 
9063 // addressBlock: gc_grtavfsdec
9064 // base address: 0x3ac00
9065 #define mmGRTAVFS_RTAVFS_REG_ADDR                                                                      0x4b00
9066 #define mmGRTAVFS_RTAVFS_REG_ADDR_BASE_IDX                                                             1
9067 #define mmRTAVFS_RTAVFS_REG_ADDR                                                                       0x4b00
9068 #define mmRTAVFS_RTAVFS_REG_ADDR_BASE_IDX                                                              1
9069 #define mmGRTAVFS_RTAVFS_WR_DATA                                                                       0x4b01
9070 #define mmGRTAVFS_RTAVFS_WR_DATA_BASE_IDX                                                              1
9071 #define mmRTAVFS_RTAVFS_WR_DATA                                                                        0x4b01
9072 #define mmRTAVFS_RTAVFS_WR_DATA_BASE_IDX                                                               1
9073 #define mmGRTAVFS_GENERAL_0                                                                            0x4b02
9074 #define mmGRTAVFS_GENERAL_0_BASE_IDX                                                                   1
9075 #define mmGRTAVFS_RTAVFS_RD_DATA                                                                       0x4b03
9076 #define mmGRTAVFS_RTAVFS_RD_DATA_BASE_IDX                                                              1
9077 #define mmGRTAVFS_RTAVFS_REG_CTRL                                                                      0x4b04
9078 #define mmGRTAVFS_RTAVFS_REG_CTRL_BASE_IDX                                                             1
9079 #define mmGRTAVFS_RTAVFS_REG_STATUS                                                                    0x4b05
9080 #define mmGRTAVFS_RTAVFS_REG_STATUS_BASE_IDX                                                           1
9081 #define mmGRTAVFS_TARG_FREQ                                                                            0x4b06
9082 #define mmGRTAVFS_TARG_FREQ_BASE_IDX                                                                   1
9083 #define mmGRTAVFS_TARG_VOLT                                                                            0x4b07
9084 #define mmGRTAVFS_TARG_VOLT_BASE_IDX                                                                   1
9085 #define mmGRTAVFS_SOFT_RESET                                                                           0x4b0f
9086 #define mmGRTAVFS_SOFT_RESET_BASE_IDX                                                                  1
9087 #define mmGRTAVFS_PSM_CNTL                                                                             0x4b10
9088 #define mmGRTAVFS_PSM_CNTL_BASE_IDX                                                                    1
9089 #define mmGRTAVFS_CLK_CNTL                                                                             0x4b11
9090 #define mmGRTAVFS_CLK_CNTL_BASE_IDX                                                                    1
9091 
9092 
9093 // addressBlock: gc_rlcdec
9094 // base address: 0x3b000
9095 #define mmRLC_CNTL                                                                                     0x4c00
9096 #define mmRLC_CNTL_BASE_IDX                                                                            1
9097 #define mmRLC_F32_UCODE_VERSION                                                                        0x4c03
9098 #define mmRLC_F32_UCODE_VERSION_BASE_IDX                                                               1
9099 #define mmRLC_STAT                                                                                     0x4c04
9100 #define mmRLC_STAT_BASE_IDX                                                                            1
9101 #define mmRLC_MEM_SLP_CNTL                                                                             0x4c06
9102 #define mmRLC_MEM_SLP_CNTL_BASE_IDX                                                                    1
9103 #define mmSMU_RLC_RESPONSE                                                                             0x4c07
9104 #define mmSMU_RLC_RESPONSE_BASE_IDX                                                                    1
9105 #define mmRLC_RLCV_SAFE_MODE                                                                           0x4c08
9106 #define mmRLC_RLCV_SAFE_MODE_BASE_IDX                                                                  1
9107 #define mmRLC_SMU_SAFE_MODE                                                                            0x4c09
9108 #define mmRLC_SMU_SAFE_MODE_BASE_IDX                                                                   1
9109 #define mmRLC_RLCV_COMMAND                                                                             0x4c0a
9110 #define mmRLC_RLCV_COMMAND_BASE_IDX                                                                    1
9111 #define mmRLC_REFCLOCK_TIMESTAMP_LSB                                                                   0x4c0c
9112 #define mmRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX                                                          1
9113 #define mmRLC_REFCLOCK_TIMESTAMP_MSB                                                                   0x4c0d
9114 #define mmRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX                                                          1
9115 #define mmRLC_GPM_TIMER_INT_0                                                                          0x4c0e
9116 #define mmRLC_GPM_TIMER_INT_0_BASE_IDX                                                                 1
9117 #define mmRLC_GPM_TIMER_INT_1                                                                          0x4c0f
9118 #define mmRLC_GPM_TIMER_INT_1_BASE_IDX                                                                 1
9119 #define mmRLC_GPM_TIMER_INT_2                                                                          0x4c10
9120 #define mmRLC_GPM_TIMER_INT_2_BASE_IDX                                                                 1
9121 #define mmRLC_GPM_TIMER_CTRL                                                                           0x4c11
9122 #define mmRLC_GPM_TIMER_CTRL_BASE_IDX                                                                  1
9123 #define mmRLC_LB_CNTR_MAX_1                                                                            0x4c12
9124 #define mmRLC_LB_CNTR_MAX_1_BASE_IDX                                                                   1
9125 #define mmRLC_GPM_TIMER_STAT                                                                           0x4c13
9126 #define mmRLC_GPM_TIMER_STAT_BASE_IDX                                                                  1
9127 #define mmRLC_GPM_TIMER_INT_3                                                                          0x4c15
9128 #define mmRLC_GPM_TIMER_INT_3_BASE_IDX                                                                 1
9129 #define mmRLC_GPM_LEGACY_INT_STAT                                                                      0x4c16
9130 #define mmRLC_GPM_LEGACY_INT_STAT_BASE_IDX                                                             1
9131 #define mmRLC_GPM_LEGACY_INT_CLEAR                                                                     0x4c17
9132 #define mmRLC_GPM_LEGACY_INT_CLEAR_BASE_IDX                                                            1
9133 #define mmRLC_INT_STAT                                                                                 0x4c18
9134 #define mmRLC_INT_STAT_BASE_IDX                                                                        1
9135 #define mmRLC_LB_CNTL                                                                                  0x4c19
9136 #define mmRLC_LB_CNTL_BASE_IDX                                                                         1
9137 #define mmRLC_MGCG_CTRL                                                                                0x4c1a
9138 #define mmRLC_MGCG_CTRL_BASE_IDX                                                                       1
9139 #define mmRLC_LB_CNTR_INIT_1                                                                           0x4c1b
9140 #define mmRLC_LB_CNTR_INIT_1_BASE_IDX                                                                  1
9141 #define mmRLC_LB_CNTR_1                                                                                0x4c1c
9142 #define mmRLC_LB_CNTR_1_BASE_IDX                                                                       1
9143 #define mmRLC_JUMP_TABLE_RESTORE                                                                       0x4c1e
9144 #define mmRLC_JUMP_TABLE_RESTORE_BASE_IDX                                                              1
9145 #define mmRLC_PG_DELAY_2                                                                               0x4c1f
9146 #define mmRLC_PG_DELAY_2_BASE_IDX                                                                      1
9147 #define mmRLC_GPU_CLOCK_COUNT_LSB                                                                      0x4c24
9148 #define mmRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX                                                             1
9149 #define mmRLC_GPU_CLOCK_COUNT_MSB                                                                      0x4c25
9150 #define mmRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX                                                             1
9151 #define mmRLC_CAPTURE_GPU_CLOCK_COUNT                                                                  0x4c26
9152 #define mmRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX                                                         1
9153 #define mmRLC_UCODE_CNTL                                                                               0x4c27
9154 #define mmRLC_UCODE_CNTL_BASE_IDX                                                                      1
9155 #define mmRLC_GPM_THREAD_RESET                                                                         0x4c28
9156 #define mmRLC_GPM_THREAD_RESET_BASE_IDX                                                                1
9157 #define mmRLC_GPM_CP_DMA_COMPLETE_T0                                                                   0x4c29
9158 #define mmRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX                                                          1
9159 #define mmRLC_GPM_CP_DMA_COMPLETE_T1                                                                   0x4c2a
9160 #define mmRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX                                                          1
9161 #define mmRLC_LB_CNTR_INIT_2                                                                           0x4c2b
9162 #define mmRLC_LB_CNTR_INIT_2_BASE_IDX                                                                  1
9163 #define mmRLC_LB_CNTR_MAX_2                                                                            0x4c2c
9164 #define mmRLC_LB_CNTR_MAX_2_BASE_IDX                                                                   1
9165 #define mmRLC_LB_CONFIG_5                                                                              0x4c2e
9166 #define mmRLC_LB_CONFIG_5_BASE_IDX                                                                     1
9167 #define mmRLC_GPM_TIMER_INT_4                                                                          0x4c2f
9168 #define mmRLC_GPM_TIMER_INT_4_BASE_IDX                                                                 1
9169 #define mmRLC_CLK_COUNT_GFXCLK_LSB                                                                     0x4c30
9170 #define mmRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX                                                            1
9171 #define mmRLC_CLK_COUNT_GFXCLK_MSB                                                                     0x4c31
9172 #define mmRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX                                                            1
9173 #define mmRLC_CLK_COUNT_REFCLK_LSB                                                                     0x4c32
9174 #define mmRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX                                                            1
9175 #define mmRLC_CLK_COUNT_REFCLK_MSB                                                                     0x4c33
9176 #define mmRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX                                                            1
9177 #define mmRLC_CLK_COUNT_CTRL                                                                           0x4c34
9178 #define mmRLC_CLK_COUNT_CTRL_BASE_IDX                                                                  1
9179 #define mmRLC_CLK_COUNT_STAT                                                                           0x4c35
9180 #define mmRLC_CLK_COUNT_STAT_BASE_IDX                                                                  1
9181 #define mmRLC_RLCG_DOORBELL_CNTL                                                                       0x4c36
9182 #define mmRLC_RLCG_DOORBELL_CNTL_BASE_IDX                                                              1
9183 #define mmRLC_RLCG_DOORBELL_STAT                                                                       0x4c37
9184 #define mmRLC_RLCG_DOORBELL_STAT_BASE_IDX                                                              1
9185 #define mmRLC_RLCG_DOORBELL_0_DATA_LO                                                                  0x4c38
9186 #define mmRLC_RLCG_DOORBELL_0_DATA_LO_BASE_IDX                                                         1
9187 #define mmRLC_RLCG_DOORBELL_0_DATA_HI                                                                  0x4c39
9188 #define mmRLC_RLCG_DOORBELL_0_DATA_HI_BASE_IDX                                                         1
9189 #define mmRLC_RLCG_DOORBELL_1_DATA_LO                                                                  0x4c3a
9190 #define mmRLC_RLCG_DOORBELL_1_DATA_LO_BASE_IDX                                                         1
9191 #define mmRLC_RLCG_DOORBELL_1_DATA_HI                                                                  0x4c3b
9192 #define mmRLC_RLCG_DOORBELL_1_DATA_HI_BASE_IDX                                                         1
9193 #define mmRLC_RLCG_DOORBELL_2_DATA_LO                                                                  0x4c3c
9194 #define mmRLC_RLCG_DOORBELL_2_DATA_LO_BASE_IDX                                                         1
9195 #define mmRLC_RLCG_DOORBELL_2_DATA_HI                                                                  0x4c3d
9196 #define mmRLC_RLCG_DOORBELL_2_DATA_HI_BASE_IDX                                                         1
9197 #define mmRLC_RLCG_DOORBELL_3_DATA_LO                                                                  0x4c3e
9198 #define mmRLC_RLCG_DOORBELL_3_DATA_LO_BASE_IDX                                                         1
9199 #define mmRLC_RLCG_DOORBELL_3_DATA_HI                                                                  0x4c3f
9200 #define mmRLC_RLCG_DOORBELL_3_DATA_HI_BASE_IDX                                                         1
9201 #define mmRLC_GPU_CLOCK_32_RES_SEL                                                                     0x4c41
9202 #define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX                                                            1
9203 #define mmRLC_GPU_CLOCK_32                                                                             0x4c42
9204 #define mmRLC_GPU_CLOCK_32_BASE_IDX                                                                    1
9205 #define mmRLC_PG_CNTL                                                                                  0x4c43
9206 #define mmRLC_PG_CNTL_BASE_IDX                                                                         1
9207 #define mmRLC_GPM_THREAD_PRIORITY                                                                      0x4c44
9208 #define mmRLC_GPM_THREAD_PRIORITY_BASE_IDX                                                             1
9209 #define mmRLC_GPM_THREAD_ENABLE                                                                        0x4c45
9210 #define mmRLC_GPM_THREAD_ENABLE_BASE_IDX                                                               1
9211 #define mmRLC_RLCG_DOORBELL_RANGE                                                                      0x4c47
9212 #define mmRLC_RLCG_DOORBELL_RANGE_BASE_IDX                                                             1
9213 #define mmRLC_CGTT_MGCG_OVERRIDE                                                                       0x4c48
9214 #define mmRLC_CGTT_MGCG_OVERRIDE_BASE_IDX                                                              1
9215 #define mmRLC_CGCG_CGLS_CTRL                                                                           0x4c49
9216 #define mmRLC_CGCG_CGLS_CTRL_BASE_IDX                                                                  1
9217 #define mmRLC_CGCG_RAMP_CTRL                                                                           0x4c4a
9218 #define mmRLC_CGCG_RAMP_CTRL_BASE_IDX                                                                  1
9219 #define mmRLC_DYN_PG_STATUS                                                                            0x4c4b
9220 #define mmRLC_DYN_PG_STATUS_BASE_IDX                                                                   1
9221 #define mmRLC_DYN_PG_REQUEST                                                                           0x4c4c
9222 #define mmRLC_DYN_PG_REQUEST_BASE_IDX                                                                  1
9223 #define mmRLC_PG_DELAY                                                                                 0x4c4d
9224 #define mmRLC_PG_DELAY_BASE_IDX                                                                        1
9225 #define mmRLC_WGP_STATUS                                                                               0x4c4e
9226 #define mmRLC_WGP_STATUS_BASE_IDX                                                                      1
9227 #define mmRLC_LB_INIT_WGP_MASK                                                                         0x4c4f
9228 #define mmRLC_LB_INIT_WGP_MASK_BASE_IDX                                                                1
9229 #define mmRLC_LB_ALWAYS_ACTIVE_WGP_MASK                                                                0x4c50
9230 #define mmRLC_LB_ALWAYS_ACTIVE_WGP_MASK_BASE_IDX                                                       1
9231 #define mmRLC_LB_PARAMS                                                                                0x4c51
9232 #define mmRLC_LB_PARAMS_BASE_IDX                                                                       1
9233 #define mmRLC_LB_DELAY                                                                                 0x4c52
9234 #define mmRLC_LB_DELAY_BASE_IDX                                                                        1
9235 #define mmRLC_PG_ALWAYS_ON_WGP_MASK                                                                    0x4c53
9236 #define mmRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX                                                           1
9237 #define mmRLC_MAX_PG_WGP                                                                               0x4c54
9238 #define mmRLC_MAX_PG_WGP_BASE_IDX                                                                      1
9239 #define mmRLC_AUTO_PG_CTRL                                                                             0x4c55
9240 #define mmRLC_AUTO_PG_CTRL_BASE_IDX                                                                    1
9241 #define mmRLC_SMU_GRBM_REG_SAVE_CTRL                                                                   0x4c56
9242 #define mmRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX                                                          1
9243 #define mmRLC_SERDES_RD_INDEX                                                                          0x4c59
9244 #define mmRLC_SERDES_RD_INDEX_BASE_IDX                                                                 1
9245 #define mmRLC_SERDES_RD_DATA_0                                                                         0x4c5a
9246 #define mmRLC_SERDES_RD_DATA_0_BASE_IDX                                                                1
9247 #define mmRLC_SERDES_RD_DATA_1                                                                         0x4c5b
9248 #define mmRLC_SERDES_RD_DATA_1_BASE_IDX                                                                1
9249 #define mmRLC_SERDES_RD_DATA_2                                                                         0x4c5c
9250 #define mmRLC_SERDES_RD_DATA_2_BASE_IDX                                                                1
9251 #define mmRLC_SERDES_RD_DATA_3                                                                         0x4c5d
9252 #define mmRLC_SERDES_RD_DATA_3_BASE_IDX                                                                1
9253 #define mmRLC_SERDES_MASK                                                                              0x4c5e
9254 #define mmRLC_SERDES_MASK_BASE_IDX                                                                     1
9255 #define mmRLC_SERDES_CTRL                                                                              0x4c5f
9256 #define mmRLC_SERDES_CTRL_BASE_IDX                                                                     1
9257 #define mmRLC_SERDES_DATA                                                                              0x4c60
9258 #define mmRLC_SERDES_DATA_BASE_IDX                                                                     1
9259 #define mmRLC_SERDES_BUSY                                                                              0x4c61
9260 #define mmRLC_SERDES_BUSY_BASE_IDX                                                                     1
9261 #define mmRLC_GPM_GENERAL_0                                                                            0x4c63
9262 #define mmRLC_GPM_GENERAL_0_BASE_IDX                                                                   1
9263 #define mmRLC_GPM_GENERAL_1                                                                            0x4c64
9264 #define mmRLC_GPM_GENERAL_1_BASE_IDX                                                                   1
9265 #define mmRLC_GPM_GENERAL_2                                                                            0x4c65
9266 #define mmRLC_GPM_GENERAL_2_BASE_IDX                                                                   1
9267 #define mmRLC_GPM_GENERAL_3                                                                            0x4c66
9268 #define mmRLC_GPM_GENERAL_3_BASE_IDX                                                                   1
9269 #define mmRLC_GPM_GENERAL_4                                                                            0x4c67
9270 #define mmRLC_GPM_GENERAL_4_BASE_IDX                                                                   1
9271 #define mmRLC_GPM_GENERAL_5                                                                            0x4c68
9272 #define mmRLC_GPM_GENERAL_5_BASE_IDX                                                                   1
9273 #define mmRLC_GPM_GENERAL_6                                                                            0x4c69
9274 #define mmRLC_GPM_GENERAL_6_BASE_IDX                                                                   1
9275 #define mmRLC_GPM_GENERAL_7                                                                            0x4c6a
9276 #define mmRLC_GPM_GENERAL_7_BASE_IDX                                                                   1
9277 #define mmRLC_STATIC_PG_STATUS                                                                         0x4c6e
9278 #define mmRLC_STATIC_PG_STATUS_BASE_IDX                                                                1
9279 #define mmRLC_SPM_INT_INFO_1                                                                           0x4c6f
9280 #define mmRLC_SPM_INT_INFO_1_BASE_IDX                                                                  1
9281 #define mmRLC_SPM_INT_INFO_2                                                                           0x4c70
9282 #define mmRLC_SPM_INT_INFO_2_BASE_IDX                                                                  1
9283 #define mmRLC_SPM_MC_CNTL                                                                              0x4c71
9284 #define mmRLC_SPM_MC_CNTL_BASE_IDX                                                                     1
9285 #define mmRLC_SPM_INT_CNTL                                                                             0x4c72
9286 #define mmRLC_SPM_INT_CNTL_BASE_IDX                                                                    1
9287 #define mmRLC_SPM_INT_STATUS                                                                           0x4c73
9288 #define mmRLC_SPM_INT_STATUS_BASE_IDX                                                                  1
9289 #define mmRLC_SMU_MESSAGE                                                                              0x4c76
9290 #define mmRLC_SMU_MESSAGE_BASE_IDX                                                                     1
9291 #define mmRLC_GPM_LOG_SIZE                                                                             0x4c77
9292 #define mmRLC_GPM_LOG_SIZE_BASE_IDX                                                                    1
9293 #define mmRLC_PG_DELAY_3                                                                               0x4c78
9294 #define mmRLC_PG_DELAY_3_BASE_IDX                                                                      1
9295 #define mmRLC_GPR_REG1                                                                                 0x4c79
9296 #define mmRLC_GPR_REG1_BASE_IDX                                                                        1
9297 #define mmRLC_GPR_REG2                                                                                 0x4c7a
9298 #define mmRLC_GPR_REG2_BASE_IDX                                                                        1
9299 #define mmRLC_GPM_LOG_CONT                                                                             0x4c7b
9300 #define mmRLC_GPM_LOG_CONT_BASE_IDX                                                                    1
9301 #define mmRLC_GPM_INT_DISABLE_TH0                                                                      0x4c7c
9302 #define mmRLC_GPM_INT_DISABLE_TH0_BASE_IDX                                                             1
9303 #define mmRLC_GPM_LEGACY_INT_DISABLE                                                                   0x4c7d
9304 #define mmRLC_GPM_LEGACY_INT_DISABLE_BASE_IDX                                                          1
9305 #define mmRLC_GPM_INT_FORCE_TH0                                                                        0x4c7e
9306 #define mmRLC_GPM_INT_FORCE_TH0_BASE_IDX                                                               1
9307 #define mmRLC_SRM_CNTL                                                                                 0x4c80
9308 #define mmRLC_SRM_CNTL_BASE_IDX                                                                        1
9309 #define mmRLC_SRM_GPM_COMMAND                                                                          0x4c87
9310 #define mmRLC_SRM_GPM_COMMAND_BASE_IDX                                                                 1
9311 #define mmRLC_SRM_GPM_COMMAND_STATUS                                                                   0x4c88
9312 #define mmRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX                                                          1
9313 #define mmRLC_SRM_RLCV_COMMAND                                                                         0x4c89
9314 #define mmRLC_SRM_RLCV_COMMAND_BASE_IDX                                                                1
9315 #define mmRLC_SRM_RLCV_COMMAND_STATUS                                                                  0x4c8a
9316 #define mmRLC_SRM_RLCV_COMMAND_STATUS_BASE_IDX                                                         1
9317 #define mmRLC_SRM_INDEX_CNTL_ADDR_0                                                                    0x4c8b
9318 #define mmRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX                                                           1
9319 #define mmRLC_SRM_INDEX_CNTL_ADDR_1                                                                    0x4c8c
9320 #define mmRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX                                                           1
9321 #define mmRLC_SRM_INDEX_CNTL_ADDR_2                                                                    0x4c8d
9322 #define mmRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX                                                           1
9323 #define mmRLC_SRM_INDEX_CNTL_ADDR_3                                                                    0x4c8e
9324 #define mmRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX                                                           1
9325 #define mmRLC_SRM_INDEX_CNTL_ADDR_4                                                                    0x4c8f
9326 #define mmRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX                                                           1
9327 #define mmRLC_SRM_INDEX_CNTL_ADDR_5                                                                    0x4c90
9328 #define mmRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX                                                           1
9329 #define mmRLC_SRM_INDEX_CNTL_ADDR_6                                                                    0x4c91
9330 #define mmRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX                                                           1
9331 #define mmRLC_SRM_INDEX_CNTL_ADDR_7                                                                    0x4c92
9332 #define mmRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX                                                           1
9333 #define mmRLC_SRM_INDEX_CNTL_DATA_0                                                                    0x4c93
9334 #define mmRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX                                                           1
9335 #define mmRLC_SRM_INDEX_CNTL_DATA_1                                                                    0x4c94
9336 #define mmRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX                                                           1
9337 #define mmRLC_SRM_INDEX_CNTL_DATA_2                                                                    0x4c95
9338 #define mmRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX                                                           1
9339 #define mmRLC_SRM_INDEX_CNTL_DATA_3                                                                    0x4c96
9340 #define mmRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX                                                           1
9341 #define mmRLC_SRM_INDEX_CNTL_DATA_4                                                                    0x4c97
9342 #define mmRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX                                                           1
9343 #define mmRLC_SRM_INDEX_CNTL_DATA_5                                                                    0x4c98
9344 #define mmRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX                                                           1
9345 #define mmRLC_SRM_INDEX_CNTL_DATA_6                                                                    0x4c99
9346 #define mmRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX                                                           1
9347 #define mmRLC_SRM_INDEX_CNTL_DATA_7                                                                    0x4c9a
9348 #define mmRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX                                                           1
9349 #define mmRLC_SRM_STAT                                                                                 0x4c9b
9350 #define mmRLC_SRM_STAT_BASE_IDX                                                                        1
9351 #define mmRLC_SRM_GPM_ABORT                                                                            0x4c9c
9352 #define mmRLC_SRM_GPM_ABORT_BASE_IDX                                                                   1
9353 #define mmRLC_SPARE_INT_2                                                                              0x4c9d
9354 #define mmRLC_SPARE_INT_2_BASE_IDX                                                                     1
9355 #define mmRLC_RLCV_SPARE_INT_1                                                                         0x4c9e
9356 #define mmRLC_RLCV_SPARE_INT_1_BASE_IDX                                                                1
9357 #define mmRLC_PACE_SPARE_INT_1                                                                         0x4c9f
9358 #define mmRLC_PACE_SPARE_INT_1_BASE_IDX                                                                1
9359 #define mmRLC_SAFE_MODE                                                                                0x4ca0
9360 #define mmRLC_SAFE_MODE_BASE_IDX                                                                       1
9361 #define mmRLC_CP_SCHEDULERS                                                                            0x4ca1
9362 #define mmRLC_CP_SCHEDULERS_BASE_IDX                                                                   1
9363 #define mmRLC_CSIB_ADDR_LO                                                                             0x4ca2
9364 #define mmRLC_CSIB_ADDR_LO_BASE_IDX                                                                    1
9365 #define mmRLC_CSIB_ADDR_HI                                                                             0x4ca3
9366 #define mmRLC_CSIB_ADDR_HI_BASE_IDX                                                                    1
9367 #define mmRLC_CSIB_LENGTH                                                                              0x4ca4
9368 #define mmRLC_CSIB_LENGTH_BASE_IDX                                                                     1
9369 #define mmRLC_SPARE_INT_0                                                                              0x4ca5
9370 #define mmRLC_SPARE_INT_0_BASE_IDX                                                                     1
9371 #define mmRLC_CP_EOF_INT_CNT                                                                           0x4ca6
9372 #define mmRLC_CP_EOF_INT_CNT_BASE_IDX                                                                  1
9373 #define mmRLC_CP_EOF_INT                                                                               0x4ca7
9374 #define mmRLC_CP_EOF_INT_BASE_IDX                                                                      1
9375 #define mmRLC_SMU_COMMAND                                                                              0x4ca9
9376 #define mmRLC_SMU_COMMAND_BASE_IDX                                                                     1
9377 #define mmRLC_SMU_ARGUMENT_1                                                                           0x4cab
9378 #define mmRLC_SMU_ARGUMENT_1_BASE_IDX                                                                  1
9379 #define mmRLC_SMU_ARGUMENT_2                                                                           0x4cac
9380 #define mmRLC_SMU_ARGUMENT_2_BASE_IDX                                                                  1
9381 #define mmRLC_GPM_GENERAL_8                                                                            0x4cad
9382 #define mmRLC_GPM_GENERAL_8_BASE_IDX                                                                   1
9383 #define mmRLC_GPM_GENERAL_9                                                                            0x4cae
9384 #define mmRLC_GPM_GENERAL_9_BASE_IDX                                                                   1
9385 #define mmRLC_GPM_GENERAL_10                                                                           0x4caf
9386 #define mmRLC_GPM_GENERAL_10_BASE_IDX                                                                  1
9387 #define mmRLC_GPM_GENERAL_11                                                                           0x4cb0
9388 #define mmRLC_GPM_GENERAL_11_BASE_IDX                                                                  1
9389 #define mmRLC_GPM_GENERAL_12                                                                           0x4cb1
9390 #define mmRLC_GPM_GENERAL_12_BASE_IDX                                                                  1
9391 #define mmRLC_GPM_UTCL1_CNTL_0                                                                         0x4cb2
9392 #define mmRLC_GPM_UTCL1_CNTL_0_BASE_IDX                                                                1
9393 #define mmRLC_GPM_UTCL1_CNTL_1                                                                         0x4cb3
9394 #define mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX                                                                1
9395 #define mmRLC_GPM_UTCL1_CNTL_2                                                                         0x4cb4
9396 #define mmRLC_GPM_UTCL1_CNTL_2_BASE_IDX                                                                1
9397 #define mmRLC_SPM_UTCL1_CNTL                                                                           0x4cb5
9398 #define mmRLC_SPM_UTCL1_CNTL_BASE_IDX                                                                  1
9399 #define mmRLC_UTCL1_STATUS_2                                                                           0x4cb6
9400 #define mmRLC_UTCL1_STATUS_2_BASE_IDX                                                                  1
9401 #define mmRLC_LB_CONFIG_2                                                                              0x4cb8
9402 #define mmRLC_LB_CONFIG_2_BASE_IDX                                                                     1
9403 #define mmRLC_LB_CONFIG_3                                                                              0x4cb9
9404 #define mmRLC_LB_CONFIG_3_BASE_IDX                                                                     1
9405 #define mmRLC_LB_CONFIG_4                                                                              0x4cba
9406 #define mmRLC_LB_CONFIG_4_BASE_IDX                                                                     1
9407 #define mmRLC_SPM_UTCL1_ERROR_1                                                                        0x4cbc
9408 #define mmRLC_SPM_UTCL1_ERROR_1_BASE_IDX                                                               1
9409 #define mmRLC_SPM_UTCL1_ERROR_2                                                                        0x4cbd
9410 #define mmRLC_SPM_UTCL1_ERROR_2_BASE_IDX                                                               1
9411 #define mmRLC_GPM_UTCL1_TH0_ERROR_1                                                                    0x4cbe
9412 #define mmRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX                                                           1
9413 #define mmRLC_LB_CONFIG_1                                                                              0x4cbf
9414 #define mmRLC_LB_CONFIG_1_BASE_IDX                                                                     1
9415 #define mmRLC_GPM_UTCL1_TH0_ERROR_2                                                                    0x4cc0
9416 #define mmRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX                                                           1
9417 #define mmRLC_GPM_UTCL1_TH1_ERROR_1                                                                    0x4cc1
9418 #define mmRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX                                                           1
9419 #define mmRLC_GPM_UTCL1_TH1_ERROR_2                                                                    0x4cc2
9420 #define mmRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX                                                           1
9421 #define mmRLC_GPM_UTCL1_TH2_ERROR_1                                                                    0x4cc3
9422 #define mmRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX                                                           1
9423 #define mmRLC_GPM_UTCL1_TH2_ERROR_2                                                                    0x4cc4
9424 #define mmRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX                                                           1
9425 #define mmRLC_CGCG_CGLS_CTRL_3D                                                                        0x4cc5
9426 #define mmRLC_CGCG_CGLS_CTRL_3D_BASE_IDX                                                               1
9427 #define mmRLC_CGCG_RAMP_CTRL_3D                                                                        0x4cc6
9428 #define mmRLC_CGCG_RAMP_CTRL_3D_BASE_IDX                                                               1
9429 #define mmRLC_SEMAPHORE_0                                                                              0x4cc7
9430 #define mmRLC_SEMAPHORE_0_BASE_IDX                                                                     1
9431 #define mmRLC_SEMAPHORE_1                                                                              0x4cc8
9432 #define mmRLC_SEMAPHORE_1_BASE_IDX                                                                     1
9433 #define mmRLC_PACE_INT_STAT                                                                            0x4ccc
9434 #define mmRLC_PACE_INT_STAT_BASE_IDX                                                                   1
9435 #define mmRLC_PREWALKER_UTCL1_CNTL                                                                     0x4ccd
9436 #define mmRLC_PREWALKER_UTCL1_CNTL_BASE_IDX                                                            1
9437 #define mmRLC_PREWALKER_UTCL1_TRIG                                                                     0x4cce
9438 #define mmRLC_PREWALKER_UTCL1_TRIG_BASE_IDX                                                            1
9439 #define mmRLC_PREWALKER_UTCL1_ADDR_LSB                                                                 0x4ccf
9440 #define mmRLC_PREWALKER_UTCL1_ADDR_LSB_BASE_IDX                                                        1
9441 #define mmRLC_PREWALKER_UTCL1_ADDR_MSB                                                                 0x4cd0
9442 #define mmRLC_PREWALKER_UTCL1_ADDR_MSB_BASE_IDX                                                        1
9443 #define mmRLC_PREWALKER_UTCL1_SIZE_LSB                                                                 0x4cd1
9444 #define mmRLC_PREWALKER_UTCL1_SIZE_LSB_BASE_IDX                                                        1
9445 #define mmRLC_PREWALKER_UTCL1_SIZE_MSB                                                                 0x4cd2
9446 #define mmRLC_PREWALKER_UTCL1_SIZE_MSB_BASE_IDX                                                        1
9447 #define mmRLC_UTCL1_STATUS                                                                             0x4cd4
9448 #define mmRLC_UTCL1_STATUS_BASE_IDX                                                                    1
9449 #define mmRLC_R2I_CNTL_0                                                                               0x4cd5
9450 #define mmRLC_R2I_CNTL_0_BASE_IDX                                                                      1
9451 #define mmRLC_R2I_CNTL_1                                                                               0x4cd6
9452 #define mmRLC_R2I_CNTL_1_BASE_IDX                                                                      1
9453 #define mmRLC_R2I_CNTL_2                                                                               0x4cd7
9454 #define mmRLC_R2I_CNTL_2_BASE_IDX                                                                      1
9455 #define mmRLC_R2I_CNTL_3                                                                               0x4cd8
9456 #define mmRLC_R2I_CNTL_3_BASE_IDX                                                                      1
9457 #define mmRLC_LB_WGP_STAT                                                                              0x4cda
9458 #define mmRLC_LB_WGP_STAT_BASE_IDX                                                                     1
9459 #define mmRLC_GPM_INT_STAT_TH0                                                                         0x4cdc
9460 #define mmRLC_GPM_INT_STAT_TH0_BASE_IDX                                                                1
9461 #define mmRLC_GPM_GENERAL_13                                                                           0x4cdd
9462 #define mmRLC_GPM_GENERAL_13_BASE_IDX                                                                  1
9463 #define mmRLC_GPM_GENERAL_14                                                                           0x4cde
9464 #define mmRLC_GPM_GENERAL_14_BASE_IDX                                                                  1
9465 #define mmRLC_GPM_GENERAL_15                                                                           0x4cdf
9466 #define mmRLC_GPM_GENERAL_15_BASE_IDX                                                                  1
9467 #define mmRLC_SPARE_INT_1                                                                              0x4ce0
9468 #define mmRLC_SPARE_INT_1_BASE_IDX                                                                     1
9469 #define mmRLC_SEMAPHORE_2                                                                              0x4ce3
9470 #define mmRLC_SEMAPHORE_2_BASE_IDX                                                                     1
9471 #define mmRLC_SEMAPHORE_3                                                                              0x4ce4
9472 #define mmRLC_SEMAPHORE_3_BASE_IDX                                                                     1
9473 #define mmRLC_SMU_ARGUMENT_3                                                                           0x4ce5
9474 #define mmRLC_SMU_ARGUMENT_3_BASE_IDX                                                                  1
9475 #define mmRLC_SMU_ARGUMENT_4                                                                           0x4ce6
9476 #define mmRLC_SMU_ARGUMENT_4_BASE_IDX                                                                  1
9477 #define mmRLC_GPU_CLOCK_COUNT_LSB_1                                                                    0x4ce8
9478 #define mmRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX                                                           1
9479 #define mmRLC_GPU_CLOCK_COUNT_MSB_1                                                                    0x4ce9
9480 #define mmRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX                                                           1
9481 #define mmRLC_CAPTURE_GPU_CLOCK_COUNT_1                                                                0x4cea
9482 #define mmRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX                                                       1
9483 #define mmRLC_GPU_CLOCK_COUNT_LSB_2                                                                    0x4ceb
9484 #define mmRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX                                                           1
9485 #define mmRLC_GPU_CLOCK_COUNT_MSB_2                                                                    0x4cec
9486 #define mmRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX                                                           1
9487 #define mmRLC_PACE_INT_DISABLE                                                                         0x4ced
9488 #define mmRLC_PACE_INT_DISABLE_BASE_IDX                                                                1
9489 #define mmRLC_CAPTURE_GPU_CLOCK_COUNT_2                                                                0x4cef
9490 #define mmRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX                                                       1
9491 #define mmRLC_RLCV_DOORBELL_RANGE                                                                      0x4cf0
9492 #define mmRLC_RLCV_DOORBELL_RANGE_BASE_IDX                                                             1
9493 #define mmRLC_RLCV_DOORBELL_CNTL                                                                       0x4cf1
9494 #define mmRLC_RLCV_DOORBELL_CNTL_BASE_IDX                                                              1
9495 #define mmRLC_RLCV_DOORBELL_STAT                                                                       0x4cf2
9496 #define mmRLC_RLCV_DOORBELL_STAT_BASE_IDX                                                              1
9497 #define mmRLC_RLCV_DOORBELL_0_DATA_LO                                                                  0x4cf3
9498 #define mmRLC_RLCV_DOORBELL_0_DATA_LO_BASE_IDX                                                         1
9499 #define mmRLC_RLCV_DOORBELL_0_DATA_HI                                                                  0x4cf4
9500 #define mmRLC_RLCV_DOORBELL_0_DATA_HI_BASE_IDX                                                         1
9501 #define mmRLC_RLCV_DOORBELL_1_DATA_LO                                                                  0x4cf5
9502 #define mmRLC_RLCV_DOORBELL_1_DATA_LO_BASE_IDX                                                         1
9503 #define mmRLC_RLCV_DOORBELL_1_DATA_HI                                                                  0x4cf6
9504 #define mmRLC_RLCV_DOORBELL_1_DATA_HI_BASE_IDX                                                         1
9505 #define mmRLC_RLCV_DOORBELL_2_DATA_LO                                                                  0x4cf7
9506 #define mmRLC_RLCV_DOORBELL_2_DATA_LO_BASE_IDX                                                         1
9507 #define mmRLC_RLCV_DOORBELL_2_DATA_HI                                                                  0x4cf8
9508 #define mmRLC_RLCV_DOORBELL_2_DATA_HI_BASE_IDX                                                         1
9509 #define mmRLC_RLCV_DOORBELL_3_DATA_LO                                                                  0x4cf9
9510 #define mmRLC_RLCV_DOORBELL_3_DATA_LO_BASE_IDX                                                         1
9511 #define mmRLC_RLCV_DOORBELL_3_DATA_HI                                                                  0x4cfa
9512 #define mmRLC_RLCV_DOORBELL_3_DATA_HI_BASE_IDX                                                         1
9513 #define mmRLC_RLCV_SPARE_INT                                                                           0x4d00
9514 #define mmRLC_RLCV_SPARE_INT_BASE_IDX                                                                  1
9515 #define mmRLC_PACE_TIMER_INT_0                                                                         0x4d04
9516 #define mmRLC_PACE_TIMER_INT_0_BASE_IDX                                                                1
9517 #define mmRLC_PACE_TIMER_CTRL                                                                          0x4d05
9518 #define mmRLC_PACE_TIMER_CTRL_BASE_IDX                                                                 1
9519 #define mmRLC_PACE_TIMER_INT_1                                                                         0x4d06
9520 #define mmRLC_PACE_TIMER_INT_1_BASE_IDX                                                                1
9521 #define mmRLC_PACE_SPARE_INT                                                                           0x4d07
9522 #define mmRLC_PACE_SPARE_INT_BASE_IDX                                                                  1
9523 #define mmRLC_SMU_CLK_REQ                                                                              0x4d08
9524 #define mmRLC_SMU_CLK_REQ_BASE_IDX                                                                     1
9525 #define mmRLC_CP_STAT_INVAL_STAT                                                                       0x4d09
9526 #define mmRLC_CP_STAT_INVAL_STAT_BASE_IDX                                                              1
9527 #define mmRLC_CP_STAT_INVAL_CTRL                                                                       0x4d0a
9528 #define mmRLC_CP_STAT_INVAL_CTRL_BASE_IDX                                                              1
9529 #define mmRLC_CLK_STATUS                                                                               0x4d0b
9530 #define mmRLC_CLK_STATUS_BASE_IDX                                                                      1
9531 #define mmRLC_SPP_CTRL                                                                                 0x4d0c
9532 #define mmRLC_SPP_CTRL_BASE_IDX                                                                        1
9533 #define mmRLC_SPP_SHADER_PROFILE_EN                                                                    0x4d0d
9534 #define mmRLC_SPP_SHADER_PROFILE_EN_BASE_IDX                                                           1
9535 #define mmRLC_SPP_SSF_CAPTURE_EN                                                                       0x4d0e
9536 #define mmRLC_SPP_SSF_CAPTURE_EN_BASE_IDX                                                              1
9537 #define mmRLC_SPP_SSF_THRESHOLD_0                                                                      0x4d0f
9538 #define mmRLC_SPP_SSF_THRESHOLD_0_BASE_IDX                                                             1
9539 #define mmRLC_SPP_SSF_THRESHOLD_1                                                                      0x4d10
9540 #define mmRLC_SPP_SSF_THRESHOLD_1_BASE_IDX                                                             1
9541 #define mmRLC_SPP_SSF_THRESHOLD_2                                                                      0x4d11
9542 #define mmRLC_SPP_SSF_THRESHOLD_2_BASE_IDX                                                             1
9543 #define mmRLC_SPP_INFLIGHT_RD_ADDR                                                                     0x4d12
9544 #define mmRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX                                                            1
9545 #define mmRLC_SPP_INFLIGHT_RD_DATA                                                                     0x4d13
9546 #define mmRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX                                                            1
9547 #define mmRLC_GPM_GENERAL_16                                                                           0x4d14
9548 #define mmRLC_GPM_GENERAL_16_BASE_IDX                                                                  1
9549 #define mmRLC_SPP_PROF_INFO_1                                                                          0x4d18
9550 #define mmRLC_SPP_PROF_INFO_1_BASE_IDX                                                                 1
9551 #define mmRLC_SPP_PROF_INFO_2                                                                          0x4d19
9552 #define mmRLC_SPP_PROF_INFO_2_BASE_IDX                                                                 1
9553 #define mmRLC_SPP_GLOBAL_SH_ID                                                                         0x4d1a
9554 #define mmRLC_SPP_GLOBAL_SH_ID_BASE_IDX                                                                1
9555 #define mmRLC_SPP_GLOBAL_SH_ID_VALID                                                                   0x4d1b
9556 #define mmRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX                                                          1
9557 #define mmRLC_SPP_STATUS                                                                               0x4d1c
9558 #define mmRLC_SPP_STATUS_BASE_IDX                                                                      1
9559 #define mmRLC_SPP_PVT_STAT_0                                                                           0x4d1d
9560 #define mmRLC_SPP_PVT_STAT_0_BASE_IDX                                                                  1
9561 #define mmRLC_SPP_PVT_STAT_1                                                                           0x4d1e
9562 #define mmRLC_SPP_PVT_STAT_1_BASE_IDX                                                                  1
9563 #define mmRLC_SPP_PVT_STAT_2                                                                           0x4d1f
9564 #define mmRLC_SPP_PVT_STAT_2_BASE_IDX                                                                  1
9565 #define mmRLC_SPP_PVT_STAT_3                                                                           0x4d20
9566 #define mmRLC_SPP_PVT_STAT_3_BASE_IDX                                                                  1
9567 #define mmRLC_SPP_PVT_LEVEL_MAX                                                                        0x4d21
9568 #define mmRLC_SPP_PVT_LEVEL_MAX_BASE_IDX                                                               1
9569 #define mmRLC_SPP_STALL_STATE_UPDATE                                                                   0x4d22
9570 #define mmRLC_SPP_STALL_STATE_UPDATE_BASE_IDX                                                          1
9571 #define mmRLC_SPP_PBB_INFO                                                                             0x4d23
9572 #define mmRLC_SPP_PBB_INFO_BASE_IDX                                                                    1
9573 #define mmRLC_SPP_RESET                                                                                0x4d24
9574 #define mmRLC_SPP_RESET_BASE_IDX                                                                       1
9575 #define mmRLC_SPM_SAMPLE_CNT                                                                           0x4d25
9576 #define mmRLC_SPM_SAMPLE_CNT_BASE_IDX                                                                  1
9577 #define mmRLC_RLCP_DOORBELL_RANGE                                                                      0x4d26
9578 #define mmRLC_RLCP_DOORBELL_RANGE_BASE_IDX                                                             1
9579 #define mmRLC_RLCP_DOORBELL_CNTL                                                                       0x4d27
9580 #define mmRLC_RLCP_DOORBELL_CNTL_BASE_IDX                                                              1
9581 #define mmRLC_RLCP_DOORBELL_STAT                                                                       0x4d28
9582 #define mmRLC_RLCP_DOORBELL_STAT_BASE_IDX                                                              1
9583 #define mmRLC_RLCP_DOORBELL_0_DATA_LO                                                                  0x4d29
9584 #define mmRLC_RLCP_DOORBELL_0_DATA_LO_BASE_IDX                                                         1
9585 #define mmRLC_RLCP_DOORBELL_0_DATA_HI                                                                  0x4d2a
9586 #define mmRLC_RLCP_DOORBELL_0_DATA_HI_BASE_IDX                                                         1
9587 #define mmRLC_RLCP_DOORBELL_1_DATA_LO                                                                  0x4d2b
9588 #define mmRLC_RLCP_DOORBELL_1_DATA_LO_BASE_IDX                                                         1
9589 #define mmRLC_RLCP_DOORBELL_1_DATA_HI                                                                  0x4d2c
9590 #define mmRLC_RLCP_DOORBELL_1_DATA_HI_BASE_IDX                                                         1
9591 #define mmRLC_RLCP_DOORBELL_2_DATA_LO                                                                  0x4d2d
9592 #define mmRLC_RLCP_DOORBELL_2_DATA_LO_BASE_IDX                                                         1
9593 #define mmRLC_RLCP_DOORBELL_2_DATA_HI                                                                  0x4d2e
9594 #define mmRLC_RLCP_DOORBELL_2_DATA_HI_BASE_IDX                                                         1
9595 #define mmRLC_RLCP_DOORBELL_3_DATA_LO                                                                  0x4d2f
9596 #define mmRLC_RLCP_DOORBELL_3_DATA_LO_BASE_IDX                                                         1
9597 #define mmRLC_RLCP_DOORBELL_3_DATA_HI                                                                  0x4d30
9598 #define mmRLC_RLCP_DOORBELL_3_DATA_HI_BASE_IDX                                                         1
9599 #define mmRLC_PCC_STRETCH_HYSTERESIS_CNTL                                                              0x4d44
9600 #define mmRLC_PCC_STRETCH_HYSTERESIS_CNTL_BASE_IDX                                                     1
9601 #define mmRLC_CAC_MASK_CNTL                                                                            0x4d45
9602 #define mmRLC_CAC_MASK_CNTL_BASE_IDX                                                                   1
9603 #define mmRLC_GPU_CLOCK_COUNT_SPM_LSB                                                                  0x4de4
9604 #define mmRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX                                                         1
9605 #define mmRLC_GPU_CLOCK_COUNT_SPM_MSB                                                                  0x4de5
9606 #define mmRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX                                                         1
9607 #define mmRLC_SPM_THREAD_TRACE_CTRL                                                                    0x4de6
9608 #define mmRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX                                                           1
9609 #define mmRLC_LB_CNTR_2                                                                                0x4de7
9610 #define mmRLC_LB_CNTR_2_BASE_IDX                                                                       1
9611 #define mmRLC_CPAXI_DOORBELL_MON_CTRL                                                                  0x4df1
9612 #define mmRLC_CPAXI_DOORBELL_MON_CTRL_BASE_IDX                                                         1
9613 #define mmRLC_CPAXI_DOORBELL_MON_STAT                                                                  0x4df2
9614 #define mmRLC_CPAXI_DOORBELL_MON_STAT_BASE_IDX                                                         1
9615 #define mmRLC_CPAXI_DOORBELL_MON_DATA_LSB                                                              0x4df3
9616 #define mmRLC_CPAXI_DOORBELL_MON_DATA_LSB_BASE_IDX                                                     1
9617 #define mmRLC_CPAXI_DOORBELL_MON_DATA_MSB                                                              0x4df4
9618 #define mmRLC_CPAXI_DOORBELL_MON_DATA_MSB_BASE_IDX                                                     1
9619 #define mmRLC_XT_DOORBELL_RANGE                                                                        0x4df5
9620 #define mmRLC_XT_DOORBELL_RANGE_BASE_IDX                                                               1
9621 #define mmRLC_XT_DOORBELL_CNTL                                                                         0x4df6
9622 #define mmRLC_XT_DOORBELL_CNTL_BASE_IDX                                                                1
9623 #define mmRLC_XT_DOORBELL_STAT                                                                         0x4df7
9624 #define mmRLC_XT_DOORBELL_STAT_BASE_IDX                                                                1
9625 #define mmRLC_XT_DOORBELL_0_DATA_LO                                                                    0x4df8
9626 #define mmRLC_XT_DOORBELL_0_DATA_LO_BASE_IDX                                                           1
9627 #define mmRLC_XT_DOORBELL_0_DATA_HI                                                                    0x4df9
9628 #define mmRLC_XT_DOORBELL_0_DATA_HI_BASE_IDX                                                           1
9629 #define mmRLC_XT_DOORBELL_1_DATA_LO                                                                    0x4dfa
9630 #define mmRLC_XT_DOORBELL_1_DATA_LO_BASE_IDX                                                           1
9631 #define mmRLC_XT_DOORBELL_1_DATA_HI                                                                    0x4dfb
9632 #define mmRLC_XT_DOORBELL_1_DATA_HI_BASE_IDX                                                           1
9633 #define mmRLC_XT_DOORBELL_2_DATA_LO                                                                    0x4dfc
9634 #define mmRLC_XT_DOORBELL_2_DATA_LO_BASE_IDX                                                           1
9635 #define mmRLC_XT_DOORBELL_2_DATA_HI                                                                    0x4dfd
9636 #define mmRLC_XT_DOORBELL_2_DATA_HI_BASE_IDX                                                           1
9637 #define mmRLC_XT_DOORBELL_3_DATA_LO                                                                    0x4dfe
9638 #define mmRLC_XT_DOORBELL_3_DATA_LO_BASE_IDX                                                           1
9639 #define mmRLC_XT_DOORBELL_3_DATA_HI                                                                    0x4dff
9640 #define mmRLC_XT_DOORBELL_3_DATA_HI_BASE_IDX                                                           1
9641 
9642 
9643 // addressBlock: gc_rlcrdec
9644 // base address: 0x3b800
9645 #define mmRLC_SPP_CAM_ADDR                                                                             0x4e00
9646 #define mmRLC_SPP_CAM_ADDR_BASE_IDX                                                                    1
9647 #define mmRLC_SPP_CAM_DATA                                                                             0x4e01
9648 #define mmRLC_SPP_CAM_DATA_BASE_IDX                                                                    1
9649 #define mmRLC_SPP_CAM_EXT_ADDR                                                                         0x4e02
9650 #define mmRLC_SPP_CAM_EXT_ADDR_BASE_IDX                                                                1
9651 #define mmRLC_SPP_CAM_EXT_DATA                                                                         0x4e03
9652 #define mmRLC_SPP_CAM_EXT_DATA_BASE_IDX                                                                1
9653 #define mmRLC_PACE_SCRATCH_ADDR                                                                        0x4e04
9654 #define mmRLC_PACE_SCRATCH_ADDR_BASE_IDX                                                               1
9655 #define mmRLC_PACE_SCRATCH_DATA                                                                        0x4e05
9656 #define mmRLC_PACE_SCRATCH_DATA_BASE_IDX                                                               1
9657 
9658 
9659 // addressBlock: gc_rlcsdec
9660 // base address: 0x3b980
9661 #define mmRLC_RLCS_DEC_START                                                                           0x4e60
9662 #define mmRLC_RLCS_DEC_START_BASE_IDX                                                                  1
9663 #define mmRLC_RLCS_DEC_DUMP_ADDR                                                                       0x4e61
9664 #define mmRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX                                                              1
9665 #define mmRLC_RLCS_EXCEPTION_REG_1                                                                     0x4e62
9666 #define mmRLC_RLCS_EXCEPTION_REG_1_BASE_IDX                                                            1
9667 #define mmRLC_RLCS_EXCEPTION_REG_2                                                                     0x4e63
9668 #define mmRLC_RLCS_EXCEPTION_REG_2_BASE_IDX                                                            1
9669 #define mmRLC_RLCS_EXCEPTION_REG_3                                                                     0x4e64
9670 #define mmRLC_RLCS_EXCEPTION_REG_3_BASE_IDX                                                            1
9671 #define mmRLC_RLCS_EXCEPTION_REG_4                                                                     0x4e65
9672 #define mmRLC_RLCS_EXCEPTION_REG_4_BASE_IDX                                                            1
9673 #define mmRLC_RLCS_GENERAL_6                                                                           0x4e66
9674 #define mmRLC_RLCS_GENERAL_6_BASE_IDX                                                                  1
9675 #define mmRLC_RLCS_GENERAL_7                                                                           0x4e67
9676 #define mmRLC_RLCS_GENERAL_7_BASE_IDX                                                                  1
9677 #define mmRLC_RLCS_CGCG_REQUEST                                                                        0x4e68
9678 #define mmRLC_RLCS_CGCG_REQUEST_BASE_IDX                                                               1
9679 #define mmRLC_RLCS_CGCG_STATUS                                                                         0x4e69
9680 #define mmRLC_RLCS_CGCG_STATUS_BASE_IDX                                                                1
9681 #define mmRLC_RLCS_SMU_GFXCLK_STATUS                                                                   0x4e6a
9682 #define mmRLC_RLCS_SMU_GFXCLK_STATUS_BASE_IDX                                                          1
9683 #define mmRLC_RLCS_SMU_GFXCLK_CONTROL                                                                  0x4e6b
9684 #define mmRLC_RLCS_SMU_GFXCLK_CONTROL_BASE_IDX                                                         1
9685 #define mmRLC_RLCS_SOC_DS_CNTL                                                                         0x4e6c
9686 #define mmRLC_RLCS_SOC_DS_CNTL_BASE_IDX                                                                1
9687 #define mmRLC_RLCS_GFX_DS_CNTL                                                                         0x4e6d
9688 #define mmRLC_RLCS_GFX_DS_CNTL_BASE_IDX                                                                1
9689 #define mmRLC_GPM_STAT                                                                                 0x4e6e
9690 #define mmRLC_GPM_STAT_BASE_IDX                                                                        1
9691 #define mmRLC_RLCS_GPM_STAT                                                                            0x4e6e
9692 #define mmRLC_RLCS_GPM_STAT_BASE_IDX                                                                   1
9693 #define mmRLC_RLCS_ABORTED_PD_SEQUENCE                                                                 0x4e6f
9694 #define mmRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX                                                        1
9695 #define mmRLC_RLCS_DIDT_FORCE_STALL                                                                    0x4e70
9696 #define mmRLC_RLCS_DIDT_FORCE_STALL_BASE_IDX                                                           1
9697 #define mmRLC_RLCS_IOV_CMD_STATUS                                                                      0x4e71
9698 #define mmRLC_RLCS_IOV_CMD_STATUS_BASE_IDX                                                             1
9699 #define mmRLC_RLCS_IOV_CNTX_LOC_SIZE                                                                   0x4e72
9700 #define mmRLC_RLCS_IOV_CNTX_LOC_SIZE_BASE_IDX                                                          1
9701 #define mmRLC_RLCS_IOV_SCH_BLOCK                                                                       0x4e73
9702 #define mmRLC_RLCS_IOV_SCH_BLOCK_BASE_IDX                                                              1
9703 #define mmRLC_RLCS_IOV_VM_BUSY_STATUS                                                                  0x4e74
9704 #define mmRLC_RLCS_IOV_VM_BUSY_STATUS_BASE_IDX                                                         1
9705 #define mmRLC_RLCS_GPM_STAT_2                                                                          0x4e75
9706 #define mmRLC_RLCS_GPM_STAT_2_BASE_IDX                                                                 1
9707 #define mmRLC_RLCS_GRBM_SOFT_RESET                                                                     0x4e76
9708 #define mmRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX                                                            1
9709 #define mmRLC_RLCS_PG_CHANGE_STATUS                                                                    0x4e77
9710 #define mmRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX                                                           1
9711 #define mmRLC_RLCS_PG_CHANGE_READ                                                                      0x4e78
9712 #define mmRLC_RLCS_PG_CHANGE_READ_BASE_IDX                                                             1
9713 #define mmRLC_RLCS_LB_STATUS                                                                           0x4e79
9714 #define mmRLC_RLCS_LB_STATUS_BASE_IDX                                                                  1
9715 #define mmRLC_RLCS_LB_READ                                                                             0x4e7a
9716 #define mmRLC_RLCS_LB_READ_BASE_IDX                                                                    1
9717 #define mmRLC_RLCS_LB_CONTROL                                                                          0x4e7b
9718 #define mmRLC_RLCS_LB_CONTROL_BASE_IDX                                                                 1
9719 #define mmRLC_RLCS_IH_SEMAPHORE                                                                        0x4e7c
9720 #define mmRLC_RLCS_IH_SEMAPHORE_BASE_IDX                                                               1
9721 #define mmRLC_RLCS_IH_COOKIE_SEMAPHORE                                                                 0x4e7d
9722 #define mmRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX                                                        1
9723 #define mmRLC_RLCS_IH_CTRL_1                                                                           0x4e7e
9724 #define mmRLC_RLCS_IH_CTRL_1_BASE_IDX                                                                  1
9725 #define mmRLC_RLCS_IH_CTRL_2                                                                           0x4e7f
9726 #define mmRLC_RLCS_IH_CTRL_2_BASE_IDX                                                                  1
9727 #define mmRLC_RLCS_IH_CTRL_3                                                                           0x4e80
9728 #define mmRLC_RLCS_IH_CTRL_3_BASE_IDX                                                                  1
9729 #define mmRLC_RLCS_IH_STATUS                                                                           0x4e81
9730 #define mmRLC_RLCS_IH_STATUS_BASE_IDX                                                                  1
9731 #define mmRLC_RLCS_WGP_STATUS                                                                          0x4e82
9732 #define mmRLC_RLCS_WGP_STATUS_BASE_IDX                                                                 1
9733 #define mmRLC_RLCS_WGP_READ                                                                            0x4e83
9734 #define mmRLC_RLCS_WGP_READ_BASE_IDX                                                                   1
9735 #define mmRLC_RLCS_CP_INT_CTRL_1                                                                       0x4e84
9736 #define mmRLC_RLCS_CP_INT_CTRL_1_BASE_IDX                                                              1
9737 #define mmRLC_RLCS_CP_INT_CTRL_2                                                                       0x4e85
9738 #define mmRLC_RLCS_CP_INT_CTRL_2_BASE_IDX                                                              1
9739 #define mmRLC_RLCS_CP_INT_INFO_1                                                                       0x4e86
9740 #define mmRLC_RLCS_CP_INT_INFO_1_BASE_IDX                                                              1
9741 #define mmRLC_RLCS_CP_INT_INFO_2                                                                       0x4e87
9742 #define mmRLC_RLCS_CP_INT_INFO_2_BASE_IDX                                                              1
9743 #define mmRLC_RLCS_SPM_INT_CTRL                                                                        0x4e88
9744 #define mmRLC_RLCS_SPM_INT_CTRL_BASE_IDX                                                               1
9745 #define mmRLC_RLCS_SPM_INT_INFO_1                                                                      0x4e89
9746 #define mmRLC_RLCS_SPM_INT_INFO_1_BASE_IDX                                                             1
9747 #define mmRLC_RLCS_SPM_INT_INFO_2                                                                      0x4e8a
9748 #define mmRLC_RLCS_SPM_INT_INFO_2_BASE_IDX                                                             1
9749 #define mmRLC_RLCS_DSM_TRIG                                                                            0x4e8b
9750 #define mmRLC_RLCS_DSM_TRIG_BASE_IDX                                                                   1
9751 #define mmRLC_RLCS_BOOTLOAD_STATUS                                                                     0x4e8d
9752 #define mmRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX                                                            1
9753 #define mmRLC_RLCS_POWER_BRAKE_CNTL                                                                    0x4e8e
9754 #define mmRLC_RLCS_POWER_BRAKE_CNTL_BASE_IDX                                                           1
9755 #define mmRLC_RLCS_GENERAL_0                                                                           0x4e8f
9756 #define mmRLC_RLCS_GENERAL_0_BASE_IDX                                                                  1
9757 #define mmRLC_RLCS_GENERAL_1                                                                           0x4e90
9758 #define mmRLC_RLCS_GENERAL_1_BASE_IDX                                                                  1
9759 #define mmRLC_RLCS_GENERAL_2                                                                           0x4e91
9760 #define mmRLC_RLCS_GENERAL_2_BASE_IDX                                                                  1
9761 #define mmRLC_RLCS_GENERAL_3                                                                           0x4e92
9762 #define mmRLC_RLCS_GENERAL_3_BASE_IDX                                                                  1
9763 #define mmRLC_RLCS_GENERAL_4                                                                           0x4e93
9764 #define mmRLC_RLCS_GENERAL_4_BASE_IDX                                                                  1
9765 #define mmRLC_RLCS_GENERAL_5                                                                           0x4e94
9766 #define mmRLC_RLCS_GENERAL_5_BASE_IDX                                                                  1
9767 #define mmRLC_RLCS_GRBM_IDLE_BUSY_STAT                                                                 0x4ec1
9768 #define mmRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX                                                        1
9769 #define mmRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL                                                             0x4ec2
9770 #define mmRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX                                                    1
9771 #define mmRLC_RLCS_CMP_IDLE_CNTL                                                                       0x4ec3
9772 #define mmRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX                                                              1
9773 #define mmRLC_RLCS_POWER_BRAKE_CNTL_TH1                                                                0x4ec4
9774 #define mmRLC_RLCS_POWER_BRAKE_CNTL_TH1_BASE_IDX                                                       1
9775 #define mmRLC_RLCS_AUXILIARY_REG_1                                                                     0x4ec5
9776 #define mmRLC_RLCS_AUXILIARY_REG_1_BASE_IDX                                                            1
9777 #define mmRLC_RLCS_AUXILIARY_REG_2                                                                     0x4ec6
9778 #define mmRLC_RLCS_AUXILIARY_REG_2_BASE_IDX                                                            1
9779 #define mmRLC_RLCS_AUXILIARY_REG_3                                                                     0x4ec7
9780 #define mmRLC_RLCS_AUXILIARY_REG_3_BASE_IDX                                                            1
9781 #define mmRLC_RLCS_AUXILIARY_REG_4                                                                     0x4ec8
9782 #define mmRLC_RLCS_AUXILIARY_REG_4_BASE_IDX                                                            1
9783 #define mmRLC_RLCS_SPM_SQTT_MODE                                                                       0x4ee0
9784 #define mmRLC_RLCS_SPM_SQTT_MODE_BASE_IDX                                                              1
9785 #define mmRLC_RLCS_CP_DMA_SRCID_OVER                                                                   0x4ee4
9786 #define mmRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX                                                          1
9787 #define mmRLC_RLCS_UTCL2_CNTL                                                                          0x4ee6
9788 #define mmRLC_RLCS_UTCL2_CNTL_BASE_IDX                                                                 1
9789 #define mmRLC_RLCS_MP1_RLC_DOORBELL_CTRL                                                               0x4ee8
9790 #define mmRLC_RLCS_MP1_RLC_DOORBELL_CTRL_BASE_IDX                                                      1
9791 #define mmRLC_RLCS_BOOTLOAD_ID_STATUS1                                                                 0x4eec
9792 #define mmRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX                                                        1
9793 #define mmRLC_RLCS_BOOTLOAD_ID_STATUS2                                                                 0x4eed
9794 #define mmRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX                                                        1
9795 #define mmRLC_RLCS_SMUIO_VIDCHG_CTRL                                                                   0x4eee
9796 #define mmRLC_RLCS_SMUIO_VIDCHG_CTRL_BASE_IDX                                                          1
9797 #define mmRLC_RLCS_EDC_INT_CNTL                                                                        0x4eef
9798 #define mmRLC_RLCS_EDC_INT_CNTL_BASE_IDX                                                               1
9799 #define mmRLC_RLCS_KMD_LOG_CNTL1                                                                       0x4ef1
9800 #define mmRLC_RLCS_KMD_LOG_CNTL1_BASE_IDX                                                              1
9801 #define mmRLC_RLCS_KMD_LOG_CNTL2                                                                       0x4ef2
9802 #define mmRLC_RLCS_KMD_LOG_CNTL2_BASE_IDX                                                              1
9803 #define mmRLC_RLCS_GPM_LEGACY_INT_STAT                                                                 0x4ef3
9804 #define mmRLC_RLCS_GPM_LEGACY_INT_STAT_BASE_IDX                                                        1
9805 #define mmRLC_RLCS_GPM_LEGACY_INT_DISABLE                                                              0x4ef4
9806 #define mmRLC_RLCS_GPM_LEGACY_INT_DISABLE_BASE_IDX                                                     1
9807 #define mmRLC_RLCS_SRM_SRCID_CNTL                                                                      0x4efd
9808 #define mmRLC_RLCS_SRM_SRCID_CNTL_BASE_IDX                                                             1
9809 #define mmRLC_RLCS_PERFMON_CLK_CNTL_UCODE                                                              0x4f03
9810 #define mmRLC_RLCS_PERFMON_CLK_CNTL_UCODE_BASE_IDX                                                     1
9811 #define mmRLC_RLCS_DEC_END                                                                             0x4fff
9812 #define mmRLC_RLCS_DEC_END_BASE_IDX                                                                    1
9813 
9814 
9815 // addressBlock: gc_pwrdec
9816 // base address: 0x3c000
9817 #define mmCGTS_RD_CTRL_REG                                                                             0x5004
9818 #define mmCGTS_RD_CTRL_REG_BASE_IDX                                                                    1
9819 #define mmCGTS_RD_REG                                                                                  0x5005
9820 #define mmCGTS_RD_REG_BASE_IDX                                                                         1
9821 #define mmCGTS_TCC_DISABLE                                                                             0x5006
9822 #define mmCGTS_TCC_DISABLE_BASE_IDX                                                                    1
9823 #define mmCGTS_USER_TCC_DISABLE                                                                        0x5007
9824 #define mmCGTS_USER_TCC_DISABLE_BASE_IDX                                                               1
9825 #define mmCGTS_STATUS_REG                                                                              0x5008
9826 #define mmCGTS_STATUS_REG_BASE_IDX                                                                     1
9827 #define mmCGTT_SPI_CGTSSM_CLK_CTRL                                                                     0x5009
9828 #define mmCGTT_SPI_CGTSSM_CLK_CTRL_BASE_IDX                                                            1
9829 #define mmCGTT_SPI_PS_CLK_CTRL                                                                         0x507d
9830 #define mmCGTT_SPI_PS_CLK_CTRL_BASE_IDX                                                                1
9831 #define mmCGTT_SPIS_CLK_CTRL                                                                           0x507e
9832 #define mmCGTT_SPIS_CLK_CTRL_BASE_IDX                                                                  1
9833 #define mmCGTT_SPI_CLK_CTRL                                                                            0x5080
9834 #define mmCGTT_SPI_CLK_CTRL_BASE_IDX                                                                   1
9835 #define mmCGTT_PC_CLK_CTRL                                                                             0x5081
9836 #define mmCGTT_PC_CLK_CTRL_BASE_IDX                                                                    1
9837 #define mmCGTT_BCI_CLK_CTRL                                                                            0x5082
9838 #define mmCGTT_BCI_CLK_CTRL_BASE_IDX                                                                   1
9839 #define mmCGTT_VGT_CLK_CTRL                                                                            0x5084
9840 #define mmCGTT_VGT_CLK_CTRL_BASE_IDX                                                                   1
9841 #define mmCGTT_IA_CLK_CTRL                                                                             0x5085
9842 #define mmCGTT_IA_CLK_CTRL_BASE_IDX                                                                    1
9843 #define mmCGTT_WD_CLK_CTRL                                                                             0x5086
9844 #define mmCGTT_WD_CLK_CTRL_BASE_IDX                                                                    1
9845 #define mmCGTT_GS_NGG_CLK_CTRL                                                                         0x5087
9846 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX                                                                1
9847 #define mmCGTT_PA_CLK_CTRL                                                                             0x5088
9848 #define mmCGTT_PA_CLK_CTRL_BASE_IDX                                                                    1
9849 #define mmCGTT_SC_CLK_CTRL0                                                                            0x5089
9850 #define mmCGTT_SC_CLK_CTRL0_BASE_IDX                                                                   1
9851 #define mmCGTT_SC_CLK_CTRL1                                                                            0x508a
9852 #define mmCGTT_SC_CLK_CTRL1_BASE_IDX                                                                   1
9853 #define mmCGTT_SC_CLK_CTRL2                                                                            0x508b
9854 #define mmCGTT_SC_CLK_CTRL2_BASE_IDX                                                                   1
9855 #define mmCGTT_SQ_CLK_CTRL                                                                             0x508c
9856 #define mmCGTT_SQ_CLK_CTRL_BASE_IDX                                                                    1
9857 #define mmCGTT_SQG_CLK_CTRL                                                                            0x508d
9858 #define mmCGTT_SQG_CLK_CTRL_BASE_IDX                                                                   1
9859 #define mmSQ_ALU_CLK_CTRL                                                                              0x508e
9860 #define mmSQ_ALU_CLK_CTRL_BASE_IDX                                                                     1
9861 #define mmSQ_TEX_CLK_CTRL                                                                              0x508f
9862 #define mmSQ_TEX_CLK_CTRL_BASE_IDX                                                                     1
9863 #define mmSQ_LDS_CLK_CTRL                                                                              0x5090
9864 #define mmSQ_LDS_CLK_CTRL_BASE_IDX                                                                     1
9865 #define mmCGTT_SX_CLK_CTRL0                                                                            0x5094
9866 #define mmCGTT_SX_CLK_CTRL0_BASE_IDX                                                                   1
9867 #define mmCGTT_SX_CLK_CTRL1                                                                            0x5095
9868 #define mmCGTT_SX_CLK_CTRL1_BASE_IDX                                                                   1
9869 #define mmCGTT_SX_CLK_CTRL2                                                                            0x5096
9870 #define mmCGTT_SX_CLK_CTRL2_BASE_IDX                                                                   1
9871 #define mmCGTT_SX_CLK_CTRL3                                                                            0x5097
9872 #define mmCGTT_SX_CLK_CTRL3_BASE_IDX                                                                   1
9873 #define mmCGTT_SX_CLK_CTRL4                                                                            0x5098
9874 #define mmCGTT_SX_CLK_CTRL4_BASE_IDX                                                                   1
9875 #define mmTD_CGTT_CTRL                                                                                 0x509c
9876 #define mmTD_CGTT_CTRL_BASE_IDX                                                                        1
9877 #define mmTA_CGTT_CTRL                                                                                 0x509d
9878 #define mmTA_CGTT_CTRL_BASE_IDX                                                                        1
9879 #define mmCGTT_TCPI_CLK_CTRL                                                                           0x5109
9880 #define mmCGTT_TCPI_CLK_CTRL_BASE_IDX                                                                  1
9881 #define mmCGTT_GDS_CLK_CTRL                                                                            0x50a0
9882 #define mmCGTT_GDS_CLK_CTRL_BASE_IDX                                                                   1
9883 #define mmDB_CGTT_CLK_CTRL_0                                                                           0x50a4
9884 #define mmDB_CGTT_CLK_CTRL_0_BASE_IDX                                                                  1
9885 #define mmCB_CGTT_SCLK_CTRL                                                                            0x50a8
9886 #define mmCB_CGTT_SCLK_CTRL_BASE_IDX                                                                   1
9887 #define mmGL2C_CGTT_SCLK_CTRL                                                                          0x50fc
9888 #define mmGL2C_CGTT_SCLK_CTRL_BASE_IDX                                                                 1
9889 #define mmGL2A_CGTT_SCLK_CTRL                                                                          0x50ac
9890 #define mmGL2A_CGTT_SCLK_CTRL_BASE_IDX                                                                 1
9891 #define mmGL2A_CGTT_SCLK_CTRL_1                                                                        0x50ad
9892 #define mmGL2A_CGTT_SCLK_CTRL_1_BASE_IDX                                                               1
9893 #define mmCGTT_CP_CLK_CTRL                                                                             0x50b0
9894 #define mmCGTT_CP_CLK_CTRL_BASE_IDX                                                                    1
9895 #define mmCGTT_CPF_CLK_CTRL                                                                            0x50b1
9896 #define mmCGTT_CPF_CLK_CTRL_BASE_IDX                                                                   1
9897 #define mmCGTT_CPC_CLK_CTRL                                                                            0x50b2
9898 #define mmCGTT_CPC_CLK_CTRL_BASE_IDX                                                                   1
9899 #define mmCGTT_RLC_CLK_CTRL                                                                            0x50b5
9900 #define mmCGTT_RLC_CLK_CTRL_BASE_IDX                                                                   1
9901 #define mmRLC_GFX_RM_CNTL                                                                              0x50b6
9902 #define mmRLC_GFX_RM_CNTL_BASE_IDX                                                                     1
9903 #define mmRMI_CGTT_SCLK_CTRL                                                                           0x50c0
9904 #define mmRMI_CGTT_SCLK_CTRL_BASE_IDX                                                                  1
9905 #define mmCGTT_TCPF_CLK_CTRL                                                                           0x5111
9906 #define mmCGTT_TCPF_CLK_CTRL_BASE_IDX                                                                  1
9907 #define mmGCR_CGTT_SCLK_CTRL                                                                           0x50c2
9908 #define mmGCR_CGTT_SCLK_CTRL_BASE_IDX                                                                  1
9909 #define mmUTCL1_CGTT_CLK_CTRL                                                                          0x50c3
9910 #define mmUTCL1_CGTT_CLK_CTRL_BASE_IDX                                                                 1
9911 #define mmGCEA_CGTT_CLK_CTRL                                                                           0x50c4
9912 #define mmGCEA_CGTT_CLK_CTRL_BASE_IDX                                                                  1
9913 #define mmSE_CAC_CGTT_CLK_CTRL                                                                         0x50d0
9914 #define mmSE_CAC_CGTT_CLK_CTRL_BASE_IDX                                                                1
9915 #define mmGC_CAC_CGTT_CLK_CTRL                                                                         0x50d8
9916 #define mmGC_CAC_CGTT_CLK_CTRL_BASE_IDX                                                                1
9917 #define mmGRBM_CGTT_CLK_CNTL                                                                           0x50e0
9918 #define mmGRBM_CGTT_CLK_CNTL_BASE_IDX                                                                  1
9919 #define mmGUS_CGTT_CLK_CTRL                                                                            0x50f4
9920 #define mmGUS_CGTT_CLK_CTRL_BASE_IDX                                                                   1
9921 #define mmCGTT_PH_CLK_CTRL0                                                                            0x50f8
9922 #define mmCGTT_PH_CLK_CTRL0_BASE_IDX                                                                   1
9923 #define mmCGTT_PH_CLK_CTRL1                                                                            0x50f9
9924 #define mmCGTT_PH_CLK_CTRL1_BASE_IDX                                                                   1
9925 #define mmCGTT_PH_CLK_CTRL2                                                                            0x50fa
9926 #define mmCGTT_PH_CLK_CTRL2_BASE_IDX                                                                   1
9927 #define mmCGTT_PH_CLK_CTRL3                                                                            0x50fb
9928 #define mmCGTT_PH_CLK_CTRL3_BASE_IDX                                                                   1
9929 
9930 
9931 // addressBlock: gc_hypdec
9932 // base address: 0x3e000
9933 #define mmCP_HYP_PFP_UCODE_ADDR                                                                        0x5814
9934 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX                                                               1
9935 #define mmCP_PFP_UCODE_ADDR                                                                            0x5814
9936 #define mmCP_PFP_UCODE_ADDR_BASE_IDX                                                                   1
9937 #define mmCP_HYP_PFP_UCODE_DATA                                                                        0x5815
9938 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX                                                               1
9939 #define mmCP_PFP_UCODE_DATA                                                                            0x5815
9940 #define mmCP_PFP_UCODE_DATA_BASE_IDX                                                                   1
9941 #define mmCP_HYP_ME_UCODE_ADDR                                                                         0x5816
9942 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX                                                                1
9943 #define mmCP_ME_RAM_RADDR                                                                              0x5816
9944 #define mmCP_ME_RAM_RADDR_BASE_IDX                                                                     1
9945 #define mmCP_ME_RAM_WADDR                                                                              0x5816
9946 #define mmCP_ME_RAM_WADDR_BASE_IDX                                                                     1
9947 #define mmCP_HYP_ME_UCODE_DATA                                                                         0x5817
9948 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX                                                                1
9949 #define mmCP_ME_RAM_DATA                                                                               0x5817
9950 #define mmCP_ME_RAM_DATA_BASE_IDX                                                                      1
9951 #define mmCP_CE_UCODE_ADDR                                                                             0x5818
9952 #define mmCP_CE_UCODE_ADDR_BASE_IDX                                                                    1
9953 #define mmCP_HYP_CE_UCODE_ADDR                                                                         0x5818
9954 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX                                                                1
9955 #define mmCP_CE_UCODE_DATA                                                                             0x5819
9956 #define mmCP_CE_UCODE_DATA_BASE_IDX                                                                    1
9957 #define mmCP_HYP_CE_UCODE_DATA                                                                         0x5819
9958 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX                                                                1
9959 #define mmCP_HYP_MEC1_UCODE_ADDR                                                                       0x581a
9960 #define mmCP_HYP_MEC1_UCODE_ADDR_BASE_IDX                                                              1
9961 #define mmCP_MEC_ME1_UCODE_ADDR                                                                        0x581a
9962 #define mmCP_MEC_ME1_UCODE_ADDR_BASE_IDX                                                               1
9963 #define mmCP_HYP_MEC1_UCODE_DATA                                                                       0x581b
9964 #define mmCP_HYP_MEC1_UCODE_DATA_BASE_IDX                                                              1
9965 #define mmCP_MEC_ME1_UCODE_DATA                                                                        0x581b
9966 #define mmCP_MEC_ME1_UCODE_DATA_BASE_IDX                                                               1
9967 #define mmCP_HYP_MEC2_UCODE_ADDR                                                                       0x581c
9968 #define mmCP_HYP_MEC2_UCODE_ADDR_BASE_IDX                                                              1
9969 #define mmCP_MEC_ME2_UCODE_ADDR                                                                        0x581c
9970 #define mmCP_MEC_ME2_UCODE_ADDR_BASE_IDX                                                               1
9971 #define mmCP_HYP_MEC2_UCODE_DATA                                                                       0x581d
9972 #define mmCP_HYP_MEC2_UCODE_DATA_BASE_IDX                                                              1
9973 #define mmCP_MEC_ME2_UCODE_DATA                                                                        0x581d
9974 #define mmCP_MEC_ME2_UCODE_DATA_BASE_IDX                                                               1
9975 #define mmCP_PFP_IC_BASE_LO                                                                            0x5840
9976 #define mmCP_PFP_IC_BASE_LO_BASE_IDX                                                                   1
9977 #define mmCP_PFP_IC_BASE_HI                                                                            0x5841
9978 #define mmCP_PFP_IC_BASE_HI_BASE_IDX                                                                   1
9979 #define mmCP_PFP_IC_BASE_CNTL                                                                          0x5842
9980 #define mmCP_PFP_IC_BASE_CNTL_BASE_IDX                                                                 1
9981 #define mmCP_PFP_IC_OP_CNTL                                                                            0x5843
9982 #define mmCP_PFP_IC_OP_CNTL_BASE_IDX                                                                   1
9983 #define mmCP_ME_IC_BASE_LO                                                                             0x5844
9984 #define mmCP_ME_IC_BASE_LO_BASE_IDX                                                                    1
9985 #define mmCP_ME_IC_BASE_HI                                                                             0x5845
9986 #define mmCP_ME_IC_BASE_HI_BASE_IDX                                                                    1
9987 #define mmCP_ME_IC_BASE_CNTL                                                                           0x5846
9988 #define mmCP_ME_IC_BASE_CNTL_BASE_IDX                                                                  1
9989 #define mmCP_ME_IC_OP_CNTL                                                                             0x5847
9990 #define mmCP_ME_IC_OP_CNTL_BASE_IDX                                                                    1
9991 #define mmCP_CE_IC_BASE_LO                                                                             0x5848
9992 #define mmCP_CE_IC_BASE_LO_BASE_IDX                                                                    1
9993 #define mmCP_CE_IC_BASE_HI                                                                             0x5849
9994 #define mmCP_CE_IC_BASE_HI_BASE_IDX                                                                    1
9995 #define mmCP_CE_IC_BASE_CNTL                                                                           0x584a
9996 #define mmCP_CE_IC_BASE_CNTL_BASE_IDX                                                                  1
9997 #define mmCP_CE_IC_OP_CNTL                                                                             0x584b
9998 #define mmCP_CE_IC_OP_CNTL_BASE_IDX                                                                    1
9999 #define mmCP_CPC_IC_BASE_LO                                                                            0x584c
10000 #define mmCP_CPC_IC_BASE_LO_BASE_IDX                                                                   1
10001 #define mmCP_CPC_IC_BASE_HI                                                                            0x584d
10002 #define mmCP_CPC_IC_BASE_HI_BASE_IDX                                                                   1
10003 #define mmCP_CPC_IC_BASE_CNTL                                                                          0x584e
10004 #define mmCP_CPC_IC_BASE_CNTL_BASE_IDX                                                                 1
10005 #define mmCP_CPC_IC_OP_CNTL                                                                            0x584f
10006 #define mmCP_CPC_IC_OP_CNTL_BASE_IDX                                                                   1
10007 #define mmCP_MES_IC_BASE_LO                                                                            0x5850
10008 #define mmCP_MES_IC_BASE_LO_BASE_IDX                                                                   1
10009 #define mmCP_MES_MIBASE_LO                                                                             0x5850
10010 #define mmCP_MES_MIBASE_LO_BASE_IDX                                                                    1
10011 #define mmCP_MES_IC_BASE_HI                                                                            0x5851
10012 #define mmCP_MES_IC_BASE_HI_BASE_IDX                                                                   1
10013 #define mmCP_MES_MIBASE_HI                                                                             0x5851
10014 #define mmCP_MES_MIBASE_HI_BASE_IDX                                                                    1
10015 #define mmCP_MES_IC_BASE_CNTL                                                                          0x5852
10016 #define mmCP_MES_IC_BASE_CNTL_BASE_IDX                                                                 1
10017 #define mmCP_MES_DC_BASE_LO                                                                            0x5854
10018 #define mmCP_MES_DC_BASE_LO_BASE_IDX                                                                   1
10019 #define mmCP_MES_MDBASE_LO                                                                             0x5854
10020 #define mmCP_MES_MDBASE_LO_BASE_IDX                                                                    1
10021 #define mmCP_MES_DC_BASE_HI                                                                            0x5855
10022 #define mmCP_MES_DC_BASE_HI_BASE_IDX                                                                   1
10023 #define mmCP_MES_MDBASE_HI                                                                             0x5855
10024 #define mmCP_MES_MDBASE_HI_BASE_IDX                                                                    1
10025 #define mmCP_MES_LOCAL_BASE0_LO                                                                        0x5856
10026 #define mmCP_MES_LOCAL_BASE0_LO_BASE_IDX                                                               1
10027 #define mmCP_MES_LOCAL_BASE0_HI                                                                        0x5857
10028 #define mmCP_MES_LOCAL_BASE0_HI_BASE_IDX                                                               1
10029 #define mmCP_MES_LOCAL_MASK0_LO                                                                        0x5858
10030 #define mmCP_MES_LOCAL_MASK0_LO_BASE_IDX                                                               1
10031 #define mmCP_MES_LOCAL_MASK0_HI                                                                        0x5859
10032 #define mmCP_MES_LOCAL_MASK0_HI_BASE_IDX                                                               1
10033 #define mmCP_MES_LOCAL_APERTURE                                                                        0x585a
10034 #define mmCP_MES_LOCAL_APERTURE_BASE_IDX                                                               1
10035 #define mmCP_MES_MIBOUND_LO                                                                            0x585b
10036 #define mmCP_MES_MIBOUND_LO_BASE_IDX                                                                   1
10037 #define mmCP_MES_MIBOUND_HI                                                                            0x585c
10038 #define mmCP_MES_MIBOUND_HI_BASE_IDX                                                                   1
10039 #define mmCP_MES_MDBOUND_LO                                                                            0x585d
10040 #define mmCP_MES_MDBOUND_LO_BASE_IDX                                                                   1
10041 #define mmCP_MES_MDBOUND_HI                                                                            0x585e
10042 #define mmCP_MES_MDBOUND_HI_BASE_IDX                                                                   1
10043 #define mmGFX_PIPE_PRIORITY                                                                            0x587f
10044 #define mmGFX_PIPE_PRIORITY_BASE_IDX                                                                   1
10045 #define mmGRBM_GFX_INDEX_SR_SELECT                                                                     0x5a00
10046 #define mmGRBM_GFX_INDEX_SR_SELECT_BASE_IDX                                                            1
10047 #define mmGRBM_GFX_INDEX_SR_DATA                                                                       0x5a01
10048 #define mmGRBM_GFX_INDEX_SR_DATA_BASE_IDX                                                              1
10049 #define mmGRBM_GFX_CNTL_SR_SELECT                                                                      0x5a02
10050 #define mmGRBM_GFX_CNTL_SR_SELECT_BASE_IDX                                                             1
10051 #define mmGRBM_GFX_CNTL_SR_DATA                                                                        0x5a03
10052 #define mmGRBM_GFX_CNTL_SR_DATA_BASE_IDX                                                               1
10053 #define mmGRBM_CAM_INDEX                                                                               0x5a04
10054 #define mmGRBM_CAM_INDEX_BASE_IDX                                                                      1
10055 #define mmGRBM_HYP_CAM_INDEX                                                                           0x5a04
10056 #define mmGRBM_HYP_CAM_INDEX_BASE_IDX                                                                  1
10057 #define mmGRBM_CAM_DATA                                                                                0x5a05
10058 #define mmGRBM_CAM_DATA_BASE_IDX                                                                       1
10059 #define mmGRBM_HYP_CAM_DATA                                                                            0x5a05
10060 #define mmGRBM_HYP_CAM_DATA_BASE_IDX                                                                   1
10061 #define mmGRBM_CAM_DATA_UPPER                                                                          0x5a06
10062 #define mmGRBM_CAM_DATA_UPPER_BASE_IDX                                                                 1
10063 #define mmGRBM_HYP_CAM_DATA_UPPER                                                                      0x5a06
10064 #define mmGRBM_HYP_CAM_DATA_UPPER_BASE_IDX                                                             1
10065 #define mmGC_IH_COOKIE_0_PTR                                                                           0x5a07
10066 #define mmGC_IH_COOKIE_0_PTR_BASE_IDX                                                                  1
10067 #define mmGRBM_SE_REMAP_CNTL                                                                           0x5a08
10068 #define mmGRBM_SE_REMAP_CNTL_BASE_IDX                                                                  1
10069 #define mmRLC_GPU_IOV_VF_ENABLE                                                                        0x5b00
10070 #define mmRLC_GPU_IOV_VF_ENABLE_BASE_IDX                                                               1
10071 #define mmRLC_GPU_IOV_CFG_REG6                                                                         0x5b06
10072 #define mmRLC_GPU_IOV_CFG_REG6_BASE_IDX                                                                1
10073 #define mmRLC_SDMA0_STATUS                                                                             0x5b12
10074 #define mmRLC_SDMA0_STATUS_BASE_IDX                                                                    1
10075 #define mmRLC_SDMA1_STATUS                                                                             0x5b13
10076 #define mmRLC_SDMA1_STATUS_BASE_IDX                                                                    1
10077 #define mmRLC_SDMA2_STATUS                                                                             0x5b14
10078 #define mmRLC_SDMA2_STATUS_BASE_IDX                                                                    1
10079 #define mmRLC_SDMA3_STATUS                                                                             0x5b15
10080 #define mmRLC_SDMA3_STATUS_BASE_IDX                                                                    1
10081 #define mmRLC_SDMA0_BUSY_STATUS                                                                        0x5b16
10082 #define mmRLC_SDMA0_BUSY_STATUS_BASE_IDX                                                               1
10083 #define mmRLC_SDMA1_BUSY_STATUS                                                                        0x5b17
10084 #define mmRLC_SDMA1_BUSY_STATUS_BASE_IDX                                                               1
10085 #define mmRLC_SDMA2_BUSY_STATUS                                                                        0x5b18
10086 #define mmRLC_SDMA2_BUSY_STATUS_BASE_IDX                                                               1
10087 #define mmRLC_SDMA3_BUSY_STATUS                                                                        0x5b19
10088 #define mmRLC_SDMA3_BUSY_STATUS_BASE_IDX                                                               1
10089 #define mmRLC_GPU_IOV_CFG_REG8                                                                         0x5b20
10090 #define mmRLC_GPU_IOV_CFG_REG8_BASE_IDX                                                                1
10091 #define mmRLC_RLCV_TIMER_INT_0                                                                         0x5b25
10092 #define mmRLC_RLCV_TIMER_INT_0_BASE_IDX                                                                1
10093 #define mmRLC_RLCV_TIMER_CTRL                                                                          0x5b26
10094 #define mmRLC_RLCV_TIMER_CTRL_BASE_IDX                                                                 1
10095 #define mmRLC_RLCV_TIMER_STAT                                                                          0x5b27
10096 #define mmRLC_RLCV_TIMER_STAT_BASE_IDX                                                                 1
10097 #define mmRLC_GPU_IOV_VF_DOORBELL_STATUS                                                               0x5b2a
10098 #define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX                                                      1
10099 #define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET                                                           0x5b2b
10100 #define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX                                                  1
10101 #define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR                                                           0x5b2c
10102 #define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX                                                  1
10103 #define mmRLC_GPU_IOV_VF_MASK                                                                          0x5b2d
10104 #define mmRLC_GPU_IOV_VF_MASK_BASE_IDX                                                                 1
10105 #define mmRLC_HYP_SEMAPHORE_0                                                                          0x5b2e
10106 #define mmRLC_HYP_SEMAPHORE_0_BASE_IDX                                                                 1
10107 #define mmRLC_HYP_SEMAPHORE_1                                                                          0x5b2f
10108 #define mmRLC_HYP_SEMAPHORE_1_BASE_IDX                                                                 1
10109 #define mmRLC_BUSY_CLK_CNTL                                                                            0x5b30
10110 #define mmRLC_BUSY_CLK_CNTL_BASE_IDX                                                                   1
10111 #define mmRLC_CLK_CNTL                                                                                 0x5b31
10112 #define mmRLC_CLK_CNTL_BASE_IDX                                                                        1
10113 #define mmRLC_PACE_TIMER_STAT                                                                          0x5b33
10114 #define mmRLC_PACE_TIMER_STAT_BASE_IDX                                                                 1
10115 #define mmRLC_GPU_IOV_SCH_BLOCK                                                                        0x5b34
10116 #define mmRLC_GPU_IOV_SCH_BLOCK_BASE_IDX                                                               1
10117 #define mmRLC_GPU_IOV_CFG_REG1                                                                         0x5b35
10118 #define mmRLC_GPU_IOV_CFG_REG1_BASE_IDX                                                                1
10119 #define mmRLC_GPU_IOV_CFG_REG2                                                                         0x5b36
10120 #define mmRLC_GPU_IOV_CFG_REG2_BASE_IDX                                                                1
10121 #define mmRLC_GPU_IOV_VM_BUSY_STATUS                                                                   0x5b37
10122 #define mmRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX                                                          1
10123 #define mmRLC_GPU_IOV_SCH_0                                                                            0x5b38
10124 #define mmRLC_GPU_IOV_SCH_0_BASE_IDX                                                                   1
10125 #define mmRLC_GPU_IOV_ACTIVE_FCN_ID                                                                    0x5b39
10126 #define mmRLC_GPU_IOV_ACTIVE_FCN_ID_BASE_IDX                                                           1
10127 #define mmRLC_GPU_IOV_SCH_3                                                                            0x5b3a
10128 #define mmRLC_GPU_IOV_SCH_3_BASE_IDX                                                                   1
10129 #define mmRLC_GPU_IOV_SCH_1                                                                            0x5b3b
10130 #define mmRLC_GPU_IOV_SCH_1_BASE_IDX                                                                   1
10131 #define mmRLC_GPU_IOV_SCH_2                                                                            0x5b3c
10132 #define mmRLC_GPU_IOV_SCH_2_BASE_IDX                                                                   1
10133 #define mmRLC_PACE_INT_FORCE                                                                           0x5b3d
10134 #define mmRLC_PACE_INT_FORCE_BASE_IDX                                                                  1
10135 #define mmRLC_PACE_INT_CLEAR                                                                           0x5b3e
10136 #define mmRLC_PACE_INT_CLEAR_BASE_IDX                                                                  1
10137 #define mmRLC_GPU_IOV_INT_STAT                                                                         0x5b3f
10138 #define mmRLC_GPU_IOV_INT_STAT_BASE_IDX                                                                1
10139 #define mmRLC_RLCV_TIMER_INT_1                                                                         0x5b40
10140 #define mmRLC_RLCV_TIMER_INT_1_BASE_IDX                                                                1
10141 #define mmRLC_IH_COOKIE                                                                                0x5b41
10142 #define mmRLC_IH_COOKIE_BASE_IDX                                                                       1
10143 #define mmRLC_IH_COOKIE_CNTL                                                                           0x5b42
10144 #define mmRLC_IH_COOKIE_CNTL_BASE_IDX                                                                  1
10145 #define mmRLC_HYP_RLCG_UCODE_CHKSUM                                                                    0x5b43
10146 #define mmRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX                                                           1
10147 #define mmRLC_HYP_RLCP_UCODE_CHKSUM                                                                    0x5b44
10148 #define mmRLC_HYP_RLCP_UCODE_CHKSUM_BASE_IDX                                                           1
10149 #define mmRLC_HYP_RLCV_UCODE_CHKSUM                                                                    0x5b45
10150 #define mmRLC_HYP_RLCV_UCODE_CHKSUM_BASE_IDX                                                           1
10151 #define mmRLC_GPU_IOV_F32_CNTL                                                                         0x5b46
10152 #define mmRLC_GPU_IOV_F32_CNTL_BASE_IDX                                                                1
10153 #define mmRLC_GPU_IOV_F32_RESET                                                                        0x5b47
10154 #define mmRLC_GPU_IOV_F32_RESET_BASE_IDX                                                               1
10155 #define mmRLC_GPU_IOV_SMU_RESPONSE                                                                     0x5b4a
10156 #define mmRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX                                                            1
10157 #define mmRLC_GPU_IOV_VIRT_RESET_REQ                                                                   0x5b4c
10158 #define mmRLC_GPU_IOV_VIRT_RESET_REQ_BASE_IDX                                                          1
10159 #define mmRLC_GPU_IOV_RLC_RESPONSE                                                                     0x5b4d
10160 #define mmRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX                                                            1
10161 #define mmRLC_GPU_IOV_INT_DISABLE                                                                      0x5b4e
10162 #define mmRLC_GPU_IOV_INT_DISABLE_BASE_IDX                                                             1
10163 #define mmRLC_GPU_IOV_INT_FORCE                                                                        0x5b4f
10164 #define mmRLC_GPU_IOV_INT_FORCE_BASE_IDX                                                               1
10165 #define mmRLC_HYP_SEMAPHORE_2                                                                          0x5b52
10166 #define mmRLC_HYP_SEMAPHORE_2_BASE_IDX                                                                 1
10167 #define mmRLC_HYP_SEMAPHORE_3                                                                          0x5b53
10168 #define mmRLC_HYP_SEMAPHORE_3_BASE_IDX                                                                 1
10169 #define mmRLC_HYP_RESET_VECTOR                                                                         0x5b54
10170 #define mmRLC_HYP_RESET_VECTOR_BASE_IDX                                                                1
10171 #define mmRLC_HYP_BOOTLOAD_SIZE                                                                        0x5b5c
10172 #define mmRLC_HYP_BOOTLOAD_SIZE_BASE_IDX                                                               1
10173 #define mmRLC_HYP_BOOTLOAD_ADDR_LO                                                                     0x5b5d
10174 #define mmRLC_HYP_BOOTLOAD_ADDR_LO_BASE_IDX                                                            1
10175 #define mmRLC_HYP_BOOTLOAD_ADDR_HI                                                                     0x5b5e
10176 #define mmRLC_HYP_BOOTLOAD_ADDR_HI_BASE_IDX                                                            1
10177 #define mmRLC_GPM_IRAM_ADDR                                                                            0x5b5f
10178 #define mmRLC_GPM_IRAM_ADDR_BASE_IDX                                                                   1
10179 #define mmRLC_GPM_IRAM_DATA                                                                            0x5b60
10180 #define mmRLC_GPM_IRAM_DATA_BASE_IDX                                                                   1
10181 #define mmRLC_GPM_UCODE_ADDR                                                                           0x5b61
10182 #define mmRLC_GPM_UCODE_ADDR_BASE_IDX                                                                  1
10183 #define mmRLC_GPM_UCODE_DATA                                                                           0x5b62
10184 #define mmRLC_GPM_UCODE_DATA_BASE_IDX                                                                  1
10185 #define mmRLC_PACE_UCODE_ADDR                                                                          0x5b63
10186 #define mmRLC_PACE_UCODE_ADDR_BASE_IDX                                                                 1
10187 #define mmRLC_PACE_UCODE_DATA                                                                          0x5b64
10188 #define mmRLC_PACE_UCODE_DATA_BASE_IDX                                                                 1
10189 #define mmRLC_GPU_IOV_UCODE_ADDR                                                                       0x5b65
10190 #define mmRLC_GPU_IOV_UCODE_ADDR_BASE_IDX                                                              1
10191 #define mmRLC_GPU_IOV_UCODE_DATA                                                                       0x5b66
10192 #define mmRLC_GPU_IOV_UCODE_DATA_BASE_IDX                                                              1
10193 #define mmRLC_GPU_IOV_SCRATCH_ADDR                                                                     0x5b67
10194 #define mmRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX                                                            1
10195 #define mmRLC_GPU_IOV_SCRATCH_DATA                                                                     0x5b68
10196 #define mmRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX                                                            1
10197 #define mmRLC_RLCV_IRAM_ADDR                                                                           0x5b69
10198 #define mmRLC_RLCV_IRAM_ADDR_BASE_IDX                                                                  1
10199 #define mmRLC_RLCV_IRAM_DATA                                                                           0x5b6a
10200 #define mmRLC_RLCV_IRAM_DATA_BASE_IDX                                                                  1
10201 #define mmRLC_RLCP_IRAM_ADDR                                                                           0x5b6b
10202 #define mmRLC_RLCP_IRAM_ADDR_BASE_IDX                                                                  1
10203 #define mmRLC_RLCP_IRAM_DATA                                                                           0x5b6c
10204 #define mmRLC_RLCP_IRAM_DATA_BASE_IDX                                                                  1
10205 #define mmRLC_SRM_DRAM_ADDR                                                                            0x5b71
10206 #define mmRLC_SRM_DRAM_ADDR_BASE_IDX                                                                   1
10207 #define mmRLC_SRM_DRAM_DATA                                                                            0x5b72
10208 #define mmRLC_SRM_DRAM_DATA_BASE_IDX                                                                   1
10209 #define mmRLC_SRM_ARAM_ADDR                                                                            0x5b73
10210 #define mmRLC_SRM_ARAM_ADDR_BASE_IDX                                                                   1
10211 #define mmRLC_SRM_ARAM_DATA                                                                            0x5b74
10212 #define mmRLC_SRM_ARAM_DATA_BASE_IDX                                                                   1
10213 #define mmRLC_GPM_SCRATCH_ADDR                                                                         0x5b75
10214 #define mmRLC_GPM_SCRATCH_ADDR_BASE_IDX                                                                1
10215 #define mmRLC_GPM_SCRATCH_DATA                                                                         0x5b76
10216 #define mmRLC_GPM_SCRATCH_DATA_BASE_IDX                                                                1
10217 #define mmRLC_GTS_OFFSET_LSB                                                                           0x5b79
10218 #define mmRLC_GTS_OFFSET_LSB_BASE_IDX                                                                  1
10219 #define mmRLC_GTS_OFFSET_MSB                                                                           0x5b7a
10220 #define mmRLC_GTS_OFFSET_MSB_BASE_IDX                                                                  1
10221 #define mmRLC_GPU_IOV_SDMA0_STATUS                                                                     0x5bc0
10222 #define mmRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX                                                            1
10223 #define mmRLC_GPU_IOV_SDMA1_STATUS                                                                     0x5bc1
10224 #define mmRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX                                                            1
10225 #define mmRLC_GPU_IOV_SDMA2_STATUS                                                                     0x5bc2
10226 #define mmRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX                                                            1
10227 #define mmRLC_GPU_IOV_SDMA3_STATUS                                                                     0x5bc3
10228 #define mmRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX                                                            1
10229 #define mmRLC_GPU_IOV_SDMA4_STATUS                                                                     0x5bc4
10230 #define mmRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX                                                            1
10231 #define mmRLC_GPU_IOV_SDMA5_STATUS                                                                     0x5bc5
10232 #define mmRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX                                                            1
10233 #define mmRLC_GPU_IOV_SDMA6_STATUS                                                                     0x5bc6
10234 #define mmRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX                                                            1
10235 #define mmRLC_GPU_IOV_SDMA7_STATUS                                                                     0x5bc7
10236 #define mmRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX                                                            1
10237 #define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS                                                                0x5bc8
10238 #define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX                                                       1
10239 #define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS                                                                0x5bc9
10240 #define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX                                                       1
10241 #define mmRLC_GPU_IOV_SDMA2_BUSY_STATUS                                                                0x5bca
10242 #define mmRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX                                                       1
10243 #define mmRLC_GPU_IOV_SDMA3_BUSY_STATUS                                                                0x5bcb
10244 #define mmRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX                                                       1
10245 #define mmRLC_GPU_IOV_SDMA4_BUSY_STATUS                                                                0x5bcc
10246 #define mmRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX                                                       1
10247 #define mmRLC_GPU_IOV_SDMA5_BUSY_STATUS                                                                0x5bcd
10248 #define mmRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX                                                       1
10249 #define mmRLC_GPU_IOV_SDMA6_BUSY_STATUS                                                                0x5bce
10250 #define mmRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX                                                       1
10251 #define mmRLC_GPU_IOV_SDMA7_BUSY_STATUS                                                                0x5bcf
10252 #define mmRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX                                                       1
10253 
10254 
10255 // addressBlock: gc_sdma0_sdma0hypdec
10256 // base address: 0x3e200
10257 #define mmSDMA0_UCODE_ADDR                                                                             0x5880
10258 #define mmSDMA0_UCODE_ADDR_BASE_IDX                                                                    1
10259 #define mmSDMA0_UCODE_DATA                                                                             0x5881
10260 #define mmSDMA0_UCODE_DATA_BASE_IDX                                                                    1
10261 #define mmSDMA0_VM_CTX_LO                                                                              0x5882
10262 #define mmSDMA0_VM_CTX_LO_BASE_IDX                                                                     1
10263 #define mmSDMA0_VM_CTX_HI                                                                              0x5883
10264 #define mmSDMA0_VM_CTX_HI_BASE_IDX                                                                     1
10265 #define mmSDMA0_ACTIVE_FCN_ID                                                                          0x5884
10266 #define mmSDMA0_ACTIVE_FCN_ID_BASE_IDX                                                                 1
10267 #define mmSDMA0_VM_CTX_CNTL                                                                            0x5885
10268 #define mmSDMA0_VM_CTX_CNTL_BASE_IDX                                                                   1
10269 #define mmSDMA0_VIRT_RESET_REQ                                                                         0x5886
10270 #define mmSDMA0_VIRT_RESET_REQ_BASE_IDX                                                                1
10271 #define mmSDMA0_VF_ENABLE                                                                              0x5887
10272 #define mmSDMA0_VF_ENABLE_BASE_IDX                                                                     1
10273 #define mmSDMA0_CONTEXT_REG_TYPE0                                                                      0x5888
10274 #define mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX                                                             1
10275 #define mmSDMA0_CONTEXT_REG_TYPE1                                                                      0x5889
10276 #define mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX                                                             1
10277 #define mmSDMA0_CONTEXT_REG_TYPE2                                                                      0x588a
10278 #define mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX                                                             1
10279 #define mmSDMA0_CONTEXT_REG_TYPE3                                                                      0x588b
10280 #define mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX                                                             1
10281 #define mmSDMA0_PUB_REG_TYPE0                                                                          0x588c
10282 #define mmSDMA0_PUB_REG_TYPE0_BASE_IDX                                                                 1
10283 #define mmSDMA0_PUB_REG_TYPE1                                                                          0x588d
10284 #define mmSDMA0_PUB_REG_TYPE1_BASE_IDX                                                                 1
10285 #define mmSDMA0_PUB_REG_TYPE2                                                                          0x588e
10286 #define mmSDMA0_PUB_REG_TYPE2_BASE_IDX                                                                 1
10287 #define mmSDMA0_PUB_REG_TYPE3                                                                          0x588f
10288 #define mmSDMA0_PUB_REG_TYPE3_BASE_IDX                                                                 1
10289 #define mmSDMA0_VM_CNTL                                                                                0x5893
10290 #define mmSDMA0_VM_CNTL_BASE_IDX                                                                       1
10291 #define mmSDMA0_BROADCAST_UCODE_ADDR                                                                   0x589c
10292 #define mmSDMA0_BROADCAST_UCODE_ADDR_BASE_IDX                                                          1
10293 #define mmSDMA0_BROADCAST_UCODE_DATA                                                                   0x589d
10294 #define mmSDMA0_BROADCAST_UCODE_DATA_BASE_IDX                                                          1
10295 
10296 
10297 // addressBlock: gc_sdma1_sdma1hypdec
10298 // base address: 0x3e280
10299 #define mmSDMA1_UCODE_ADDR                                                                             0x58a0
10300 #define mmSDMA1_UCODE_ADDR_BASE_IDX                                                                    1
10301 #define mmSDMA1_UCODE_DATA                                                                             0x58a1
10302 #define mmSDMA1_UCODE_DATA_BASE_IDX                                                                    1
10303 #define mmSDMA1_VM_CTX_LO                                                                              0x58a2
10304 #define mmSDMA1_VM_CTX_LO_BASE_IDX                                                                     1
10305 #define mmSDMA1_VM_CTX_HI                                                                              0x58a3
10306 #define mmSDMA1_VM_CTX_HI_BASE_IDX                                                                     1
10307 #define mmSDMA1_ACTIVE_FCN_ID                                                                          0x58a4
10308 #define mmSDMA1_ACTIVE_FCN_ID_BASE_IDX                                                                 1
10309 #define mmSDMA1_VM_CTX_CNTL                                                                            0x58a5
10310 #define mmSDMA1_VM_CTX_CNTL_BASE_IDX                                                                   1
10311 #define mmSDMA1_VIRT_RESET_REQ                                                                         0x58a6
10312 #define mmSDMA1_VIRT_RESET_REQ_BASE_IDX                                                                1
10313 #define mmSDMA1_VF_ENABLE                                                                              0x58a7
10314 #define mmSDMA1_VF_ENABLE_BASE_IDX                                                                     1
10315 #define mmSDMA1_CONTEXT_REG_TYPE0                                                                      0x58a8
10316 #define mmSDMA1_CONTEXT_REG_TYPE0_BASE_IDX                                                             1
10317 #define mmSDMA1_CONTEXT_REG_TYPE1                                                                      0x58a9
10318 #define mmSDMA1_CONTEXT_REG_TYPE1_BASE_IDX                                                             1
10319 #define mmSDMA1_CONTEXT_REG_TYPE2                                                                      0x58aa
10320 #define mmSDMA1_CONTEXT_REG_TYPE2_BASE_IDX                                                             1
10321 #define mmSDMA1_CONTEXT_REG_TYPE3                                                                      0x58ab
10322 #define mmSDMA1_CONTEXT_REG_TYPE3_BASE_IDX                                                             1
10323 #define mmSDMA1_PUB_REG_TYPE0                                                                          0x58ac
10324 #define mmSDMA1_PUB_REG_TYPE0_BASE_IDX                                                                 1
10325 #define mmSDMA1_PUB_REG_TYPE1                                                                          0x58ad
10326 #define mmSDMA1_PUB_REG_TYPE1_BASE_IDX                                                                 1
10327 #define mmSDMA1_PUB_REG_TYPE2                                                                          0x58ae
10328 #define mmSDMA1_PUB_REG_TYPE2_BASE_IDX                                                                 1
10329 #define mmSDMA1_PUB_REG_TYPE3                                                                          0x58af
10330 #define mmSDMA1_PUB_REG_TYPE3_BASE_IDX                                                                 1
10331 #define mmSDMA1_VM_CNTL                                                                                0x58b3
10332 #define mmSDMA1_VM_CNTL_BASE_IDX                                                                       1
10333 
10334 
10335 // addressBlock: gc_sdma2_sdma2hypdec
10336 // base address: 0x3e300
10337 #define mmSDMA2_UCODE_ADDR                                                                             0x58c0
10338 #define mmSDMA2_UCODE_ADDR_BASE_IDX                                                                    1
10339 #define mmSDMA2_UCODE_DATA                                                                             0x58c1
10340 #define mmSDMA2_UCODE_DATA_BASE_IDX                                                                    1
10341 #define mmSDMA2_VM_CTX_LO                                                                              0x58c2
10342 #define mmSDMA2_VM_CTX_LO_BASE_IDX                                                                     1
10343 #define mmSDMA2_VM_CTX_HI                                                                              0x58c3
10344 #define mmSDMA2_VM_CTX_HI_BASE_IDX                                                                     1
10345 #define mmSDMA2_ACTIVE_FCN_ID                                                                          0x58c4
10346 #define mmSDMA2_ACTIVE_FCN_ID_BASE_IDX                                                                 1
10347 #define mmSDMA2_VM_CTX_CNTL                                                                            0x58c5
10348 #define mmSDMA2_VM_CTX_CNTL_BASE_IDX                                                                   1
10349 #define mmSDMA2_VIRT_RESET_REQ                                                                         0x58c6
10350 #define mmSDMA2_VIRT_RESET_REQ_BASE_IDX                                                                1
10351 #define mmSDMA2_VF_ENABLE                                                                              0x58c7
10352 #define mmSDMA2_VF_ENABLE_BASE_IDX                                                                     1
10353 #define mmSDMA2_CONTEXT_REG_TYPE0                                                                      0x58c8
10354 #define mmSDMA2_CONTEXT_REG_TYPE0_BASE_IDX                                                             1
10355 #define mmSDMA2_CONTEXT_REG_TYPE1                                                                      0x58c9
10356 #define mmSDMA2_CONTEXT_REG_TYPE1_BASE_IDX                                                             1
10357 #define mmSDMA2_CONTEXT_REG_TYPE2                                                                      0x58ca
10358 #define mmSDMA2_CONTEXT_REG_TYPE2_BASE_IDX                                                             1
10359 #define mmSDMA2_CONTEXT_REG_TYPE3                                                                      0x58cb
10360 #define mmSDMA2_CONTEXT_REG_TYPE3_BASE_IDX                                                             1
10361 #define mmSDMA2_PUB_REG_TYPE0                                                                          0x58cc
10362 #define mmSDMA2_PUB_REG_TYPE0_BASE_IDX                                                                 1
10363 #define mmSDMA2_PUB_REG_TYPE1                                                                          0x58cd
10364 #define mmSDMA2_PUB_REG_TYPE1_BASE_IDX                                                                 1
10365 #define mmSDMA2_PUB_REG_TYPE2                                                                          0x58ce
10366 #define mmSDMA2_PUB_REG_TYPE2_BASE_IDX                                                                 1
10367 #define mmSDMA2_PUB_REG_TYPE3                                                                          0x58cf
10368 #define mmSDMA2_PUB_REG_TYPE3_BASE_IDX                                                                 1
10369 #define mmSDMA2_VM_CNTL                                                                                0x58d3
10370 #define mmSDMA2_VM_CNTL_BASE_IDX                                                                       1
10371 
10372 
10373 // addressBlock: gc_sdma3_sdma3hypdec
10374 // base address: 0x3e380
10375 #define mmSDMA3_UCODE_ADDR                                                                             0x58e0
10376 #define mmSDMA3_UCODE_ADDR_BASE_IDX                                                                    1
10377 #define mmSDMA3_UCODE_DATA                                                                             0x58e1
10378 #define mmSDMA3_UCODE_DATA_BASE_IDX                                                                    1
10379 #define mmSDMA3_VM_CTX_LO                                                                              0x58e2
10380 #define mmSDMA3_VM_CTX_LO_BASE_IDX                                                                     1
10381 #define mmSDMA3_VM_CTX_HI                                                                              0x58e3
10382 #define mmSDMA3_VM_CTX_HI_BASE_IDX                                                                     1
10383 #define mmSDMA3_ACTIVE_FCN_ID                                                                          0x58e4
10384 #define mmSDMA3_ACTIVE_FCN_ID_BASE_IDX                                                                 1
10385 #define mmSDMA3_VM_CTX_CNTL                                                                            0x58e5
10386 #define mmSDMA3_VM_CTX_CNTL_BASE_IDX                                                                   1
10387 #define mmSDMA3_VIRT_RESET_REQ                                                                         0x58e6
10388 #define mmSDMA3_VIRT_RESET_REQ_BASE_IDX                                                                1
10389 #define mmSDMA3_VF_ENABLE                                                                              0x58e7
10390 #define mmSDMA3_VF_ENABLE_BASE_IDX                                                                     1
10391 #define mmSDMA3_CONTEXT_REG_TYPE0                                                                      0x58e8
10392 #define mmSDMA3_CONTEXT_REG_TYPE0_BASE_IDX                                                             1
10393 #define mmSDMA3_CONTEXT_REG_TYPE1                                                                      0x58e9
10394 #define mmSDMA3_CONTEXT_REG_TYPE1_BASE_IDX                                                             1
10395 #define mmSDMA3_CONTEXT_REG_TYPE2                                                                      0x58ea
10396 #define mmSDMA3_CONTEXT_REG_TYPE2_BASE_IDX                                                             1
10397 #define mmSDMA3_CONTEXT_REG_TYPE3                                                                      0x58eb
10398 #define mmSDMA3_CONTEXT_REG_TYPE3_BASE_IDX                                                             1
10399 #define mmSDMA3_PUB_REG_TYPE0                                                                          0x58ec
10400 #define mmSDMA3_PUB_REG_TYPE0_BASE_IDX                                                                 1
10401 #define mmSDMA3_PUB_REG_TYPE1                                                                          0x58ed
10402 #define mmSDMA3_PUB_REG_TYPE1_BASE_IDX                                                                 1
10403 #define mmSDMA3_PUB_REG_TYPE2                                                                          0x58ee
10404 #define mmSDMA3_PUB_REG_TYPE2_BASE_IDX                                                                 1
10405 #define mmSDMA3_PUB_REG_TYPE3                                                                          0x58ef
10406 #define mmSDMA3_PUB_REG_TYPE3_BASE_IDX                                                                 1
10407 #define mmSDMA3_VM_CNTL                                                                                0x58f3
10408 #define mmSDMA3_VM_CNTL_BASE_IDX                                                                       1
10409 
10410 
10411 // addressBlock: gc_gcvmsharedhvdec
10412 // base address: 0x3ea00
10413 #define mmGCMC_VM_FB_SIZE_OFFSET_VF0                                                                   0x5a80
10414 #define mmGCMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX                                                          1
10415 #define mmGCMC_VM_FB_SIZE_OFFSET_VF1                                                                   0x5a81
10416 #define mmGCMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX                                                          1
10417 #define mmGCMC_VM_FB_SIZE_OFFSET_VF2                                                                   0x5a82
10418 #define mmGCMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX                                                          1
10419 #define mmGCMC_VM_FB_SIZE_OFFSET_VF3                                                                   0x5a83
10420 #define mmGCMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX                                                          1
10421 #define mmGCMC_VM_FB_SIZE_OFFSET_VF4                                                                   0x5a84
10422 #define mmGCMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX                                                          1
10423 #define mmGCMC_VM_FB_SIZE_OFFSET_VF5                                                                   0x5a85
10424 #define mmGCMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX                                                          1
10425 #define mmGCMC_VM_FB_SIZE_OFFSET_VF6                                                                   0x5a86
10426 #define mmGCMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX                                                          1
10427 #define mmGCMC_VM_FB_SIZE_OFFSET_VF7                                                                   0x5a87
10428 #define mmGCMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX                                                          1
10429 #define mmGCMC_VM_FB_SIZE_OFFSET_VF8                                                                   0x5a88
10430 #define mmGCMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX                                                          1
10431 #define mmGCMC_VM_FB_SIZE_OFFSET_VF9                                                                   0x5a89
10432 #define mmGCMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX                                                          1
10433 #define mmGCMC_VM_FB_SIZE_OFFSET_VF10                                                                  0x5a8a
10434 #define mmGCMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX                                                         1
10435 #define mmGCMC_VM_FB_SIZE_OFFSET_VF11                                                                  0x5a8b
10436 #define mmGCMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX                                                         1
10437 #define mmGCMC_VM_FB_SIZE_OFFSET_VF12                                                                  0x5a8c
10438 #define mmGCMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX                                                         1
10439 #define mmGCMC_VM_FB_SIZE_OFFSET_VF13                                                                  0x5a8d
10440 #define mmGCMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX                                                         1
10441 #define mmGCMC_VM_FB_SIZE_OFFSET_VF14                                                                  0x5a8e
10442 #define mmGCMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX                                                         1
10443 #define mmGCMC_VM_FB_SIZE_OFFSET_VF15                                                                  0x5a8f
10444 #define mmGCMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX                                                         1
10445 #define mmGCMC_VM_FB_SIZE_OFFSET_VF16                                                                  0x5a90
10446 #define mmGCMC_VM_FB_SIZE_OFFSET_VF16_BASE_IDX                                                         1
10447 #define mmGCMC_VM_FB_SIZE_OFFSET_VF17                                                                  0x5a91
10448 #define mmGCMC_VM_FB_SIZE_OFFSET_VF17_BASE_IDX                                                         1
10449 #define mmGCMC_VM_FB_SIZE_OFFSET_VF18                                                                  0x5a92
10450 #define mmGCMC_VM_FB_SIZE_OFFSET_VF18_BASE_IDX                                                         1
10451 #define mmGCMC_VM_FB_SIZE_OFFSET_VF19                                                                  0x5a93
10452 #define mmGCMC_VM_FB_SIZE_OFFSET_VF19_BASE_IDX                                                         1
10453 #define mmGCMC_VM_FB_SIZE_OFFSET_VF20                                                                  0x5a94
10454 #define mmGCMC_VM_FB_SIZE_OFFSET_VF20_BASE_IDX                                                         1
10455 #define mmGCMC_VM_FB_SIZE_OFFSET_VF21                                                                  0x5a95
10456 #define mmGCMC_VM_FB_SIZE_OFFSET_VF21_BASE_IDX                                                         1
10457 #define mmGCMC_VM_FB_SIZE_OFFSET_VF22                                                                  0x5a96
10458 #define mmGCMC_VM_FB_SIZE_OFFSET_VF22_BASE_IDX                                                         1
10459 #define mmGCMC_VM_FB_SIZE_OFFSET_VF23                                                                  0x5a97
10460 #define mmGCMC_VM_FB_SIZE_OFFSET_VF23_BASE_IDX                                                         1
10461 #define mmGCMC_VM_FB_SIZE_OFFSET_VF24                                                                  0x5a98
10462 #define mmGCMC_VM_FB_SIZE_OFFSET_VF24_BASE_IDX                                                         1
10463 #define mmGCMC_VM_FB_SIZE_OFFSET_VF25                                                                  0x5a99
10464 #define mmGCMC_VM_FB_SIZE_OFFSET_VF25_BASE_IDX                                                         1
10465 #define mmGCMC_VM_FB_SIZE_OFFSET_VF26                                                                  0x5a9a
10466 #define mmGCMC_VM_FB_SIZE_OFFSET_VF26_BASE_IDX                                                         1
10467 #define mmGCMC_VM_FB_SIZE_OFFSET_VF27                                                                  0x5a9b
10468 #define mmGCMC_VM_FB_SIZE_OFFSET_VF27_BASE_IDX                                                         1
10469 #define mmGCMC_VM_FB_SIZE_OFFSET_VF28                                                                  0x5a9c
10470 #define mmGCMC_VM_FB_SIZE_OFFSET_VF28_BASE_IDX                                                         1
10471 #define mmGCMC_VM_FB_SIZE_OFFSET_VF29                                                                  0x5a9d
10472 #define mmGCMC_VM_FB_SIZE_OFFSET_VF29_BASE_IDX                                                         1
10473 #define mmGCMC_VM_FB_SIZE_OFFSET_VF30                                                                  0x5a9e
10474 #define mmGCMC_VM_FB_SIZE_OFFSET_VF30_BASE_IDX                                                         1
10475 #define mmGCMC_VM_FB_SIZE_OFFSET_VF31                                                                  0x5a9f
10476 #define mmGCMC_VM_FB_SIZE_OFFSET_VF31_BASE_IDX                                                         1
10477 #define mmGCVM_IOMMU_MMIO_CNTRL_1                                                                      0x5aa0
10478 #define mmGCVM_IOMMU_MMIO_CNTRL_1_BASE_IDX                                                             1
10479 #define mmGCMC_VM_MARC_BASE_LO_0                                                                       0x5aa1
10480 #define mmGCMC_VM_MARC_BASE_LO_0_BASE_IDX                                                              1
10481 #define mmGCMC_VM_MARC_BASE_LO_1                                                                       0x5aa2
10482 #define mmGCMC_VM_MARC_BASE_LO_1_BASE_IDX                                                              1
10483 #define mmGCMC_VM_MARC_BASE_LO_2                                                                       0x5aa3
10484 #define mmGCMC_VM_MARC_BASE_LO_2_BASE_IDX                                                              1
10485 #define mmGCMC_VM_MARC_BASE_LO_3                                                                       0x5aa4
10486 #define mmGCMC_VM_MARC_BASE_LO_3_BASE_IDX                                                              1
10487 #define mmGCMC_VM_MARC_BASE_HI_0                                                                       0x5aa5
10488 #define mmGCMC_VM_MARC_BASE_HI_0_BASE_IDX                                                              1
10489 #define mmGCMC_VM_MARC_BASE_HI_1                                                                       0x5aa6
10490 #define mmGCMC_VM_MARC_BASE_HI_1_BASE_IDX                                                              1
10491 #define mmGCMC_VM_MARC_BASE_HI_2                                                                       0x5aa7
10492 #define mmGCMC_VM_MARC_BASE_HI_2_BASE_IDX                                                              1
10493 #define mmGCMC_VM_MARC_BASE_HI_3                                                                       0x5aa8
10494 #define mmGCMC_VM_MARC_BASE_HI_3_BASE_IDX                                                              1
10495 #define mmGCMC_VM_MARC_RELOC_LO_0                                                                      0x5aa9
10496 #define mmGCMC_VM_MARC_RELOC_LO_0_BASE_IDX                                                             1
10497 #define mmGCMC_VM_MARC_RELOC_LO_1                                                                      0x5aaa
10498 #define mmGCMC_VM_MARC_RELOC_LO_1_BASE_IDX                                                             1
10499 #define mmGCMC_VM_MARC_RELOC_LO_2                                                                      0x5aab
10500 #define mmGCMC_VM_MARC_RELOC_LO_2_BASE_IDX                                                             1
10501 #define mmGCMC_VM_MARC_RELOC_LO_3                                                                      0x5aac
10502 #define mmGCMC_VM_MARC_RELOC_LO_3_BASE_IDX                                                             1
10503 #define mmGCMC_VM_MARC_RELOC_HI_0                                                                      0x5aad
10504 #define mmGCMC_VM_MARC_RELOC_HI_0_BASE_IDX                                                             1
10505 #define mmGCMC_VM_MARC_RELOC_HI_1                                                                      0x5aae
10506 #define mmGCMC_VM_MARC_RELOC_HI_1_BASE_IDX                                                             1
10507 #define mmGCMC_VM_MARC_RELOC_HI_2                                                                      0x5aaf
10508 #define mmGCMC_VM_MARC_RELOC_HI_2_BASE_IDX                                                             1
10509 #define mmGCMC_VM_MARC_RELOC_HI_3                                                                      0x5ab0
10510 #define mmGCMC_VM_MARC_RELOC_HI_3_BASE_IDX                                                             1
10511 #define mmGCMC_VM_MARC_LEN_LO_0                                                                        0x5ab1
10512 #define mmGCMC_VM_MARC_LEN_LO_0_BASE_IDX                                                               1
10513 #define mmGCMC_VM_MARC_LEN_LO_1                                                                        0x5ab2
10514 #define mmGCMC_VM_MARC_LEN_LO_1_BASE_IDX                                                               1
10515 #define mmGCMC_VM_MARC_LEN_LO_2                                                                        0x5ab3
10516 #define mmGCMC_VM_MARC_LEN_LO_2_BASE_IDX                                                               1
10517 #define mmGCMC_VM_MARC_LEN_LO_3                                                                        0x5ab4
10518 #define mmGCMC_VM_MARC_LEN_LO_3_BASE_IDX                                                               1
10519 #define mmGCMC_VM_MARC_LEN_HI_0                                                                        0x5ab5
10520 #define mmGCMC_VM_MARC_LEN_HI_0_BASE_IDX                                                               1
10521 #define mmGCMC_VM_MARC_LEN_HI_1                                                                        0x5ab6
10522 #define mmGCMC_VM_MARC_LEN_HI_1_BASE_IDX                                                               1
10523 #define mmGCMC_VM_MARC_LEN_HI_2                                                                        0x5ab7
10524 #define mmGCMC_VM_MARC_LEN_HI_2_BASE_IDX                                                               1
10525 #define mmGCMC_VM_MARC_LEN_HI_3                                                                        0x5ab8
10526 #define mmGCMC_VM_MARC_LEN_HI_3_BASE_IDX                                                               1
10527 #define mmGCVM_IOMMU_CONTROL_REGISTER                                                                  0x5ab9
10528 #define mmGCVM_IOMMU_CONTROL_REGISTER_BASE_IDX                                                         1
10529 #define mmGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER                                         0x5aba
10530 #define mmGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX                                1
10531 #define mmGCMC_VM_XGMI_GPUIOV_ENABLE                                                                   0x5abb
10532 #define mmGCMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX                                                          1
10533 
10534 
10535 // addressBlock: gc_pspdec
10536 // base address: 0x3f000
10537 #define mmCPG_PSP_DEBUG                                                                                0x5c10
10538 #define mmCPG_PSP_DEBUG_BASE_IDX                                                                       1
10539 #define mmCPC_PSP_DEBUG                                                                                0x5c11
10540 #define mmCPC_PSP_DEBUG_BASE_IDX                                                                       1
10541 #define mmGRBM_SEC_CNTL                                                                                0x5e0d
10542 #define mmGRBM_SEC_CNTL_BASE_IDX                                                                       1
10543 #define mmRLC_FWL_FIRST_VIOL_ADDR                                                                      0x5f12
10544 #define mmRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX                                                             1
10545 #define mmRLC_SRM_FWL_FIRST_VIOL_ADDR                                                                  0x5f3d
10546 #define mmRLC_SRM_FWL_FIRST_VIOL_ADDR_BASE_IDX                                                         1
10547 
10548 
10549 // addressBlock: gc_gcvml2pspdec
10550 // base address: 0x3f700
10551 #define mmGCVM_L2_ID_CTRL0                                                                             0x5dc0
10552 #define mmGCVM_L2_ID_CTRL0_BASE_IDX                                                                    1
10553 #define mmGCVM_L2_ID_CTRL1                                                                             0x5dc1
10554 #define mmGCVM_L2_ID_CTRL1_BASE_IDX                                                                    1
10555 #define mmGCVM_L2_ID_CTRL2                                                                             0x5dc2
10556 #define mmGCVM_L2_ID_CTRL2_BASE_IDX                                                                    1
10557 #define mmGCVM_L2_ID_CTRL3                                                                             0x5dc3
10558 #define mmGCVM_L2_ID_CTRL3_BASE_IDX                                                                    1
10559 #define mmGCVM_L2_ID_CTRL4                                                                             0x5dc4
10560 #define mmGCVM_L2_ID_CTRL4_BASE_IDX                                                                    1
10561 #define mmGCVM_L2_ID_CTRL5                                                                             0x5dc5
10562 #define mmGCVM_L2_ID_CTRL5_BASE_IDX                                                                    1
10563 #define mmGCVM_L2_ID_CTRL6                                                                             0x5dc6
10564 #define mmGCVM_L2_ID_CTRL6_BASE_IDX                                                                    1
10565 #define mmGCVM_L2_ID_CTRL7                                                                             0x5dc7
10566 #define mmGCVM_L2_ID_CTRL7_BASE_IDX                                                                    1
10567 #define mmGCVM_L2_ID_CTRL_HI                                                                           0x5dc8
10568 #define mmGCVM_L2_ID_CTRL_HI_BASE_IDX                                                                  1
10569 #define mmGCVM_L2_ID_STATUS                                                                            0x5dc9
10570 #define mmGCVM_L2_ID_STATUS_BASE_IDX                                                                   1
10571 #define mmGCUTCL2_TRANSLATION_BYPASS_BY_VMID                                                           0x5dcb
10572 #define mmGCUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX                                                  1
10573 #define mmGCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE                                                       0x5dcd
10574 #define mmGCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE_BASE_IDX                                              1
10575 #define mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO                                               0x5dce
10576 #define mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX                                      1
10577 #define mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI                                               0x5dcf
10578 #define mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX                                      1
10579 #define mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO                                              0x5dd0
10580 #define mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX                                     1
10581 #define mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI                                              0x5dd1
10582 #define mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX                                     1
10583 
10584 
10585 // addressBlock: gc_sdma2_sdma2dec
10586 // base address: 0x70000
10587 #define mmSDMA2_DEC_START                                                                              0x0000
10588 #define mmSDMA2_DEC_START_BASE_IDX                                                                     2
10589 #define mmSDMA2_GLOBAL_TIMESTAMP_LO                                                                    0x000f
10590 #define mmSDMA2_GLOBAL_TIMESTAMP_LO_BASE_IDX                                                           2
10591 #define mmSDMA2_GLOBAL_TIMESTAMP_HI                                                                    0x0010
10592 #define mmSDMA2_GLOBAL_TIMESTAMP_HI_BASE_IDX                                                           2
10593 #define mmSDMA2_PG_CNTL                                                                                0x0016
10594 #define mmSDMA2_PG_CNTL_BASE_IDX                                                                       2
10595 #define mmSDMA2_PG_CTX_LO                                                                              0x0017
10596 #define mmSDMA2_PG_CTX_LO_BASE_IDX                                                                     2
10597 #define mmSDMA2_PG_CTX_HI                                                                              0x0018
10598 #define mmSDMA2_PG_CTX_HI_BASE_IDX                                                                     2
10599 #define mmSDMA2_PG_CTX_CNTL                                                                            0x0019
10600 #define mmSDMA2_PG_CTX_CNTL_BASE_IDX                                                                   2
10601 #define mmSDMA2_POWER_CNTL                                                                             0x001a
10602 #define mmSDMA2_POWER_CNTL_BASE_IDX                                                                    2
10603 #define mmSDMA2_CLK_CTRL                                                                               0x001b
10604 #define mmSDMA2_CLK_CTRL_BASE_IDX                                                                      2
10605 #define mmSDMA2_CNTL                                                                                   0x001c
10606 #define mmSDMA2_CNTL_BASE_IDX                                                                          2
10607 #define mmSDMA2_CHICKEN_BITS                                                                           0x001d
10608 #define mmSDMA2_CHICKEN_BITS_BASE_IDX                                                                  2
10609 #define mmSDMA2_GB_ADDR_CONFIG                                                                         0x001e
10610 #define mmSDMA2_GB_ADDR_CONFIG_BASE_IDX                                                                2
10611 #define mmSDMA2_GB_ADDR_CONFIG_READ                                                                    0x001f
10612 #define mmSDMA2_GB_ADDR_CONFIG_READ_BASE_IDX                                                           2
10613 #define mmSDMA2_RB_RPTR_FETCH_HI                                                                       0x0020
10614 #define mmSDMA2_RB_RPTR_FETCH_HI_BASE_IDX                                                              2
10615 #define mmSDMA2_SEM_WAIT_FAIL_TIMER_CNTL                                                               0x0021
10616 #define mmSDMA2_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX                                                      2
10617 #define mmSDMA2_RB_RPTR_FETCH                                                                          0x0022
10618 #define mmSDMA2_RB_RPTR_FETCH_BASE_IDX                                                                 2
10619 #define mmSDMA2_IB_OFFSET_FETCH                                                                        0x0023
10620 #define mmSDMA2_IB_OFFSET_FETCH_BASE_IDX                                                               2
10621 #define mmSDMA2_PROGRAM                                                                                0x0024
10622 #define mmSDMA2_PROGRAM_BASE_IDX                                                                       2
10623 #define mmSDMA2_STATUS_REG                                                                             0x0025
10624 #define mmSDMA2_STATUS_REG_BASE_IDX                                                                    2
10625 #define mmSDMA2_STATUS1_REG                                                                            0x0026
10626 #define mmSDMA2_STATUS1_REG_BASE_IDX                                                                   2
10627 #define mmSDMA2_RD_BURST_CNTL                                                                          0x0027
10628 #define mmSDMA2_RD_BURST_CNTL_BASE_IDX                                                                 2
10629 #define mmSDMA2_HBM_PAGE_CONFIG                                                                        0x0028
10630 #define mmSDMA2_HBM_PAGE_CONFIG_BASE_IDX                                                               2
10631 #define mmSDMA2_UCODE_CHECKSUM                                                                         0x0029
10632 #define mmSDMA2_UCODE_CHECKSUM_BASE_IDX                                                                2
10633 #define mmSDMA2_F32_CNTL                                                                               0x002a
10634 #define mmSDMA2_F32_CNTL_BASE_IDX                                                                      2
10635 #define mmSDMA2_FREEZE                                                                                 0x002b
10636 #define mmSDMA2_FREEZE_BASE_IDX                                                                        2
10637 #define mmSDMA2_PHASE0_QUANTUM                                                                         0x002c
10638 #define mmSDMA2_PHASE0_QUANTUM_BASE_IDX                                                                2
10639 #define mmSDMA2_PHASE1_QUANTUM                                                                         0x002d
10640 #define mmSDMA2_PHASE1_QUANTUM_BASE_IDX                                                                2
10641 #define mmSDMA2_EDC_CONFIG                                                                             0x0032
10642 #define mmSDMA2_EDC_CONFIG_BASE_IDX                                                                    2
10643 #define mmSDMA2_BA_THRESHOLD                                                                           0x0033
10644 #define mmSDMA2_BA_THRESHOLD_BASE_IDX                                                                  2
10645 #define mmSDMA2_ID                                                                                     0x0034
10646 #define mmSDMA2_ID_BASE_IDX                                                                            2
10647 #define mmSDMA2_VERSION                                                                                0x0035
10648 #define mmSDMA2_VERSION_BASE_IDX                                                                       2
10649 #define mmSDMA2_EDC_COUNTER                                                                            0x0036
10650 #define mmSDMA2_EDC_COUNTER_BASE_IDX                                                                   2
10651 #define mmSDMA2_EDC_COUNTER_CLEAR                                                                      0x0037
10652 #define mmSDMA2_EDC_COUNTER_CLEAR_BASE_IDX                                                             2
10653 #define mmSDMA2_STATUS2_REG                                                                            0x0038
10654 #define mmSDMA2_STATUS2_REG_BASE_IDX                                                                   2
10655 #define mmSDMA2_ATOMIC_CNTL                                                                            0x0039
10656 #define mmSDMA2_ATOMIC_CNTL_BASE_IDX                                                                   2
10657 #define mmSDMA2_ATOMIC_PREOP_LO                                                                        0x003a
10658 #define mmSDMA2_ATOMIC_PREOP_LO_BASE_IDX                                                               2
10659 #define mmSDMA2_ATOMIC_PREOP_HI                                                                        0x003b
10660 #define mmSDMA2_ATOMIC_PREOP_HI_BASE_IDX                                                               2
10661 #define mmSDMA2_UTCL1_CNTL                                                                             0x003c
10662 #define mmSDMA2_UTCL1_CNTL_BASE_IDX                                                                    2
10663 #define mmSDMA2_UTCL1_WATERMK                                                                          0x003d
10664 #define mmSDMA2_UTCL1_WATERMK_BASE_IDX                                                                 2
10665 #define mmSDMA2_UTCL1_RD_STATUS                                                                        0x003e
10666 #define mmSDMA2_UTCL1_RD_STATUS_BASE_IDX                                                               2
10667 #define mmSDMA2_UTCL1_WR_STATUS                                                                        0x003f
10668 #define mmSDMA2_UTCL1_WR_STATUS_BASE_IDX                                                               2
10669 #define mmSDMA2_UTCL1_INV0                                                                             0x0040
10670 #define mmSDMA2_UTCL1_INV0_BASE_IDX                                                                    2
10671 #define mmSDMA2_UTCL1_INV1                                                                             0x0041
10672 #define mmSDMA2_UTCL1_INV1_BASE_IDX                                                                    2
10673 #define mmSDMA2_UTCL1_INV2                                                                             0x0042
10674 #define mmSDMA2_UTCL1_INV2_BASE_IDX                                                                    2
10675 #define mmSDMA2_UTCL1_RD_XNACK0                                                                        0x0043
10676 #define mmSDMA2_UTCL1_RD_XNACK0_BASE_IDX                                                               2
10677 #define mmSDMA2_UTCL1_RD_XNACK1                                                                        0x0044
10678 #define mmSDMA2_UTCL1_RD_XNACK1_BASE_IDX                                                               2
10679 #define mmSDMA2_UTCL1_WR_XNACK0                                                                        0x0045
10680 #define mmSDMA2_UTCL1_WR_XNACK0_BASE_IDX                                                               2
10681 #define mmSDMA2_UTCL1_WR_XNACK1                                                                        0x0046
10682 #define mmSDMA2_UTCL1_WR_XNACK1_BASE_IDX                                                               2
10683 #define mmSDMA2_UTCL1_TIMEOUT                                                                          0x0047
10684 #define mmSDMA2_UTCL1_TIMEOUT_BASE_IDX                                                                 2
10685 #define mmSDMA2_UTCL1_PAGE                                                                             0x0048
10686 #define mmSDMA2_UTCL1_PAGE_BASE_IDX                                                                    2
10687 #define mmSDMA2_RELAX_ORDERING_LUT                                                                     0x004a
10688 #define mmSDMA2_RELAX_ORDERING_LUT_BASE_IDX                                                            2
10689 #define mmSDMA2_CHICKEN_BITS_2                                                                         0x004b
10690 #define mmSDMA2_CHICKEN_BITS_2_BASE_IDX                                                                2
10691 #define mmSDMA2_STATUS3_REG                                                                            0x004c
10692 #define mmSDMA2_STATUS3_REG_BASE_IDX                                                                   2
10693 #define mmSDMA2_PHYSICAL_ADDR_LO                                                                       0x004d
10694 #define mmSDMA2_PHYSICAL_ADDR_LO_BASE_IDX                                                              2
10695 #define mmSDMA2_PHYSICAL_ADDR_HI                                                                       0x004e
10696 #define mmSDMA2_PHYSICAL_ADDR_HI_BASE_IDX                                                              2
10697 #define mmSDMA2_PHASE2_QUANTUM                                                                         0x004f
10698 #define mmSDMA2_PHASE2_QUANTUM_BASE_IDX                                                                2
10699 #define mmSDMA2_ERROR_LOG                                                                              0x0050
10700 #define mmSDMA2_ERROR_LOG_BASE_IDX                                                                     2
10701 #define mmSDMA2_PUB_DUMMY_REG0                                                                         0x0051
10702 #define mmSDMA2_PUB_DUMMY_REG0_BASE_IDX                                                                2
10703 #define mmSDMA2_PUB_DUMMY_REG1                                                                         0x0052
10704 #define mmSDMA2_PUB_DUMMY_REG1_BASE_IDX                                                                2
10705 #define mmSDMA2_PUB_DUMMY_REG2                                                                         0x0053
10706 #define mmSDMA2_PUB_DUMMY_REG2_BASE_IDX                                                                2
10707 #define mmSDMA2_PUB_DUMMY_REG3                                                                         0x0054
10708 #define mmSDMA2_PUB_DUMMY_REG3_BASE_IDX                                                                2
10709 #define mmSDMA2_F32_COUNTER                                                                            0x0055
10710 #define mmSDMA2_F32_COUNTER_BASE_IDX                                                                   2
10711 #define mmSDMA2_CRD_CNTL                                                                               0x005b
10712 #define mmSDMA2_CRD_CNTL_BASE_IDX                                                                      2
10713 #define mmSDMA2_AQL_STATUS                                                                             0x005f
10714 #define mmSDMA2_AQL_STATUS_BASE_IDX                                                                    2
10715 #define mmSDMA2_EA_DBIT_ADDR_DATA                                                                      0x0060
10716 #define mmSDMA2_EA_DBIT_ADDR_DATA_BASE_IDX                                                             2
10717 #define mmSDMA2_EA_DBIT_ADDR_INDEX                                                                     0x0061
10718 #define mmSDMA2_EA_DBIT_ADDR_INDEX_BASE_IDX                                                            2
10719 #define mmSDMA2_TLBI_GCR_CNTL                                                                          0x0062
10720 #define mmSDMA2_TLBI_GCR_CNTL_BASE_IDX                                                                 2
10721 #define mmSDMA2_TILING_CONFIG                                                                          0x0063
10722 #define mmSDMA2_TILING_CONFIG_BASE_IDX                                                                 2
10723 #define mmSDMA2_INT_STATUS                                                                             0x0070
10724 #define mmSDMA2_INT_STATUS_BASE_IDX                                                                    2
10725 #define mmSDMA2_HOLE_ADDR_LO                                                                           0x0072
10726 #define mmSDMA2_HOLE_ADDR_LO_BASE_IDX                                                                  2
10727 #define mmSDMA2_HOLE_ADDR_HI                                                                           0x0073
10728 #define mmSDMA2_HOLE_ADDR_HI_BASE_IDX                                                                  2
10729 #define mmSDMA2_CLOCK_GATING_REG                                                                       0x0075
10730 #define mmSDMA2_CLOCK_GATING_REG_BASE_IDX                                                              2
10731 #define mmSDMA2_STATUS4_REG                                                                            0x0076
10732 #define mmSDMA2_STATUS4_REG_BASE_IDX                                                                   2
10733 #define mmSDMA2_SCRATCH_RAM_DATA                                                                       0x0077
10734 #define mmSDMA2_SCRATCH_RAM_DATA_BASE_IDX                                                              2
10735 #define mmSDMA2_SCRATCH_RAM_ADDR                                                                       0x0078
10736 #define mmSDMA2_SCRATCH_RAM_ADDR_BASE_IDX                                                              2
10737 #define mmSDMA2_TIMESTAMP_CNTL                                                                         0x0079
10738 #define mmSDMA2_TIMESTAMP_CNTL_BASE_IDX                                                                2
10739 #define mmSDMA2_STATUS5_REG                                                                            0x007a
10740 #define mmSDMA2_STATUS5_REG_BASE_IDX                                                                   2
10741 #define mmSDMA2_QUEUE_RESET_REQ                                                                        0x007b
10742 #define mmSDMA2_QUEUE_RESET_REQ_BASE_IDX                                                               2
10743 #define mmSDMA2_GFX_RB_CNTL                                                                            0x0080
10744 #define mmSDMA2_GFX_RB_CNTL_BASE_IDX                                                                   2
10745 #define mmSDMA2_GFX_RB_BASE                                                                            0x0081
10746 #define mmSDMA2_GFX_RB_BASE_BASE_IDX                                                                   2
10747 #define mmSDMA2_GFX_RB_BASE_HI                                                                         0x0082
10748 #define mmSDMA2_GFX_RB_BASE_HI_BASE_IDX                                                                2
10749 #define mmSDMA2_GFX_RB_RPTR                                                                            0x0083
10750 #define mmSDMA2_GFX_RB_RPTR_BASE_IDX                                                                   2
10751 #define mmSDMA2_GFX_RB_RPTR_HI                                                                         0x0084
10752 #define mmSDMA2_GFX_RB_RPTR_HI_BASE_IDX                                                                2
10753 #define mmSDMA2_GFX_RB_WPTR                                                                            0x0085
10754 #define mmSDMA2_GFX_RB_WPTR_BASE_IDX                                                                   2
10755 #define mmSDMA2_GFX_RB_WPTR_HI                                                                         0x0086
10756 #define mmSDMA2_GFX_RB_WPTR_HI_BASE_IDX                                                                2
10757 #define mmSDMA2_GFX_RB_WPTR_POLL_CNTL                                                                  0x0087
10758 #define mmSDMA2_GFX_RB_WPTR_POLL_CNTL_BASE_IDX                                                         2
10759 #define mmSDMA2_GFX_RB_RPTR_ADDR_HI                                                                    0x0088
10760 #define mmSDMA2_GFX_RB_RPTR_ADDR_HI_BASE_IDX                                                           2
10761 #define mmSDMA2_GFX_RB_RPTR_ADDR_LO                                                                    0x0089
10762 #define mmSDMA2_GFX_RB_RPTR_ADDR_LO_BASE_IDX                                                           2
10763 #define mmSDMA2_GFX_IB_CNTL                                                                            0x008a
10764 #define mmSDMA2_GFX_IB_CNTL_BASE_IDX                                                                   2
10765 #define mmSDMA2_GFX_IB_RPTR                                                                            0x008b
10766 #define mmSDMA2_GFX_IB_RPTR_BASE_IDX                                                                   2
10767 #define mmSDMA2_GFX_IB_OFFSET                                                                          0x008c
10768 #define mmSDMA2_GFX_IB_OFFSET_BASE_IDX                                                                 2
10769 #define mmSDMA2_GFX_IB_BASE_LO                                                                         0x008d
10770 #define mmSDMA2_GFX_IB_BASE_LO_BASE_IDX                                                                2
10771 #define mmSDMA2_GFX_IB_BASE_HI                                                                         0x008e
10772 #define mmSDMA2_GFX_IB_BASE_HI_BASE_IDX                                                                2
10773 #define mmSDMA2_GFX_IB_SIZE                                                                            0x008f
10774 #define mmSDMA2_GFX_IB_SIZE_BASE_IDX                                                                   2
10775 #define mmSDMA2_GFX_SKIP_CNTL                                                                          0x0090
10776 #define mmSDMA2_GFX_SKIP_CNTL_BASE_IDX                                                                 2
10777 #define mmSDMA2_GFX_CONTEXT_STATUS                                                                     0x0091
10778 #define mmSDMA2_GFX_CONTEXT_STATUS_BASE_IDX                                                            2
10779 #define mmSDMA2_GFX_DOORBELL                                                                           0x0092
10780 #define mmSDMA2_GFX_DOORBELL_BASE_IDX                                                                  2
10781 #define mmSDMA2_GFX_CONTEXT_CNTL                                                                       0x0093
10782 #define mmSDMA2_GFX_CONTEXT_CNTL_BASE_IDX                                                              2
10783 #define mmSDMA2_GFX_STATUS                                                                             0x00a8
10784 #define mmSDMA2_GFX_STATUS_BASE_IDX                                                                    2
10785 #define mmSDMA2_GFX_DOORBELL_LOG                                                                       0x00a9
10786 #define mmSDMA2_GFX_DOORBELL_LOG_BASE_IDX                                                              2
10787 #define mmSDMA2_GFX_WATERMARK                                                                          0x00aa
10788 #define mmSDMA2_GFX_WATERMARK_BASE_IDX                                                                 2
10789 #define mmSDMA2_GFX_DOORBELL_OFFSET                                                                    0x00ab
10790 #define mmSDMA2_GFX_DOORBELL_OFFSET_BASE_IDX                                                           2
10791 #define mmSDMA2_GFX_CSA_ADDR_LO                                                                        0x00ac
10792 #define mmSDMA2_GFX_CSA_ADDR_LO_BASE_IDX                                                               2
10793 #define mmSDMA2_GFX_CSA_ADDR_HI                                                                        0x00ad
10794 #define mmSDMA2_GFX_CSA_ADDR_HI_BASE_IDX                                                               2
10795 #define mmSDMA2_GFX_IB_SUB_REMAIN                                                                      0x00af
10796 #define mmSDMA2_GFX_IB_SUB_REMAIN_BASE_IDX                                                             2
10797 #define mmSDMA2_GFX_PREEMPT                                                                            0x00b0
10798 #define mmSDMA2_GFX_PREEMPT_BASE_IDX                                                                   2
10799 #define mmSDMA2_GFX_DUMMY_REG                                                                          0x00b1
10800 #define mmSDMA2_GFX_DUMMY_REG_BASE_IDX                                                                 2
10801 #define mmSDMA2_GFX_RB_WPTR_POLL_ADDR_HI                                                               0x00b2
10802 #define mmSDMA2_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                      2
10803 #define mmSDMA2_GFX_RB_WPTR_POLL_ADDR_LO                                                               0x00b3
10804 #define mmSDMA2_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                      2
10805 #define mmSDMA2_GFX_RB_AQL_CNTL                                                                        0x00b4
10806 #define mmSDMA2_GFX_RB_AQL_CNTL_BASE_IDX                                                               2
10807 #define mmSDMA2_GFX_MINOR_PTR_UPDATE                                                                   0x00b5
10808 #define mmSDMA2_GFX_MINOR_PTR_UPDATE_BASE_IDX                                                          2
10809 #define mmSDMA2_GFX_MIDCMD_DATA0                                                                       0x00c0
10810 #define mmSDMA2_GFX_MIDCMD_DATA0_BASE_IDX                                                              2
10811 #define mmSDMA2_GFX_MIDCMD_DATA1                                                                       0x00c1
10812 #define mmSDMA2_GFX_MIDCMD_DATA1_BASE_IDX                                                              2
10813 #define mmSDMA2_GFX_MIDCMD_DATA2                                                                       0x00c2
10814 #define mmSDMA2_GFX_MIDCMD_DATA2_BASE_IDX                                                              2
10815 #define mmSDMA2_GFX_MIDCMD_DATA3                                                                       0x00c3
10816 #define mmSDMA2_GFX_MIDCMD_DATA3_BASE_IDX                                                              2
10817 #define mmSDMA2_GFX_MIDCMD_DATA4                                                                       0x00c4
10818 #define mmSDMA2_GFX_MIDCMD_DATA4_BASE_IDX                                                              2
10819 #define mmSDMA2_GFX_MIDCMD_DATA5                                                                       0x00c5
10820 #define mmSDMA2_GFX_MIDCMD_DATA5_BASE_IDX                                                              2
10821 #define mmSDMA2_GFX_MIDCMD_DATA6                                                                       0x00c6
10822 #define mmSDMA2_GFX_MIDCMD_DATA6_BASE_IDX                                                              2
10823 #define mmSDMA2_GFX_MIDCMD_DATA7                                                                       0x00c7
10824 #define mmSDMA2_GFX_MIDCMD_DATA7_BASE_IDX                                                              2
10825 #define mmSDMA2_GFX_MIDCMD_DATA8                                                                       0x00c8
10826 #define mmSDMA2_GFX_MIDCMD_DATA8_BASE_IDX                                                              2
10827 #define mmSDMA2_GFX_MIDCMD_DATA9                                                                       0x00c9
10828 #define mmSDMA2_GFX_MIDCMD_DATA9_BASE_IDX                                                              2
10829 #define mmSDMA2_GFX_MIDCMD_DATA10                                                                      0x00ca
10830 #define mmSDMA2_GFX_MIDCMD_DATA10_BASE_IDX                                                             2
10831 #define mmSDMA2_GFX_MIDCMD_CNTL                                                                        0x00cb
10832 #define mmSDMA2_GFX_MIDCMD_CNTL_BASE_IDX                                                               2
10833 #define mmSDMA2_PAGE_RB_CNTL                                                                           0x00d8
10834 #define mmSDMA2_PAGE_RB_CNTL_BASE_IDX                                                                  2
10835 #define mmSDMA2_PAGE_RB_BASE                                                                           0x00d9
10836 #define mmSDMA2_PAGE_RB_BASE_BASE_IDX                                                                  2
10837 #define mmSDMA2_PAGE_RB_BASE_HI                                                                        0x00da
10838 #define mmSDMA2_PAGE_RB_BASE_HI_BASE_IDX                                                               2
10839 #define mmSDMA2_PAGE_RB_RPTR                                                                           0x00db
10840 #define mmSDMA2_PAGE_RB_RPTR_BASE_IDX                                                                  2
10841 #define mmSDMA2_PAGE_RB_RPTR_HI                                                                        0x00dc
10842 #define mmSDMA2_PAGE_RB_RPTR_HI_BASE_IDX                                                               2
10843 #define mmSDMA2_PAGE_RB_WPTR                                                                           0x00dd
10844 #define mmSDMA2_PAGE_RB_WPTR_BASE_IDX                                                                  2
10845 #define mmSDMA2_PAGE_RB_WPTR_HI                                                                        0x00de
10846 #define mmSDMA2_PAGE_RB_WPTR_HI_BASE_IDX                                                               2
10847 #define mmSDMA2_PAGE_RB_WPTR_POLL_CNTL                                                                 0x00df
10848 #define mmSDMA2_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX                                                        2
10849 #define mmSDMA2_PAGE_RB_RPTR_ADDR_HI                                                                   0x00e0
10850 #define mmSDMA2_PAGE_RB_RPTR_ADDR_HI_BASE_IDX                                                          2
10851 #define mmSDMA2_PAGE_RB_RPTR_ADDR_LO                                                                   0x00e1
10852 #define mmSDMA2_PAGE_RB_RPTR_ADDR_LO_BASE_IDX                                                          2
10853 #define mmSDMA2_PAGE_IB_CNTL                                                                           0x00e2
10854 #define mmSDMA2_PAGE_IB_CNTL_BASE_IDX                                                                  2
10855 #define mmSDMA2_PAGE_IB_RPTR                                                                           0x00e3
10856 #define mmSDMA2_PAGE_IB_RPTR_BASE_IDX                                                                  2
10857 #define mmSDMA2_PAGE_IB_OFFSET                                                                         0x00e4
10858 #define mmSDMA2_PAGE_IB_OFFSET_BASE_IDX                                                                2
10859 #define mmSDMA2_PAGE_IB_BASE_LO                                                                        0x00e5
10860 #define mmSDMA2_PAGE_IB_BASE_LO_BASE_IDX                                                               2
10861 #define mmSDMA2_PAGE_IB_BASE_HI                                                                        0x00e6
10862 #define mmSDMA2_PAGE_IB_BASE_HI_BASE_IDX                                                               2
10863 #define mmSDMA2_PAGE_IB_SIZE                                                                           0x00e7
10864 #define mmSDMA2_PAGE_IB_SIZE_BASE_IDX                                                                  2
10865 #define mmSDMA2_PAGE_SKIP_CNTL                                                                         0x00e8
10866 #define mmSDMA2_PAGE_SKIP_CNTL_BASE_IDX                                                                2
10867 #define mmSDMA2_PAGE_CONTEXT_STATUS                                                                    0x00e9
10868 #define mmSDMA2_PAGE_CONTEXT_STATUS_BASE_IDX                                                           2
10869 #define mmSDMA2_PAGE_DOORBELL                                                                          0x00ea
10870 #define mmSDMA2_PAGE_DOORBELL_BASE_IDX                                                                 2
10871 #define mmSDMA2_PAGE_STATUS                                                                            0x0100
10872 #define mmSDMA2_PAGE_STATUS_BASE_IDX                                                                   2
10873 #define mmSDMA2_PAGE_DOORBELL_LOG                                                                      0x0101
10874 #define mmSDMA2_PAGE_DOORBELL_LOG_BASE_IDX                                                             2
10875 #define mmSDMA2_PAGE_WATERMARK                                                                         0x0102
10876 #define mmSDMA2_PAGE_WATERMARK_BASE_IDX                                                                2
10877 #define mmSDMA2_PAGE_DOORBELL_OFFSET                                                                   0x0103
10878 #define mmSDMA2_PAGE_DOORBELL_OFFSET_BASE_IDX                                                          2
10879 #define mmSDMA2_PAGE_CSA_ADDR_LO                                                                       0x0104
10880 #define mmSDMA2_PAGE_CSA_ADDR_LO_BASE_IDX                                                              2
10881 #define mmSDMA2_PAGE_CSA_ADDR_HI                                                                       0x0105
10882 #define mmSDMA2_PAGE_CSA_ADDR_HI_BASE_IDX                                                              2
10883 #define mmSDMA2_PAGE_IB_SUB_REMAIN                                                                     0x0107
10884 #define mmSDMA2_PAGE_IB_SUB_REMAIN_BASE_IDX                                                            2
10885 #define mmSDMA2_PAGE_PREEMPT                                                                           0x0108
10886 #define mmSDMA2_PAGE_PREEMPT_BASE_IDX                                                                  2
10887 #define mmSDMA2_PAGE_DUMMY_REG                                                                         0x0109
10888 #define mmSDMA2_PAGE_DUMMY_REG_BASE_IDX                                                                2
10889 #define mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI                                                              0x010a
10890 #define mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     2
10891 #define mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO                                                              0x010b
10892 #define mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     2
10893 #define mmSDMA2_PAGE_RB_AQL_CNTL                                                                       0x010c
10894 #define mmSDMA2_PAGE_RB_AQL_CNTL_BASE_IDX                                                              2
10895 #define mmSDMA2_PAGE_MINOR_PTR_UPDATE                                                                  0x010d
10896 #define mmSDMA2_PAGE_MINOR_PTR_UPDATE_BASE_IDX                                                         2
10897 #define mmSDMA2_PAGE_MIDCMD_DATA0                                                                      0x0118
10898 #define mmSDMA2_PAGE_MIDCMD_DATA0_BASE_IDX                                                             2
10899 #define mmSDMA2_PAGE_MIDCMD_DATA1                                                                      0x0119
10900 #define mmSDMA2_PAGE_MIDCMD_DATA1_BASE_IDX                                                             2
10901 #define mmSDMA2_PAGE_MIDCMD_DATA2                                                                      0x011a
10902 #define mmSDMA2_PAGE_MIDCMD_DATA2_BASE_IDX                                                             2
10903 #define mmSDMA2_PAGE_MIDCMD_DATA3                                                                      0x011b
10904 #define mmSDMA2_PAGE_MIDCMD_DATA3_BASE_IDX                                                             2
10905 #define mmSDMA2_PAGE_MIDCMD_DATA4                                                                      0x011c
10906 #define mmSDMA2_PAGE_MIDCMD_DATA4_BASE_IDX                                                             2
10907 #define mmSDMA2_PAGE_MIDCMD_DATA5                                                                      0x011d
10908 #define mmSDMA2_PAGE_MIDCMD_DATA5_BASE_IDX                                                             2
10909 #define mmSDMA2_PAGE_MIDCMD_DATA6                                                                      0x011e
10910 #define mmSDMA2_PAGE_MIDCMD_DATA6_BASE_IDX                                                             2
10911 #define mmSDMA2_PAGE_MIDCMD_DATA7                                                                      0x011f
10912 #define mmSDMA2_PAGE_MIDCMD_DATA7_BASE_IDX                                                             2
10913 #define mmSDMA2_PAGE_MIDCMD_DATA8                                                                      0x0120
10914 #define mmSDMA2_PAGE_MIDCMD_DATA8_BASE_IDX                                                             2
10915 #define mmSDMA2_PAGE_MIDCMD_DATA9                                                                      0x0121
10916 #define mmSDMA2_PAGE_MIDCMD_DATA9_BASE_IDX                                                             2
10917 #define mmSDMA2_PAGE_MIDCMD_DATA10                                                                     0x0122
10918 #define mmSDMA2_PAGE_MIDCMD_DATA10_BASE_IDX                                                            2
10919 #define mmSDMA2_PAGE_MIDCMD_CNTL                                                                       0x0123
10920 #define mmSDMA2_PAGE_MIDCMD_CNTL_BASE_IDX                                                              2
10921 #define mmSDMA2_RLC0_RB_CNTL                                                                           0x0130
10922 #define mmSDMA2_RLC0_RB_CNTL_BASE_IDX                                                                  2
10923 #define mmSDMA2_RLC0_RB_BASE                                                                           0x0131
10924 #define mmSDMA2_RLC0_RB_BASE_BASE_IDX                                                                  2
10925 #define mmSDMA2_RLC0_RB_BASE_HI                                                                        0x0132
10926 #define mmSDMA2_RLC0_RB_BASE_HI_BASE_IDX                                                               2
10927 #define mmSDMA2_RLC0_RB_RPTR                                                                           0x0133
10928 #define mmSDMA2_RLC0_RB_RPTR_BASE_IDX                                                                  2
10929 #define mmSDMA2_RLC0_RB_RPTR_HI                                                                        0x0134
10930 #define mmSDMA2_RLC0_RB_RPTR_HI_BASE_IDX                                                               2
10931 #define mmSDMA2_RLC0_RB_WPTR                                                                           0x0135
10932 #define mmSDMA2_RLC0_RB_WPTR_BASE_IDX                                                                  2
10933 #define mmSDMA2_RLC0_RB_WPTR_HI                                                                        0x0136
10934 #define mmSDMA2_RLC0_RB_WPTR_HI_BASE_IDX                                                               2
10935 #define mmSDMA2_RLC0_RB_WPTR_POLL_CNTL                                                                 0x0137
10936 #define mmSDMA2_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX                                                        2
10937 #define mmSDMA2_RLC0_RB_RPTR_ADDR_HI                                                                   0x0138
10938 #define mmSDMA2_RLC0_RB_RPTR_ADDR_HI_BASE_IDX                                                          2
10939 #define mmSDMA2_RLC0_RB_RPTR_ADDR_LO                                                                   0x0139
10940 #define mmSDMA2_RLC0_RB_RPTR_ADDR_LO_BASE_IDX                                                          2
10941 #define mmSDMA2_RLC0_IB_CNTL                                                                           0x013a
10942 #define mmSDMA2_RLC0_IB_CNTL_BASE_IDX                                                                  2
10943 #define mmSDMA2_RLC0_IB_RPTR                                                                           0x013b
10944 #define mmSDMA2_RLC0_IB_RPTR_BASE_IDX                                                                  2
10945 #define mmSDMA2_RLC0_IB_OFFSET                                                                         0x013c
10946 #define mmSDMA2_RLC0_IB_OFFSET_BASE_IDX                                                                2
10947 #define mmSDMA2_RLC0_IB_BASE_LO                                                                        0x013d
10948 #define mmSDMA2_RLC0_IB_BASE_LO_BASE_IDX                                                               2
10949 #define mmSDMA2_RLC0_IB_BASE_HI                                                                        0x013e
10950 #define mmSDMA2_RLC0_IB_BASE_HI_BASE_IDX                                                               2
10951 #define mmSDMA2_RLC0_IB_SIZE                                                                           0x013f
10952 #define mmSDMA2_RLC0_IB_SIZE_BASE_IDX                                                                  2
10953 #define mmSDMA2_RLC0_SKIP_CNTL                                                                         0x0140
10954 #define mmSDMA2_RLC0_SKIP_CNTL_BASE_IDX                                                                2
10955 #define mmSDMA2_RLC0_CONTEXT_STATUS                                                                    0x0141
10956 #define mmSDMA2_RLC0_CONTEXT_STATUS_BASE_IDX                                                           2
10957 #define mmSDMA2_RLC0_DOORBELL                                                                          0x0142
10958 #define mmSDMA2_RLC0_DOORBELL_BASE_IDX                                                                 2
10959 #define mmSDMA2_RLC0_STATUS                                                                            0x0158
10960 #define mmSDMA2_RLC0_STATUS_BASE_IDX                                                                   2
10961 #define mmSDMA2_RLC0_DOORBELL_LOG                                                                      0x0159
10962 #define mmSDMA2_RLC0_DOORBELL_LOG_BASE_IDX                                                             2
10963 #define mmSDMA2_RLC0_WATERMARK                                                                         0x015a
10964 #define mmSDMA2_RLC0_WATERMARK_BASE_IDX                                                                2
10965 #define mmSDMA2_RLC0_DOORBELL_OFFSET                                                                   0x015b
10966 #define mmSDMA2_RLC0_DOORBELL_OFFSET_BASE_IDX                                                          2
10967 #define mmSDMA2_RLC0_CSA_ADDR_LO                                                                       0x015c
10968 #define mmSDMA2_RLC0_CSA_ADDR_LO_BASE_IDX                                                              2
10969 #define mmSDMA2_RLC0_CSA_ADDR_HI                                                                       0x015d
10970 #define mmSDMA2_RLC0_CSA_ADDR_HI_BASE_IDX                                                              2
10971 #define mmSDMA2_RLC0_IB_SUB_REMAIN                                                                     0x015f
10972 #define mmSDMA2_RLC0_IB_SUB_REMAIN_BASE_IDX                                                            2
10973 #define mmSDMA2_RLC0_PREEMPT                                                                           0x0160
10974 #define mmSDMA2_RLC0_PREEMPT_BASE_IDX                                                                  2
10975 #define mmSDMA2_RLC0_DUMMY_REG                                                                         0x0161
10976 #define mmSDMA2_RLC0_DUMMY_REG_BASE_IDX                                                                2
10977 #define mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI                                                              0x0162
10978 #define mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     2
10979 #define mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO                                                              0x0163
10980 #define mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     2
10981 #define mmSDMA2_RLC0_RB_AQL_CNTL                                                                       0x0164
10982 #define mmSDMA2_RLC0_RB_AQL_CNTL_BASE_IDX                                                              2
10983 #define mmSDMA2_RLC0_MINOR_PTR_UPDATE                                                                  0x0165
10984 #define mmSDMA2_RLC0_MINOR_PTR_UPDATE_BASE_IDX                                                         2
10985 #define mmSDMA2_RLC0_MIDCMD_DATA0                                                                      0x0170
10986 #define mmSDMA2_RLC0_MIDCMD_DATA0_BASE_IDX                                                             2
10987 #define mmSDMA2_RLC0_MIDCMD_DATA1                                                                      0x0171
10988 #define mmSDMA2_RLC0_MIDCMD_DATA1_BASE_IDX                                                             2
10989 #define mmSDMA2_RLC0_MIDCMD_DATA2                                                                      0x0172
10990 #define mmSDMA2_RLC0_MIDCMD_DATA2_BASE_IDX                                                             2
10991 #define mmSDMA2_RLC0_MIDCMD_DATA3                                                                      0x0173
10992 #define mmSDMA2_RLC0_MIDCMD_DATA3_BASE_IDX                                                             2
10993 #define mmSDMA2_RLC0_MIDCMD_DATA4                                                                      0x0174
10994 #define mmSDMA2_RLC0_MIDCMD_DATA4_BASE_IDX                                                             2
10995 #define mmSDMA2_RLC0_MIDCMD_DATA5                                                                      0x0175
10996 #define mmSDMA2_RLC0_MIDCMD_DATA5_BASE_IDX                                                             2
10997 #define mmSDMA2_RLC0_MIDCMD_DATA6                                                                      0x0176
10998 #define mmSDMA2_RLC0_MIDCMD_DATA6_BASE_IDX                                                             2
10999 #define mmSDMA2_RLC0_MIDCMD_DATA7                                                                      0x0177
11000 #define mmSDMA2_RLC0_MIDCMD_DATA7_BASE_IDX                                                             2
11001 #define mmSDMA2_RLC0_MIDCMD_DATA8                                                                      0x0178
11002 #define mmSDMA2_RLC0_MIDCMD_DATA8_BASE_IDX                                                             2
11003 #define mmSDMA2_RLC0_MIDCMD_DATA9                                                                      0x0179
11004 #define mmSDMA2_RLC0_MIDCMD_DATA9_BASE_IDX                                                             2
11005 #define mmSDMA2_RLC0_MIDCMD_DATA10                                                                     0x017a
11006 #define mmSDMA2_RLC0_MIDCMD_DATA10_BASE_IDX                                                            2
11007 #define mmSDMA2_RLC0_MIDCMD_CNTL                                                                       0x017b
11008 #define mmSDMA2_RLC0_MIDCMD_CNTL_BASE_IDX                                                              2
11009 #define mmSDMA2_RLC1_RB_CNTL                                                                           0x0188
11010 #define mmSDMA2_RLC1_RB_CNTL_BASE_IDX                                                                  2
11011 #define mmSDMA2_RLC1_RB_BASE                                                                           0x0189
11012 #define mmSDMA2_RLC1_RB_BASE_BASE_IDX                                                                  2
11013 #define mmSDMA2_RLC1_RB_BASE_HI                                                                        0x018a
11014 #define mmSDMA2_RLC1_RB_BASE_HI_BASE_IDX                                                               2
11015 #define mmSDMA2_RLC1_RB_RPTR                                                                           0x018b
11016 #define mmSDMA2_RLC1_RB_RPTR_BASE_IDX                                                                  2
11017 #define mmSDMA2_RLC1_RB_RPTR_HI                                                                        0x018c
11018 #define mmSDMA2_RLC1_RB_RPTR_HI_BASE_IDX                                                               2
11019 #define mmSDMA2_RLC1_RB_WPTR                                                                           0x018d
11020 #define mmSDMA2_RLC1_RB_WPTR_BASE_IDX                                                                  2
11021 #define mmSDMA2_RLC1_RB_WPTR_HI                                                                        0x018e
11022 #define mmSDMA2_RLC1_RB_WPTR_HI_BASE_IDX                                                               2
11023 #define mmSDMA2_RLC1_RB_WPTR_POLL_CNTL                                                                 0x018f
11024 #define mmSDMA2_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX                                                        2
11025 #define mmSDMA2_RLC1_RB_RPTR_ADDR_HI                                                                   0x0190
11026 #define mmSDMA2_RLC1_RB_RPTR_ADDR_HI_BASE_IDX                                                          2
11027 #define mmSDMA2_RLC1_RB_RPTR_ADDR_LO                                                                   0x0191
11028 #define mmSDMA2_RLC1_RB_RPTR_ADDR_LO_BASE_IDX                                                          2
11029 #define mmSDMA2_RLC1_IB_CNTL                                                                           0x0192
11030 #define mmSDMA2_RLC1_IB_CNTL_BASE_IDX                                                                  2
11031 #define mmSDMA2_RLC1_IB_RPTR                                                                           0x0193
11032 #define mmSDMA2_RLC1_IB_RPTR_BASE_IDX                                                                  2
11033 #define mmSDMA2_RLC1_IB_OFFSET                                                                         0x0194
11034 #define mmSDMA2_RLC1_IB_OFFSET_BASE_IDX                                                                2
11035 #define mmSDMA2_RLC1_IB_BASE_LO                                                                        0x0195
11036 #define mmSDMA2_RLC1_IB_BASE_LO_BASE_IDX                                                               2
11037 #define mmSDMA2_RLC1_IB_BASE_HI                                                                        0x0196
11038 #define mmSDMA2_RLC1_IB_BASE_HI_BASE_IDX                                                               2
11039 #define mmSDMA2_RLC1_IB_SIZE                                                                           0x0197
11040 #define mmSDMA2_RLC1_IB_SIZE_BASE_IDX                                                                  2
11041 #define mmSDMA2_RLC1_SKIP_CNTL                                                                         0x0198
11042 #define mmSDMA2_RLC1_SKIP_CNTL_BASE_IDX                                                                2
11043 #define mmSDMA2_RLC1_CONTEXT_STATUS                                                                    0x0199
11044 #define mmSDMA2_RLC1_CONTEXT_STATUS_BASE_IDX                                                           2
11045 #define mmSDMA2_RLC1_DOORBELL                                                                          0x019a
11046 #define mmSDMA2_RLC1_DOORBELL_BASE_IDX                                                                 2
11047 #define mmSDMA2_RLC1_STATUS                                                                            0x01b0
11048 #define mmSDMA2_RLC1_STATUS_BASE_IDX                                                                   2
11049 #define mmSDMA2_RLC1_DOORBELL_LOG                                                                      0x01b1
11050 #define mmSDMA2_RLC1_DOORBELL_LOG_BASE_IDX                                                             2
11051 #define mmSDMA2_RLC1_WATERMARK                                                                         0x01b2
11052 #define mmSDMA2_RLC1_WATERMARK_BASE_IDX                                                                2
11053 #define mmSDMA2_RLC1_DOORBELL_OFFSET                                                                   0x01b3
11054 #define mmSDMA2_RLC1_DOORBELL_OFFSET_BASE_IDX                                                          2
11055 #define mmSDMA2_RLC1_CSA_ADDR_LO                                                                       0x01b4
11056 #define mmSDMA2_RLC1_CSA_ADDR_LO_BASE_IDX                                                              2
11057 #define mmSDMA2_RLC1_CSA_ADDR_HI                                                                       0x01b5
11058 #define mmSDMA2_RLC1_CSA_ADDR_HI_BASE_IDX                                                              2
11059 #define mmSDMA2_RLC1_IB_SUB_REMAIN                                                                     0x01b7
11060 #define mmSDMA2_RLC1_IB_SUB_REMAIN_BASE_IDX                                                            2
11061 #define mmSDMA2_RLC1_PREEMPT                                                                           0x01b8
11062 #define mmSDMA2_RLC1_PREEMPT_BASE_IDX                                                                  2
11063 #define mmSDMA2_RLC1_DUMMY_REG                                                                         0x01b9
11064 #define mmSDMA2_RLC1_DUMMY_REG_BASE_IDX                                                                2
11065 #define mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI                                                              0x01ba
11066 #define mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     2
11067 #define mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO                                                              0x01bb
11068 #define mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     2
11069 #define mmSDMA2_RLC1_RB_AQL_CNTL                                                                       0x01bc
11070 #define mmSDMA2_RLC1_RB_AQL_CNTL_BASE_IDX                                                              2
11071 #define mmSDMA2_RLC1_MINOR_PTR_UPDATE                                                                  0x01bd
11072 #define mmSDMA2_RLC1_MINOR_PTR_UPDATE_BASE_IDX                                                         2
11073 #define mmSDMA2_RLC1_MIDCMD_DATA0                                                                      0x01c8
11074 #define mmSDMA2_RLC1_MIDCMD_DATA0_BASE_IDX                                                             2
11075 #define mmSDMA2_RLC1_MIDCMD_DATA1                                                                      0x01c9
11076 #define mmSDMA2_RLC1_MIDCMD_DATA1_BASE_IDX                                                             2
11077 #define mmSDMA2_RLC1_MIDCMD_DATA2                                                                      0x01ca
11078 #define mmSDMA2_RLC1_MIDCMD_DATA2_BASE_IDX                                                             2
11079 #define mmSDMA2_RLC1_MIDCMD_DATA3                                                                      0x01cb
11080 #define mmSDMA2_RLC1_MIDCMD_DATA3_BASE_IDX                                                             2
11081 #define mmSDMA2_RLC1_MIDCMD_DATA4                                                                      0x01cc
11082 #define mmSDMA2_RLC1_MIDCMD_DATA4_BASE_IDX                                                             2
11083 #define mmSDMA2_RLC1_MIDCMD_DATA5                                                                      0x01cd
11084 #define mmSDMA2_RLC1_MIDCMD_DATA5_BASE_IDX                                                             2
11085 #define mmSDMA2_RLC1_MIDCMD_DATA6                                                                      0x01ce
11086 #define mmSDMA2_RLC1_MIDCMD_DATA6_BASE_IDX                                                             2
11087 #define mmSDMA2_RLC1_MIDCMD_DATA7                                                                      0x01cf
11088 #define mmSDMA2_RLC1_MIDCMD_DATA7_BASE_IDX                                                             2
11089 #define mmSDMA2_RLC1_MIDCMD_DATA8                                                                      0x01d0
11090 #define mmSDMA2_RLC1_MIDCMD_DATA8_BASE_IDX                                                             2
11091 #define mmSDMA2_RLC1_MIDCMD_DATA9                                                                      0x01d1
11092 #define mmSDMA2_RLC1_MIDCMD_DATA9_BASE_IDX                                                             2
11093 #define mmSDMA2_RLC1_MIDCMD_DATA10                                                                     0x01d2
11094 #define mmSDMA2_RLC1_MIDCMD_DATA10_BASE_IDX                                                            2
11095 #define mmSDMA2_RLC1_MIDCMD_CNTL                                                                       0x01d3
11096 #define mmSDMA2_RLC1_MIDCMD_CNTL_BASE_IDX                                                              2
11097 #define mmSDMA2_RLC2_RB_CNTL                                                                           0x01e0
11098 #define mmSDMA2_RLC2_RB_CNTL_BASE_IDX                                                                  2
11099 #define mmSDMA2_RLC2_RB_BASE                                                                           0x01e1
11100 #define mmSDMA2_RLC2_RB_BASE_BASE_IDX                                                                  2
11101 #define mmSDMA2_RLC2_RB_BASE_HI                                                                        0x01e2
11102 #define mmSDMA2_RLC2_RB_BASE_HI_BASE_IDX                                                               2
11103 #define mmSDMA2_RLC2_RB_RPTR                                                                           0x01e3
11104 #define mmSDMA2_RLC2_RB_RPTR_BASE_IDX                                                                  2
11105 #define mmSDMA2_RLC2_RB_RPTR_HI                                                                        0x01e4
11106 #define mmSDMA2_RLC2_RB_RPTR_HI_BASE_IDX                                                               2
11107 #define mmSDMA2_RLC2_RB_WPTR                                                                           0x01e5
11108 #define mmSDMA2_RLC2_RB_WPTR_BASE_IDX                                                                  2
11109 #define mmSDMA2_RLC2_RB_WPTR_HI                                                                        0x01e6
11110 #define mmSDMA2_RLC2_RB_WPTR_HI_BASE_IDX                                                               2
11111 #define mmSDMA2_RLC2_RB_WPTR_POLL_CNTL                                                                 0x01e7
11112 #define mmSDMA2_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX                                                        2
11113 #define mmSDMA2_RLC2_RB_RPTR_ADDR_HI                                                                   0x01e8
11114 #define mmSDMA2_RLC2_RB_RPTR_ADDR_HI_BASE_IDX                                                          2
11115 #define mmSDMA2_RLC2_RB_RPTR_ADDR_LO                                                                   0x01e9
11116 #define mmSDMA2_RLC2_RB_RPTR_ADDR_LO_BASE_IDX                                                          2
11117 #define mmSDMA2_RLC2_IB_CNTL                                                                           0x01ea
11118 #define mmSDMA2_RLC2_IB_CNTL_BASE_IDX                                                                  2
11119 #define mmSDMA2_RLC2_IB_RPTR                                                                           0x01eb
11120 #define mmSDMA2_RLC2_IB_RPTR_BASE_IDX                                                                  2
11121 #define mmSDMA2_RLC2_IB_OFFSET                                                                         0x01ec
11122 #define mmSDMA2_RLC2_IB_OFFSET_BASE_IDX                                                                2
11123 #define mmSDMA2_RLC2_IB_BASE_LO                                                                        0x01ed
11124 #define mmSDMA2_RLC2_IB_BASE_LO_BASE_IDX                                                               2
11125 #define mmSDMA2_RLC2_IB_BASE_HI                                                                        0x01ee
11126 #define mmSDMA2_RLC2_IB_BASE_HI_BASE_IDX                                                               2
11127 #define mmSDMA2_RLC2_IB_SIZE                                                                           0x01ef
11128 #define mmSDMA2_RLC2_IB_SIZE_BASE_IDX                                                                  2
11129 #define mmSDMA2_RLC2_SKIP_CNTL                                                                         0x01f0
11130 #define mmSDMA2_RLC2_SKIP_CNTL_BASE_IDX                                                                2
11131 #define mmSDMA2_RLC2_CONTEXT_STATUS                                                                    0x01f1
11132 #define mmSDMA2_RLC2_CONTEXT_STATUS_BASE_IDX                                                           2
11133 #define mmSDMA2_RLC2_DOORBELL                                                                          0x01f2
11134 #define mmSDMA2_RLC2_DOORBELL_BASE_IDX                                                                 2
11135 #define mmSDMA2_RLC2_STATUS                                                                            0x0208
11136 #define mmSDMA2_RLC2_STATUS_BASE_IDX                                                                   2
11137 #define mmSDMA2_RLC2_DOORBELL_LOG                                                                      0x0209
11138 #define mmSDMA2_RLC2_DOORBELL_LOG_BASE_IDX                                                             2
11139 #define mmSDMA2_RLC2_WATERMARK                                                                         0x020a
11140 #define mmSDMA2_RLC2_WATERMARK_BASE_IDX                                                                2
11141 #define mmSDMA2_RLC2_DOORBELL_OFFSET                                                                   0x020b
11142 #define mmSDMA2_RLC2_DOORBELL_OFFSET_BASE_IDX                                                          2
11143 #define mmSDMA2_RLC2_CSA_ADDR_LO                                                                       0x020c
11144 #define mmSDMA2_RLC2_CSA_ADDR_LO_BASE_IDX                                                              2
11145 #define mmSDMA2_RLC2_CSA_ADDR_HI                                                                       0x020d
11146 #define mmSDMA2_RLC2_CSA_ADDR_HI_BASE_IDX                                                              2
11147 #define mmSDMA2_RLC2_IB_SUB_REMAIN                                                                     0x020f
11148 #define mmSDMA2_RLC2_IB_SUB_REMAIN_BASE_IDX                                                            2
11149 #define mmSDMA2_RLC2_PREEMPT                                                                           0x0210
11150 #define mmSDMA2_RLC2_PREEMPT_BASE_IDX                                                                  2
11151 #define mmSDMA2_RLC2_DUMMY_REG                                                                         0x0211
11152 #define mmSDMA2_RLC2_DUMMY_REG_BASE_IDX                                                                2
11153 #define mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI                                                              0x0212
11154 #define mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     2
11155 #define mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO                                                              0x0213
11156 #define mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     2
11157 #define mmSDMA2_RLC2_RB_AQL_CNTL                                                                       0x0214
11158 #define mmSDMA2_RLC2_RB_AQL_CNTL_BASE_IDX                                                              2
11159 #define mmSDMA2_RLC2_MINOR_PTR_UPDATE                                                                  0x0215
11160 #define mmSDMA2_RLC2_MINOR_PTR_UPDATE_BASE_IDX                                                         2
11161 #define mmSDMA2_RLC2_MIDCMD_DATA0                                                                      0x0220
11162 #define mmSDMA2_RLC2_MIDCMD_DATA0_BASE_IDX                                                             2
11163 #define mmSDMA2_RLC2_MIDCMD_DATA1                                                                      0x0221
11164 #define mmSDMA2_RLC2_MIDCMD_DATA1_BASE_IDX                                                             2
11165 #define mmSDMA2_RLC2_MIDCMD_DATA2                                                                      0x0222
11166 #define mmSDMA2_RLC2_MIDCMD_DATA2_BASE_IDX                                                             2
11167 #define mmSDMA2_RLC2_MIDCMD_DATA3                                                                      0x0223
11168 #define mmSDMA2_RLC2_MIDCMD_DATA3_BASE_IDX                                                             2
11169 #define mmSDMA2_RLC2_MIDCMD_DATA4                                                                      0x0224
11170 #define mmSDMA2_RLC2_MIDCMD_DATA4_BASE_IDX                                                             2
11171 #define mmSDMA2_RLC2_MIDCMD_DATA5                                                                      0x0225
11172 #define mmSDMA2_RLC2_MIDCMD_DATA5_BASE_IDX                                                             2
11173 #define mmSDMA2_RLC2_MIDCMD_DATA6                                                                      0x0226
11174 #define mmSDMA2_RLC2_MIDCMD_DATA6_BASE_IDX                                                             2
11175 #define mmSDMA2_RLC2_MIDCMD_DATA7                                                                      0x0227
11176 #define mmSDMA2_RLC2_MIDCMD_DATA7_BASE_IDX                                                             2
11177 #define mmSDMA2_RLC2_MIDCMD_DATA8                                                                      0x0228
11178 #define mmSDMA2_RLC2_MIDCMD_DATA8_BASE_IDX                                                             2
11179 #define mmSDMA2_RLC2_MIDCMD_DATA9                                                                      0x0229
11180 #define mmSDMA2_RLC2_MIDCMD_DATA9_BASE_IDX                                                             2
11181 #define mmSDMA2_RLC2_MIDCMD_DATA10                                                                     0x022a
11182 #define mmSDMA2_RLC2_MIDCMD_DATA10_BASE_IDX                                                            2
11183 #define mmSDMA2_RLC2_MIDCMD_CNTL                                                                       0x022b
11184 #define mmSDMA2_RLC2_MIDCMD_CNTL_BASE_IDX                                                              2
11185 #define mmSDMA2_RLC3_RB_CNTL                                                                           0x0238
11186 #define mmSDMA2_RLC3_RB_CNTL_BASE_IDX                                                                  2
11187 #define mmSDMA2_RLC3_RB_BASE                                                                           0x0239
11188 #define mmSDMA2_RLC3_RB_BASE_BASE_IDX                                                                  2
11189 #define mmSDMA2_RLC3_RB_BASE_HI                                                                        0x023a
11190 #define mmSDMA2_RLC3_RB_BASE_HI_BASE_IDX                                                               2
11191 #define mmSDMA2_RLC3_RB_RPTR                                                                           0x023b
11192 #define mmSDMA2_RLC3_RB_RPTR_BASE_IDX                                                                  2
11193 #define mmSDMA2_RLC3_RB_RPTR_HI                                                                        0x023c
11194 #define mmSDMA2_RLC3_RB_RPTR_HI_BASE_IDX                                                               2
11195 #define mmSDMA2_RLC3_RB_WPTR                                                                           0x023d
11196 #define mmSDMA2_RLC3_RB_WPTR_BASE_IDX                                                                  2
11197 #define mmSDMA2_RLC3_RB_WPTR_HI                                                                        0x023e
11198 #define mmSDMA2_RLC3_RB_WPTR_HI_BASE_IDX                                                               2
11199 #define mmSDMA2_RLC3_RB_WPTR_POLL_CNTL                                                                 0x023f
11200 #define mmSDMA2_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX                                                        2
11201 #define mmSDMA2_RLC3_RB_RPTR_ADDR_HI                                                                   0x0240
11202 #define mmSDMA2_RLC3_RB_RPTR_ADDR_HI_BASE_IDX                                                          2
11203 #define mmSDMA2_RLC3_RB_RPTR_ADDR_LO                                                                   0x0241
11204 #define mmSDMA2_RLC3_RB_RPTR_ADDR_LO_BASE_IDX                                                          2
11205 #define mmSDMA2_RLC3_IB_CNTL                                                                           0x0242
11206 #define mmSDMA2_RLC3_IB_CNTL_BASE_IDX                                                                  2
11207 #define mmSDMA2_RLC3_IB_RPTR                                                                           0x0243
11208 #define mmSDMA2_RLC3_IB_RPTR_BASE_IDX                                                                  2
11209 #define mmSDMA2_RLC3_IB_OFFSET                                                                         0x0244
11210 #define mmSDMA2_RLC3_IB_OFFSET_BASE_IDX                                                                2
11211 #define mmSDMA2_RLC3_IB_BASE_LO                                                                        0x0245
11212 #define mmSDMA2_RLC3_IB_BASE_LO_BASE_IDX                                                               2
11213 #define mmSDMA2_RLC3_IB_BASE_HI                                                                        0x0246
11214 #define mmSDMA2_RLC3_IB_BASE_HI_BASE_IDX                                                               2
11215 #define mmSDMA2_RLC3_IB_SIZE                                                                           0x0247
11216 #define mmSDMA2_RLC3_IB_SIZE_BASE_IDX                                                                  2
11217 #define mmSDMA2_RLC3_SKIP_CNTL                                                                         0x0248
11218 #define mmSDMA2_RLC3_SKIP_CNTL_BASE_IDX                                                                2
11219 #define mmSDMA2_RLC3_CONTEXT_STATUS                                                                    0x0249
11220 #define mmSDMA2_RLC3_CONTEXT_STATUS_BASE_IDX                                                           2
11221 #define mmSDMA2_RLC3_DOORBELL                                                                          0x024a
11222 #define mmSDMA2_RLC3_DOORBELL_BASE_IDX                                                                 2
11223 #define mmSDMA2_RLC3_STATUS                                                                            0x0260
11224 #define mmSDMA2_RLC3_STATUS_BASE_IDX                                                                   2
11225 #define mmSDMA2_RLC3_DOORBELL_LOG                                                                      0x0261
11226 #define mmSDMA2_RLC3_DOORBELL_LOG_BASE_IDX                                                             2
11227 #define mmSDMA2_RLC3_WATERMARK                                                                         0x0262
11228 #define mmSDMA2_RLC3_WATERMARK_BASE_IDX                                                                2
11229 #define mmSDMA2_RLC3_DOORBELL_OFFSET                                                                   0x0263
11230 #define mmSDMA2_RLC3_DOORBELL_OFFSET_BASE_IDX                                                          2
11231 #define mmSDMA2_RLC3_CSA_ADDR_LO                                                                       0x0264
11232 #define mmSDMA2_RLC3_CSA_ADDR_LO_BASE_IDX                                                              2
11233 #define mmSDMA2_RLC3_CSA_ADDR_HI                                                                       0x0265
11234 #define mmSDMA2_RLC3_CSA_ADDR_HI_BASE_IDX                                                              2
11235 #define mmSDMA2_RLC3_IB_SUB_REMAIN                                                                     0x0267
11236 #define mmSDMA2_RLC3_IB_SUB_REMAIN_BASE_IDX                                                            2
11237 #define mmSDMA2_RLC3_PREEMPT                                                                           0x0268
11238 #define mmSDMA2_RLC3_PREEMPT_BASE_IDX                                                                  2
11239 #define mmSDMA2_RLC3_DUMMY_REG                                                                         0x0269
11240 #define mmSDMA2_RLC3_DUMMY_REG_BASE_IDX                                                                2
11241 #define mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI                                                              0x026a
11242 #define mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     2
11243 #define mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO                                                              0x026b
11244 #define mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     2
11245 #define mmSDMA2_RLC3_RB_AQL_CNTL                                                                       0x026c
11246 #define mmSDMA2_RLC3_RB_AQL_CNTL_BASE_IDX                                                              2
11247 #define mmSDMA2_RLC3_MINOR_PTR_UPDATE                                                                  0x026d
11248 #define mmSDMA2_RLC3_MINOR_PTR_UPDATE_BASE_IDX                                                         2
11249 #define mmSDMA2_RLC3_MIDCMD_DATA0                                                                      0x0278
11250 #define mmSDMA2_RLC3_MIDCMD_DATA0_BASE_IDX                                                             2
11251 #define mmSDMA2_RLC3_MIDCMD_DATA1                                                                      0x0279
11252 #define mmSDMA2_RLC3_MIDCMD_DATA1_BASE_IDX                                                             2
11253 #define mmSDMA2_RLC3_MIDCMD_DATA2                                                                      0x027a
11254 #define mmSDMA2_RLC3_MIDCMD_DATA2_BASE_IDX                                                             2
11255 #define mmSDMA2_RLC3_MIDCMD_DATA3                                                                      0x027b
11256 #define mmSDMA2_RLC3_MIDCMD_DATA3_BASE_IDX                                                             2
11257 #define mmSDMA2_RLC3_MIDCMD_DATA4                                                                      0x027c
11258 #define mmSDMA2_RLC3_MIDCMD_DATA4_BASE_IDX                                                             2
11259 #define mmSDMA2_RLC3_MIDCMD_DATA5                                                                      0x027d
11260 #define mmSDMA2_RLC3_MIDCMD_DATA5_BASE_IDX                                                             2
11261 #define mmSDMA2_RLC3_MIDCMD_DATA6                                                                      0x027e
11262 #define mmSDMA2_RLC3_MIDCMD_DATA6_BASE_IDX                                                             2
11263 #define mmSDMA2_RLC3_MIDCMD_DATA7                                                                      0x027f
11264 #define mmSDMA2_RLC3_MIDCMD_DATA7_BASE_IDX                                                             2
11265 #define mmSDMA2_RLC3_MIDCMD_DATA8                                                                      0x0280
11266 #define mmSDMA2_RLC3_MIDCMD_DATA8_BASE_IDX                                                             2
11267 #define mmSDMA2_RLC3_MIDCMD_DATA9                                                                      0x0281
11268 #define mmSDMA2_RLC3_MIDCMD_DATA9_BASE_IDX                                                             2
11269 #define mmSDMA2_RLC3_MIDCMD_DATA10                                                                     0x0282
11270 #define mmSDMA2_RLC3_MIDCMD_DATA10_BASE_IDX                                                            2
11271 #define mmSDMA2_RLC3_MIDCMD_CNTL                                                                       0x0283
11272 #define mmSDMA2_RLC3_MIDCMD_CNTL_BASE_IDX                                                              2
11273 #define mmSDMA2_RLC4_RB_CNTL                                                                           0x0290
11274 #define mmSDMA2_RLC4_RB_CNTL_BASE_IDX                                                                  2
11275 #define mmSDMA2_RLC4_RB_BASE                                                                           0x0291
11276 #define mmSDMA2_RLC4_RB_BASE_BASE_IDX                                                                  2
11277 #define mmSDMA2_RLC4_RB_BASE_HI                                                                        0x0292
11278 #define mmSDMA2_RLC4_RB_BASE_HI_BASE_IDX                                                               2
11279 #define mmSDMA2_RLC4_RB_RPTR                                                                           0x0293
11280 #define mmSDMA2_RLC4_RB_RPTR_BASE_IDX                                                                  2
11281 #define mmSDMA2_RLC4_RB_RPTR_HI                                                                        0x0294
11282 #define mmSDMA2_RLC4_RB_RPTR_HI_BASE_IDX                                                               2
11283 #define mmSDMA2_RLC4_RB_WPTR                                                                           0x0295
11284 #define mmSDMA2_RLC4_RB_WPTR_BASE_IDX                                                                  2
11285 #define mmSDMA2_RLC4_RB_WPTR_HI                                                                        0x0296
11286 #define mmSDMA2_RLC4_RB_WPTR_HI_BASE_IDX                                                               2
11287 #define mmSDMA2_RLC4_RB_WPTR_POLL_CNTL                                                                 0x0297
11288 #define mmSDMA2_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX                                                        2
11289 #define mmSDMA2_RLC4_RB_RPTR_ADDR_HI                                                                   0x0298
11290 #define mmSDMA2_RLC4_RB_RPTR_ADDR_HI_BASE_IDX                                                          2
11291 #define mmSDMA2_RLC4_RB_RPTR_ADDR_LO                                                                   0x0299
11292 #define mmSDMA2_RLC4_RB_RPTR_ADDR_LO_BASE_IDX                                                          2
11293 #define mmSDMA2_RLC4_IB_CNTL                                                                           0x029a
11294 #define mmSDMA2_RLC4_IB_CNTL_BASE_IDX                                                                  2
11295 #define mmSDMA2_RLC4_IB_RPTR                                                                           0x029b
11296 #define mmSDMA2_RLC4_IB_RPTR_BASE_IDX                                                                  2
11297 #define mmSDMA2_RLC4_IB_OFFSET                                                                         0x029c
11298 #define mmSDMA2_RLC4_IB_OFFSET_BASE_IDX                                                                2
11299 #define mmSDMA2_RLC4_IB_BASE_LO                                                                        0x029d
11300 #define mmSDMA2_RLC4_IB_BASE_LO_BASE_IDX                                                               2
11301 #define mmSDMA2_RLC4_IB_BASE_HI                                                                        0x029e
11302 #define mmSDMA2_RLC4_IB_BASE_HI_BASE_IDX                                                               2
11303 #define mmSDMA2_RLC4_IB_SIZE                                                                           0x029f
11304 #define mmSDMA2_RLC4_IB_SIZE_BASE_IDX                                                                  2
11305 #define mmSDMA2_RLC4_SKIP_CNTL                                                                         0x02a0
11306 #define mmSDMA2_RLC4_SKIP_CNTL_BASE_IDX                                                                2
11307 #define mmSDMA2_RLC4_CONTEXT_STATUS                                                                    0x02a1
11308 #define mmSDMA2_RLC4_CONTEXT_STATUS_BASE_IDX                                                           2
11309 #define mmSDMA2_RLC4_DOORBELL                                                                          0x02a2
11310 #define mmSDMA2_RLC4_DOORBELL_BASE_IDX                                                                 2
11311 #define mmSDMA2_RLC4_STATUS                                                                            0x02b8
11312 #define mmSDMA2_RLC4_STATUS_BASE_IDX                                                                   2
11313 #define mmSDMA2_RLC4_DOORBELL_LOG                                                                      0x02b9
11314 #define mmSDMA2_RLC4_DOORBELL_LOG_BASE_IDX                                                             2
11315 #define mmSDMA2_RLC4_WATERMARK                                                                         0x02ba
11316 #define mmSDMA2_RLC4_WATERMARK_BASE_IDX                                                                2
11317 #define mmSDMA2_RLC4_DOORBELL_OFFSET                                                                   0x02bb
11318 #define mmSDMA2_RLC4_DOORBELL_OFFSET_BASE_IDX                                                          2
11319 #define mmSDMA2_RLC4_CSA_ADDR_LO                                                                       0x02bc
11320 #define mmSDMA2_RLC4_CSA_ADDR_LO_BASE_IDX                                                              2
11321 #define mmSDMA2_RLC4_CSA_ADDR_HI                                                                       0x02bd
11322 #define mmSDMA2_RLC4_CSA_ADDR_HI_BASE_IDX                                                              2
11323 #define mmSDMA2_RLC4_IB_SUB_REMAIN                                                                     0x02bf
11324 #define mmSDMA2_RLC4_IB_SUB_REMAIN_BASE_IDX                                                            2
11325 #define mmSDMA2_RLC4_PREEMPT                                                                           0x02c0
11326 #define mmSDMA2_RLC4_PREEMPT_BASE_IDX                                                                  2
11327 #define mmSDMA2_RLC4_DUMMY_REG                                                                         0x02c1
11328 #define mmSDMA2_RLC4_DUMMY_REG_BASE_IDX                                                                2
11329 #define mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI                                                              0x02c2
11330 #define mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     2
11331 #define mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO                                                              0x02c3
11332 #define mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     2
11333 #define mmSDMA2_RLC4_RB_AQL_CNTL                                                                       0x02c4
11334 #define mmSDMA2_RLC4_RB_AQL_CNTL_BASE_IDX                                                              2
11335 #define mmSDMA2_RLC4_MINOR_PTR_UPDATE                                                                  0x02c5
11336 #define mmSDMA2_RLC4_MINOR_PTR_UPDATE_BASE_IDX                                                         2
11337 #define mmSDMA2_RLC4_MIDCMD_DATA0                                                                      0x02d0
11338 #define mmSDMA2_RLC4_MIDCMD_DATA0_BASE_IDX                                                             2
11339 #define mmSDMA2_RLC4_MIDCMD_DATA1                                                                      0x02d1
11340 #define mmSDMA2_RLC4_MIDCMD_DATA1_BASE_IDX                                                             2
11341 #define mmSDMA2_RLC4_MIDCMD_DATA2                                                                      0x02d2
11342 #define mmSDMA2_RLC4_MIDCMD_DATA2_BASE_IDX                                                             2
11343 #define mmSDMA2_RLC4_MIDCMD_DATA3                                                                      0x02d3
11344 #define mmSDMA2_RLC4_MIDCMD_DATA3_BASE_IDX                                                             2
11345 #define mmSDMA2_RLC4_MIDCMD_DATA4                                                                      0x02d4
11346 #define mmSDMA2_RLC4_MIDCMD_DATA4_BASE_IDX                                                             2
11347 #define mmSDMA2_RLC4_MIDCMD_DATA5                                                                      0x02d5
11348 #define mmSDMA2_RLC4_MIDCMD_DATA5_BASE_IDX                                                             2
11349 #define mmSDMA2_RLC4_MIDCMD_DATA6                                                                      0x02d6
11350 #define mmSDMA2_RLC4_MIDCMD_DATA6_BASE_IDX                                                             2
11351 #define mmSDMA2_RLC4_MIDCMD_DATA7                                                                      0x02d7
11352 #define mmSDMA2_RLC4_MIDCMD_DATA7_BASE_IDX                                                             2
11353 #define mmSDMA2_RLC4_MIDCMD_DATA8                                                                      0x02d8
11354 #define mmSDMA2_RLC4_MIDCMD_DATA8_BASE_IDX                                                             2
11355 #define mmSDMA2_RLC4_MIDCMD_DATA9                                                                      0x02d9
11356 #define mmSDMA2_RLC4_MIDCMD_DATA9_BASE_IDX                                                             2
11357 #define mmSDMA2_RLC4_MIDCMD_DATA10                                                                     0x02da
11358 #define mmSDMA2_RLC4_MIDCMD_DATA10_BASE_IDX                                                            2
11359 #define mmSDMA2_RLC4_MIDCMD_CNTL                                                                       0x02db
11360 #define mmSDMA2_RLC4_MIDCMD_CNTL_BASE_IDX                                                              2
11361 #define mmSDMA2_RLC5_RB_CNTL                                                                           0x02e8
11362 #define mmSDMA2_RLC5_RB_CNTL_BASE_IDX                                                                  2
11363 #define mmSDMA2_RLC5_RB_BASE                                                                           0x02e9
11364 #define mmSDMA2_RLC5_RB_BASE_BASE_IDX                                                                  2
11365 #define mmSDMA2_RLC5_RB_BASE_HI                                                                        0x02ea
11366 #define mmSDMA2_RLC5_RB_BASE_HI_BASE_IDX                                                               2
11367 #define mmSDMA2_RLC5_RB_RPTR                                                                           0x02eb
11368 #define mmSDMA2_RLC5_RB_RPTR_BASE_IDX                                                                  2
11369 #define mmSDMA2_RLC5_RB_RPTR_HI                                                                        0x02ec
11370 #define mmSDMA2_RLC5_RB_RPTR_HI_BASE_IDX                                                               2
11371 #define mmSDMA2_RLC5_RB_WPTR                                                                           0x02ed
11372 #define mmSDMA2_RLC5_RB_WPTR_BASE_IDX                                                                  2
11373 #define mmSDMA2_RLC5_RB_WPTR_HI                                                                        0x02ee
11374 #define mmSDMA2_RLC5_RB_WPTR_HI_BASE_IDX                                                               2
11375 #define mmSDMA2_RLC5_RB_WPTR_POLL_CNTL                                                                 0x02ef
11376 #define mmSDMA2_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX                                                        2
11377 #define mmSDMA2_RLC5_RB_RPTR_ADDR_HI                                                                   0x02f0
11378 #define mmSDMA2_RLC5_RB_RPTR_ADDR_HI_BASE_IDX                                                          2
11379 #define mmSDMA2_RLC5_RB_RPTR_ADDR_LO                                                                   0x02f1
11380 #define mmSDMA2_RLC5_RB_RPTR_ADDR_LO_BASE_IDX                                                          2
11381 #define mmSDMA2_RLC5_IB_CNTL                                                                           0x02f2
11382 #define mmSDMA2_RLC5_IB_CNTL_BASE_IDX                                                                  2
11383 #define mmSDMA2_RLC5_IB_RPTR                                                                           0x02f3
11384 #define mmSDMA2_RLC5_IB_RPTR_BASE_IDX                                                                  2
11385 #define mmSDMA2_RLC5_IB_OFFSET                                                                         0x02f4
11386 #define mmSDMA2_RLC5_IB_OFFSET_BASE_IDX                                                                2
11387 #define mmSDMA2_RLC5_IB_BASE_LO                                                                        0x02f5
11388 #define mmSDMA2_RLC5_IB_BASE_LO_BASE_IDX                                                               2
11389 #define mmSDMA2_RLC5_IB_BASE_HI                                                                        0x02f6
11390 #define mmSDMA2_RLC5_IB_BASE_HI_BASE_IDX                                                               2
11391 #define mmSDMA2_RLC5_IB_SIZE                                                                           0x02f7
11392 #define mmSDMA2_RLC5_IB_SIZE_BASE_IDX                                                                  2
11393 #define mmSDMA2_RLC5_SKIP_CNTL                                                                         0x02f8
11394 #define mmSDMA2_RLC5_SKIP_CNTL_BASE_IDX                                                                2
11395 #define mmSDMA2_RLC5_CONTEXT_STATUS                                                                    0x02f9
11396 #define mmSDMA2_RLC5_CONTEXT_STATUS_BASE_IDX                                                           2
11397 #define mmSDMA2_RLC5_DOORBELL                                                                          0x02fa
11398 #define mmSDMA2_RLC5_DOORBELL_BASE_IDX                                                                 2
11399 #define mmSDMA2_RLC5_STATUS                                                                            0x0310
11400 #define mmSDMA2_RLC5_STATUS_BASE_IDX                                                                   2
11401 #define mmSDMA2_RLC5_DOORBELL_LOG                                                                      0x0311
11402 #define mmSDMA2_RLC5_DOORBELL_LOG_BASE_IDX                                                             2
11403 #define mmSDMA2_RLC5_WATERMARK                                                                         0x0312
11404 #define mmSDMA2_RLC5_WATERMARK_BASE_IDX                                                                2
11405 #define mmSDMA2_RLC5_DOORBELL_OFFSET                                                                   0x0313
11406 #define mmSDMA2_RLC5_DOORBELL_OFFSET_BASE_IDX                                                          2
11407 #define mmSDMA2_RLC5_CSA_ADDR_LO                                                                       0x0314
11408 #define mmSDMA2_RLC5_CSA_ADDR_LO_BASE_IDX                                                              2
11409 #define mmSDMA2_RLC5_CSA_ADDR_HI                                                                       0x0315
11410 #define mmSDMA2_RLC5_CSA_ADDR_HI_BASE_IDX                                                              2
11411 #define mmSDMA2_RLC5_IB_SUB_REMAIN                                                                     0x0317
11412 #define mmSDMA2_RLC5_IB_SUB_REMAIN_BASE_IDX                                                            2
11413 #define mmSDMA2_RLC5_PREEMPT                                                                           0x0318
11414 #define mmSDMA2_RLC5_PREEMPT_BASE_IDX                                                                  2
11415 #define mmSDMA2_RLC5_DUMMY_REG                                                                         0x0319
11416 #define mmSDMA2_RLC5_DUMMY_REG_BASE_IDX                                                                2
11417 #define mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI                                                              0x031a
11418 #define mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     2
11419 #define mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO                                                              0x031b
11420 #define mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     2
11421 #define mmSDMA2_RLC5_RB_AQL_CNTL                                                                       0x031c
11422 #define mmSDMA2_RLC5_RB_AQL_CNTL_BASE_IDX                                                              2
11423 #define mmSDMA2_RLC5_MINOR_PTR_UPDATE                                                                  0x031d
11424 #define mmSDMA2_RLC5_MINOR_PTR_UPDATE_BASE_IDX                                                         2
11425 #define mmSDMA2_RLC5_MIDCMD_DATA0                                                                      0x0328
11426 #define mmSDMA2_RLC5_MIDCMD_DATA0_BASE_IDX                                                             2
11427 #define mmSDMA2_RLC5_MIDCMD_DATA1                                                                      0x0329
11428 #define mmSDMA2_RLC5_MIDCMD_DATA1_BASE_IDX                                                             2
11429 #define mmSDMA2_RLC5_MIDCMD_DATA2                                                                      0x032a
11430 #define mmSDMA2_RLC5_MIDCMD_DATA2_BASE_IDX                                                             2
11431 #define mmSDMA2_RLC5_MIDCMD_DATA3                                                                      0x032b
11432 #define mmSDMA2_RLC5_MIDCMD_DATA3_BASE_IDX                                                             2
11433 #define mmSDMA2_RLC5_MIDCMD_DATA4                                                                      0x032c
11434 #define mmSDMA2_RLC5_MIDCMD_DATA4_BASE_IDX                                                             2
11435 #define mmSDMA2_RLC5_MIDCMD_DATA5                                                                      0x032d
11436 #define mmSDMA2_RLC5_MIDCMD_DATA5_BASE_IDX                                                             2
11437 #define mmSDMA2_RLC5_MIDCMD_DATA6                                                                      0x032e
11438 #define mmSDMA2_RLC5_MIDCMD_DATA6_BASE_IDX                                                             2
11439 #define mmSDMA2_RLC5_MIDCMD_DATA7                                                                      0x032f
11440 #define mmSDMA2_RLC5_MIDCMD_DATA7_BASE_IDX                                                             2
11441 #define mmSDMA2_RLC5_MIDCMD_DATA8                                                                      0x0330
11442 #define mmSDMA2_RLC5_MIDCMD_DATA8_BASE_IDX                                                             2
11443 #define mmSDMA2_RLC5_MIDCMD_DATA9                                                                      0x0331
11444 #define mmSDMA2_RLC5_MIDCMD_DATA9_BASE_IDX                                                             2
11445 #define mmSDMA2_RLC5_MIDCMD_DATA10                                                                     0x0332
11446 #define mmSDMA2_RLC5_MIDCMD_DATA10_BASE_IDX                                                            2
11447 #define mmSDMA2_RLC5_MIDCMD_CNTL                                                                       0x0333
11448 #define mmSDMA2_RLC5_MIDCMD_CNTL_BASE_IDX                                                              2
11449 #define mmSDMA2_RLC6_RB_CNTL                                                                           0x0340
11450 #define mmSDMA2_RLC6_RB_CNTL_BASE_IDX                                                                  2
11451 #define mmSDMA2_RLC6_RB_BASE                                                                           0x0341
11452 #define mmSDMA2_RLC6_RB_BASE_BASE_IDX                                                                  2
11453 #define mmSDMA2_RLC6_RB_BASE_HI                                                                        0x0342
11454 #define mmSDMA2_RLC6_RB_BASE_HI_BASE_IDX                                                               2
11455 #define mmSDMA2_RLC6_RB_RPTR                                                                           0x0343
11456 #define mmSDMA2_RLC6_RB_RPTR_BASE_IDX                                                                  2
11457 #define mmSDMA2_RLC6_RB_RPTR_HI                                                                        0x0344
11458 #define mmSDMA2_RLC6_RB_RPTR_HI_BASE_IDX                                                               2
11459 #define mmSDMA2_RLC6_RB_WPTR                                                                           0x0345
11460 #define mmSDMA2_RLC6_RB_WPTR_BASE_IDX                                                                  2
11461 #define mmSDMA2_RLC6_RB_WPTR_HI                                                                        0x0346
11462 #define mmSDMA2_RLC6_RB_WPTR_HI_BASE_IDX                                                               2
11463 #define mmSDMA2_RLC6_RB_WPTR_POLL_CNTL                                                                 0x0347
11464 #define mmSDMA2_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX                                                        2
11465 #define mmSDMA2_RLC6_RB_RPTR_ADDR_HI                                                                   0x0348
11466 #define mmSDMA2_RLC6_RB_RPTR_ADDR_HI_BASE_IDX                                                          2
11467 #define mmSDMA2_RLC6_RB_RPTR_ADDR_LO                                                                   0x0349
11468 #define mmSDMA2_RLC6_RB_RPTR_ADDR_LO_BASE_IDX                                                          2
11469 #define mmSDMA2_RLC6_IB_CNTL                                                                           0x034a
11470 #define mmSDMA2_RLC6_IB_CNTL_BASE_IDX                                                                  2
11471 #define mmSDMA2_RLC6_IB_RPTR                                                                           0x034b
11472 #define mmSDMA2_RLC6_IB_RPTR_BASE_IDX                                                                  2
11473 #define mmSDMA2_RLC6_IB_OFFSET                                                                         0x034c
11474 #define mmSDMA2_RLC6_IB_OFFSET_BASE_IDX                                                                2
11475 #define mmSDMA2_RLC6_IB_BASE_LO                                                                        0x034d
11476 #define mmSDMA2_RLC6_IB_BASE_LO_BASE_IDX                                                               2
11477 #define mmSDMA2_RLC6_IB_BASE_HI                                                                        0x034e
11478 #define mmSDMA2_RLC6_IB_BASE_HI_BASE_IDX                                                               2
11479 #define mmSDMA2_RLC6_IB_SIZE                                                                           0x034f
11480 #define mmSDMA2_RLC6_IB_SIZE_BASE_IDX                                                                  2
11481 #define mmSDMA2_RLC6_SKIP_CNTL                                                                         0x0350
11482 #define mmSDMA2_RLC6_SKIP_CNTL_BASE_IDX                                                                2
11483 #define mmSDMA2_RLC6_CONTEXT_STATUS                                                                    0x0351
11484 #define mmSDMA2_RLC6_CONTEXT_STATUS_BASE_IDX                                                           2
11485 #define mmSDMA2_RLC6_DOORBELL                                                                          0x0352
11486 #define mmSDMA2_RLC6_DOORBELL_BASE_IDX                                                                 2
11487 #define mmSDMA2_RLC6_STATUS                                                                            0x0368
11488 #define mmSDMA2_RLC6_STATUS_BASE_IDX                                                                   2
11489 #define mmSDMA2_RLC6_DOORBELL_LOG                                                                      0x0369
11490 #define mmSDMA2_RLC6_DOORBELL_LOG_BASE_IDX                                                             2
11491 #define mmSDMA2_RLC6_WATERMARK                                                                         0x036a
11492 #define mmSDMA2_RLC6_WATERMARK_BASE_IDX                                                                2
11493 #define mmSDMA2_RLC6_DOORBELL_OFFSET                                                                   0x036b
11494 #define mmSDMA2_RLC6_DOORBELL_OFFSET_BASE_IDX                                                          2
11495 #define mmSDMA2_RLC6_CSA_ADDR_LO                                                                       0x036c
11496 #define mmSDMA2_RLC6_CSA_ADDR_LO_BASE_IDX                                                              2
11497 #define mmSDMA2_RLC6_CSA_ADDR_HI                                                                       0x036d
11498 #define mmSDMA2_RLC6_CSA_ADDR_HI_BASE_IDX                                                              2
11499 #define mmSDMA2_RLC6_IB_SUB_REMAIN                                                                     0x036f
11500 #define mmSDMA2_RLC6_IB_SUB_REMAIN_BASE_IDX                                                            2
11501 #define mmSDMA2_RLC6_PREEMPT                                                                           0x0370
11502 #define mmSDMA2_RLC6_PREEMPT_BASE_IDX                                                                  2
11503 #define mmSDMA2_RLC6_DUMMY_REG                                                                         0x0371
11504 #define mmSDMA2_RLC6_DUMMY_REG_BASE_IDX                                                                2
11505 #define mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI                                                              0x0372
11506 #define mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     2
11507 #define mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO                                                              0x0373
11508 #define mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     2
11509 #define mmSDMA2_RLC6_RB_AQL_CNTL                                                                       0x0374
11510 #define mmSDMA2_RLC6_RB_AQL_CNTL_BASE_IDX                                                              2
11511 #define mmSDMA2_RLC6_MINOR_PTR_UPDATE                                                                  0x0375
11512 #define mmSDMA2_RLC6_MINOR_PTR_UPDATE_BASE_IDX                                                         2
11513 #define mmSDMA2_RLC6_MIDCMD_DATA0                                                                      0x0380
11514 #define mmSDMA2_RLC6_MIDCMD_DATA0_BASE_IDX                                                             2
11515 #define mmSDMA2_RLC6_MIDCMD_DATA1                                                                      0x0381
11516 #define mmSDMA2_RLC6_MIDCMD_DATA1_BASE_IDX                                                             2
11517 #define mmSDMA2_RLC6_MIDCMD_DATA2                                                                      0x0382
11518 #define mmSDMA2_RLC6_MIDCMD_DATA2_BASE_IDX                                                             2
11519 #define mmSDMA2_RLC6_MIDCMD_DATA3                                                                      0x0383
11520 #define mmSDMA2_RLC6_MIDCMD_DATA3_BASE_IDX                                                             2
11521 #define mmSDMA2_RLC6_MIDCMD_DATA4                                                                      0x0384
11522 #define mmSDMA2_RLC6_MIDCMD_DATA4_BASE_IDX                                                             2
11523 #define mmSDMA2_RLC6_MIDCMD_DATA5                                                                      0x0385
11524 #define mmSDMA2_RLC6_MIDCMD_DATA5_BASE_IDX                                                             2
11525 #define mmSDMA2_RLC6_MIDCMD_DATA6                                                                      0x0386
11526 #define mmSDMA2_RLC6_MIDCMD_DATA6_BASE_IDX                                                             2
11527 #define mmSDMA2_RLC6_MIDCMD_DATA7                                                                      0x0387
11528 #define mmSDMA2_RLC6_MIDCMD_DATA7_BASE_IDX                                                             2
11529 #define mmSDMA2_RLC6_MIDCMD_DATA8                                                                      0x0388
11530 #define mmSDMA2_RLC6_MIDCMD_DATA8_BASE_IDX                                                             2
11531 #define mmSDMA2_RLC6_MIDCMD_DATA9                                                                      0x0389
11532 #define mmSDMA2_RLC6_MIDCMD_DATA9_BASE_IDX                                                             2
11533 #define mmSDMA2_RLC6_MIDCMD_DATA10                                                                     0x038a
11534 #define mmSDMA2_RLC6_MIDCMD_DATA10_BASE_IDX                                                            2
11535 #define mmSDMA2_RLC6_MIDCMD_CNTL                                                                       0x038b
11536 #define mmSDMA2_RLC6_MIDCMD_CNTL_BASE_IDX                                                              2
11537 #define mmSDMA2_RLC7_RB_CNTL                                                                           0x0398
11538 #define mmSDMA2_RLC7_RB_CNTL_BASE_IDX                                                                  2
11539 #define mmSDMA2_RLC7_RB_BASE                                                                           0x0399
11540 #define mmSDMA2_RLC7_RB_BASE_BASE_IDX                                                                  2
11541 #define mmSDMA2_RLC7_RB_BASE_HI                                                                        0x039a
11542 #define mmSDMA2_RLC7_RB_BASE_HI_BASE_IDX                                                               2
11543 #define mmSDMA2_RLC7_RB_RPTR                                                                           0x039b
11544 #define mmSDMA2_RLC7_RB_RPTR_BASE_IDX                                                                  2
11545 #define mmSDMA2_RLC7_RB_RPTR_HI                                                                        0x039c
11546 #define mmSDMA2_RLC7_RB_RPTR_HI_BASE_IDX                                                               2
11547 #define mmSDMA2_RLC7_RB_WPTR                                                                           0x039d
11548 #define mmSDMA2_RLC7_RB_WPTR_BASE_IDX                                                                  2
11549 #define mmSDMA2_RLC7_RB_WPTR_HI                                                                        0x039e
11550 #define mmSDMA2_RLC7_RB_WPTR_HI_BASE_IDX                                                               2
11551 #define mmSDMA2_RLC7_RB_WPTR_POLL_CNTL                                                                 0x039f
11552 #define mmSDMA2_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX                                                        2
11553 #define mmSDMA2_RLC7_RB_RPTR_ADDR_HI                                                                   0x03a0
11554 #define mmSDMA2_RLC7_RB_RPTR_ADDR_HI_BASE_IDX                                                          2
11555 #define mmSDMA2_RLC7_RB_RPTR_ADDR_LO                                                                   0x03a1
11556 #define mmSDMA2_RLC7_RB_RPTR_ADDR_LO_BASE_IDX                                                          2
11557 #define mmSDMA2_RLC7_IB_CNTL                                                                           0x03a2
11558 #define mmSDMA2_RLC7_IB_CNTL_BASE_IDX                                                                  2
11559 #define mmSDMA2_RLC7_IB_RPTR                                                                           0x03a3
11560 #define mmSDMA2_RLC7_IB_RPTR_BASE_IDX                                                                  2
11561 #define mmSDMA2_RLC7_IB_OFFSET                                                                         0x03a4
11562 #define mmSDMA2_RLC7_IB_OFFSET_BASE_IDX                                                                2
11563 #define mmSDMA2_RLC7_IB_BASE_LO                                                                        0x03a5
11564 #define mmSDMA2_RLC7_IB_BASE_LO_BASE_IDX                                                               2
11565 #define mmSDMA2_RLC7_IB_BASE_HI                                                                        0x03a6
11566 #define mmSDMA2_RLC7_IB_BASE_HI_BASE_IDX                                                               2
11567 #define mmSDMA2_RLC7_IB_SIZE                                                                           0x03a7
11568 #define mmSDMA2_RLC7_IB_SIZE_BASE_IDX                                                                  2
11569 #define mmSDMA2_RLC7_SKIP_CNTL                                                                         0x03a8
11570 #define mmSDMA2_RLC7_SKIP_CNTL_BASE_IDX                                                                2
11571 #define mmSDMA2_RLC7_CONTEXT_STATUS                                                                    0x03a9
11572 #define mmSDMA2_RLC7_CONTEXT_STATUS_BASE_IDX                                                           2
11573 #define mmSDMA2_RLC7_DOORBELL                                                                          0x03aa
11574 #define mmSDMA2_RLC7_DOORBELL_BASE_IDX                                                                 2
11575 #define mmSDMA2_RLC7_STATUS                                                                            0x03c0
11576 #define mmSDMA2_RLC7_STATUS_BASE_IDX                                                                   2
11577 #define mmSDMA2_RLC7_DOORBELL_LOG                                                                      0x03c1
11578 #define mmSDMA2_RLC7_DOORBELL_LOG_BASE_IDX                                                             2
11579 #define mmSDMA2_RLC7_WATERMARK                                                                         0x03c2
11580 #define mmSDMA2_RLC7_WATERMARK_BASE_IDX                                                                2
11581 #define mmSDMA2_RLC7_DOORBELL_OFFSET                                                                   0x03c3
11582 #define mmSDMA2_RLC7_DOORBELL_OFFSET_BASE_IDX                                                          2
11583 #define mmSDMA2_RLC7_CSA_ADDR_LO                                                                       0x03c4
11584 #define mmSDMA2_RLC7_CSA_ADDR_LO_BASE_IDX                                                              2
11585 #define mmSDMA2_RLC7_CSA_ADDR_HI                                                                       0x03c5
11586 #define mmSDMA2_RLC7_CSA_ADDR_HI_BASE_IDX                                                              2
11587 #define mmSDMA2_RLC7_IB_SUB_REMAIN                                                                     0x03c7
11588 #define mmSDMA2_RLC7_IB_SUB_REMAIN_BASE_IDX                                                            2
11589 #define mmSDMA2_RLC7_PREEMPT                                                                           0x03c8
11590 #define mmSDMA2_RLC7_PREEMPT_BASE_IDX                                                                  2
11591 #define mmSDMA2_RLC7_DUMMY_REG                                                                         0x03c9
11592 #define mmSDMA2_RLC7_DUMMY_REG_BASE_IDX                                                                2
11593 #define mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI                                                              0x03ca
11594 #define mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     2
11595 #define mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO                                                              0x03cb
11596 #define mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     2
11597 #define mmSDMA2_RLC7_RB_AQL_CNTL                                                                       0x03cc
11598 #define mmSDMA2_RLC7_RB_AQL_CNTL_BASE_IDX                                                              2
11599 #define mmSDMA2_RLC7_MINOR_PTR_UPDATE                                                                  0x03cd
11600 #define mmSDMA2_RLC7_MINOR_PTR_UPDATE_BASE_IDX                                                         2
11601 #define mmSDMA2_RLC7_MIDCMD_DATA0                                                                      0x03d8
11602 #define mmSDMA2_RLC7_MIDCMD_DATA0_BASE_IDX                                                             2
11603 #define mmSDMA2_RLC7_MIDCMD_DATA1                                                                      0x03d9
11604 #define mmSDMA2_RLC7_MIDCMD_DATA1_BASE_IDX                                                             2
11605 #define mmSDMA2_RLC7_MIDCMD_DATA2                                                                      0x03da
11606 #define mmSDMA2_RLC7_MIDCMD_DATA2_BASE_IDX                                                             2
11607 #define mmSDMA2_RLC7_MIDCMD_DATA3                                                                      0x03db
11608 #define mmSDMA2_RLC7_MIDCMD_DATA3_BASE_IDX                                                             2
11609 #define mmSDMA2_RLC7_MIDCMD_DATA4                                                                      0x03dc
11610 #define mmSDMA2_RLC7_MIDCMD_DATA4_BASE_IDX                                                             2
11611 #define mmSDMA2_RLC7_MIDCMD_DATA5                                                                      0x03dd
11612 #define mmSDMA2_RLC7_MIDCMD_DATA5_BASE_IDX                                                             2
11613 #define mmSDMA2_RLC7_MIDCMD_DATA6                                                                      0x03de
11614 #define mmSDMA2_RLC7_MIDCMD_DATA6_BASE_IDX                                                             2
11615 #define mmSDMA2_RLC7_MIDCMD_DATA7                                                                      0x03df
11616 #define mmSDMA2_RLC7_MIDCMD_DATA7_BASE_IDX                                                             2
11617 #define mmSDMA2_RLC7_MIDCMD_DATA8                                                                      0x03e0
11618 #define mmSDMA2_RLC7_MIDCMD_DATA8_BASE_IDX                                                             2
11619 #define mmSDMA2_RLC7_MIDCMD_DATA9                                                                      0x03e1
11620 #define mmSDMA2_RLC7_MIDCMD_DATA9_BASE_IDX                                                             2
11621 #define mmSDMA2_RLC7_MIDCMD_DATA10                                                                     0x03e2
11622 #define mmSDMA2_RLC7_MIDCMD_DATA10_BASE_IDX                                                            2
11623 #define mmSDMA2_RLC7_MIDCMD_CNTL                                                                       0x03e3
11624 #define mmSDMA2_RLC7_MIDCMD_CNTL_BASE_IDX                                                              2
11625 
11626 
11627 // addressBlock: gc_sdma3_sdma3dec
11628 // base address: 0x71000
11629 #define mmSDMA3_DEC_START                                                                              0x0400
11630 #define mmSDMA3_DEC_START_BASE_IDX                                                                     2
11631 #define mmSDMA3_GLOBAL_TIMESTAMP_LO                                                                    0x040f
11632 #define mmSDMA3_GLOBAL_TIMESTAMP_LO_BASE_IDX                                                           2
11633 #define mmSDMA3_GLOBAL_TIMESTAMP_HI                                                                    0x0410
11634 #define mmSDMA3_GLOBAL_TIMESTAMP_HI_BASE_IDX                                                           2
11635 #define mmSDMA3_PG_CNTL                                                                                0x0416
11636 #define mmSDMA3_PG_CNTL_BASE_IDX                                                                       2
11637 #define mmSDMA3_PG_CTX_LO                                                                              0x0417
11638 #define mmSDMA3_PG_CTX_LO_BASE_IDX                                                                     2
11639 #define mmSDMA3_PG_CTX_HI                                                                              0x0418
11640 #define mmSDMA3_PG_CTX_HI_BASE_IDX                                                                     2
11641 #define mmSDMA3_PG_CTX_CNTL                                                                            0x0419
11642 #define mmSDMA3_PG_CTX_CNTL_BASE_IDX                                                                   2
11643 #define mmSDMA3_POWER_CNTL                                                                             0x041a
11644 #define mmSDMA3_POWER_CNTL_BASE_IDX                                                                    2
11645 #define mmSDMA3_CLK_CTRL                                                                               0x041b
11646 #define mmSDMA3_CLK_CTRL_BASE_IDX                                                                      2
11647 #define mmSDMA3_CNTL                                                                                   0x041c
11648 #define mmSDMA3_CNTL_BASE_IDX                                                                          2
11649 #define mmSDMA3_CHICKEN_BITS                                                                           0x041d
11650 #define mmSDMA3_CHICKEN_BITS_BASE_IDX                                                                  2
11651 #define mmSDMA3_GB_ADDR_CONFIG                                                                         0x041e
11652 #define mmSDMA3_GB_ADDR_CONFIG_BASE_IDX                                                                2
11653 #define mmSDMA3_GB_ADDR_CONFIG_READ                                                                    0x041f
11654 #define mmSDMA3_GB_ADDR_CONFIG_READ_BASE_IDX                                                           2
11655 #define mmSDMA3_RB_RPTR_FETCH_HI                                                                       0x0420
11656 #define mmSDMA3_RB_RPTR_FETCH_HI_BASE_IDX                                                              2
11657 #define mmSDMA3_SEM_WAIT_FAIL_TIMER_CNTL                                                               0x0421
11658 #define mmSDMA3_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX                                                      2
11659 #define mmSDMA3_RB_RPTR_FETCH                                                                          0x0422
11660 #define mmSDMA3_RB_RPTR_FETCH_BASE_IDX                                                                 2
11661 #define mmSDMA3_IB_OFFSET_FETCH                                                                        0x0423
11662 #define mmSDMA3_IB_OFFSET_FETCH_BASE_IDX                                                               2
11663 #define mmSDMA3_PROGRAM                                                                                0x0424
11664 #define mmSDMA3_PROGRAM_BASE_IDX                                                                       2
11665 #define mmSDMA3_STATUS_REG                                                                             0x0425
11666 #define mmSDMA3_STATUS_REG_BASE_IDX                                                                    2
11667 #define mmSDMA3_STATUS1_REG                                                                            0x0426
11668 #define mmSDMA3_STATUS1_REG_BASE_IDX                                                                   2
11669 #define mmSDMA3_RD_BURST_CNTL                                                                          0x0427
11670 #define mmSDMA3_RD_BURST_CNTL_BASE_IDX                                                                 2
11671 #define mmSDMA3_HBM_PAGE_CONFIG                                                                        0x0428
11672 #define mmSDMA3_HBM_PAGE_CONFIG_BASE_IDX                                                               2
11673 #define mmSDMA3_UCODE_CHECKSUM                                                                         0x0429
11674 #define mmSDMA3_UCODE_CHECKSUM_BASE_IDX                                                                2
11675 #define mmSDMA3_F32_CNTL                                                                               0x042a
11676 #define mmSDMA3_F32_CNTL_BASE_IDX                                                                      2
11677 #define mmSDMA3_FREEZE                                                                                 0x042b
11678 #define mmSDMA3_FREEZE_BASE_IDX                                                                        2
11679 #define mmSDMA3_PHASE0_QUANTUM                                                                         0x042c
11680 #define mmSDMA3_PHASE0_QUANTUM_BASE_IDX                                                                2
11681 #define mmSDMA3_PHASE1_QUANTUM                                                                         0x042d
11682 #define mmSDMA3_PHASE1_QUANTUM_BASE_IDX                                                                2
11683 #define mmSDMA3_EDC_CONFIG                                                                             0x0432
11684 #define mmSDMA3_EDC_CONFIG_BASE_IDX                                                                    2
11685 #define mmSDMA3_BA_THRESHOLD                                                                           0x0433
11686 #define mmSDMA3_BA_THRESHOLD_BASE_IDX                                                                  2
11687 #define mmSDMA3_ID                                                                                     0x0434
11688 #define mmSDMA3_ID_BASE_IDX                                                                            2
11689 #define mmSDMA3_VERSION                                                                                0x0435
11690 #define mmSDMA3_VERSION_BASE_IDX                                                                       2
11691 #define mmSDMA3_EDC_COUNTER                                                                            0x0436
11692 #define mmSDMA3_EDC_COUNTER_BASE_IDX                                                                   2
11693 #define mmSDMA3_EDC_COUNTER_CLEAR                                                                      0x0437
11694 #define mmSDMA3_EDC_COUNTER_CLEAR_BASE_IDX                                                             2
11695 #define mmSDMA3_STATUS2_REG                                                                            0x0438
11696 #define mmSDMA3_STATUS2_REG_BASE_IDX                                                                   2
11697 #define mmSDMA3_ATOMIC_CNTL                                                                            0x0439
11698 #define mmSDMA3_ATOMIC_CNTL_BASE_IDX                                                                   2
11699 #define mmSDMA3_ATOMIC_PREOP_LO                                                                        0x043a
11700 #define mmSDMA3_ATOMIC_PREOP_LO_BASE_IDX                                                               2
11701 #define mmSDMA3_ATOMIC_PREOP_HI                                                                        0x043b
11702 #define mmSDMA3_ATOMIC_PREOP_HI_BASE_IDX                                                               2
11703 #define mmSDMA3_UTCL1_CNTL                                                                             0x043c
11704 #define mmSDMA3_UTCL1_CNTL_BASE_IDX                                                                    2
11705 #define mmSDMA3_UTCL1_WATERMK                                                                          0x043d
11706 #define mmSDMA3_UTCL1_WATERMK_BASE_IDX                                                                 2
11707 #define mmSDMA3_UTCL1_RD_STATUS                                                                        0x043e
11708 #define mmSDMA3_UTCL1_RD_STATUS_BASE_IDX                                                               2
11709 #define mmSDMA3_UTCL1_WR_STATUS                                                                        0x043f
11710 #define mmSDMA3_UTCL1_WR_STATUS_BASE_IDX                                                               2
11711 #define mmSDMA3_UTCL1_INV0                                                                             0x0440
11712 #define mmSDMA3_UTCL1_INV0_BASE_IDX                                                                    2
11713 #define mmSDMA3_UTCL1_INV1                                                                             0x0441
11714 #define mmSDMA3_UTCL1_INV1_BASE_IDX                                                                    2
11715 #define mmSDMA3_UTCL1_INV2                                                                             0x0442
11716 #define mmSDMA3_UTCL1_INV2_BASE_IDX                                                                    2
11717 #define mmSDMA3_UTCL1_RD_XNACK0                                                                        0x0443
11718 #define mmSDMA3_UTCL1_RD_XNACK0_BASE_IDX                                                               2
11719 #define mmSDMA3_UTCL1_RD_XNACK1                                                                        0x0444
11720 #define mmSDMA3_UTCL1_RD_XNACK1_BASE_IDX                                                               2
11721 #define mmSDMA3_UTCL1_WR_XNACK0                                                                        0x0445
11722 #define mmSDMA3_UTCL1_WR_XNACK0_BASE_IDX                                                               2
11723 #define mmSDMA3_UTCL1_WR_XNACK1                                                                        0x0446
11724 #define mmSDMA3_UTCL1_WR_XNACK1_BASE_IDX                                                               2
11725 #define mmSDMA3_UTCL1_TIMEOUT                                                                          0x0447
11726 #define mmSDMA3_UTCL1_TIMEOUT_BASE_IDX                                                                 2
11727 #define mmSDMA3_UTCL1_PAGE                                                                             0x0448
11728 #define mmSDMA3_UTCL1_PAGE_BASE_IDX                                                                    2
11729 #define mmSDMA3_RELAX_ORDERING_LUT                                                                     0x044a
11730 #define mmSDMA3_RELAX_ORDERING_LUT_BASE_IDX                                                            2
11731 #define mmSDMA3_CHICKEN_BITS_2                                                                         0x044b
11732 #define mmSDMA3_CHICKEN_BITS_2_BASE_IDX                                                                2
11733 #define mmSDMA3_STATUS3_REG                                                                            0x044c
11734 #define mmSDMA3_STATUS3_REG_BASE_IDX                                                                   2
11735 #define mmSDMA3_PHYSICAL_ADDR_LO                                                                       0x044d
11736 #define mmSDMA3_PHYSICAL_ADDR_LO_BASE_IDX                                                              2
11737 #define mmSDMA3_PHYSICAL_ADDR_HI                                                                       0x044e
11738 #define mmSDMA3_PHYSICAL_ADDR_HI_BASE_IDX                                                              2
11739 #define mmSDMA3_PHASE2_QUANTUM                                                                         0x044f
11740 #define mmSDMA3_PHASE2_QUANTUM_BASE_IDX                                                                2
11741 #define mmSDMA3_ERROR_LOG                                                                              0x0450
11742 #define mmSDMA3_ERROR_LOG_BASE_IDX                                                                     2
11743 #define mmSDMA3_PUB_DUMMY_REG0                                                                         0x0451
11744 #define mmSDMA3_PUB_DUMMY_REG0_BASE_IDX                                                                2
11745 #define mmSDMA3_PUB_DUMMY_REG1                                                                         0x0452
11746 #define mmSDMA3_PUB_DUMMY_REG1_BASE_IDX                                                                2
11747 #define mmSDMA3_PUB_DUMMY_REG2                                                                         0x0453
11748 #define mmSDMA3_PUB_DUMMY_REG2_BASE_IDX                                                                2
11749 #define mmSDMA3_PUB_DUMMY_REG3                                                                         0x0454
11750 #define mmSDMA3_PUB_DUMMY_REG3_BASE_IDX                                                                2
11751 #define mmSDMA3_F32_COUNTER                                                                            0x0455
11752 #define mmSDMA3_F32_COUNTER_BASE_IDX                                                                   2
11753 #define mmSDMA3_CRD_CNTL                                                                               0x045b
11754 #define mmSDMA3_CRD_CNTL_BASE_IDX                                                                      2
11755 #define mmSDMA3_AQL_STATUS                                                                             0x045f
11756 #define mmSDMA3_AQL_STATUS_BASE_IDX                                                                    2
11757 #define mmSDMA3_EA_DBIT_ADDR_DATA                                                                      0x0460
11758 #define mmSDMA3_EA_DBIT_ADDR_DATA_BASE_IDX                                                             2
11759 #define mmSDMA3_EA_DBIT_ADDR_INDEX                                                                     0x0461
11760 #define mmSDMA3_EA_DBIT_ADDR_INDEX_BASE_IDX                                                            2
11761 #define mmSDMA3_TLBI_GCR_CNTL                                                                          0x0462
11762 #define mmSDMA3_TLBI_GCR_CNTL_BASE_IDX                                                                 2
11763 #define mmSDMA3_TILING_CONFIG                                                                          0x0463
11764 #define mmSDMA3_TILING_CONFIG_BASE_IDX                                                                 2
11765 #define mmSDMA3_INT_STATUS                                                                             0x0470
11766 #define mmSDMA3_INT_STATUS_BASE_IDX                                                                    2
11767 #define mmSDMA3_HOLE_ADDR_LO                                                                           0x0472
11768 #define mmSDMA3_HOLE_ADDR_LO_BASE_IDX                                                                  2
11769 #define mmSDMA3_HOLE_ADDR_HI                                                                           0x0473
11770 #define mmSDMA3_HOLE_ADDR_HI_BASE_IDX                                                                  2
11771 #define mmSDMA3_CLOCK_GATING_REG                                                                       0x0475
11772 #define mmSDMA3_CLOCK_GATING_REG_BASE_IDX                                                              2
11773 #define mmSDMA3_STATUS4_REG                                                                            0x0476
11774 #define mmSDMA3_STATUS4_REG_BASE_IDX                                                                   2
11775 #define mmSDMA3_SCRATCH_RAM_DATA                                                                       0x0477
11776 #define mmSDMA3_SCRATCH_RAM_DATA_BASE_IDX                                                              2
11777 #define mmSDMA3_SCRATCH_RAM_ADDR                                                                       0x0478
11778 #define mmSDMA3_SCRATCH_RAM_ADDR_BASE_IDX                                                              2
11779 #define mmSDMA3_TIMESTAMP_CNTL                                                                         0x0479
11780 #define mmSDMA3_TIMESTAMP_CNTL_BASE_IDX                                                                2
11781 #define mmSDMA3_STATUS5_REG                                                                            0x047a
11782 #define mmSDMA3_STATUS5_REG_BASE_IDX                                                                   2
11783 #define mmSDMA3_QUEUE_RESET_REQ                                                                        0x047b
11784 #define mmSDMA3_QUEUE_RESET_REQ_BASE_IDX                                                               2
11785 #define mmSDMA3_GFX_RB_CNTL                                                                            0x0480
11786 #define mmSDMA3_GFX_RB_CNTL_BASE_IDX                                                                   2
11787 #define mmSDMA3_GFX_RB_BASE                                                                            0x0481
11788 #define mmSDMA3_GFX_RB_BASE_BASE_IDX                                                                   2
11789 #define mmSDMA3_GFX_RB_BASE_HI                                                                         0x0482
11790 #define mmSDMA3_GFX_RB_BASE_HI_BASE_IDX                                                                2
11791 #define mmSDMA3_GFX_RB_RPTR                                                                            0x0483
11792 #define mmSDMA3_GFX_RB_RPTR_BASE_IDX                                                                   2
11793 #define mmSDMA3_GFX_RB_RPTR_HI                                                                         0x0484
11794 #define mmSDMA3_GFX_RB_RPTR_HI_BASE_IDX                                                                2
11795 #define mmSDMA3_GFX_RB_WPTR                                                                            0x0485
11796 #define mmSDMA3_GFX_RB_WPTR_BASE_IDX                                                                   2
11797 #define mmSDMA3_GFX_RB_WPTR_HI                                                                         0x0486
11798 #define mmSDMA3_GFX_RB_WPTR_HI_BASE_IDX                                                                2
11799 #define mmSDMA3_GFX_RB_WPTR_POLL_CNTL                                                                  0x0487
11800 #define mmSDMA3_GFX_RB_WPTR_POLL_CNTL_BASE_IDX                                                         2
11801 #define mmSDMA3_GFX_RB_RPTR_ADDR_HI                                                                    0x0488
11802 #define mmSDMA3_GFX_RB_RPTR_ADDR_HI_BASE_IDX                                                           2
11803 #define mmSDMA3_GFX_RB_RPTR_ADDR_LO                                                                    0x0489
11804 #define mmSDMA3_GFX_RB_RPTR_ADDR_LO_BASE_IDX                                                           2
11805 #define mmSDMA3_GFX_IB_CNTL                                                                            0x048a
11806 #define mmSDMA3_GFX_IB_CNTL_BASE_IDX                                                                   2
11807 #define mmSDMA3_GFX_IB_RPTR                                                                            0x048b
11808 #define mmSDMA3_GFX_IB_RPTR_BASE_IDX                                                                   2
11809 #define mmSDMA3_GFX_IB_OFFSET                                                                          0x048c
11810 #define mmSDMA3_GFX_IB_OFFSET_BASE_IDX                                                                 2
11811 #define mmSDMA3_GFX_IB_BASE_LO                                                                         0x048d
11812 #define mmSDMA3_GFX_IB_BASE_LO_BASE_IDX                                                                2
11813 #define mmSDMA3_GFX_IB_BASE_HI                                                                         0x048e
11814 #define mmSDMA3_GFX_IB_BASE_HI_BASE_IDX                                                                2
11815 #define mmSDMA3_GFX_IB_SIZE                                                                            0x048f
11816 #define mmSDMA3_GFX_IB_SIZE_BASE_IDX                                                                   2
11817 #define mmSDMA3_GFX_SKIP_CNTL                                                                          0x0490
11818 #define mmSDMA3_GFX_SKIP_CNTL_BASE_IDX                                                                 2
11819 #define mmSDMA3_GFX_CONTEXT_STATUS                                                                     0x0491
11820 #define mmSDMA3_GFX_CONTEXT_STATUS_BASE_IDX                                                            2
11821 #define mmSDMA3_GFX_DOORBELL                                                                           0x0492
11822 #define mmSDMA3_GFX_DOORBELL_BASE_IDX                                                                  2
11823 #define mmSDMA3_GFX_CONTEXT_CNTL                                                                       0x0493
11824 #define mmSDMA3_GFX_CONTEXT_CNTL_BASE_IDX                                                              2
11825 #define mmSDMA3_GFX_STATUS                                                                             0x04a8
11826 #define mmSDMA3_GFX_STATUS_BASE_IDX                                                                    2
11827 #define mmSDMA3_GFX_DOORBELL_LOG                                                                       0x04a9
11828 #define mmSDMA3_GFX_DOORBELL_LOG_BASE_IDX                                                              2
11829 #define mmSDMA3_GFX_WATERMARK                                                                          0x04aa
11830 #define mmSDMA3_GFX_WATERMARK_BASE_IDX                                                                 2
11831 #define mmSDMA3_GFX_DOORBELL_OFFSET                                                                    0x04ab
11832 #define mmSDMA3_GFX_DOORBELL_OFFSET_BASE_IDX                                                           2
11833 #define mmSDMA3_GFX_CSA_ADDR_LO                                                                        0x04ac
11834 #define mmSDMA3_GFX_CSA_ADDR_LO_BASE_IDX                                                               2
11835 #define mmSDMA3_GFX_CSA_ADDR_HI                                                                        0x04ad
11836 #define mmSDMA3_GFX_CSA_ADDR_HI_BASE_IDX                                                               2
11837 #define mmSDMA3_GFX_IB_SUB_REMAIN                                                                      0x04af
11838 #define mmSDMA3_GFX_IB_SUB_REMAIN_BASE_IDX                                                             2
11839 #define mmSDMA3_GFX_PREEMPT                                                                            0x04b0
11840 #define mmSDMA3_GFX_PREEMPT_BASE_IDX                                                                   2
11841 #define mmSDMA3_GFX_DUMMY_REG                                                                          0x04b1
11842 #define mmSDMA3_GFX_DUMMY_REG_BASE_IDX                                                                 2
11843 #define mmSDMA3_GFX_RB_WPTR_POLL_ADDR_HI                                                               0x04b2
11844 #define mmSDMA3_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                      2
11845 #define mmSDMA3_GFX_RB_WPTR_POLL_ADDR_LO                                                               0x04b3
11846 #define mmSDMA3_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                      2
11847 #define mmSDMA3_GFX_RB_AQL_CNTL                                                                        0x04b4
11848 #define mmSDMA3_GFX_RB_AQL_CNTL_BASE_IDX                                                               2
11849 #define mmSDMA3_GFX_MINOR_PTR_UPDATE                                                                   0x04b5
11850 #define mmSDMA3_GFX_MINOR_PTR_UPDATE_BASE_IDX                                                          2
11851 #define mmSDMA3_GFX_MIDCMD_DATA0                                                                       0x04c0
11852 #define mmSDMA3_GFX_MIDCMD_DATA0_BASE_IDX                                                              2
11853 #define mmSDMA3_GFX_MIDCMD_DATA1                                                                       0x04c1
11854 #define mmSDMA3_GFX_MIDCMD_DATA1_BASE_IDX                                                              2
11855 #define mmSDMA3_GFX_MIDCMD_DATA2                                                                       0x04c2
11856 #define mmSDMA3_GFX_MIDCMD_DATA2_BASE_IDX                                                              2
11857 #define mmSDMA3_GFX_MIDCMD_DATA3                                                                       0x04c3
11858 #define mmSDMA3_GFX_MIDCMD_DATA3_BASE_IDX                                                              2
11859 #define mmSDMA3_GFX_MIDCMD_DATA4                                                                       0x04c4
11860 #define mmSDMA3_GFX_MIDCMD_DATA4_BASE_IDX                                                              2
11861 #define mmSDMA3_GFX_MIDCMD_DATA5                                                                       0x04c5
11862 #define mmSDMA3_GFX_MIDCMD_DATA5_BASE_IDX                                                              2
11863 #define mmSDMA3_GFX_MIDCMD_DATA6                                                                       0x04c6
11864 #define mmSDMA3_GFX_MIDCMD_DATA6_BASE_IDX                                                              2
11865 #define mmSDMA3_GFX_MIDCMD_DATA7                                                                       0x04c7
11866 #define mmSDMA3_GFX_MIDCMD_DATA7_BASE_IDX                                                              2
11867 #define mmSDMA3_GFX_MIDCMD_DATA8                                                                       0x04c8
11868 #define mmSDMA3_GFX_MIDCMD_DATA8_BASE_IDX                                                              2
11869 #define mmSDMA3_GFX_MIDCMD_DATA9                                                                       0x04c9
11870 #define mmSDMA3_GFX_MIDCMD_DATA9_BASE_IDX                                                              2
11871 #define mmSDMA3_GFX_MIDCMD_DATA10                                                                      0x04ca
11872 #define mmSDMA3_GFX_MIDCMD_DATA10_BASE_IDX                                                             2
11873 #define mmSDMA3_GFX_MIDCMD_CNTL                                                                        0x04cb
11874 #define mmSDMA3_GFX_MIDCMD_CNTL_BASE_IDX                                                               2
11875 #define mmSDMA3_PAGE_RB_CNTL                                                                           0x04d8
11876 #define mmSDMA3_PAGE_RB_CNTL_BASE_IDX                                                                  2
11877 #define mmSDMA3_PAGE_RB_BASE                                                                           0x04d9
11878 #define mmSDMA3_PAGE_RB_BASE_BASE_IDX                                                                  2
11879 #define mmSDMA3_PAGE_RB_BASE_HI                                                                        0x04da
11880 #define mmSDMA3_PAGE_RB_BASE_HI_BASE_IDX                                                               2
11881 #define mmSDMA3_PAGE_RB_RPTR                                                                           0x04db
11882 #define mmSDMA3_PAGE_RB_RPTR_BASE_IDX                                                                  2
11883 #define mmSDMA3_PAGE_RB_RPTR_HI                                                                        0x04dc
11884 #define mmSDMA3_PAGE_RB_RPTR_HI_BASE_IDX                                                               2
11885 #define mmSDMA3_PAGE_RB_WPTR                                                                           0x04dd
11886 #define mmSDMA3_PAGE_RB_WPTR_BASE_IDX                                                                  2
11887 #define mmSDMA3_PAGE_RB_WPTR_HI                                                                        0x04de
11888 #define mmSDMA3_PAGE_RB_WPTR_HI_BASE_IDX                                                               2
11889 #define mmSDMA3_PAGE_RB_WPTR_POLL_CNTL                                                                 0x04df
11890 #define mmSDMA3_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX                                                        2
11891 #define mmSDMA3_PAGE_RB_RPTR_ADDR_HI                                                                   0x04e0
11892 #define mmSDMA3_PAGE_RB_RPTR_ADDR_HI_BASE_IDX                                                          2
11893 #define mmSDMA3_PAGE_RB_RPTR_ADDR_LO                                                                   0x04e1
11894 #define mmSDMA3_PAGE_RB_RPTR_ADDR_LO_BASE_IDX                                                          2
11895 #define mmSDMA3_PAGE_IB_CNTL                                                                           0x04e2
11896 #define mmSDMA3_PAGE_IB_CNTL_BASE_IDX                                                                  2
11897 #define mmSDMA3_PAGE_IB_RPTR                                                                           0x04e3
11898 #define mmSDMA3_PAGE_IB_RPTR_BASE_IDX                                                                  2
11899 #define mmSDMA3_PAGE_IB_OFFSET                                                                         0x04e4
11900 #define mmSDMA3_PAGE_IB_OFFSET_BASE_IDX                                                                2
11901 #define mmSDMA3_PAGE_IB_BASE_LO                                                                        0x04e5
11902 #define mmSDMA3_PAGE_IB_BASE_LO_BASE_IDX                                                               2
11903 #define mmSDMA3_PAGE_IB_BASE_HI                                                                        0x04e6
11904 #define mmSDMA3_PAGE_IB_BASE_HI_BASE_IDX                                                               2
11905 #define mmSDMA3_PAGE_IB_SIZE                                                                           0x04e7
11906 #define mmSDMA3_PAGE_IB_SIZE_BASE_IDX                                                                  2
11907 #define mmSDMA3_PAGE_SKIP_CNTL                                                                         0x04e8
11908 #define mmSDMA3_PAGE_SKIP_CNTL_BASE_IDX                                                                2
11909 #define mmSDMA3_PAGE_CONTEXT_STATUS                                                                    0x04e9
11910 #define mmSDMA3_PAGE_CONTEXT_STATUS_BASE_IDX                                                           2
11911 #define mmSDMA3_PAGE_DOORBELL                                                                          0x04ea
11912 #define mmSDMA3_PAGE_DOORBELL_BASE_IDX                                                                 2
11913 #define mmSDMA3_PAGE_STATUS                                                                            0x0500
11914 #define mmSDMA3_PAGE_STATUS_BASE_IDX                                                                   2
11915 #define mmSDMA3_PAGE_DOORBELL_LOG                                                                      0x0501
11916 #define mmSDMA3_PAGE_DOORBELL_LOG_BASE_IDX                                                             2
11917 #define mmSDMA3_PAGE_WATERMARK                                                                         0x0502
11918 #define mmSDMA3_PAGE_WATERMARK_BASE_IDX                                                                2
11919 #define mmSDMA3_PAGE_DOORBELL_OFFSET                                                                   0x0503
11920 #define mmSDMA3_PAGE_DOORBELL_OFFSET_BASE_IDX                                                          2
11921 #define mmSDMA3_PAGE_CSA_ADDR_LO                                                                       0x0504
11922 #define mmSDMA3_PAGE_CSA_ADDR_LO_BASE_IDX                                                              2
11923 #define mmSDMA3_PAGE_CSA_ADDR_HI                                                                       0x0505
11924 #define mmSDMA3_PAGE_CSA_ADDR_HI_BASE_IDX                                                              2
11925 #define mmSDMA3_PAGE_IB_SUB_REMAIN                                                                     0x0507
11926 #define mmSDMA3_PAGE_IB_SUB_REMAIN_BASE_IDX                                                            2
11927 #define mmSDMA3_PAGE_PREEMPT                                                                           0x0508
11928 #define mmSDMA3_PAGE_PREEMPT_BASE_IDX                                                                  2
11929 #define mmSDMA3_PAGE_DUMMY_REG                                                                         0x0509
11930 #define mmSDMA3_PAGE_DUMMY_REG_BASE_IDX                                                                2
11931 #define mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI                                                              0x050a
11932 #define mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     2
11933 #define mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO                                                              0x050b
11934 #define mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     2
11935 #define mmSDMA3_PAGE_RB_AQL_CNTL                                                                       0x050c
11936 #define mmSDMA3_PAGE_RB_AQL_CNTL_BASE_IDX                                                              2
11937 #define mmSDMA3_PAGE_MINOR_PTR_UPDATE                                                                  0x050d
11938 #define mmSDMA3_PAGE_MINOR_PTR_UPDATE_BASE_IDX                                                         2
11939 #define mmSDMA3_PAGE_MIDCMD_DATA0                                                                      0x0518
11940 #define mmSDMA3_PAGE_MIDCMD_DATA0_BASE_IDX                                                             2
11941 #define mmSDMA3_PAGE_MIDCMD_DATA1                                                                      0x0519
11942 #define mmSDMA3_PAGE_MIDCMD_DATA1_BASE_IDX                                                             2
11943 #define mmSDMA3_PAGE_MIDCMD_DATA2                                                                      0x051a
11944 #define mmSDMA3_PAGE_MIDCMD_DATA2_BASE_IDX                                                             2
11945 #define mmSDMA3_PAGE_MIDCMD_DATA3                                                                      0x051b
11946 #define mmSDMA3_PAGE_MIDCMD_DATA3_BASE_IDX                                                             2
11947 #define mmSDMA3_PAGE_MIDCMD_DATA4                                                                      0x051c
11948 #define mmSDMA3_PAGE_MIDCMD_DATA4_BASE_IDX                                                             2
11949 #define mmSDMA3_PAGE_MIDCMD_DATA5                                                                      0x051d
11950 #define mmSDMA3_PAGE_MIDCMD_DATA5_BASE_IDX                                                             2
11951 #define mmSDMA3_PAGE_MIDCMD_DATA6                                                                      0x051e
11952 #define mmSDMA3_PAGE_MIDCMD_DATA6_BASE_IDX                                                             2
11953 #define mmSDMA3_PAGE_MIDCMD_DATA7                                                                      0x051f
11954 #define mmSDMA3_PAGE_MIDCMD_DATA7_BASE_IDX                                                             2
11955 #define mmSDMA3_PAGE_MIDCMD_DATA8                                                                      0x0520
11956 #define mmSDMA3_PAGE_MIDCMD_DATA8_BASE_IDX                                                             2
11957 #define mmSDMA3_PAGE_MIDCMD_DATA9                                                                      0x0521
11958 #define mmSDMA3_PAGE_MIDCMD_DATA9_BASE_IDX                                                             2
11959 #define mmSDMA3_PAGE_MIDCMD_DATA10                                                                     0x0522
11960 #define mmSDMA3_PAGE_MIDCMD_DATA10_BASE_IDX                                                            2
11961 #define mmSDMA3_PAGE_MIDCMD_CNTL                                                                       0x0523
11962 #define mmSDMA3_PAGE_MIDCMD_CNTL_BASE_IDX                                                              2
11963 #define mmSDMA3_RLC0_RB_CNTL                                                                           0x0530
11964 #define mmSDMA3_RLC0_RB_CNTL_BASE_IDX                                                                  2
11965 #define mmSDMA3_RLC0_RB_BASE                                                                           0x0531
11966 #define mmSDMA3_RLC0_RB_BASE_BASE_IDX                                                                  2
11967 #define mmSDMA3_RLC0_RB_BASE_HI                                                                        0x0532
11968 #define mmSDMA3_RLC0_RB_BASE_HI_BASE_IDX                                                               2
11969 #define mmSDMA3_RLC0_RB_RPTR                                                                           0x0533
11970 #define mmSDMA3_RLC0_RB_RPTR_BASE_IDX                                                                  2
11971 #define mmSDMA3_RLC0_RB_RPTR_HI                                                                        0x0534
11972 #define mmSDMA3_RLC0_RB_RPTR_HI_BASE_IDX                                                               2
11973 #define mmSDMA3_RLC0_RB_WPTR                                                                           0x0535
11974 #define mmSDMA3_RLC0_RB_WPTR_BASE_IDX                                                                  2
11975 #define mmSDMA3_RLC0_RB_WPTR_HI                                                                        0x0536
11976 #define mmSDMA3_RLC0_RB_WPTR_HI_BASE_IDX                                                               2
11977 #define mmSDMA3_RLC0_RB_WPTR_POLL_CNTL                                                                 0x0537
11978 #define mmSDMA3_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX                                                        2
11979 #define mmSDMA3_RLC0_RB_RPTR_ADDR_HI                                                                   0x0538
11980 #define mmSDMA3_RLC0_RB_RPTR_ADDR_HI_BASE_IDX                                                          2
11981 #define mmSDMA3_RLC0_RB_RPTR_ADDR_LO                                                                   0x0539
11982 #define mmSDMA3_RLC0_RB_RPTR_ADDR_LO_BASE_IDX                                                          2
11983 #define mmSDMA3_RLC0_IB_CNTL                                                                           0x053a
11984 #define mmSDMA3_RLC0_IB_CNTL_BASE_IDX                                                                  2
11985 #define mmSDMA3_RLC0_IB_RPTR                                                                           0x053b
11986 #define mmSDMA3_RLC0_IB_RPTR_BASE_IDX                                                                  2
11987 #define mmSDMA3_RLC0_IB_OFFSET                                                                         0x053c
11988 #define mmSDMA3_RLC0_IB_OFFSET_BASE_IDX                                                                2
11989 #define mmSDMA3_RLC0_IB_BASE_LO                                                                        0x053d
11990 #define mmSDMA3_RLC0_IB_BASE_LO_BASE_IDX                                                               2
11991 #define mmSDMA3_RLC0_IB_BASE_HI                                                                        0x053e
11992 #define mmSDMA3_RLC0_IB_BASE_HI_BASE_IDX                                                               2
11993 #define mmSDMA3_RLC0_IB_SIZE                                                                           0x053f
11994 #define mmSDMA3_RLC0_IB_SIZE_BASE_IDX                                                                  2
11995 #define mmSDMA3_RLC0_SKIP_CNTL                                                                         0x0540
11996 #define mmSDMA3_RLC0_SKIP_CNTL_BASE_IDX                                                                2
11997 #define mmSDMA3_RLC0_CONTEXT_STATUS                                                                    0x0541
11998 #define mmSDMA3_RLC0_CONTEXT_STATUS_BASE_IDX                                                           2
11999 #define mmSDMA3_RLC0_DOORBELL                                                                          0x0542
12000 #define mmSDMA3_RLC0_DOORBELL_BASE_IDX                                                                 2
12001 #define mmSDMA3_RLC0_STATUS                                                                            0x0558
12002 #define mmSDMA3_RLC0_STATUS_BASE_IDX                                                                   2
12003 #define mmSDMA3_RLC0_DOORBELL_LOG                                                                      0x0559
12004 #define mmSDMA3_RLC0_DOORBELL_LOG_BASE_IDX                                                             2
12005 #define mmSDMA3_RLC0_WATERMARK                                                                         0x055a
12006 #define mmSDMA3_RLC0_WATERMARK_BASE_IDX                                                                2
12007 #define mmSDMA3_RLC0_DOORBELL_OFFSET                                                                   0x055b
12008 #define mmSDMA3_RLC0_DOORBELL_OFFSET_BASE_IDX                                                          2
12009 #define mmSDMA3_RLC0_CSA_ADDR_LO                                                                       0x055c
12010 #define mmSDMA3_RLC0_CSA_ADDR_LO_BASE_IDX                                                              2
12011 #define mmSDMA3_RLC0_CSA_ADDR_HI                                                                       0x055d
12012 #define mmSDMA3_RLC0_CSA_ADDR_HI_BASE_IDX                                                              2
12013 #define mmSDMA3_RLC0_IB_SUB_REMAIN                                                                     0x055f
12014 #define mmSDMA3_RLC0_IB_SUB_REMAIN_BASE_IDX                                                            2
12015 #define mmSDMA3_RLC0_PREEMPT                                                                           0x0560
12016 #define mmSDMA3_RLC0_PREEMPT_BASE_IDX                                                                  2
12017 #define mmSDMA3_RLC0_DUMMY_REG                                                                         0x0561
12018 #define mmSDMA3_RLC0_DUMMY_REG_BASE_IDX                                                                2
12019 #define mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI                                                              0x0562
12020 #define mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     2
12021 #define mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO                                                              0x0563
12022 #define mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     2
12023 #define mmSDMA3_RLC0_RB_AQL_CNTL                                                                       0x0564
12024 #define mmSDMA3_RLC0_RB_AQL_CNTL_BASE_IDX                                                              2
12025 #define mmSDMA3_RLC0_MINOR_PTR_UPDATE                                                                  0x0565
12026 #define mmSDMA3_RLC0_MINOR_PTR_UPDATE_BASE_IDX                                                         2
12027 #define mmSDMA3_RLC0_MIDCMD_DATA0                                                                      0x0570
12028 #define mmSDMA3_RLC0_MIDCMD_DATA0_BASE_IDX                                                             2
12029 #define mmSDMA3_RLC0_MIDCMD_DATA1                                                                      0x0571
12030 #define mmSDMA3_RLC0_MIDCMD_DATA1_BASE_IDX                                                             2
12031 #define mmSDMA3_RLC0_MIDCMD_DATA2                                                                      0x0572
12032 #define mmSDMA3_RLC0_MIDCMD_DATA2_BASE_IDX                                                             2
12033 #define mmSDMA3_RLC0_MIDCMD_DATA3                                                                      0x0573
12034 #define mmSDMA3_RLC0_MIDCMD_DATA3_BASE_IDX                                                             2
12035 #define mmSDMA3_RLC0_MIDCMD_DATA4                                                                      0x0574
12036 #define mmSDMA3_RLC0_MIDCMD_DATA4_BASE_IDX                                                             2
12037 #define mmSDMA3_RLC0_MIDCMD_DATA5                                                                      0x0575
12038 #define mmSDMA3_RLC0_MIDCMD_DATA5_BASE_IDX                                                             2
12039 #define mmSDMA3_RLC0_MIDCMD_DATA6                                                                      0x0576
12040 #define mmSDMA3_RLC0_MIDCMD_DATA6_BASE_IDX                                                             2
12041 #define mmSDMA3_RLC0_MIDCMD_DATA7                                                                      0x0577
12042 #define mmSDMA3_RLC0_MIDCMD_DATA7_BASE_IDX                                                             2
12043 #define mmSDMA3_RLC0_MIDCMD_DATA8                                                                      0x0578
12044 #define mmSDMA3_RLC0_MIDCMD_DATA8_BASE_IDX                                                             2
12045 #define mmSDMA3_RLC0_MIDCMD_DATA9                                                                      0x0579
12046 #define mmSDMA3_RLC0_MIDCMD_DATA9_BASE_IDX                                                             2
12047 #define mmSDMA3_RLC0_MIDCMD_DATA10                                                                     0x057a
12048 #define mmSDMA3_RLC0_MIDCMD_DATA10_BASE_IDX                                                            2
12049 #define mmSDMA3_RLC0_MIDCMD_CNTL                                                                       0x057b
12050 #define mmSDMA3_RLC0_MIDCMD_CNTL_BASE_IDX                                                              2
12051 #define mmSDMA3_RLC1_RB_CNTL                                                                           0x0588
12052 #define mmSDMA3_RLC1_RB_CNTL_BASE_IDX                                                                  2
12053 #define mmSDMA3_RLC1_RB_BASE                                                                           0x0589
12054 #define mmSDMA3_RLC1_RB_BASE_BASE_IDX                                                                  2
12055 #define mmSDMA3_RLC1_RB_BASE_HI                                                                        0x058a
12056 #define mmSDMA3_RLC1_RB_BASE_HI_BASE_IDX                                                               2
12057 #define mmSDMA3_RLC1_RB_RPTR                                                                           0x058b
12058 #define mmSDMA3_RLC1_RB_RPTR_BASE_IDX                                                                  2
12059 #define mmSDMA3_RLC1_RB_RPTR_HI                                                                        0x058c
12060 #define mmSDMA3_RLC1_RB_RPTR_HI_BASE_IDX                                                               2
12061 #define mmSDMA3_RLC1_RB_WPTR                                                                           0x058d
12062 #define mmSDMA3_RLC1_RB_WPTR_BASE_IDX                                                                  2
12063 #define mmSDMA3_RLC1_RB_WPTR_HI                                                                        0x058e
12064 #define mmSDMA3_RLC1_RB_WPTR_HI_BASE_IDX                                                               2
12065 #define mmSDMA3_RLC1_RB_WPTR_POLL_CNTL                                                                 0x058f
12066 #define mmSDMA3_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX                                                        2
12067 #define mmSDMA3_RLC1_RB_RPTR_ADDR_HI                                                                   0x0590
12068 #define mmSDMA3_RLC1_RB_RPTR_ADDR_HI_BASE_IDX                                                          2
12069 #define mmSDMA3_RLC1_RB_RPTR_ADDR_LO                                                                   0x0591
12070 #define mmSDMA3_RLC1_RB_RPTR_ADDR_LO_BASE_IDX                                                          2
12071 #define mmSDMA3_RLC1_IB_CNTL                                                                           0x0592
12072 #define mmSDMA3_RLC1_IB_CNTL_BASE_IDX                                                                  2
12073 #define mmSDMA3_RLC1_IB_RPTR                                                                           0x0593
12074 #define mmSDMA3_RLC1_IB_RPTR_BASE_IDX                                                                  2
12075 #define mmSDMA3_RLC1_IB_OFFSET                                                                         0x0594
12076 #define mmSDMA3_RLC1_IB_OFFSET_BASE_IDX                                                                2
12077 #define mmSDMA3_RLC1_IB_BASE_LO                                                                        0x0595
12078 #define mmSDMA3_RLC1_IB_BASE_LO_BASE_IDX                                                               2
12079 #define mmSDMA3_RLC1_IB_BASE_HI                                                                        0x0596
12080 #define mmSDMA3_RLC1_IB_BASE_HI_BASE_IDX                                                               2
12081 #define mmSDMA3_RLC1_IB_SIZE                                                                           0x0597
12082 #define mmSDMA3_RLC1_IB_SIZE_BASE_IDX                                                                  2
12083 #define mmSDMA3_RLC1_SKIP_CNTL                                                                         0x0598
12084 #define mmSDMA3_RLC1_SKIP_CNTL_BASE_IDX                                                                2
12085 #define mmSDMA3_RLC1_CONTEXT_STATUS                                                                    0x0599
12086 #define mmSDMA3_RLC1_CONTEXT_STATUS_BASE_IDX                                                           2
12087 #define mmSDMA3_RLC1_DOORBELL                                                                          0x059a
12088 #define mmSDMA3_RLC1_DOORBELL_BASE_IDX                                                                 2
12089 #define mmSDMA3_RLC1_STATUS                                                                            0x05b0
12090 #define mmSDMA3_RLC1_STATUS_BASE_IDX                                                                   2
12091 #define mmSDMA3_RLC1_DOORBELL_LOG                                                                      0x05b1
12092 #define mmSDMA3_RLC1_DOORBELL_LOG_BASE_IDX                                                             2
12093 #define mmSDMA3_RLC1_WATERMARK                                                                         0x05b2
12094 #define mmSDMA3_RLC1_WATERMARK_BASE_IDX                                                                2
12095 #define mmSDMA3_RLC1_DOORBELL_OFFSET                                                                   0x05b3
12096 #define mmSDMA3_RLC1_DOORBELL_OFFSET_BASE_IDX                                                          2
12097 #define mmSDMA3_RLC1_CSA_ADDR_LO                                                                       0x05b4
12098 #define mmSDMA3_RLC1_CSA_ADDR_LO_BASE_IDX                                                              2
12099 #define mmSDMA3_RLC1_CSA_ADDR_HI                                                                       0x05b5
12100 #define mmSDMA3_RLC1_CSA_ADDR_HI_BASE_IDX                                                              2
12101 #define mmSDMA3_RLC1_IB_SUB_REMAIN                                                                     0x05b7
12102 #define mmSDMA3_RLC1_IB_SUB_REMAIN_BASE_IDX                                                            2
12103 #define mmSDMA3_RLC1_PREEMPT                                                                           0x05b8
12104 #define mmSDMA3_RLC1_PREEMPT_BASE_IDX                                                                  2
12105 #define mmSDMA3_RLC1_DUMMY_REG                                                                         0x05b9
12106 #define mmSDMA3_RLC1_DUMMY_REG_BASE_IDX                                                                2
12107 #define mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI                                                              0x05ba
12108 #define mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     2
12109 #define mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO                                                              0x05bb
12110 #define mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     2
12111 #define mmSDMA3_RLC1_RB_AQL_CNTL                                                                       0x05bc
12112 #define mmSDMA3_RLC1_RB_AQL_CNTL_BASE_IDX                                                              2
12113 #define mmSDMA3_RLC1_MINOR_PTR_UPDATE                                                                  0x05bd
12114 #define mmSDMA3_RLC1_MINOR_PTR_UPDATE_BASE_IDX                                                         2
12115 #define mmSDMA3_RLC1_MIDCMD_DATA0                                                                      0x05c8
12116 #define mmSDMA3_RLC1_MIDCMD_DATA0_BASE_IDX                                                             2
12117 #define mmSDMA3_RLC1_MIDCMD_DATA1                                                                      0x05c9
12118 #define mmSDMA3_RLC1_MIDCMD_DATA1_BASE_IDX                                                             2
12119 #define mmSDMA3_RLC1_MIDCMD_DATA2                                                                      0x05ca
12120 #define mmSDMA3_RLC1_MIDCMD_DATA2_BASE_IDX                                                             2
12121 #define mmSDMA3_RLC1_MIDCMD_DATA3                                                                      0x05cb
12122 #define mmSDMA3_RLC1_MIDCMD_DATA3_BASE_IDX                                                             2
12123 #define mmSDMA3_RLC1_MIDCMD_DATA4                                                                      0x05cc
12124 #define mmSDMA3_RLC1_MIDCMD_DATA4_BASE_IDX                                                             2
12125 #define mmSDMA3_RLC1_MIDCMD_DATA5                                                                      0x05cd
12126 #define mmSDMA3_RLC1_MIDCMD_DATA5_BASE_IDX                                                             2
12127 #define mmSDMA3_RLC1_MIDCMD_DATA6                                                                      0x05ce
12128 #define mmSDMA3_RLC1_MIDCMD_DATA6_BASE_IDX                                                             2
12129 #define mmSDMA3_RLC1_MIDCMD_DATA7                                                                      0x05cf
12130 #define mmSDMA3_RLC1_MIDCMD_DATA7_BASE_IDX                                                             2
12131 #define mmSDMA3_RLC1_MIDCMD_DATA8                                                                      0x05d0
12132 #define mmSDMA3_RLC1_MIDCMD_DATA8_BASE_IDX                                                             2
12133 #define mmSDMA3_RLC1_MIDCMD_DATA9                                                                      0x05d1
12134 #define mmSDMA3_RLC1_MIDCMD_DATA9_BASE_IDX                                                             2
12135 #define mmSDMA3_RLC1_MIDCMD_DATA10                                                                     0x05d2
12136 #define mmSDMA3_RLC1_MIDCMD_DATA10_BASE_IDX                                                            2
12137 #define mmSDMA3_RLC1_MIDCMD_CNTL                                                                       0x05d3
12138 #define mmSDMA3_RLC1_MIDCMD_CNTL_BASE_IDX                                                              2
12139 #define mmSDMA3_RLC2_RB_CNTL                                                                           0x05e0
12140 #define mmSDMA3_RLC2_RB_CNTL_BASE_IDX                                                                  2
12141 #define mmSDMA3_RLC2_RB_BASE                                                                           0x05e1
12142 #define mmSDMA3_RLC2_RB_BASE_BASE_IDX                                                                  2
12143 #define mmSDMA3_RLC2_RB_BASE_HI                                                                        0x05e2
12144 #define mmSDMA3_RLC2_RB_BASE_HI_BASE_IDX                                                               2
12145 #define mmSDMA3_RLC2_RB_RPTR                                                                           0x05e3
12146 #define mmSDMA3_RLC2_RB_RPTR_BASE_IDX                                                                  2
12147 #define mmSDMA3_RLC2_RB_RPTR_HI                                                                        0x05e4
12148 #define mmSDMA3_RLC2_RB_RPTR_HI_BASE_IDX                                                               2
12149 #define mmSDMA3_RLC2_RB_WPTR                                                                           0x05e5
12150 #define mmSDMA3_RLC2_RB_WPTR_BASE_IDX                                                                  2
12151 #define mmSDMA3_RLC2_RB_WPTR_HI                                                                        0x05e6
12152 #define mmSDMA3_RLC2_RB_WPTR_HI_BASE_IDX                                                               2
12153 #define mmSDMA3_RLC2_RB_WPTR_POLL_CNTL                                                                 0x05e7
12154 #define mmSDMA3_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX                                                        2
12155 #define mmSDMA3_RLC2_RB_RPTR_ADDR_HI                                                                   0x05e8
12156 #define mmSDMA3_RLC2_RB_RPTR_ADDR_HI_BASE_IDX                                                          2
12157 #define mmSDMA3_RLC2_RB_RPTR_ADDR_LO                                                                   0x05e9
12158 #define mmSDMA3_RLC2_RB_RPTR_ADDR_LO_BASE_IDX                                                          2
12159 #define mmSDMA3_RLC2_IB_CNTL                                                                           0x05ea
12160 #define mmSDMA3_RLC2_IB_CNTL_BASE_IDX                                                                  2
12161 #define mmSDMA3_RLC2_IB_RPTR                                                                           0x05eb
12162 #define mmSDMA3_RLC2_IB_RPTR_BASE_IDX                                                                  2
12163 #define mmSDMA3_RLC2_IB_OFFSET                                                                         0x05ec
12164 #define mmSDMA3_RLC2_IB_OFFSET_BASE_IDX                                                                2
12165 #define mmSDMA3_RLC2_IB_BASE_LO                                                                        0x05ed
12166 #define mmSDMA3_RLC2_IB_BASE_LO_BASE_IDX                                                               2
12167 #define mmSDMA3_RLC2_IB_BASE_HI                                                                        0x05ee
12168 #define mmSDMA3_RLC2_IB_BASE_HI_BASE_IDX                                                               2
12169 #define mmSDMA3_RLC2_IB_SIZE                                                                           0x05ef
12170 #define mmSDMA3_RLC2_IB_SIZE_BASE_IDX                                                                  2
12171 #define mmSDMA3_RLC2_SKIP_CNTL                                                                         0x05f0
12172 #define mmSDMA3_RLC2_SKIP_CNTL_BASE_IDX                                                                2
12173 #define mmSDMA3_RLC2_CONTEXT_STATUS                                                                    0x05f1
12174 #define mmSDMA3_RLC2_CONTEXT_STATUS_BASE_IDX                                                           2
12175 #define mmSDMA3_RLC2_DOORBELL                                                                          0x05f2
12176 #define mmSDMA3_RLC2_DOORBELL_BASE_IDX                                                                 2
12177 #define mmSDMA3_RLC2_STATUS                                                                            0x0608
12178 #define mmSDMA3_RLC2_STATUS_BASE_IDX                                                                   2
12179 #define mmSDMA3_RLC2_DOORBELL_LOG                                                                      0x0609
12180 #define mmSDMA3_RLC2_DOORBELL_LOG_BASE_IDX                                                             2
12181 #define mmSDMA3_RLC2_WATERMARK                                                                         0x060a
12182 #define mmSDMA3_RLC2_WATERMARK_BASE_IDX                                                                2
12183 #define mmSDMA3_RLC2_DOORBELL_OFFSET                                                                   0x060b
12184 #define mmSDMA3_RLC2_DOORBELL_OFFSET_BASE_IDX                                                          2
12185 #define mmSDMA3_RLC2_CSA_ADDR_LO                                                                       0x060c
12186 #define mmSDMA3_RLC2_CSA_ADDR_LO_BASE_IDX                                                              2
12187 #define mmSDMA3_RLC2_CSA_ADDR_HI                                                                       0x060d
12188 #define mmSDMA3_RLC2_CSA_ADDR_HI_BASE_IDX                                                              2
12189 #define mmSDMA3_RLC2_IB_SUB_REMAIN                                                                     0x060f
12190 #define mmSDMA3_RLC2_IB_SUB_REMAIN_BASE_IDX                                                            2
12191 #define mmSDMA3_RLC2_PREEMPT                                                                           0x0610
12192 #define mmSDMA3_RLC2_PREEMPT_BASE_IDX                                                                  2
12193 #define mmSDMA3_RLC2_DUMMY_REG                                                                         0x0611
12194 #define mmSDMA3_RLC2_DUMMY_REG_BASE_IDX                                                                2
12195 #define mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI                                                              0x0612
12196 #define mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     2
12197 #define mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO                                                              0x0613
12198 #define mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     2
12199 #define mmSDMA3_RLC2_RB_AQL_CNTL                                                                       0x0614
12200 #define mmSDMA3_RLC2_RB_AQL_CNTL_BASE_IDX                                                              2
12201 #define mmSDMA3_RLC2_MINOR_PTR_UPDATE                                                                  0x0615
12202 #define mmSDMA3_RLC2_MINOR_PTR_UPDATE_BASE_IDX                                                         2
12203 #define mmSDMA3_RLC2_MIDCMD_DATA0                                                                      0x0620
12204 #define mmSDMA3_RLC2_MIDCMD_DATA0_BASE_IDX                                                             2
12205 #define mmSDMA3_RLC2_MIDCMD_DATA1                                                                      0x0621
12206 #define mmSDMA3_RLC2_MIDCMD_DATA1_BASE_IDX                                                             2
12207 #define mmSDMA3_RLC2_MIDCMD_DATA2                                                                      0x0622
12208 #define mmSDMA3_RLC2_MIDCMD_DATA2_BASE_IDX                                                             2
12209 #define mmSDMA3_RLC2_MIDCMD_DATA3                                                                      0x0623
12210 #define mmSDMA3_RLC2_MIDCMD_DATA3_BASE_IDX                                                             2
12211 #define mmSDMA3_RLC2_MIDCMD_DATA4                                                                      0x0624
12212 #define mmSDMA3_RLC2_MIDCMD_DATA4_BASE_IDX                                                             2
12213 #define mmSDMA3_RLC2_MIDCMD_DATA5                                                                      0x0625
12214 #define mmSDMA3_RLC2_MIDCMD_DATA5_BASE_IDX                                                             2
12215 #define mmSDMA3_RLC2_MIDCMD_DATA6                                                                      0x0626
12216 #define mmSDMA3_RLC2_MIDCMD_DATA6_BASE_IDX                                                             2
12217 #define mmSDMA3_RLC2_MIDCMD_DATA7                                                                      0x0627
12218 #define mmSDMA3_RLC2_MIDCMD_DATA7_BASE_IDX                                                             2
12219 #define mmSDMA3_RLC2_MIDCMD_DATA8                                                                      0x0628
12220 #define mmSDMA3_RLC2_MIDCMD_DATA8_BASE_IDX                                                             2
12221 #define mmSDMA3_RLC2_MIDCMD_DATA9                                                                      0x0629
12222 #define mmSDMA3_RLC2_MIDCMD_DATA9_BASE_IDX                                                             2
12223 #define mmSDMA3_RLC2_MIDCMD_DATA10                                                                     0x062a
12224 #define mmSDMA3_RLC2_MIDCMD_DATA10_BASE_IDX                                                            2
12225 #define mmSDMA3_RLC2_MIDCMD_CNTL                                                                       0x062b
12226 #define mmSDMA3_RLC2_MIDCMD_CNTL_BASE_IDX                                                              2
12227 #define mmSDMA3_RLC3_RB_CNTL                                                                           0x0638
12228 #define mmSDMA3_RLC3_RB_CNTL_BASE_IDX                                                                  2
12229 #define mmSDMA3_RLC3_RB_BASE                                                                           0x0639
12230 #define mmSDMA3_RLC3_RB_BASE_BASE_IDX                                                                  2
12231 #define mmSDMA3_RLC3_RB_BASE_HI                                                                        0x063a
12232 #define mmSDMA3_RLC3_RB_BASE_HI_BASE_IDX                                                               2
12233 #define mmSDMA3_RLC3_RB_RPTR                                                                           0x063b
12234 #define mmSDMA3_RLC3_RB_RPTR_BASE_IDX                                                                  2
12235 #define mmSDMA3_RLC3_RB_RPTR_HI                                                                        0x063c
12236 #define mmSDMA3_RLC3_RB_RPTR_HI_BASE_IDX                                                               2
12237 #define mmSDMA3_RLC3_RB_WPTR                                                                           0x063d
12238 #define mmSDMA3_RLC3_RB_WPTR_BASE_IDX                                                                  2
12239 #define mmSDMA3_RLC3_RB_WPTR_HI                                                                        0x063e
12240 #define mmSDMA3_RLC3_RB_WPTR_HI_BASE_IDX                                                               2
12241 #define mmSDMA3_RLC3_RB_WPTR_POLL_CNTL                                                                 0x063f
12242 #define mmSDMA3_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX                                                        2
12243 #define mmSDMA3_RLC3_RB_RPTR_ADDR_HI                                                                   0x0640
12244 #define mmSDMA3_RLC3_RB_RPTR_ADDR_HI_BASE_IDX                                                          2
12245 #define mmSDMA3_RLC3_RB_RPTR_ADDR_LO                                                                   0x0641
12246 #define mmSDMA3_RLC3_RB_RPTR_ADDR_LO_BASE_IDX                                                          2
12247 #define mmSDMA3_RLC3_IB_CNTL                                                                           0x0642
12248 #define mmSDMA3_RLC3_IB_CNTL_BASE_IDX                                                                  2
12249 #define mmSDMA3_RLC3_IB_RPTR                                                                           0x0643
12250 #define mmSDMA3_RLC3_IB_RPTR_BASE_IDX                                                                  2
12251 #define mmSDMA3_RLC3_IB_OFFSET                                                                         0x0644
12252 #define mmSDMA3_RLC3_IB_OFFSET_BASE_IDX                                                                2
12253 #define mmSDMA3_RLC3_IB_BASE_LO                                                                        0x0645
12254 #define mmSDMA3_RLC3_IB_BASE_LO_BASE_IDX                                                               2
12255 #define mmSDMA3_RLC3_IB_BASE_HI                                                                        0x0646
12256 #define mmSDMA3_RLC3_IB_BASE_HI_BASE_IDX                                                               2
12257 #define mmSDMA3_RLC3_IB_SIZE                                                                           0x0647
12258 #define mmSDMA3_RLC3_IB_SIZE_BASE_IDX                                                                  2
12259 #define mmSDMA3_RLC3_SKIP_CNTL                                                                         0x0648
12260 #define mmSDMA3_RLC3_SKIP_CNTL_BASE_IDX                                                                2
12261 #define mmSDMA3_RLC3_CONTEXT_STATUS                                                                    0x0649
12262 #define mmSDMA3_RLC3_CONTEXT_STATUS_BASE_IDX                                                           2
12263 #define mmSDMA3_RLC3_DOORBELL                                                                          0x064a
12264 #define mmSDMA3_RLC3_DOORBELL_BASE_IDX                                                                 2
12265 #define mmSDMA3_RLC3_STATUS                                                                            0x0660
12266 #define mmSDMA3_RLC3_STATUS_BASE_IDX                                                                   2
12267 #define mmSDMA3_RLC3_DOORBELL_LOG                                                                      0x0661
12268 #define mmSDMA3_RLC3_DOORBELL_LOG_BASE_IDX                                                             2
12269 #define mmSDMA3_RLC3_WATERMARK                                                                         0x0662
12270 #define mmSDMA3_RLC3_WATERMARK_BASE_IDX                                                                2
12271 #define mmSDMA3_RLC3_DOORBELL_OFFSET                                                                   0x0663
12272 #define mmSDMA3_RLC3_DOORBELL_OFFSET_BASE_IDX                                                          2
12273 #define mmSDMA3_RLC3_CSA_ADDR_LO                                                                       0x0664
12274 #define mmSDMA3_RLC3_CSA_ADDR_LO_BASE_IDX                                                              2
12275 #define mmSDMA3_RLC3_CSA_ADDR_HI                                                                       0x0665
12276 #define mmSDMA3_RLC3_CSA_ADDR_HI_BASE_IDX                                                              2
12277 #define mmSDMA3_RLC3_IB_SUB_REMAIN                                                                     0x0667
12278 #define mmSDMA3_RLC3_IB_SUB_REMAIN_BASE_IDX                                                            2
12279 #define mmSDMA3_RLC3_PREEMPT                                                                           0x0668
12280 #define mmSDMA3_RLC3_PREEMPT_BASE_IDX                                                                  2
12281 #define mmSDMA3_RLC3_DUMMY_REG                                                                         0x0669
12282 #define mmSDMA3_RLC3_DUMMY_REG_BASE_IDX                                                                2
12283 #define mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI                                                              0x066a
12284 #define mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     2
12285 #define mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO                                                              0x066b
12286 #define mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     2
12287 #define mmSDMA3_RLC3_RB_AQL_CNTL                                                                       0x066c
12288 #define mmSDMA3_RLC3_RB_AQL_CNTL_BASE_IDX                                                              2
12289 #define mmSDMA3_RLC3_MINOR_PTR_UPDATE                                                                  0x066d
12290 #define mmSDMA3_RLC3_MINOR_PTR_UPDATE_BASE_IDX                                                         2
12291 #define mmSDMA3_RLC3_MIDCMD_DATA0                                                                      0x0678
12292 #define mmSDMA3_RLC3_MIDCMD_DATA0_BASE_IDX                                                             2
12293 #define mmSDMA3_RLC3_MIDCMD_DATA1                                                                      0x0679
12294 #define mmSDMA3_RLC3_MIDCMD_DATA1_BASE_IDX                                                             2
12295 #define mmSDMA3_RLC3_MIDCMD_DATA2                                                                      0x067a
12296 #define mmSDMA3_RLC3_MIDCMD_DATA2_BASE_IDX                                                             2
12297 #define mmSDMA3_RLC3_MIDCMD_DATA3                                                                      0x067b
12298 #define mmSDMA3_RLC3_MIDCMD_DATA3_BASE_IDX                                                             2
12299 #define mmSDMA3_RLC3_MIDCMD_DATA4                                                                      0x067c
12300 #define mmSDMA3_RLC3_MIDCMD_DATA4_BASE_IDX                                                             2
12301 #define mmSDMA3_RLC3_MIDCMD_DATA5                                                                      0x067d
12302 #define mmSDMA3_RLC3_MIDCMD_DATA5_BASE_IDX                                                             2
12303 #define mmSDMA3_RLC3_MIDCMD_DATA6                                                                      0x067e
12304 #define mmSDMA3_RLC3_MIDCMD_DATA6_BASE_IDX                                                             2
12305 #define mmSDMA3_RLC3_MIDCMD_DATA7                                                                      0x067f
12306 #define mmSDMA3_RLC3_MIDCMD_DATA7_BASE_IDX                                                             2
12307 #define mmSDMA3_RLC3_MIDCMD_DATA8                                                                      0x0680
12308 #define mmSDMA3_RLC3_MIDCMD_DATA8_BASE_IDX                                                             2
12309 #define mmSDMA3_RLC3_MIDCMD_DATA9                                                                      0x0681
12310 #define mmSDMA3_RLC3_MIDCMD_DATA9_BASE_IDX                                                             2
12311 #define mmSDMA3_RLC3_MIDCMD_DATA10                                                                     0x0682
12312 #define mmSDMA3_RLC3_MIDCMD_DATA10_BASE_IDX                                                            2
12313 #define mmSDMA3_RLC3_MIDCMD_CNTL                                                                       0x0683
12314 #define mmSDMA3_RLC3_MIDCMD_CNTL_BASE_IDX                                                              2
12315 #define mmSDMA3_RLC4_RB_CNTL                                                                           0x0690
12316 #define mmSDMA3_RLC4_RB_CNTL_BASE_IDX                                                                  2
12317 #define mmSDMA3_RLC4_RB_BASE                                                                           0x0691
12318 #define mmSDMA3_RLC4_RB_BASE_BASE_IDX                                                                  2
12319 #define mmSDMA3_RLC4_RB_BASE_HI                                                                        0x0692
12320 #define mmSDMA3_RLC4_RB_BASE_HI_BASE_IDX                                                               2
12321 #define mmSDMA3_RLC4_RB_RPTR                                                                           0x0693
12322 #define mmSDMA3_RLC4_RB_RPTR_BASE_IDX                                                                  2
12323 #define mmSDMA3_RLC4_RB_RPTR_HI                                                                        0x0694
12324 #define mmSDMA3_RLC4_RB_RPTR_HI_BASE_IDX                                                               2
12325 #define mmSDMA3_RLC4_RB_WPTR                                                                           0x0695
12326 #define mmSDMA3_RLC4_RB_WPTR_BASE_IDX                                                                  2
12327 #define mmSDMA3_RLC4_RB_WPTR_HI                                                                        0x0696
12328 #define mmSDMA3_RLC4_RB_WPTR_HI_BASE_IDX                                                               2
12329 #define mmSDMA3_RLC4_RB_WPTR_POLL_CNTL                                                                 0x0697
12330 #define mmSDMA3_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX                                                        2
12331 #define mmSDMA3_RLC4_RB_RPTR_ADDR_HI                                                                   0x0698
12332 #define mmSDMA3_RLC4_RB_RPTR_ADDR_HI_BASE_IDX                                                          2
12333 #define mmSDMA3_RLC4_RB_RPTR_ADDR_LO                                                                   0x0699
12334 #define mmSDMA3_RLC4_RB_RPTR_ADDR_LO_BASE_IDX                                                          2
12335 #define mmSDMA3_RLC4_IB_CNTL                                                                           0x069a
12336 #define mmSDMA3_RLC4_IB_CNTL_BASE_IDX                                                                  2
12337 #define mmSDMA3_RLC4_IB_RPTR                                                                           0x069b
12338 #define mmSDMA3_RLC4_IB_RPTR_BASE_IDX                                                                  2
12339 #define mmSDMA3_RLC4_IB_OFFSET                                                                         0x069c
12340 #define mmSDMA3_RLC4_IB_OFFSET_BASE_IDX                                                                2
12341 #define mmSDMA3_RLC4_IB_BASE_LO                                                                        0x069d
12342 #define mmSDMA3_RLC4_IB_BASE_LO_BASE_IDX                                                               2
12343 #define mmSDMA3_RLC4_IB_BASE_HI                                                                        0x069e
12344 #define mmSDMA3_RLC4_IB_BASE_HI_BASE_IDX                                                               2
12345 #define mmSDMA3_RLC4_IB_SIZE                                                                           0x069f
12346 #define mmSDMA3_RLC4_IB_SIZE_BASE_IDX                                                                  2
12347 #define mmSDMA3_RLC4_SKIP_CNTL                                                                         0x06a0
12348 #define mmSDMA3_RLC4_SKIP_CNTL_BASE_IDX                                                                2
12349 #define mmSDMA3_RLC4_CONTEXT_STATUS                                                                    0x06a1
12350 #define mmSDMA3_RLC4_CONTEXT_STATUS_BASE_IDX                                                           2
12351 #define mmSDMA3_RLC4_DOORBELL                                                                          0x06a2
12352 #define mmSDMA3_RLC4_DOORBELL_BASE_IDX                                                                 2
12353 #define mmSDMA3_RLC4_STATUS                                                                            0x06b8
12354 #define mmSDMA3_RLC4_STATUS_BASE_IDX                                                                   2
12355 #define mmSDMA3_RLC4_DOORBELL_LOG                                                                      0x06b9
12356 #define mmSDMA3_RLC4_DOORBELL_LOG_BASE_IDX                                                             2
12357 #define mmSDMA3_RLC4_WATERMARK                                                                         0x06ba
12358 #define mmSDMA3_RLC4_WATERMARK_BASE_IDX                                                                2
12359 #define mmSDMA3_RLC4_DOORBELL_OFFSET                                                                   0x06bb
12360 #define mmSDMA3_RLC4_DOORBELL_OFFSET_BASE_IDX                                                          2
12361 #define mmSDMA3_RLC4_CSA_ADDR_LO                                                                       0x06bc
12362 #define mmSDMA3_RLC4_CSA_ADDR_LO_BASE_IDX                                                              2
12363 #define mmSDMA3_RLC4_CSA_ADDR_HI                                                                       0x06bd
12364 #define mmSDMA3_RLC4_CSA_ADDR_HI_BASE_IDX                                                              2
12365 #define mmSDMA3_RLC4_IB_SUB_REMAIN                                                                     0x06bf
12366 #define mmSDMA3_RLC4_IB_SUB_REMAIN_BASE_IDX                                                            2
12367 #define mmSDMA3_RLC4_PREEMPT                                                                           0x06c0
12368 #define mmSDMA3_RLC4_PREEMPT_BASE_IDX                                                                  2
12369 #define mmSDMA3_RLC4_DUMMY_REG                                                                         0x06c1
12370 #define mmSDMA3_RLC4_DUMMY_REG_BASE_IDX                                                                2
12371 #define mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI                                                              0x06c2
12372 #define mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     2
12373 #define mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO                                                              0x06c3
12374 #define mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     2
12375 #define mmSDMA3_RLC4_RB_AQL_CNTL                                                                       0x06c4
12376 #define mmSDMA3_RLC4_RB_AQL_CNTL_BASE_IDX                                                              2
12377 #define mmSDMA3_RLC4_MINOR_PTR_UPDATE                                                                  0x06c5
12378 #define mmSDMA3_RLC4_MINOR_PTR_UPDATE_BASE_IDX                                                         2
12379 #define mmSDMA3_RLC4_MIDCMD_DATA0                                                                      0x06d0
12380 #define mmSDMA3_RLC4_MIDCMD_DATA0_BASE_IDX                                                             2
12381 #define mmSDMA3_RLC4_MIDCMD_DATA1                                                                      0x06d1
12382 #define mmSDMA3_RLC4_MIDCMD_DATA1_BASE_IDX                                                             2
12383 #define mmSDMA3_RLC4_MIDCMD_DATA2                                                                      0x06d2
12384 #define mmSDMA3_RLC4_MIDCMD_DATA2_BASE_IDX                                                             2
12385 #define mmSDMA3_RLC4_MIDCMD_DATA3                                                                      0x06d3
12386 #define mmSDMA3_RLC4_MIDCMD_DATA3_BASE_IDX                                                             2
12387 #define mmSDMA3_RLC4_MIDCMD_DATA4                                                                      0x06d4
12388 #define mmSDMA3_RLC4_MIDCMD_DATA4_BASE_IDX                                                             2
12389 #define mmSDMA3_RLC4_MIDCMD_DATA5                                                                      0x06d5
12390 #define mmSDMA3_RLC4_MIDCMD_DATA5_BASE_IDX                                                             2
12391 #define mmSDMA3_RLC4_MIDCMD_DATA6                                                                      0x06d6
12392 #define mmSDMA3_RLC4_MIDCMD_DATA6_BASE_IDX                                                             2
12393 #define mmSDMA3_RLC4_MIDCMD_DATA7                                                                      0x06d7
12394 #define mmSDMA3_RLC4_MIDCMD_DATA7_BASE_IDX                                                             2
12395 #define mmSDMA3_RLC4_MIDCMD_DATA8                                                                      0x06d8
12396 #define mmSDMA3_RLC4_MIDCMD_DATA8_BASE_IDX                                                             2
12397 #define mmSDMA3_RLC4_MIDCMD_DATA9                                                                      0x06d9
12398 #define mmSDMA3_RLC4_MIDCMD_DATA9_BASE_IDX                                                             2
12399 #define mmSDMA3_RLC4_MIDCMD_DATA10                                                                     0x06da
12400 #define mmSDMA3_RLC4_MIDCMD_DATA10_BASE_IDX                                                            2
12401 #define mmSDMA3_RLC4_MIDCMD_CNTL                                                                       0x06db
12402 #define mmSDMA3_RLC4_MIDCMD_CNTL_BASE_IDX                                                              2
12403 #define mmSDMA3_RLC5_RB_CNTL                                                                           0x06e8
12404 #define mmSDMA3_RLC5_RB_CNTL_BASE_IDX                                                                  2
12405 #define mmSDMA3_RLC5_RB_BASE                                                                           0x06e9
12406 #define mmSDMA3_RLC5_RB_BASE_BASE_IDX                                                                  2
12407 #define mmSDMA3_RLC5_RB_BASE_HI                                                                        0x06ea
12408 #define mmSDMA3_RLC5_RB_BASE_HI_BASE_IDX                                                               2
12409 #define mmSDMA3_RLC5_RB_RPTR                                                                           0x06eb
12410 #define mmSDMA3_RLC5_RB_RPTR_BASE_IDX                                                                  2
12411 #define mmSDMA3_RLC5_RB_RPTR_HI                                                                        0x06ec
12412 #define mmSDMA3_RLC5_RB_RPTR_HI_BASE_IDX                                                               2
12413 #define mmSDMA3_RLC5_RB_WPTR                                                                           0x06ed
12414 #define mmSDMA3_RLC5_RB_WPTR_BASE_IDX                                                                  2
12415 #define mmSDMA3_RLC5_RB_WPTR_HI                                                                        0x06ee
12416 #define mmSDMA3_RLC5_RB_WPTR_HI_BASE_IDX                                                               2
12417 #define mmSDMA3_RLC5_RB_WPTR_POLL_CNTL                                                                 0x06ef
12418 #define mmSDMA3_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX                                                        2
12419 #define mmSDMA3_RLC5_RB_RPTR_ADDR_HI                                                                   0x06f0
12420 #define mmSDMA3_RLC5_RB_RPTR_ADDR_HI_BASE_IDX                                                          2
12421 #define mmSDMA3_RLC5_RB_RPTR_ADDR_LO                                                                   0x06f1
12422 #define mmSDMA3_RLC5_RB_RPTR_ADDR_LO_BASE_IDX                                                          2
12423 #define mmSDMA3_RLC5_IB_CNTL                                                                           0x06f2
12424 #define mmSDMA3_RLC5_IB_CNTL_BASE_IDX                                                                  2
12425 #define mmSDMA3_RLC5_IB_RPTR                                                                           0x06f3
12426 #define mmSDMA3_RLC5_IB_RPTR_BASE_IDX                                                                  2
12427 #define mmSDMA3_RLC5_IB_OFFSET                                                                         0x06f4
12428 #define mmSDMA3_RLC5_IB_OFFSET_BASE_IDX                                                                2
12429 #define mmSDMA3_RLC5_IB_BASE_LO                                                                        0x06f5
12430 #define mmSDMA3_RLC5_IB_BASE_LO_BASE_IDX                                                               2
12431 #define mmSDMA3_RLC5_IB_BASE_HI                                                                        0x06f6
12432 #define mmSDMA3_RLC5_IB_BASE_HI_BASE_IDX                                                               2
12433 #define mmSDMA3_RLC5_IB_SIZE                                                                           0x06f7
12434 #define mmSDMA3_RLC5_IB_SIZE_BASE_IDX                                                                  2
12435 #define mmSDMA3_RLC5_SKIP_CNTL                                                                         0x06f8
12436 #define mmSDMA3_RLC5_SKIP_CNTL_BASE_IDX                                                                2
12437 #define mmSDMA3_RLC5_CONTEXT_STATUS                                                                    0x06f9
12438 #define mmSDMA3_RLC5_CONTEXT_STATUS_BASE_IDX                                                           2
12439 #define mmSDMA3_RLC5_DOORBELL                                                                          0x06fa
12440 #define mmSDMA3_RLC5_DOORBELL_BASE_IDX                                                                 2
12441 #define mmSDMA3_RLC5_STATUS                                                                            0x0710
12442 #define mmSDMA3_RLC5_STATUS_BASE_IDX                                                                   2
12443 #define mmSDMA3_RLC5_DOORBELL_LOG                                                                      0x0711
12444 #define mmSDMA3_RLC5_DOORBELL_LOG_BASE_IDX                                                             2
12445 #define mmSDMA3_RLC5_WATERMARK                                                                         0x0712
12446 #define mmSDMA3_RLC5_WATERMARK_BASE_IDX                                                                2
12447 #define mmSDMA3_RLC5_DOORBELL_OFFSET                                                                   0x0713
12448 #define mmSDMA3_RLC5_DOORBELL_OFFSET_BASE_IDX                                                          2
12449 #define mmSDMA3_RLC5_CSA_ADDR_LO                                                                       0x0714
12450 #define mmSDMA3_RLC5_CSA_ADDR_LO_BASE_IDX                                                              2
12451 #define mmSDMA3_RLC5_CSA_ADDR_HI                                                                       0x0715
12452 #define mmSDMA3_RLC5_CSA_ADDR_HI_BASE_IDX                                                              2
12453 #define mmSDMA3_RLC5_IB_SUB_REMAIN                                                                     0x0717
12454 #define mmSDMA3_RLC5_IB_SUB_REMAIN_BASE_IDX                                                            2
12455 #define mmSDMA3_RLC5_PREEMPT                                                                           0x0718
12456 #define mmSDMA3_RLC5_PREEMPT_BASE_IDX                                                                  2
12457 #define mmSDMA3_RLC5_DUMMY_REG                                                                         0x0719
12458 #define mmSDMA3_RLC5_DUMMY_REG_BASE_IDX                                                                2
12459 #define mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI                                                              0x071a
12460 #define mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     2
12461 #define mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO                                                              0x071b
12462 #define mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     2
12463 #define mmSDMA3_RLC5_RB_AQL_CNTL                                                                       0x071c
12464 #define mmSDMA3_RLC5_RB_AQL_CNTL_BASE_IDX                                                              2
12465 #define mmSDMA3_RLC5_MINOR_PTR_UPDATE                                                                  0x071d
12466 #define mmSDMA3_RLC5_MINOR_PTR_UPDATE_BASE_IDX                                                         2
12467 #define mmSDMA3_RLC5_MIDCMD_DATA0                                                                      0x0728
12468 #define mmSDMA3_RLC5_MIDCMD_DATA0_BASE_IDX                                                             2
12469 #define mmSDMA3_RLC5_MIDCMD_DATA1                                                                      0x0729
12470 #define mmSDMA3_RLC5_MIDCMD_DATA1_BASE_IDX                                                             2
12471 #define mmSDMA3_RLC5_MIDCMD_DATA2                                                                      0x072a
12472 #define mmSDMA3_RLC5_MIDCMD_DATA2_BASE_IDX                                                             2
12473 #define mmSDMA3_RLC5_MIDCMD_DATA3                                                                      0x072b
12474 #define mmSDMA3_RLC5_MIDCMD_DATA3_BASE_IDX                                                             2
12475 #define mmSDMA3_RLC5_MIDCMD_DATA4                                                                      0x072c
12476 #define mmSDMA3_RLC5_MIDCMD_DATA4_BASE_IDX                                                             2
12477 #define mmSDMA3_RLC5_MIDCMD_DATA5                                                                      0x072d
12478 #define mmSDMA3_RLC5_MIDCMD_DATA5_BASE_IDX                                                             2
12479 #define mmSDMA3_RLC5_MIDCMD_DATA6                                                                      0x072e
12480 #define mmSDMA3_RLC5_MIDCMD_DATA6_BASE_IDX                                                             2
12481 #define mmSDMA3_RLC5_MIDCMD_DATA7                                                                      0x072f
12482 #define mmSDMA3_RLC5_MIDCMD_DATA7_BASE_IDX                                                             2
12483 #define mmSDMA3_RLC5_MIDCMD_DATA8                                                                      0x0730
12484 #define mmSDMA3_RLC5_MIDCMD_DATA8_BASE_IDX                                                             2
12485 #define mmSDMA3_RLC5_MIDCMD_DATA9                                                                      0x0731
12486 #define mmSDMA3_RLC5_MIDCMD_DATA9_BASE_IDX                                                             2
12487 #define mmSDMA3_RLC5_MIDCMD_DATA10                                                                     0x0732
12488 #define mmSDMA3_RLC5_MIDCMD_DATA10_BASE_IDX                                                            2
12489 #define mmSDMA3_RLC5_MIDCMD_CNTL                                                                       0x0733
12490 #define mmSDMA3_RLC5_MIDCMD_CNTL_BASE_IDX                                                              2
12491 #define mmSDMA3_RLC6_RB_CNTL                                                                           0x0740
12492 #define mmSDMA3_RLC6_RB_CNTL_BASE_IDX                                                                  2
12493 #define mmSDMA3_RLC6_RB_BASE                                                                           0x0741
12494 #define mmSDMA3_RLC6_RB_BASE_BASE_IDX                                                                  2
12495 #define mmSDMA3_RLC6_RB_BASE_HI                                                                        0x0742
12496 #define mmSDMA3_RLC6_RB_BASE_HI_BASE_IDX                                                               2
12497 #define mmSDMA3_RLC6_RB_RPTR                                                                           0x0743
12498 #define mmSDMA3_RLC6_RB_RPTR_BASE_IDX                                                                  2
12499 #define mmSDMA3_RLC6_RB_RPTR_HI                                                                        0x0744
12500 #define mmSDMA3_RLC6_RB_RPTR_HI_BASE_IDX                                                               2
12501 #define mmSDMA3_RLC6_RB_WPTR                                                                           0x0745
12502 #define mmSDMA3_RLC6_RB_WPTR_BASE_IDX                                                                  2
12503 #define mmSDMA3_RLC6_RB_WPTR_HI                                                                        0x0746
12504 #define mmSDMA3_RLC6_RB_WPTR_HI_BASE_IDX                                                               2
12505 #define mmSDMA3_RLC6_RB_WPTR_POLL_CNTL                                                                 0x0747
12506 #define mmSDMA3_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX                                                        2
12507 #define mmSDMA3_RLC6_RB_RPTR_ADDR_HI                                                                   0x0748
12508 #define mmSDMA3_RLC6_RB_RPTR_ADDR_HI_BASE_IDX                                                          2
12509 #define mmSDMA3_RLC6_RB_RPTR_ADDR_LO                                                                   0x0749
12510 #define mmSDMA3_RLC6_RB_RPTR_ADDR_LO_BASE_IDX                                                          2
12511 #define mmSDMA3_RLC6_IB_CNTL                                                                           0x074a
12512 #define mmSDMA3_RLC6_IB_CNTL_BASE_IDX                                                                  2
12513 #define mmSDMA3_RLC6_IB_RPTR                                                                           0x074b
12514 #define mmSDMA3_RLC6_IB_RPTR_BASE_IDX                                                                  2
12515 #define mmSDMA3_RLC6_IB_OFFSET                                                                         0x074c
12516 #define mmSDMA3_RLC6_IB_OFFSET_BASE_IDX                                                                2
12517 #define mmSDMA3_RLC6_IB_BASE_LO                                                                        0x074d
12518 #define mmSDMA3_RLC6_IB_BASE_LO_BASE_IDX                                                               2
12519 #define mmSDMA3_RLC6_IB_BASE_HI                                                                        0x074e
12520 #define mmSDMA3_RLC6_IB_BASE_HI_BASE_IDX                                                               2
12521 #define mmSDMA3_RLC6_IB_SIZE                                                                           0x074f
12522 #define mmSDMA3_RLC6_IB_SIZE_BASE_IDX                                                                  2
12523 #define mmSDMA3_RLC6_SKIP_CNTL                                                                         0x0750
12524 #define mmSDMA3_RLC6_SKIP_CNTL_BASE_IDX                                                                2
12525 #define mmSDMA3_RLC6_CONTEXT_STATUS                                                                    0x0751
12526 #define mmSDMA3_RLC6_CONTEXT_STATUS_BASE_IDX                                                           2
12527 #define mmSDMA3_RLC6_DOORBELL                                                                          0x0752
12528 #define mmSDMA3_RLC6_DOORBELL_BASE_IDX                                                                 2
12529 #define mmSDMA3_RLC6_STATUS                                                                            0x0768
12530 #define mmSDMA3_RLC6_STATUS_BASE_IDX                                                                   2
12531 #define mmSDMA3_RLC6_DOORBELL_LOG                                                                      0x0769
12532 #define mmSDMA3_RLC6_DOORBELL_LOG_BASE_IDX                                                             2
12533 #define mmSDMA3_RLC6_WATERMARK                                                                         0x076a
12534 #define mmSDMA3_RLC6_WATERMARK_BASE_IDX                                                                2
12535 #define mmSDMA3_RLC6_DOORBELL_OFFSET                                                                   0x076b
12536 #define mmSDMA3_RLC6_DOORBELL_OFFSET_BASE_IDX                                                          2
12537 #define mmSDMA3_RLC6_CSA_ADDR_LO                                                                       0x076c
12538 #define mmSDMA3_RLC6_CSA_ADDR_LO_BASE_IDX                                                              2
12539 #define mmSDMA3_RLC6_CSA_ADDR_HI                                                                       0x076d
12540 #define mmSDMA3_RLC6_CSA_ADDR_HI_BASE_IDX                                                              2
12541 #define mmSDMA3_RLC6_IB_SUB_REMAIN                                                                     0x076f
12542 #define mmSDMA3_RLC6_IB_SUB_REMAIN_BASE_IDX                                                            2
12543 #define mmSDMA3_RLC6_PREEMPT                                                                           0x0770
12544 #define mmSDMA3_RLC6_PREEMPT_BASE_IDX                                                                  2
12545 #define mmSDMA3_RLC6_DUMMY_REG                                                                         0x0771
12546 #define mmSDMA3_RLC6_DUMMY_REG_BASE_IDX                                                                2
12547 #define mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI                                                              0x0772
12548 #define mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     2
12549 #define mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO                                                              0x0773
12550 #define mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     2
12551 #define mmSDMA3_RLC6_RB_AQL_CNTL                                                                       0x0774
12552 #define mmSDMA3_RLC6_RB_AQL_CNTL_BASE_IDX                                                              2
12553 #define mmSDMA3_RLC6_MINOR_PTR_UPDATE                                                                  0x0775
12554 #define mmSDMA3_RLC6_MINOR_PTR_UPDATE_BASE_IDX                                                         2
12555 #define mmSDMA3_RLC6_MIDCMD_DATA0                                                                      0x0780
12556 #define mmSDMA3_RLC6_MIDCMD_DATA0_BASE_IDX                                                             2
12557 #define mmSDMA3_RLC6_MIDCMD_DATA1                                                                      0x0781
12558 #define mmSDMA3_RLC6_MIDCMD_DATA1_BASE_IDX                                                             2
12559 #define mmSDMA3_RLC6_MIDCMD_DATA2                                                                      0x0782
12560 #define mmSDMA3_RLC6_MIDCMD_DATA2_BASE_IDX                                                             2
12561 #define mmSDMA3_RLC6_MIDCMD_DATA3                                                                      0x0783
12562 #define mmSDMA3_RLC6_MIDCMD_DATA3_BASE_IDX                                                             2
12563 #define mmSDMA3_RLC6_MIDCMD_DATA4                                                                      0x0784
12564 #define mmSDMA3_RLC6_MIDCMD_DATA4_BASE_IDX                                                             2
12565 #define mmSDMA3_RLC6_MIDCMD_DATA5                                                                      0x0785
12566 #define mmSDMA3_RLC6_MIDCMD_DATA5_BASE_IDX                                                             2
12567 #define mmSDMA3_RLC6_MIDCMD_DATA6                                                                      0x0786
12568 #define mmSDMA3_RLC6_MIDCMD_DATA6_BASE_IDX                                                             2
12569 #define mmSDMA3_RLC6_MIDCMD_DATA7                                                                      0x0787
12570 #define mmSDMA3_RLC6_MIDCMD_DATA7_BASE_IDX                                                             2
12571 #define mmSDMA3_RLC6_MIDCMD_DATA8                                                                      0x0788
12572 #define mmSDMA3_RLC6_MIDCMD_DATA8_BASE_IDX                                                             2
12573 #define mmSDMA3_RLC6_MIDCMD_DATA9                                                                      0x0789
12574 #define mmSDMA3_RLC6_MIDCMD_DATA9_BASE_IDX                                                             2
12575 #define mmSDMA3_RLC6_MIDCMD_DATA10                                                                     0x078a
12576 #define mmSDMA3_RLC6_MIDCMD_DATA10_BASE_IDX                                                            2
12577 #define mmSDMA3_RLC6_MIDCMD_CNTL                                                                       0x078b
12578 #define mmSDMA3_RLC6_MIDCMD_CNTL_BASE_IDX                                                              2
12579 #define mmSDMA3_RLC7_RB_CNTL                                                                           0x0798
12580 #define mmSDMA3_RLC7_RB_CNTL_BASE_IDX                                                                  2
12581 #define mmSDMA3_RLC7_RB_BASE                                                                           0x0799
12582 #define mmSDMA3_RLC7_RB_BASE_BASE_IDX                                                                  2
12583 #define mmSDMA3_RLC7_RB_BASE_HI                                                                        0x079a
12584 #define mmSDMA3_RLC7_RB_BASE_HI_BASE_IDX                                                               2
12585 #define mmSDMA3_RLC7_RB_RPTR                                                                           0x079b
12586 #define mmSDMA3_RLC7_RB_RPTR_BASE_IDX                                                                  2
12587 #define mmSDMA3_RLC7_RB_RPTR_HI                                                                        0x079c
12588 #define mmSDMA3_RLC7_RB_RPTR_HI_BASE_IDX                                                               2
12589 #define mmSDMA3_RLC7_RB_WPTR                                                                           0x079d
12590 #define mmSDMA3_RLC7_RB_WPTR_BASE_IDX                                                                  2
12591 #define mmSDMA3_RLC7_RB_WPTR_HI                                                                        0x079e
12592 #define mmSDMA3_RLC7_RB_WPTR_HI_BASE_IDX                                                               2
12593 #define mmSDMA3_RLC7_RB_WPTR_POLL_CNTL                                                                 0x079f
12594 #define mmSDMA3_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX                                                        2
12595 #define mmSDMA3_RLC7_RB_RPTR_ADDR_HI                                                                   0x07a0
12596 #define mmSDMA3_RLC7_RB_RPTR_ADDR_HI_BASE_IDX                                                          2
12597 #define mmSDMA3_RLC7_RB_RPTR_ADDR_LO                                                                   0x07a1
12598 #define mmSDMA3_RLC7_RB_RPTR_ADDR_LO_BASE_IDX                                                          2
12599 #define mmSDMA3_RLC7_IB_CNTL                                                                           0x07a2
12600 #define mmSDMA3_RLC7_IB_CNTL_BASE_IDX                                                                  2
12601 #define mmSDMA3_RLC7_IB_RPTR                                                                           0x07a3
12602 #define mmSDMA3_RLC7_IB_RPTR_BASE_IDX                                                                  2
12603 #define mmSDMA3_RLC7_IB_OFFSET                                                                         0x07a4
12604 #define mmSDMA3_RLC7_IB_OFFSET_BASE_IDX                                                                2
12605 #define mmSDMA3_RLC7_IB_BASE_LO                                                                        0x07a5
12606 #define mmSDMA3_RLC7_IB_BASE_LO_BASE_IDX                                                               2
12607 #define mmSDMA3_RLC7_IB_BASE_HI                                                                        0x07a6
12608 #define mmSDMA3_RLC7_IB_BASE_HI_BASE_IDX                                                               2
12609 #define mmSDMA3_RLC7_IB_SIZE                                                                           0x07a7
12610 #define mmSDMA3_RLC7_IB_SIZE_BASE_IDX                                                                  2
12611 #define mmSDMA3_RLC7_SKIP_CNTL                                                                         0x07a8
12612 #define mmSDMA3_RLC7_SKIP_CNTL_BASE_IDX                                                                2
12613 #define mmSDMA3_RLC7_CONTEXT_STATUS                                                                    0x07a9
12614 #define mmSDMA3_RLC7_CONTEXT_STATUS_BASE_IDX                                                           2
12615 #define mmSDMA3_RLC7_DOORBELL                                                                          0x07aa
12616 #define mmSDMA3_RLC7_DOORBELL_BASE_IDX                                                                 2
12617 #define mmSDMA3_RLC7_STATUS                                                                            0x07c0
12618 #define mmSDMA3_RLC7_STATUS_BASE_IDX                                                                   2
12619 #define mmSDMA3_RLC7_DOORBELL_LOG                                                                      0x07c1
12620 #define mmSDMA3_RLC7_DOORBELL_LOG_BASE_IDX                                                             2
12621 #define mmSDMA3_RLC7_WATERMARK                                                                         0x07c2
12622 #define mmSDMA3_RLC7_WATERMARK_BASE_IDX                                                                2
12623 #define mmSDMA3_RLC7_DOORBELL_OFFSET                                                                   0x07c3
12624 #define mmSDMA3_RLC7_DOORBELL_OFFSET_BASE_IDX                                                          2
12625 #define mmSDMA3_RLC7_CSA_ADDR_LO                                                                       0x07c4
12626 #define mmSDMA3_RLC7_CSA_ADDR_LO_BASE_IDX                                                              2
12627 #define mmSDMA3_RLC7_CSA_ADDR_HI                                                                       0x07c5
12628 #define mmSDMA3_RLC7_CSA_ADDR_HI_BASE_IDX                                                              2
12629 #define mmSDMA3_RLC7_IB_SUB_REMAIN                                                                     0x07c7
12630 #define mmSDMA3_RLC7_IB_SUB_REMAIN_BASE_IDX                                                            2
12631 #define mmSDMA3_RLC7_PREEMPT                                                                           0x07c8
12632 #define mmSDMA3_RLC7_PREEMPT_BASE_IDX                                                                  2
12633 #define mmSDMA3_RLC7_DUMMY_REG                                                                         0x07c9
12634 #define mmSDMA3_RLC7_DUMMY_REG_BASE_IDX                                                                2
12635 #define mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI                                                              0x07ca
12636 #define mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     2
12637 #define mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO                                                              0x07cb
12638 #define mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     2
12639 #define mmSDMA3_RLC7_RB_AQL_CNTL                                                                       0x07cc
12640 #define mmSDMA3_RLC7_RB_AQL_CNTL_BASE_IDX                                                              2
12641 #define mmSDMA3_RLC7_MINOR_PTR_UPDATE                                                                  0x07cd
12642 #define mmSDMA3_RLC7_MINOR_PTR_UPDATE_BASE_IDX                                                         2
12643 #define mmSDMA3_RLC7_MIDCMD_DATA0                                                                      0x07d8
12644 #define mmSDMA3_RLC7_MIDCMD_DATA0_BASE_IDX                                                             2
12645 #define mmSDMA3_RLC7_MIDCMD_DATA1                                                                      0x07d9
12646 #define mmSDMA3_RLC7_MIDCMD_DATA1_BASE_IDX                                                             2
12647 #define mmSDMA3_RLC7_MIDCMD_DATA2                                                                      0x07da
12648 #define mmSDMA3_RLC7_MIDCMD_DATA2_BASE_IDX                                                             2
12649 #define mmSDMA3_RLC7_MIDCMD_DATA3                                                                      0x07db
12650 #define mmSDMA3_RLC7_MIDCMD_DATA3_BASE_IDX                                                             2
12651 #define mmSDMA3_RLC7_MIDCMD_DATA4                                                                      0x07dc
12652 #define mmSDMA3_RLC7_MIDCMD_DATA4_BASE_IDX                                                             2
12653 #define mmSDMA3_RLC7_MIDCMD_DATA5                                                                      0x07dd
12654 #define mmSDMA3_RLC7_MIDCMD_DATA5_BASE_IDX                                                             2
12655 #define mmSDMA3_RLC7_MIDCMD_DATA6                                                                      0x07de
12656 #define mmSDMA3_RLC7_MIDCMD_DATA6_BASE_IDX                                                             2
12657 #define mmSDMA3_RLC7_MIDCMD_DATA7                                                                      0x07df
12658 #define mmSDMA3_RLC7_MIDCMD_DATA7_BASE_IDX                                                             2
12659 #define mmSDMA3_RLC7_MIDCMD_DATA8                                                                      0x07e0
12660 #define mmSDMA3_RLC7_MIDCMD_DATA8_BASE_IDX                                                             2
12661 #define mmSDMA3_RLC7_MIDCMD_DATA9                                                                      0x07e1
12662 #define mmSDMA3_RLC7_MIDCMD_DATA9_BASE_IDX                                                             2
12663 #define mmSDMA3_RLC7_MIDCMD_DATA10                                                                     0x07e2
12664 #define mmSDMA3_RLC7_MIDCMD_DATA10_BASE_IDX                                                            2
12665 #define mmSDMA3_RLC7_MIDCMD_CNTL                                                                       0x07e3
12666 #define mmSDMA3_RLC7_MIDCMD_CNTL_BASE_IDX                                                              2
12667 
12668 
12669 // addressBlock: gccacind
12670 // base address: 0x0
12671 #define ixPCC_STALL_PATTERN_CTRL                                                                       0x0000
12672 #define ixPWRBRK_STALL_PATTERN_CTRL                                                                    0x0001
12673 #define ixPCC_STALL_PATTERN_1_2                                                                        0x0006
12674 #define ixPCC_STALL_PATTERN_3_4                                                                        0x0007
12675 #define ixPCC_STALL_PATTERN_5_6                                                                        0x0008
12676 #define ixPCC_STALL_PATTERN_7                                                                          0x0009
12677 #define ixPWRBRK_STALL_PATTERN_1_2                                                                     0x000a
12678 #define ixPWRBRK_STALL_PATTERN_3_4                                                                     0x000b
12679 #define ixPWRBRK_STALL_PATTERN_5_6                                                                     0x000c
12680 #define ixPWRBRK_STALL_PATTERN_7                                                                       0x000d
12681 #define ixPCC_PWRBRK_HYSTERESIS_CTRL                                                                   0x000e
12682 #define ixEDC_STRETCH_PERF_COUNTER                                                                     0x000f
12683 #define ixEDC_UNSTRETCH_PERF_COUNTER                                                                   0x0010
12684 #define ixEDC_STRETCH_NUM_PERF_COUNTER                                                                 0x0011
12685 #define ixGC_CAC_ID                                                                                    0x0020
12686 #define ixGC_CAC_CNTL                                                                                  0x0021
12687 #define ixGC_CAC_OVR_SEL                                                                               0x0022
12688 #define ixGC_CAC_OVR_VAL                                                                               0x0023
12689 #define ixGC_CAC_WEIGHT_BCI_0                                                                          0x0024
12690 #define ixGC_CAC_WEIGHT_CB_0                                                                           0x0025
12691 #define ixGC_CAC_WEIGHT_CB_1                                                                           0x0026
12692 #define ixGC_CAC_WEIGHT_CB_2                                                                           0x0027
12693 #define ixGC_CAC_WEIGHT_CB_3                                                                           0x0028
12694 #define ixGC_CAC_WEIGHT_CB_4                                                                           0x0029
12695 #define ixGC_CAC_WEIGHT_CP_0                                                                           0x002a
12696 #define ixGC_CAC_WEIGHT_CP_1                                                                           0x002b
12697 #define ixGC_CAC_WEIGHT_DB_0                                                                           0x002c
12698 #define ixGC_CAC_WEIGHT_DB_1                                                                           0x002d
12699 #define ixGC_CAC_WEIGHT_DB_2                                                                           0x002e
12700 #define ixGC_CAC_WEIGHT_DB_3                                                                           0x002f
12701 #define ixGC_CAC_WEIGHT_DB_4                                                                           0x0030
12702 #define ixGC_CAC_WEIGHT_GDS_0                                                                          0x0031
12703 #define ixGC_CAC_WEIGHT_GDS_1                                                                          0x0032
12704 #define ixGC_CAC_WEIGHT_GDS_2                                                                          0x0033
12705 #define ixGC_CAC_WEIGHT_LDS_0                                                                          0x0034
12706 #define ixGC_CAC_WEIGHT_LDS_1                                                                          0x0035
12707 #define ixGC_CAC_WEIGHT_LDS_2                                                                          0x0036
12708 #define ixGC_CAC_WEIGHT_LDS_3                                                                          0x0037
12709 #define ixGC_CAC_WEIGHT_LDS_4                                                                          0x0038
12710 #define ixGC_CAC_WEIGHT_PA_0                                                                           0x0039
12711 #define ixGC_CAC_WEIGHT_PA_1                                                                           0x003a
12712 #define ixGC_CAC_WEIGHT_PA_2                                                                           0x003b
12713 #define ixGC_CAC_WEIGHT_PA_3                                                                           0x003c
12714 #define ixGC_CAC_WEIGHT_PC_0                                                                           0x003d
12715 #define ixGC_CAC_WEIGHT_SC_0                                                                           0x003e
12716 #define ixGC_CAC_WEIGHT_SC_1                                                                           0x003f
12717 #define ixGC_CAC_WEIGHT_SC_2                                                                           0x0040
12718 #define ixGC_CAC_WEIGHT_SC_3                                                                           0x0041
12719 #define ixGC_CAC_WEIGHT_SPI_0                                                                          0x0042
12720 #define ixGC_CAC_WEIGHT_SPI_1                                                                          0x0043
12721 #define ixGC_CAC_WEIGHT_SPI_2                                                                          0x0044
12722 #define ixGC_CAC_WEIGHT_SQ_0                                                                           0x0045
12723 #define ixGC_CAC_WEIGHT_SQ_1                                                                           0x0046
12724 #define ixGC_CAC_WEIGHT_SQ_2                                                                           0x0047
12725 #define ixGC_CAC_WEIGHT_SQ_3                                                                           0x0048
12726 #define ixGC_CAC_WEIGHT_SX_0                                                                           0x0049
12727 #define ixGC_CAC_WEIGHT_SXRB_0                                                                         0x004a
12728 #define ixGC_CAC_WEIGHT_TA_0                                                                           0x004b
12729 #define ixGC_CAC_WEIGHT_TCP_0                                                                          0x004c
12730 #define ixGC_CAC_WEIGHT_TCP_1                                                                          0x004d
12731 #define ixGC_CAC_WEIGHT_TCP_2                                                                          0x004e
12732 #define ixGC_CAC_WEIGHT_TCP_3                                                                          0x004f
12733 #define ixGC_CAC_WEIGHT_TD_0                                                                           0x0050
12734 #define ixGC_CAC_WEIGHT_TD_1                                                                           0x0051
12735 #define ixGC_CAC_WEIGHT_TD_2                                                                           0x0052
12736 #define ixGC_CAC_WEIGHT_TD_3                                                                           0x0053
12737 #define ixGC_CAC_WEIGHT_TD_4                                                                           0x0054
12738 #define ixGC_CAC_WEIGHT_TD_5                                                                           0x0055
12739 #define ixGC_CAC_WEIGHT_RMI_0                                                                          0x0056
12740 #define ixGC_CAC_WEIGHT_RMI_1                                                                          0x0057
12741 #define ixGC_CAC_WEIGHT_EA_0                                                                           0x0058
12742 #define ixGC_CAC_WEIGHT_EA_1                                                                           0x0059
12743 #define ixGC_CAC_WEIGHT_EA_2                                                                           0x005a
12744 #define ixGC_CAC_WEIGHT_UTCL2_ATCL2_0                                                                  0x005b
12745 #define ixGC_CAC_WEIGHT_UTCL2_ATCL2_1                                                                  0x005c
12746 #define ixGC_CAC_WEIGHT_UTCL2_ATCL2_2                                                                  0x005d
12747 #define ixGC_CAC_WEIGHT_UTCL2_ROUTER_0                                                                 0x005e
12748 #define ixGC_CAC_WEIGHT_UTCL2_ROUTER_1                                                                 0x005f
12749 #define ixGC_CAC_WEIGHT_UTCL2_ROUTER_2                                                                 0x0060
12750 #define ixGC_CAC_WEIGHT_UTCL2_ROUTER_3                                                                 0x0061
12751 #define ixGC_CAC_WEIGHT_UTCL2_ROUTER_4                                                                 0x0062
12752 #define ixGC_CAC_WEIGHT_UTCL2_VML2_0                                                                   0x0063
12753 #define ixGC_CAC_WEIGHT_UTCL2_VML2_1                                                                   0x0064
12754 #define ixGC_CAC_WEIGHT_UTCL2_VML2_2                                                                   0x0065
12755 #define ixGC_CAC_WEIGHT_UTCL2_WALKER_0                                                                 0x0066
12756 #define ixGC_CAC_WEIGHT_UTCL2_WALKER_1                                                                 0x0067
12757 #define ixGC_CAC_WEIGHT_UTCL2_WALKER_2                                                                 0x0068
12758 #define ixGC_CAC_WEIGHT_CU_0                                                                           0x0069
12759 #define ixGC_CAC_WEIGHT_UTCL1_0                                                                        0x006a
12760 #define ixGC_CAC_WEIGHT_GE_0                                                                           0x006b
12761 #define ixGC_CAC_WEIGHT_GE_1                                                                           0x006c
12762 #define ixGC_CAC_WEIGHT_GE_2                                                                           0x006d
12763 #define ixGC_CAC_WEIGHT_GE_3                                                                           0x006e
12764 #define ixGC_CAC_WEIGHT_GE_4                                                                           0x006f
12765 #define ixGC_CAC_WEIGHT_GE_5                                                                           0x0070
12766 #define ixGC_CAC_WEIGHT_GE_6                                                                           0x0071
12767 #define ixGC_CAC_WEIGHT_GE_7                                                                           0x0072
12768 #define ixGC_CAC_WEIGHT_GE_8                                                                           0x0073
12769 #define ixGC_CAC_WEIGHT_GE_9                                                                           0x0074
12770 #define ixGC_CAC_WEIGHT_GE_10                                                                          0x0075
12771 #define ixGC_CAC_WEIGHT_PMM_0                                                                          0x0076
12772 #define ixGC_CAC_WEIGHT_GL2C_0                                                                         0x0077
12773 #define ixGC_CAC_WEIGHT_GL2C_1                                                                         0x0078
12774 #define ixGC_CAC_WEIGHT_GL2C_2                                                                         0x0079
12775 #define ixGC_CAC_WEIGHT_GUS_0                                                                          0x007a
12776 #define ixGC_CAC_WEIGHT_GUS_1                                                                          0x007b
12777 #define ixGC_CAC_WEIGHT_PH_0                                                                           0x007c
12778 #define ixGC_CAC_WEIGHT_PH_1                                                                           0x007d
12779 #define ixGC_CAC_WEIGHT_PH_2                                                                           0x007e
12780 #define ixGC_CAC_WEIGHT_PH_3                                                                           0x007f
12781 #define ixGC_CAC_WEIGHT_SDMA_0                                                                         0x0080
12782 #define ixGC_CAC_WEIGHT_SDMA_1                                                                         0x0081
12783 #define ixGC_CAC_WEIGHT_SDMA_2                                                                         0x0082
12784 #define ixGC_CAC_WEIGHT_SDMA_3                                                                         0x0083
12785 #define ixGC_CAC_WEIGHT_SDMA_4                                                                         0x0084
12786 #define ixGC_CAC_WEIGHT_SDMA_5                                                                         0x0085
12787 #define ixGC_CAC_WEIGHT_SP_0                                                                           0x0086
12788 #define ixGC_CAC_WEIGHT_SP_1                                                                           0x0087
12789 #define ixGC_CAC_WEIGHT_GL1C_0                                                                         0x0088
12790 #define ixGC_CAC_WEIGHT_GL1C_1                                                                         0x0089
12791 #define ixGC_CAC_WEIGHT_GL1C_2                                                                         0x008a
12792 #define ixGC_CAC_WEIGHT_CHC_0                                                                          0x008b
12793 #define ixGC_CAC_WEIGHT_CHC_1                                                                          0x008c
12794 #define ixGC_CAC_WEIGHT_SQC_0                                                                          0x008d
12795 #define ixGC_CAC_WEIGHT_SQC_1                                                                          0x008e
12796 #define ixGC_CAC_WEIGHT_RLC_0                                                                          0x008f
12797 #define ixGC_CAC_ACC_LDS0                                                                              0x0100
12798 #define ixGC_CAC_ACC_LDS1                                                                              0x0101
12799 #define ixGC_CAC_ACC_LDS2                                                                              0x0102
12800 #define ixGC_CAC_ACC_LDS3                                                                              0x0103
12801 #define ixGC_CAC_ACC_LDS4                                                                              0x0104
12802 #define ixGC_CAC_ACC_LDS5                                                                              0x0105
12803 #define ixGC_CAC_ACC_LDS6                                                                              0x0106
12804 #define ixGC_CAC_ACC_LDS7                                                                              0x0107
12805 #define ixGC_CAC_ACC_LDS8                                                                              0x0108
12806 #define ixGC_CAC_ACC_BCI0                                                                              0x0109
12807 #define ixGC_CAC_ACC_BCI1                                                                              0x010a
12808 #define ixGC_CAC_ACC_CB0                                                                               0x010b
12809 #define ixGC_CAC_ACC_CB1                                                                               0x010c
12810 #define ixGC_CAC_ACC_CB2                                                                               0x010d
12811 #define ixGC_CAC_ACC_CB3                                                                               0x010e
12812 #define ixGC_CAC_ACC_CB4                                                                               0x010f
12813 #define ixGC_CAC_ACC_CB5                                                                               0x0110
12814 #define ixGC_CAC_ACC_CB6                                                                               0x0111
12815 #define ixGC_CAC_ACC_CB7                                                                               0x0112
12816 #define ixGC_CAC_ACC_CB8                                                                               0x0113
12817 #define ixGC_CAC_ACC_CB9                                                                               0x0114
12818 #define ixGC_CAC_ACC_CP0                                                                               0x0115
12819 #define ixGC_CAC_ACC_CP1                                                                               0x0116
12820 #define ixGC_CAC_ACC_CP2                                                                               0x0117
12821 #define ixGC_CAC_ACC_DB0                                                                               0x0118
12822 #define ixGC_CAC_ACC_DB1                                                                               0x0119
12823 #define ixGC_CAC_ACC_DB2                                                                               0x011a
12824 #define ixGC_CAC_ACC_DB3                                                                               0x011b
12825 #define ixGC_CAC_ACC_DB4                                                                               0x011c
12826 #define ixGC_CAC_ACC_DB5                                                                               0x011d
12827 #define ixGC_CAC_ACC_DB6                                                                               0x011e
12828 #define ixGC_CAC_ACC_DB7                                                                               0x011f
12829 #define ixGC_CAC_ACC_DB8                                                                               0x0120
12830 #define ixGC_CAC_ACC_DB9                                                                               0x0121
12831 #define ixGC_CAC_ACC_GDS0                                                                              0x0122
12832 #define ixGC_CAC_ACC_GDS1                                                                              0x0123
12833 #define ixGC_CAC_ACC_GDS2                                                                              0x0124
12834 #define ixGC_CAC_ACC_GDS3                                                                              0x0125
12835 #define ixGC_CAC_ACC_GDS4                                                                              0x0126
12836 #define ixGC_CAC_ACC_GDS5                                                                              0x0127
12837 #define ixGC_CAC_ACC_GDS6                                                                              0x0128
12838 #define ixGC_CAC_ACC_PA0                                                                               0x0129
12839 #define ixGC_CAC_ACC_PA1                                                                               0x012a
12840 #define ixGC_CAC_ACC_PA2                                                                               0x012b
12841 #define ixGC_CAC_ACC_PA3                                                                               0x012c
12842 #define ixGC_CAC_ACC_PA4                                                                               0x012d
12843 #define ixGC_CAC_ACC_PA5                                                                               0x012e
12844 #define ixGC_CAC_ACC_PA6                                                                               0x012f
12845 #define ixGC_CAC_ACC_PA7                                                                               0x0130
12846 #define ixGC_CAC_ACC_PC0                                                                               0x0131
12847 #define ixGC_CAC_ACC_SC0                                                                               0x0132
12848 #define ixGC_CAC_ACC_SC1                                                                               0x0133
12849 #define ixGC_CAC_ACC_SC2                                                                               0x0134
12850 #define ixGC_CAC_ACC_SC3                                                                               0x0135
12851 #define ixGC_CAC_ACC_SC4                                                                               0x0136
12852 #define ixGC_CAC_ACC_SC5                                                                               0x0137
12853 #define ixGC_CAC_ACC_SC6                                                                               0x0138
12854 #define ixGC_CAC_ACC_SC7                                                                               0x0139
12855 #define ixGC_CAC_ACC_SPI0                                                                              0x013a
12856 #define ixGC_CAC_ACC_SPI1                                                                              0x013b
12857 #define ixGC_CAC_ACC_SPI2                                                                              0x013c
12858 #define ixGC_CAC_ACC_SPI3                                                                              0x013d
12859 #define ixGC_CAC_ACC_SPI4                                                                              0x013e
12860 #define ixGC_CAC_ACC_SPI5                                                                              0x013f
12861 #define ixGC_CAC_ACC_SQ0_LOWER                                                                         0x0140
12862 #define ixGC_CAC_ACC_SQ0_UPPER                                                                         0x0141
12863 #define ixGC_CAC_ACC_SQ1_LOWER                                                                         0x0142
12864 #define ixGC_CAC_ACC_SQ1_UPPER                                                                         0x0143
12865 #define ixGC_CAC_ACC_SQ2_LOWER                                                                         0x0144
12866 #define ixGC_CAC_ACC_SQ2_UPPER                                                                         0x0145
12867 #define ixGC_CAC_ACC_SQ3_LOWER                                                                         0x0146
12868 #define ixGC_CAC_ACC_SQ3_UPPER                                                                         0x0147
12869 #define ixGC_CAC_ACC_SQ4_LOWER                                                                         0x0148
12870 #define ixGC_CAC_ACC_SQ4_UPPER                                                                         0x0149
12871 #define ixGC_CAC_ACC_SQ5_LOWER                                                                         0x014a
12872 #define ixGC_CAC_ACC_SQ5_UPPER                                                                         0x014b
12873 #define ixGC_CAC_ACC_SQ6_LOWER                                                                         0x014c
12874 #define ixGC_CAC_ACC_SQ6_UPPER                                                                         0x014d
12875 #define ixGC_CAC_ACC_SQ7_LOWER                                                                         0x014e
12876 #define ixGC_CAC_ACC_SQ7_UPPER                                                                         0x014f
12877 #define ixGC_CAC_ACC_SQ8_LOWER                                                                         0x0150
12878 #define ixGC_CAC_ACC_SQ8_UPPER                                                                         0x0151
12879 #define ixGC_CAC_ACC_SX0                                                                               0x0152
12880 #define ixGC_CAC_ACC_SXRB0                                                                             0x0153
12881 #define ixGC_CAC_ACC_TA0                                                                               0x0154
12882 #define ixGC_CAC_ACC_TCP0                                                                              0x0155
12883 #define ixGC_CAC_ACC_TCP1                                                                              0x0156
12884 #define ixGC_CAC_ACC_TCP2                                                                              0x0157
12885 #define ixGC_CAC_ACC_TCP3                                                                              0x0158
12886 #define ixGC_CAC_ACC_TCP4                                                                              0x0159
12887 #define ixGC_CAC_ACC_TCP5                                                                              0x015a
12888 #define ixGC_CAC_ACC_TCP6                                                                              0x015b
12889 #define ixGC_CAC_ACC_TCP7                                                                              0x015c
12890 #define ixGC_CAC_ACC_TD0                                                                               0x015d
12891 #define ixGC_CAC_ACC_TD1                                                                               0x015e
12892 #define ixGC_CAC_ACC_TD2                                                                               0x015f
12893 #define ixGC_CAC_ACC_TD3                                                                               0x0160
12894 #define ixGC_CAC_ACC_TD4                                                                               0x0161
12895 #define ixGC_CAC_ACC_TD5                                                                               0x0162
12896 #define ixGC_CAC_ACC_TD6                                                                               0x0163
12897 #define ixGC_CAC_ACC_TD7                                                                               0x0164
12898 #define ixGC_CAC_ACC_TD8                                                                               0x0165
12899 #define ixGC_CAC_ACC_TD9                                                                               0x0166
12900 #define ixGC_CAC_ACC_TD10                                                                              0x0167
12901 #define ixGC_CAC_ACC_RMI0                                                                              0x0168
12902 #define ixGC_CAC_ACC_RMI1                                                                              0x0169
12903 #define ixGC_CAC_ACC_RMI2                                                                              0x016a
12904 #define ixGC_CAC_ACC_RMI3                                                                              0x016b
12905 #define ixGC_CAC_ACC_EA0                                                                               0x016c
12906 #define ixGC_CAC_ACC_EA1                                                                               0x016d
12907 #define ixGC_CAC_ACC_EA2                                                                               0x016e
12908 #define ixGC_CAC_ACC_EA3                                                                               0x016f
12909 #define ixGC_CAC_ACC_EA4                                                                               0x0170
12910 #define ixGC_CAC_ACC_EA5                                                                               0x0171
12911 #define ixGC_CAC_ACC_UTCL2_ATCL20                                                                      0x0172
12912 #define ixGC_CAC_ACC_UTCL2_ATCL21                                                                      0x0173
12913 #define ixGC_CAC_ACC_UTCL2_ATCL22                                                                      0x0174
12914 #define ixGC_CAC_ACC_UTCL2_ATCL23                                                                      0x0175
12915 #define ixGC_CAC_ACC_UTCL2_ATCL24                                                                      0x0176
12916 #define ixGC_CAC_ACC_UTCL2_ROUTER0                                                                     0x0177
12917 #define ixGC_CAC_ACC_UTCL2_ROUTER1                                                                     0x0178
12918 #define ixGC_CAC_ACC_UTCL2_ROUTER2                                                                     0x0179
12919 #define ixGC_CAC_ACC_UTCL2_ROUTER3                                                                     0x017a
12920 #define ixGC_CAC_ACC_UTCL2_ROUTER4                                                                     0x017b
12921 #define ixGC_CAC_ACC_UTCL2_ROUTER5                                                                     0x017c
12922 #define ixGC_CAC_ACC_UTCL2_ROUTER6                                                                     0x017d
12923 #define ixGC_CAC_ACC_UTCL2_ROUTER7                                                                     0x017e
12924 #define ixGC_CAC_ACC_UTCL2_ROUTER8                                                                     0x017f
12925 #define ixGC_CAC_ACC_UTCL2_ROUTER9                                                                     0x0180
12926 #define ixGC_CAC_ACC_UTCL2_VML20                                                                       0x0181
12927 #define ixGC_CAC_ACC_UTCL2_VML21                                                                       0x0182
12928 #define ixGC_CAC_ACC_UTCL2_VML22                                                                       0x0183
12929 #define ixGC_CAC_ACC_UTCL2_VML23                                                                       0x0184
12930 #define ixGC_CAC_ACC_UTCL2_VML24                                                                       0x0185
12931 #define ixGC_CAC_ACC_UTCL2_WALKER0                                                                     0x0186
12932 #define ixGC_CAC_ACC_UTCL2_WALKER1                                                                     0x0187
12933 #define ixGC_CAC_ACC_UTCL2_WALKER2                                                                     0x0188
12934 #define ixGC_CAC_ACC_UTCL2_WALKER3                                                                     0x0189
12935 #define ixGC_CAC_ACC_UTCL2_WALKER4                                                                     0x018a
12936 #define ixGC_CAC_ACC_CU0                                                                               0x018b
12937 #define ixGC_CAC_ACC_UTCL10                                                                            0x018c
12938 #define ixGC_CAC_ACC_CHC0                                                                              0x018d
12939 #define ixGC_CAC_ACC_CHC1                                                                              0x018e
12940 #define ixGC_CAC_ACC_CHC2                                                                              0x018f
12941 #define ixGC_CAC_ACC_GE0                                                                               0x0190
12942 #define ixGC_CAC_ACC_GE1                                                                               0x0191
12943 #define ixGC_CAC_ACC_GE2                                                                               0x0192
12944 #define ixGC_CAC_ACC_GE3                                                                               0x0193
12945 #define ixGC_CAC_ACC_GE4                                                                               0x0194
12946 #define ixGC_CAC_ACC_GE5                                                                               0x0195
12947 #define ixGC_CAC_ACC_GE6                                                                               0x0196
12948 #define ixGC_CAC_ACC_GE7                                                                               0x0197
12949 #define ixGC_CAC_ACC_GE8                                                                               0x0198
12950 #define ixGC_CAC_ACC_GE9                                                                               0x0199
12951 #define ixGC_CAC_ACC_GE10                                                                              0x019a
12952 #define ixGC_CAC_ACC_GE11                                                                              0x019b
12953 #define ixGC_CAC_ACC_GE12                                                                              0x019c
12954 #define ixGC_CAC_ACC_GE13                                                                              0x019d
12955 #define ixGC_CAC_ACC_GE14                                                                              0x019e
12956 #define ixGC_CAC_ACC_GE15                                                                              0x019f
12957 #define ixGC_CAC_ACC_GE16                                                                              0x01a0
12958 #define ixGC_CAC_ACC_GE17                                                                              0x01a1
12959 #define ixGC_CAC_ACC_GE18                                                                              0x01a2
12960 #define ixGC_CAC_ACC_GE19                                                                              0x01a3
12961 #define ixGC_CAC_ACC_GE20                                                                              0x01a4
12962 #define ixGC_CAC_ACC_PMM0                                                                              0x01a5
12963 #define ixGC_CAC_ACC_GL2C0                                                                             0x01a6
12964 #define ixGC_CAC_ACC_GL2C1                                                                             0x01a7
12965 #define ixGC_CAC_ACC_GL2C2                                                                             0x01a8
12966 #define ixGC_CAC_ACC_GL2C3                                                                             0x01a9
12967 #define ixGC_CAC_ACC_GL2C4                                                                             0x01aa
12968 #define ixGC_CAC_ACC_GUS0                                                                              0x01ab
12969 #define ixGC_CAC_ACC_GUS1                                                                              0x01ac
12970 #define ixGC_CAC_ACC_GUS2                                                                              0x01ad
12971 #define ixGC_CAC_ACC_PH0                                                                               0x01ae
12972 #define ixGC_CAC_ACC_PH1                                                                               0x01af
12973 #define ixGC_CAC_ACC_PH2                                                                               0x01b0
12974 #define ixGC_CAC_ACC_PH3                                                                               0x01b1
12975 #define ixGC_CAC_ACC_PH4                                                                               0x01b2
12976 #define ixGC_CAC_ACC_PH5                                                                               0x01b3
12977 #define ixGC_CAC_ACC_PH6                                                                               0x01b4
12978 #define ixGC_CAC_ACC_PH7                                                                               0x01b5
12979 #define ixGC_CAC_ACC_SDMA0                                                                             0x01b6
12980 #define ixGC_CAC_ACC_SDMA1                                                                             0x01b7
12981 #define ixGC_CAC_ACC_SDMA2                                                                             0x01b8
12982 #define ixGC_CAC_ACC_SDMA3                                                                             0x01b9
12983 #define ixGC_CAC_ACC_SDMA4                                                                             0x01ba
12984 #define ixGC_CAC_ACC_SDMA5                                                                             0x01bb
12985 #define ixGC_CAC_ACC_SDMA6                                                                             0x01bc
12986 #define ixGC_CAC_ACC_SDMA7                                                                             0x01bd
12987 #define ixGC_CAC_ACC_SDMA8                                                                             0x01be
12988 #define ixGC_CAC_ACC_SDMA9                                                                             0x01bf
12989 #define ixGC_CAC_ACC_SDMA10                                                                            0x01c0
12990 #define ixGC_CAC_ACC_SDMA11                                                                            0x01c1
12991 #define ixGC_CAC_ACC_SP0_LOWER                                                                         0x01c2
12992 #define ixGC_CAC_ACC_SP0_UPPER                                                                         0x01c3
12993 #define ixGC_CAC_ACC_SP1_LOWER                                                                         0x01c4
12994 #define ixGC_CAC_ACC_SP1_UPPER                                                                         0x01c5
12995 #define ixGC_CAC_ACC_SP2_LOWER                                                                         0x01c6
12996 #define ixGC_CAC_ACC_SP2_UPPER                                                                         0x01c7
12997 #define ixGC_CAC_ACC_GL1C0                                                                             0x01c8
12998 #define ixGC_CAC_ACC_GL1C1                                                                             0x01c9
12999 #define ixGC_CAC_ACC_GL1C2                                                                             0x01ca
13000 #define ixGC_CAC_ACC_GL1C3                                                                             0x01cb
13001 #define ixGC_CAC_ACC_GL1C4                                                                             0x01cc
13002 #define ixGC_CAC_ACC_SQC0                                                                              0x01cd
13003 #define ixGC_CAC_ACC_SQC1                                                                              0x01ce
13004 #define ixGC_CAC_ACC_SQC2                                                                              0x01cf
13005 #define ixGC_CAC_ACC_RLC0                                                                              0x01d0
13006 #define ixGC_CAC_OVRD_BCI                                                                              0x0200
13007 #define ixGC_CAC_OVRD_CB                                                                               0x0201
13008 #define ixGC_CAC_OVRD_CP                                                                               0x0203
13009 #define ixGC_CAC_OVRD_DB                                                                               0x0204
13010 #define ixGC_CAC_OVRD_GDS                                                                              0x0206
13011 #define ixGC_CAC_OVRD_LDS                                                                              0x0207
13012 #define ixGC_CAC_OVRD_PA                                                                               0x0208
13013 #define ixGC_CAC_OVRD_PC                                                                               0x0209
13014 #define ixGC_CAC_OVRD_SC                                                                               0x020a
13015 #define ixGC_CAC_OVRD_SPI                                                                              0x020b
13016 #define ixGC_CAC_OVRD_CU                                                                               0x020c
13017 #define ixGC_CAC_OVRD_SQ                                                                               0x020d
13018 #define ixGC_CAC_OVRD_SX                                                                               0x020e
13019 #define ixGC_CAC_OVRD_SXRB                                                                             0x020f
13020 #define ixGC_CAC_OVRD_TA                                                                               0x0210
13021 #define ixGC_CAC_OVRD_TCP                                                                              0x0211
13022 #define ixGC_CAC_OVRD_TD                                                                               0x0212
13023 #define ixGC_CAC_OVRD_RMI                                                                              0x0213
13024 #define ixGC_CAC_OVRD_EA                                                                               0x0214
13025 #define ixGC_CAC_OVRD_UTCL2_ATCL2                                                                      0x0215
13026 #define ixGC_CAC_OVRD_UTCL2_ROUTER                                                                     0x0216
13027 #define ixGC_CAC_OVRD_UTCL2_VML2                                                                       0x0217
13028 #define ixGC_CAC_OVRD_UTCL2_WALKER                                                                     0x0218
13029 #define ixGC_CAC_OVRD_SP                                                                               0x0219
13030 #define ixGC_CAC_OVRD_UTCL1                                                                            0x021a
13031 #define ixGC_CAC_OVRD_CHC                                                                              0x021b
13032 #define ixGC_CAC_OVRD_GE                                                                               0x021c
13033 #define ixGC_CAC_OVRD_PMM                                                                              0x021d
13034 #define ixGC_CAC_OVRD_GL2C                                                                             0x021e
13035 #define ixGC_CAC_OVRD_GUS                                                                              0x021f
13036 #define ixGC_CAC_OVRD_PH                                                                               0x0220
13037 #define ixGC_CAC_OVRD_SDMA                                                                             0x0221
13038 #define ixGC_CAC_OVRD_GL1C                                                                             0x0222
13039 #define ixGC_CAC_OVRD_SQC                                                                              0x0223
13040 #define ixGC_CAC_OVRD_RLC                                                                              0x0224
13041 #define ixGC_CAC_OVRD_GE_HI                                                                            0x0225
13042 #define ixRELEASE_TO_STALL_LUT_1_8                                                                     0x0230
13043 #define ixRELEASE_TO_STALL_LUT_9_16                                                                    0x0231
13044 #define ixRELEASE_TO_STALL_LUT_17_20                                                                   0x0232
13045 #define ixSTALL_TO_RELEASE_LUT_1_4                                                                     0x0233
13046 #define ixSTALL_TO_RELEASE_LUT_5_7                                                                     0x0234
13047 #define ixSTALL_TO_PWRBRK_LUT_1_4                                                                      0x0235
13048 #define ixSTALL_TO_PWRBRK_LUT_5_7                                                                      0x0236
13049 #define ixPWRBRK_STALL_TO_RELEASE_LUT_1_4                                                              0x0237
13050 #define ixPWRBRK_STALL_TO_RELEASE_LUT_5_7                                                              0x0238
13051 #define ixPWRBRK_RELEASE_TO_STALL_LUT_1_8                                                              0x0239
13052 #define ixPWRBRK_RELEASE_TO_STALL_LUT_9_16                                                             0x023a
13053 #define ixPWRBRK_RELEASE_TO_STALL_LUT_17_20                                                            0x023b
13054 #define ixFIXED_PATTERN_PERF_COUNTER_1                                                                 0x023c
13055 #define ixFIXED_PATTERN_PERF_COUNTER_2                                                                 0x023d
13056 #define ixFIXED_PATTERN_PERF_COUNTER_3                                                                 0x023e
13057 #define ixFIXED_PATTERN_PERF_COUNTER_4                                                                 0x023f
13058 #define ixFIXED_PATTERN_PERF_COUNTER_5                                                                 0x0240
13059 #define ixFIXED_PATTERN_PERF_COUNTER_6                                                                 0x0241
13060 #define ixFIXED_PATTERN_PERF_COUNTER_7                                                                 0x0242
13061 #define ixFIXED_PATTERN_PERF_COUNTER_8                                                                 0x0243
13062 #define ixFIXED_PATTERN_PERF_COUNTER_9                                                                 0x0244
13063 #define ixFIXED_PATTERN_PERF_COUNTER_10                                                                0x0245
13064 #define ixHW_LUT_UPDATE_STATUS                                                                         0x0246
13065 
13066 
13067 // addressBlock: secacind
13068 // base address: 0x0
13069 #define ixSE_CAC_ID                                                                                    0x0000
13070 #define ixSE_CAC_CNTL                                                                                  0x0001
13071 #define ixSE_CAC_OVR_SEL                                                                               0x0002
13072 #define ixSE_CAC_OVR_VAL                                                                               0x0003
13073 
13074 
13075 // addressBlock: spmglbind
13076 // base address: 0x0
13077 #define ixGLB_CPG_SAMPLEDELAY                                                                          0x0000
13078 #define ixGLB_CPC_SAMPLEDELAY                                                                          0x0001
13079 #define ixGLB_CPF_SAMPLEDELAY                                                                          0x0002
13080 #define ixGLB_GDS_SAMPLEDELAY                                                                          0x0003
13081 #define ixGLB_GCR_SAMPLEDELAY                                                                          0x0004
13082 #define ixGLB_PH_SAMPLEDELAY                                                                           0x0005
13083 #define ixGLB_GE1_SAMPLEDELAY                                                                          0x0006
13084 #define ixGLB_GE2DIST_SAMPLEDELAY                                                                      0x0007
13085 #define ixGLB_GUS_SAMPLEDELAY                                                                          0x0008
13086 #define ixGLB_CHA_SAMPLEDELAY                                                                          0x0009
13087 #define ixGLB_CHCG_SAMPLEDELAY                                                                         0x000a
13088 #define ixGLB_ATCL2_SAMPLEDELAY                                                                        0x000b
13089 #define ixGLB_VML2_SAMPLEDELAY                                                                         0x000c
13090 #define ixGLB_SDMA0_SAMPLEDELAY                                                                        0x000d
13091 #define ixGLB_SDMA1_SAMPLEDELAY                                                                        0x000e
13092 #define ixGLB_SDMA2_SAMPLEDELAY                                                                        0x000f
13093 #define ixGLB_SDMA3_SAMPLEDELAY                                                                        0x0010
13094 #define ixGLB_GL2A0_SAMPLEDELAY                                                                        0x0011
13095 #define ixGLB_GL2A1_SAMPLEDELAY                                                                        0x0012
13096 #define ixGLB_GL2A2_SAMPLEDELAY                                                                        0x0013
13097 #define ixGLB_GL2A3_SAMPLEDELAY                                                                        0x0014
13098 #define ixGLB_GL2C0_SAMPLEDELAY                                                                        0x0015
13099 #define ixGLB_GL2C1_SAMPLEDELAY                                                                        0x0016
13100 #define ixGLB_GL2C2_SAMPLEDELAY                                                                        0x0017
13101 #define ixGLB_GL2C3_SAMPLEDELAY                                                                        0x0018
13102 #define ixGLB_GL2C4_SAMPLEDELAY                                                                        0x0019
13103 #define ixGLB_GL2C5_SAMPLEDELAY                                                                        0x001a
13104 #define ixGLB_GL2C6_SAMPLEDELAY                                                                        0x001b
13105 #define ixGLB_GL2C7_SAMPLEDELAY                                                                        0x001c
13106 #define ixGLB_GL2C8_SAMPLEDELAY                                                                        0x001d
13107 #define ixGLB_GL2C9_SAMPLEDELAY                                                                        0x001e
13108 #define ixGLB_GL2C10_SAMPLEDELAY                                                                       0x001f
13109 #define ixGLB_GL2C11_SAMPLEDELAY                                                                       0x0020
13110 #define ixGLB_GL2C12_SAMPLEDELAY                                                                       0x0021
13111 #define ixGLB_GL2C13_SAMPLEDELAY                                                                       0x0022
13112 #define ixGLB_GL2C14_SAMPLEDELAY                                                                       0x0023
13113 #define ixGLB_GL2C15_SAMPLEDELAY                                                                       0x0024
13114 #define ixGLB_EA0_SAMPLEDELAY                                                                          0x0025
13115 #define ixGLB_EA1_SAMPLEDELAY                                                                          0x0026
13116 #define ixGLB_EA2_SAMPLEDELAY                                                                          0x0027
13117 #define ixGLB_EA3_SAMPLEDELAY                                                                          0x0028
13118 #define ixGLB_EA4_SAMPLEDELAY                                                                          0x0029
13119 #define ixGLB_EA5_SAMPLEDELAY                                                                          0x002a
13120 #define ixGLB_EA6_SAMPLEDELAY                                                                          0x002b
13121 #define ixGLB_EA7_SAMPLEDELAY                                                                          0x002c
13122 #define ixGLB_EA8_SAMPLEDELAY                                                                          0x002d
13123 #define ixGLB_EA9_SAMPLEDELAY                                                                          0x002e
13124 #define ixGLB_EA10_SAMPLEDELAY                                                                         0x002f
13125 #define ixGLB_EA11_SAMPLEDELAY                                                                         0x0030
13126 #define ixGLB_EA12_SAMPLEDELAY                                                                         0x0031
13127 #define ixGLB_EA13_SAMPLEDELAY                                                                         0x0032
13128 #define ixGLB_EA14_SAMPLEDELAY                                                                         0x0033
13129 #define ixGLB_EA15_SAMPLEDELAY                                                                         0x0034
13130 #define ixGLB_CHC0_SAMPLEDELAY                                                                         0x0035
13131 #define ixGLB_CHC1_SAMPLEDELAY                                                                         0x0036
13132 #define ixGLB_CHC2_SAMPLEDELAY                                                                         0x0037
13133 #define ixGLB_CHC3_SAMPLEDELAY                                                                         0x0038
13134 #define ixGLB_GE2SE0_SAMPLEDELAY                                                                       0x0039
13135 #define ixGLB_GE2SE1_SAMPLEDELAY                                                                       0x003a
13136 #define ixGLB_GE2SE2_SAMPLEDELAY                                                                       0x003b
13137 #define ixGLB_GE2SE3_SAMPLEDELAY                                                                       0x003c
13138 
13139 
13140 // addressBlock: spmind
13141 // base address: 0x0
13142 #define ixSE_SPI_SAMPLEDELAY                                                                           0x0000
13143 #define ixSE_SQG_SAMPLEDELAY                                                                           0x0001
13144 #define ixSE_CBR_SAMPLEDELAY                                                                           0x0002
13145 #define ixSE_DBR_SAMPLEDELAY                                                                           0x0003
13146 #define ixSE_PA_SAMPLEDELAY                                                                            0x0004
13147 #define ixSE_SA0SX_SAMPLEDELAY                                                                         0x0005
13148 #define ixSE_SA0GL1A_SAMPLEDELAY                                                                       0x0006
13149 #define ixSE_SA0GL1CG_SAMPLEDELAY                                                                      0x0007
13150 #define ixSE_SA0CB0_SAMPLEDELAY                                                                        0x0008
13151 #define ixSE_SA0CB1_SAMPLEDELAY                                                                        0x0009
13152 #define ixSE_SA0DB0_SAMPLEDELAY                                                                        0x000a
13153 #define ixSE_SA0DB1_SAMPLEDELAY                                                                        0x000b
13154 #define ixSE_SA0SC0_SAMPLEDELAY                                                                        0x000c
13155 #define ixSE_SA0SC1_SAMPLEDELAY                                                                        0x000d
13156 #define ixSE_SA0RMI0_SAMPLEDELAY                                                                       0x000e
13157 #define ixSE_SA0RMI1_SAMPLEDELAY                                                                       0x000f
13158 #define ixSE_SA0GL1C0_SAMPLEDELAY                                                                      0x0010
13159 #define ixSE_SA0GL1C1_SAMPLEDELAY                                                                      0x0011
13160 #define ixSE_SA0GL1C2_SAMPLEDELAY                                                                      0x0012
13161 #define ixSE_SA0GL1C3_SAMPLEDELAY                                                                      0x0013
13162 #define ixSE_SA0WGP00TA0_SAMPLEDELAY                                                                   0x0014
13163 #define ixSE_SA0WGP00TA1_SAMPLEDELAY                                                                   0x0015
13164 #define ixSE_SA0WGP00TD0_SAMPLEDELAY                                                                   0x0016
13165 #define ixSE_SA0WGP00TD1_SAMPLEDELAY                                                                   0x0017
13166 #define ixSE_SA0WGP00TCP0_SAMPLEDELAY                                                                  0x0018
13167 #define ixSE_SA0WGP00TCP1_SAMPLEDELAY                                                                  0x0019
13168 #define ixSE_SA0WGP01TA0_SAMPLEDELAY                                                                   0x001a
13169 #define ixSE_SA0WGP01TA1_SAMPLEDELAY                                                                   0x001b
13170 #define ixSE_SA0WGP01TD0_SAMPLEDELAY                                                                   0x001c
13171 #define ixSE_SA0WGP01TD1_SAMPLEDELAY                                                                   0x001d
13172 #define ixSE_SA0WGP01TCP0_SAMPLEDELAY                                                                  0x001e
13173 #define ixSE_SA0WGP01TCP1_SAMPLEDELAY                                                                  0x001f
13174 #define ixSE_SA0WGP02TA0_SAMPLEDELAY                                                                   0x0020
13175 #define ixSE_SA0WGP02TA1_SAMPLEDELAY                                                                   0x0021
13176 #define ixSE_SA0WGP02TD0_SAMPLEDELAY                                                                   0x0022
13177 #define ixSE_SA0WGP02TD1_SAMPLEDELAY                                                                   0x0023
13178 #define ixSE_SA0WGP02TCP0_SAMPLEDELAY                                                                  0x0024
13179 #define ixSE_SA0WGP02TCP1_SAMPLEDELAY                                                                  0x0025
13180 #define ixSE_SA0WGP03TA0_SAMPLEDELAY                                                                   0x0026
13181 #define ixSE_SA0WGP03TA1_SAMPLEDELAY                                                                   0x0027
13182 #define ixSE_SA0WGP03TD0_SAMPLEDELAY                                                                   0x0028
13183 #define ixSE_SA0WGP03TD1_SAMPLEDELAY                                                                   0x0029
13184 #define ixSE_SA0WGP03TCP0_SAMPLEDELAY                                                                  0x002a
13185 #define ixSE_SA0WGP03TCP1_SAMPLEDELAY                                                                  0x002b
13186 #define ixSE_SA0WGP04TA0_SAMPLEDELAY                                                                   0x002c
13187 #define ixSE_SA0WGP04TA1_SAMPLEDELAY                                                                   0x002d
13188 #define ixSE_SA0WGP04TD0_SAMPLEDELAY                                                                   0x002e
13189 #define ixSE_SA0WGP04TD1_SAMPLEDELAY                                                                   0x002f
13190 #define ixSE_SA0WGP04TCP0_SAMPLEDELAY                                                                  0x0030
13191 #define ixSE_SA0WGP04TCP1_SAMPLEDELAY                                                                  0x0031
13192 #define ixSE_SA1SX_SAMPLEDELAY                                                                         0x0032
13193 #define ixSE_SA1GL1A_SAMPLEDELAY                                                                       0x0033
13194 #define ixSE_SA1GL1CG_SAMPLEDELAY                                                                      0x0034
13195 #define ixSE_SA1CB0_SAMPLEDELAY                                                                        0x0035
13196 #define ixSE_SA1CB1_SAMPLEDELAY                                                                        0x0036
13197 #define ixSE_SA1DB0_SAMPLEDELAY                                                                        0x0037
13198 #define ixSE_SA1DB1_SAMPLEDELAY                                                                        0x0038
13199 #define ixSE_SA1SC0_SAMPLEDELAY                                                                        0x0039
13200 #define ixSE_SA1SC1_SAMPLEDELAY                                                                        0x003a
13201 #define ixSE_SA1RMI0_SAMPLEDELAY                                                                       0x003b
13202 #define ixSE_SA1RMI1_SAMPLEDELAY                                                                       0x003c
13203 #define ixSE_SA1GL1C0_SAMPLEDELAY                                                                      0x003d
13204 #define ixSE_SA1GL1C1_SAMPLEDELAY                                                                      0x003e
13205 #define ixSE_SA1GL1C2_SAMPLEDELAY                                                                      0x003f
13206 #define ixSE_SA1GL1C3_SAMPLEDELAY                                                                      0x0040
13207 #define ixSE_SA1WGP00TA0_SAMPLEDELAY                                                                   0x0041
13208 #define ixSE_SA1WGP00TA1_SAMPLEDELAY                                                                   0x0042
13209 #define ixSE_SA1WGP00TD0_SAMPLEDELAY                                                                   0x0043
13210 #define ixSE_SA1WGP00TD1_SAMPLEDELAY                                                                   0x0044
13211 #define ixSE_SA1WGP00TCP0_SAMPLEDELAY                                                                  0x0045
13212 #define ixSE_SA1WGP00TCP1_SAMPLEDELAY                                                                  0x0046
13213 #define ixSE_SA1WGP01TA0_SAMPLEDELAY                                                                   0x0047
13214 #define ixSE_SA1WGP01TA1_SAMPLEDELAY                                                                   0x0048
13215 #define ixSE_SA1WGP01TD0_SAMPLEDELAY                                                                   0x0049
13216 #define ixSE_SA1WGP01TD1_SAMPLEDELAY                                                                   0x004a
13217 #define ixSE_SA1WGP01TCP0_SAMPLEDELAY                                                                  0x004b
13218 #define ixSE_SA1WGP01TCP1_SAMPLEDELAY                                                                  0x004c
13219 #define ixSE_SA1WGP02TA0_SAMPLEDELAY                                                                   0x004d
13220 #define ixSE_SA1WGP02TA1_SAMPLEDELAY                                                                   0x004e
13221 #define ixSE_SA1WGP02TD0_SAMPLEDELAY                                                                   0x004f
13222 #define ixSE_SA1WGP02TD1_SAMPLEDELAY                                                                   0x0050
13223 #define ixSE_SA1WGP02TCP0_SAMPLEDELAY                                                                  0x0051
13224 #define ixSE_SA1WGP02TCP1_SAMPLEDELAY                                                                  0x0052
13225 #define ixSE_SA1WGP03TA0_SAMPLEDELAY                                                                   0x0053
13226 #define ixSE_SA1WGP03TA1_SAMPLEDELAY                                                                   0x0054
13227 #define ixSE_SA1WGP03TD0_SAMPLEDELAY                                                                   0x0055
13228 #define ixSE_SA1WGP03TD1_SAMPLEDELAY                                                                   0x0056
13229 #define ixSE_SA1WGP03TCP0_SAMPLEDELAY                                                                  0x0057
13230 #define ixSE_SA1WGP03TCP1_SAMPLEDELAY                                                                  0x0058
13231 #define ixSE_SA1WGP04TA0_SAMPLEDELAY                                                                   0x0059
13232 #define ixSE_SA1WGP04TA1_SAMPLEDELAY                                                                   0x005a
13233 #define ixSE_SA1WGP04TD0_SAMPLEDELAY                                                                   0x005b
13234 #define ixSE_SA1WGP04TD1_SAMPLEDELAY                                                                   0x005c
13235 #define ixSE_SA1WGP04TCP0_SAMPLEDELAY                                                                  0x005d
13236 #define ixSE_SA1WGP04TCP1_SAMPLEDELAY                                                                  0x005e
13237 
13238 
13239 // base address: 0x0
13240 
13241 
13242 // addressBlock: grtavfsind
13243 // base address: 0x0
13244 #define ixRTAVFS_REG0                                                                                  0x0000
13245 #define ixRTAVFS_REG1                                                                                  0x0001
13246 #define ixRTAVFS_REG2                                                                                  0x0002
13247 #define ixRTAVFS_REG3                                                                                  0x0003
13248 #define ixRTAVFS_REG4                                                                                  0x0004
13249 #define ixRTAVFS_REG5                                                                                  0x0005
13250 #define ixRTAVFS_REG6                                                                                  0x0006
13251 #define ixRTAVFS_REG7                                                                                  0x0007
13252 #define ixRTAVFS_REG8                                                                                  0x0008
13253 #define ixRTAVFS_REG9                                                                                  0x0009
13254 #define ixRTAVFS_REG10                                                                                 0x000a
13255 #define ixRTAVFS_REG11                                                                                 0x000b
13256 #define ixRTAVFS_REG12                                                                                 0x000c
13257 #define ixRTAVFS_REG13                                                                                 0x000d
13258 #define ixRTAVFS_REG14                                                                                 0x000e
13259 #define ixRTAVFS_REG15                                                                                 0x000f
13260 #define ixRTAVFS_REG16                                                                                 0x0010
13261 #define ixRTAVFS_REG17                                                                                 0x0011
13262 #define ixRTAVFS_REG18                                                                                 0x0012
13263 #define ixRTAVFS_REG19                                                                                 0x0013
13264 #define ixRTAVFS_REG20                                                                                 0x0014
13265 #define ixRTAVFS_REG21                                                                                 0x0015
13266 #define ixRTAVFS_REG22                                                                                 0x0016
13267 #define ixRTAVFS_REG23                                                                                 0x0017
13268 #define ixRTAVFS_REG24                                                                                 0x0018
13269 #define ixRTAVFS_REG25                                                                                 0x0019
13270 #define ixRTAVFS_REG26                                                                                 0x001a
13271 #define ixRTAVFS_REG27                                                                                 0x001b
13272 #define ixRTAVFS_REG28                                                                                 0x001c
13273 #define ixRTAVFS_REG29                                                                                 0x001d
13274 #define ixRTAVFS_REG30                                                                                 0x001e
13275 #define ixRTAVFS_REG31                                                                                 0x001f
13276 #define ixRTAVFS_REG32                                                                                 0x0020
13277 #define ixRTAVFS_REG33                                                                                 0x0021
13278 #define ixRTAVFS_REG34                                                                                 0x0022
13279 #define ixRTAVFS_REG35                                                                                 0x0023
13280 #define ixRTAVFS_REG36                                                                                 0x0024
13281 #define ixRTAVFS_REG37                                                                                 0x0025
13282 #define ixRTAVFS_REG38                                                                                 0x0026
13283 #define ixRTAVFS_REG39                                                                                 0x0027
13284 #define ixRTAVFS_REG40                                                                                 0x0028
13285 #define ixRTAVFS_REG41                                                                                 0x0029
13286 #define ixRTAVFS_REG42                                                                                 0x002a
13287 #define ixRTAVFS_REG43                                                                                 0x002b
13288 #define ixRTAVFS_REG44                                                                                 0x002c
13289 #define ixRTAVFS_REG45                                                                                 0x002d
13290 #define ixRTAVFS_REG46                                                                                 0x002e
13291 #define ixRTAVFS_REG47                                                                                 0x002f
13292 #define ixRTAVFS_REG48                                                                                 0x0030
13293 #define ixRTAVFS_REG49                                                                                 0x0031
13294 #define ixRTAVFS_REG50                                                                                 0x0032
13295 #define ixRTAVFS_REG51                                                                                 0x0033
13296 #define ixRTAVFS_REG52                                                                                 0x0034
13297 #define ixRTAVFS_REG53                                                                                 0x0035
13298 #define ixRTAVFS_REG54                                                                                 0x0036
13299 #define ixRTAVFS_REG55                                                                                 0x0037
13300 #define ixRTAVFS_REG56                                                                                 0x0038
13301 #define ixRTAVFS_REG57                                                                                 0x0039
13302 #define ixRTAVFS_REG58                                                                                 0x003a
13303 #define ixRTAVFS_REG59                                                                                 0x003b
13304 #define ixRTAVFS_REG60                                                                                 0x003c
13305 #define ixRTAVFS_REG61                                                                                 0x003d
13306 #define ixRTAVFS_REG62                                                                                 0x003e
13307 #define ixRTAVFS_REG63                                                                                 0x003f
13308 #define ixRTAVFS_REG64                                                                                 0x0040
13309 #define ixRTAVFS_REG65                                                                                 0x0041
13310 #define ixRTAVFS_REG66                                                                                 0x0042
13311 #define ixRTAVFS_REG67                                                                                 0x0043
13312 #define ixRTAVFS_REG68                                                                                 0x0044
13313 #define ixRTAVFS_REG69                                                                                 0x0045
13314 #define ixRTAVFS_REG70                                                                                 0x0046
13315 #define ixRTAVFS_REG71                                                                                 0x0047
13316 #define ixRTAVFS_REG72                                                                                 0x0048
13317 #define ixRTAVFS_REG73                                                                                 0x0049
13318 #define ixRTAVFS_REG74                                                                                 0x004a
13319 #define ixRTAVFS_REG75                                                                                 0x004b
13320 #define ixRTAVFS_REG76                                                                                 0x004c
13321 #define ixRTAVFS_REG77                                                                                 0x004d
13322 #define ixRTAVFS_REG78                                                                                 0x004e
13323 #define ixRTAVFS_REG79                                                                                 0x004f
13324 #define ixRTAVFS_REG80                                                                                 0x0050
13325 #define ixRTAVFS_REG81                                                                                 0x0051
13326 #define ixRTAVFS_REG82                                                                                 0x0052
13327 #define ixRTAVFS_REG83                                                                                 0x0053
13328 #define ixRTAVFS_REG84                                                                                 0x0054
13329 #define ixRTAVFS_REG85                                                                                 0x0055
13330 #define ixRTAVFS_REG86                                                                                 0x0056
13331 #define ixRTAVFS_REG87                                                                                 0x0057
13332 #define ixRTAVFS_REG88                                                                                 0x0058
13333 #define ixRTAVFS_REG89                                                                                 0x0059
13334 #define ixRTAVFS_REG90                                                                                 0x005a
13335 #define ixRTAVFS_REG91                                                                                 0x005b
13336 #define ixRTAVFS_REG92                                                                                 0x005c
13337 #define ixRTAVFS_REG93                                                                                 0x005d
13338 #define ixRTAVFS_REG94                                                                                 0x005e
13339 #define ixRTAVFS_REG95                                                                                 0x005f
13340 #define ixRTAVFS_REG96                                                                                 0x0060
13341 #define ixRTAVFS_REG97                                                                                 0x0061
13342 #define ixRTAVFS_REG98                                                                                 0x0062
13343 #define ixRTAVFS_REG99                                                                                 0x0063
13344 #define ixRTAVFS_REG100                                                                                0x0064
13345 #define ixRTAVFS_REG101                                                                                0x0065
13346 #define ixRTAVFS_REG102                                                                                0x0066
13347 #define ixRTAVFS_REG103                                                                                0x0067
13348 #define ixRTAVFS_REG104                                                                                0x0068
13349 #define ixRTAVFS_REG105                                                                                0x0069
13350 #define ixRTAVFS_REG106                                                                                0x006a
13351 #define ixRTAVFS_REG107                                                                                0x006b
13352 #define ixRTAVFS_REG108                                                                                0x006c
13353 #define ixRTAVFS_REG109                                                                                0x006d
13354 #define ixRTAVFS_REG110                                                                                0x006e
13355 #define ixRTAVFS_REG111                                                                                0x006f
13356 #define ixRTAVFS_REG112                                                                                0x0070
13357 #define ixRTAVFS_REG113                                                                                0x0071
13358 #define ixRTAVFS_REG114                                                                                0x0072
13359 #define ixRTAVFS_REG115                                                                                0x0073
13360 #define ixRTAVFS_REG116                                                                                0x0074
13361 #define ixRTAVFS_REG117                                                                                0x0075
13362 #define ixRTAVFS_REG118                                                                                0x0076
13363 #define ixRTAVFS_REG119                                                                                0x0077
13364 #define ixRTAVFS_REG120                                                                                0x0078
13365 #define ixRTAVFS_REG121                                                                                0x0079
13366 #define ixRTAVFS_REG122                                                                                0x007a
13367 #define ixRTAVFS_REG123                                                                                0x007b
13368 #define ixRTAVFS_REG124                                                                                0x007c
13369 #define ixRTAVFS_REG125                                                                                0x007d
13370 #define ixRTAVFS_REG126                                                                                0x007e
13371 #define ixRTAVFS_REG127                                                                                0x007f
13372 #define ixRTAVFS_REG128                                                                                0x0080
13373 #define ixRTAVFS_REG129                                                                                0x0081
13374 #define ixRTAVFS_REG130                                                                                0x0082
13375 #define ixRTAVFS_REG131                                                                                0x0083
13376 #define ixRTAVFS_REG132                                                                                0x0084
13377 #define ixRTAVFS_REG133                                                                                0x0085
13378 #define ixRTAVFS_REG134                                                                                0x0086
13379 #define ixRTAVFS_REG135                                                                                0x0087
13380 #define ixRTAVFS_REG136                                                                                0x0088
13381 #define ixRTAVFS_REG137                                                                                0x0089
13382 #define ixRTAVFS_REG138                                                                                0x008a
13383 #define ixRTAVFS_REG139                                                                                0x008b
13384 #define ixRTAVFS_REG140                                                                                0x008c
13385 #define ixRTAVFS_REG141                                                                                0x008d
13386 #define ixRTAVFS_REG142                                                                                0x008e
13387 #define ixRTAVFS_REG143                                                                                0x008f
13388 #define ixRTAVFS_REG144                                                                                0x0090
13389 #define ixRTAVFS_REG145                                                                                0x0091
13390 #define ixRTAVFS_REG146                                                                                0x0092
13391 #define ixRTAVFS_REG147                                                                                0x0093
13392 #define ixRTAVFS_REG148                                                                                0x0094
13393 #define ixRTAVFS_REG149                                                                                0x0095
13394 #define ixRTAVFS_REG150                                                                                0x0096
13395 #define ixRTAVFS_REG151                                                                                0x0097
13396 #define ixRTAVFS_REG152                                                                                0x0098
13397 #define ixRTAVFS_REG153                                                                                0x0099
13398 #define ixRTAVFS_REG154                                                                                0x009a
13399 #define ixRTAVFS_REG155                                                                                0x009b
13400 #define ixRTAVFS_REG156                                                                                0x009c
13401 #define ixRTAVFS_REG157                                                                                0x009d
13402 #define ixRTAVFS_REG158                                                                                0x009e
13403 #define ixRTAVFS_REG159                                                                                0x009f
13404 #define ixRTAVFS_REG160                                                                                0x00a0
13405 #define ixRTAVFS_REG161                                                                                0x00a1
13406 #define ixRTAVFS_REG162                                                                                0x00a2
13407 #define ixRTAVFS_REG163                                                                                0x00a3
13408 #define ixRTAVFS_REG164                                                                                0x00a4
13409 #define ixRTAVFS_REG165                                                                                0x00a5
13410 
13411 
13412 // addressBlock: spiind
13413 // base address: 0x0
13414 #define ixSA_WGP_BLK_ID                                                                                0x0000
13415 
13416 
13417 // addressBlock: sqind
13418 // base address: 0x0
13419 #define ixSQ_DEBUG_STS_LOCAL                                                                           0x0008
13420 #define ixSQ_WAVE_ACTIVE                                                                               0x000a
13421 #define ixSQ_WAVE_VALID_AND_IDLE                                                                       0x000b
13422 #define ixSQ_WAVE_MODE                                                                                 0x0101
13423 #define ixSQ_WAVE_STATUS                                                                               0x0102
13424 #define ixSQ_WAVE_TRAPSTS                                                                              0x0103
13425 #define ixSQ_WAVE_HW_ID_LEGACY                                                                         0x0104
13426 #define ixSQ_WAVE_GPR_ALLOC                                                                            0x0105
13427 #define ixSQ_WAVE_LDS_ALLOC                                                                            0x0106
13428 #define ixSQ_WAVE_IB_STS                                                                               0x0107
13429 #define ixSQ_WAVE_PC_LO                                                                                0x0108
13430 #define ixSQ_WAVE_PC_HI                                                                                0x0109
13431 #define ixSQ_WAVE_INST_DW0                                                                             0x010a
13432 #define ixSQ_WAVE_IB_DBG1                                                                              0x010d
13433 #define ixSQ_WAVE_FLUSH_IB                                                                             0x010e
13434 #define ixSQ_WAVE_FLAT_SCRATCH_LO                                                                      0x0114
13435 #define ixSQ_WAVE_FLAT_SCRATCH_HI                                                                      0x0115
13436 #define ixSQ_WAVE_HW_ID1                                                                               0x0117
13437 #define ixSQ_WAVE_HW_ID2                                                                               0x0118
13438 #define ixSQ_WAVE_POPS_PACKER                                                                          0x0119
13439 #define ixSQ_WAVE_SCHED_MODE                                                                           0x011a
13440 #define ixSQ_WAVE_VGPR_OFFSET                                                                          0x011b
13441 #define ixSQ_WAVE_IB_STS2                                                                              0x011c
13442 #define ixSQ_WAVE_SHADER_CYCLES                                                                        0x011d
13443 #define ixSQ_WAVE_TTMP0                                                                                0x026c
13444 #define ixSQ_WAVE_TTMP1                                                                                0x026d
13445 #define ixSQ_WAVE_TTMP2                                                                                0x026e
13446 #define ixSQ_WAVE_TTMP3                                                                                0x026f
13447 #define ixSQ_WAVE_TTMP4                                                                                0x0270
13448 #define ixSQ_WAVE_TTMP5                                                                                0x0271
13449 #define ixSQ_WAVE_TTMP6                                                                                0x0272
13450 #define ixSQ_WAVE_TTMP7                                                                                0x0273
13451 #define ixSQ_WAVE_TTMP8                                                                                0x0274
13452 #define ixSQ_WAVE_TTMP9                                                                                0x0275
13453 #define ixSQ_WAVE_TTMP10                                                                               0x0276
13454 #define ixSQ_WAVE_TTMP11                                                                               0x0277
13455 #define ixSQ_WAVE_TTMP12                                                                               0x0278
13456 #define ixSQ_WAVE_TTMP13                                                                               0x0279
13457 #define ixSQ_WAVE_TTMP14                                                                               0x027a
13458 #define ixSQ_WAVE_TTMP15                                                                               0x027b
13459 #define ixSQ_WAVE_M0                                                                                   0x027c
13460 #define ixSQ_WAVE_EXEC_LO                                                                              0x027e
13461 #define ixSQ_WAVE_EXEC_HI                                                                              0x027f
13462 #define ixSQ_INTERRUPT_WORD_AUTO                                                                       0x20c0
13463 #define ixSQ_INTERRUPT_WORD_ERROR                                                                      0x20c0
13464 #define ixSQ_INTERRUPT_WORD_WAVE                                                                       0x20c0
13465 
13466 
13467 // addressBlock: didtind
13468 // base address: 0x0
13469 #define ixDIDT_SQ_CTRL0                                                                                0x0000
13470 #define ixDIDT_SQ_CTRL1                                                                                0x0001
13471 #define ixDIDT_SQ_CTRL2                                                                                0x0002
13472 #define ixDIDT_SQ_CTRL_OCP                                                                             0x0003
13473 #define ixDIDT_SQ_STALL_CTRL                                                                           0x0004
13474 #define ixDIDT_SQ_TUNING_CTRL                                                                          0x0005
13475 #define ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL                                                              0x0006
13476 #define ixDIDT_SQ_CTRL3                                                                                0x0007
13477 #define ixDIDT_SQ_STALL_PATTERN_1_2                                                                    0x0008
13478 #define ixDIDT_SQ_STALL_PATTERN_3_4                                                                    0x0009
13479 #define ixDIDT_SQ_STALL_PATTERN_5_6                                                                    0x000a
13480 #define ixDIDT_SQ_STALL_PATTERN_7                                                                      0x000b
13481 #define ixDIDT_SQ_MPD_SCALE_FACTOR                                                                     0x000c
13482 #define ixDIDT_SQ_STALL_RELEASE_CNTL0                                                                  0x000d
13483 #define ixDIDT_SQ_STALL_RELEASE_CNTL1                                                                  0x000e
13484 #define ixDIDT_SQ_STALL_RELEASE_CNTL_STATUS                                                            0x000f
13485 #define ixDIDT_SQ_WEIGHT0_3                                                                            0x0010
13486 #define ixDIDT_SQ_WEIGHT4_7                                                                            0x0011
13487 #define ixDIDT_SQ_WEIGHT8_11                                                                           0x0012
13488 #define ixDIDT_SQ_EDC_CTRL                                                                             0x0013
13489 #define ixDIDT_SQ_EDC_THRESHOLD                                                                        0x0014
13490 #define ixDIDT_SQ_EDC_STALL_PATTERN_1_2                                                                0x0015
13491 #define ixDIDT_SQ_EDC_STALL_PATTERN_3_4                                                                0x0016
13492 #define ixDIDT_SQ_EDC_STALL_PATTERN_5_6                                                                0x0017
13493 #define ixDIDT_SQ_EDC_STALL_PATTERN_7                                                                  0x0018
13494 #define ixDIDT_SQ_EDC_TIMER_PERIOD                                                                     0x0019
13495 #define ixDIDT_SQ_THROTTLE_CTRL                                                                        0x001a
13496 #define ixDIDT_SQ_EDC_STALL_DELAY_1                                                                    0x001b
13497 #define ixDIDT_SQ_EDC_STALL_DELAY_2                                                                    0x001c
13498 #define ixDIDT_SQ_EDC_STALL_DELAY_3                                                                    0x001d
13499 #define ixDIDT_SQ_EDC_STATUS                                                                           0x001f
13500 #define ixDIDT_SQ_EDC_OVERFLOW                                                                         0x0020
13501 #define ixDIDT_SQ_EDC_ROLLING_POWER_DELTA                                                              0x0021
13502 #define ixDIDT_SQ_EDC_PCC_PERF_COUNTER                                                                 0x0022
13503 #define ixDIDT_DB_CTRL0                                                                                0x0030
13504 #define ixDIDT_DB_CTRL1                                                                                0x0031
13505 #define ixDIDT_DB_CTRL2                                                                                0x0032
13506 #define ixDIDT_DB_CTRL_OCP                                                                             0x0033
13507 #define ixDIDT_DB_STALL_CTRL                                                                           0x0034
13508 #define ixDIDT_DB_TUNING_CTRL                                                                          0x0035
13509 #define ixDIDT_DB_STALL_AUTO_RELEASE_CTRL                                                              0x0036
13510 #define ixDIDT_DB_CTRL3                                                                                0x0037
13511 #define ixDIDT_DB_STALL_PATTERN_1_2                                                                    0x0038
13512 #define ixDIDT_DB_STALL_PATTERN_3_4                                                                    0x0039
13513 #define ixDIDT_DB_STALL_PATTERN_5_6                                                                    0x003a
13514 #define ixDIDT_DB_STALL_PATTERN_7                                                                      0x003b
13515 #define ixDIDT_DB_MPD_SCALE_FACTOR                                                                     0x003c
13516 #define ixDIDT_DB_STALL_RELEASE_CNTL0                                                                  0x003d
13517 #define ixDIDT_DB_STALL_RELEASE_CNTL1                                                                  0x003e
13518 #define ixDIDT_DB_STALL_RELEASE_CNTL_STATUS                                                            0x003f
13519 #define ixDIDT_DB_WEIGHT0_3                                                                            0x0040
13520 #define ixDIDT_DB_WEIGHT4_7                                                                            0x0041
13521 #define ixDIDT_DB_WEIGHT8_11                                                                           0x0042
13522 #define ixDIDT_DB_EDC_CTRL                                                                             0x0043
13523 #define ixDIDT_DB_EDC_THRESHOLD                                                                        0x0044
13524 #define ixDIDT_DB_EDC_STALL_PATTERN_1_2                                                                0x0045
13525 #define ixDIDT_DB_EDC_STALL_PATTERN_3_4                                                                0x0046
13526 #define ixDIDT_DB_EDC_STALL_PATTERN_5_6                                                                0x0047
13527 #define ixDIDT_DB_EDC_STALL_PATTERN_7                                                                  0x0048
13528 #define ixDIDT_DB_EDC_TIMER_PERIOD                                                                     0x0049
13529 #define ixDIDT_DB_THROTTLE_CTRL                                                                        0x004a
13530 #define ixDIDT_DB_EDC_STALL_DELAY_1                                                                    0x004b
13531 #define ixDIDT_DB_EDC_STATUS                                                                           0x004f
13532 #define ixDIDT_DB_EDC_OVERFLOW                                                                         0x0050
13533 #define ixDIDT_DB_EDC_ROLLING_POWER_DELTA                                                              0x0051
13534 #define ixDIDT_DB_EDC_PCC_PERF_COUNTER                                                                 0x0052
13535 #define ixDIDT_TD_CTRL0                                                                                0x0060
13536 #define ixDIDT_TD_CTRL1                                                                                0x0061
13537 #define ixDIDT_TD_CTRL2                                                                                0x0062
13538 #define ixDIDT_TD_CTRL_OCP                                                                             0x0063
13539 #define ixDIDT_TD_STALL_CTRL                                                                           0x0064
13540 #define ixDIDT_TD_TUNING_CTRL                                                                          0x0065
13541 #define ixDIDT_TD_STALL_AUTO_RELEASE_CTRL                                                              0x0066
13542 #define ixDIDT_TD_CTRL3                                                                                0x0067
13543 #define ixDIDT_TD_STALL_PATTERN_1_2                                                                    0x0068
13544 #define ixDIDT_TD_STALL_PATTERN_3_4                                                                    0x0069
13545 #define ixDIDT_TD_STALL_PATTERN_5_6                                                                    0x006a
13546 #define ixDIDT_TD_STALL_PATTERN_7                                                                      0x006b
13547 #define ixDIDT_TD_MPD_SCALE_FACTOR                                                                     0x006c
13548 #define ixDIDT_TD_STALL_RELEASE_CNTL0                                                                  0x006d
13549 #define ixDIDT_TD_STALL_RELEASE_CNTL1                                                                  0x006e
13550 #define ixDIDT_TD_STALL_RELEASE_CNTL_STATUS                                                            0x006f
13551 #define ixDIDT_TD_WEIGHT0_3                                                                            0x0070
13552 #define ixDIDT_TD_WEIGHT4_7                                                                            0x0071
13553 #define ixDIDT_TD_WEIGHT8_11                                                                           0x0072
13554 #define ixDIDT_TD_EDC_CTRL                                                                             0x0073
13555 #define ixDIDT_TD_EDC_THRESHOLD                                                                        0x0074
13556 #define ixDIDT_TD_EDC_STALL_PATTERN_1_2                                                                0x0075
13557 #define ixDIDT_TD_EDC_STALL_PATTERN_3_4                                                                0x0076
13558 #define ixDIDT_TD_EDC_STALL_PATTERN_5_6                                                                0x0077
13559 #define ixDIDT_TD_EDC_STALL_PATTERN_7                                                                  0x0078
13560 #define ixDIDT_TD_EDC_TIMER_PERIOD                                                                     0x0079
13561 #define ixDIDT_TD_THROTTLE_CTRL                                                                        0x007a
13562 #define ixDIDT_TD_EDC_STALL_DELAY_1                                                                    0x007b
13563 #define ixDIDT_TD_EDC_STALL_DELAY_2                                                                    0x007c
13564 #define ixDIDT_TD_EDC_STALL_DELAY_3                                                                    0x007d
13565 #define ixDIDT_TD_EDC_STATUS                                                                           0x007f
13566 #define ixDIDT_TD_EDC_OVERFLOW                                                                         0x0080
13567 #define ixDIDT_TD_EDC_ROLLING_POWER_DELTA                                                              0x0081
13568 #define ixDIDT_TD_EDC_PCC_PERF_COUNTER                                                                 0x0082
13569 #define ixDIDT_TCP_CTRL0                                                                               0x0090
13570 #define ixDIDT_TCP_CTRL1                                                                               0x0091
13571 #define ixDIDT_TCP_CTRL2                                                                               0x0092
13572 #define ixDIDT_TCP_CTRL_OCP                                                                            0x0093
13573 #define ixDIDT_TCP_STALL_CTRL                                                                          0x0094
13574 #define ixDIDT_TCP_TUNING_CTRL                                                                         0x0095
13575 #define ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL                                                             0x0096
13576 #define ixDIDT_TCP_CTRL3                                                                               0x0097
13577 #define ixDIDT_TCP_STALL_PATTERN_1_2                                                                   0x0098
13578 #define ixDIDT_TCP_STALL_PATTERN_3_4                                                                   0x0099
13579 #define ixDIDT_TCP_STALL_PATTERN_5_6                                                                   0x009a
13580 #define ixDIDT_TCP_STALL_PATTERN_7                                                                     0x009b
13581 #define ixDIDT_TCP_MPD_SCALE_FACTOR                                                                    0x009c
13582 #define ixDIDT_TCP_STALL_RELEASE_CNTL0                                                                 0x009d
13583 #define ixDIDT_TCP_STALL_RELEASE_CNTL1                                                                 0x009e
13584 #define ixDIDT_TCP_STALL_RELEASE_CNTL_STATUS                                                           0x009f
13585 #define ixDIDT_TCP_WEIGHT0_3                                                                           0x00a0
13586 #define ixDIDT_TCP_WEIGHT4_7                                                                           0x00a1
13587 #define ixDIDT_TCP_WEIGHT8_11                                                                          0x00a2
13588 #define ixDIDT_TCP_EDC_CTRL                                                                            0x00a3
13589 #define ixDIDT_TCP_EDC_THRESHOLD                                                                       0x00a4
13590 #define ixDIDT_TCP_EDC_STALL_PATTERN_1_2                                                               0x00a5
13591 #define ixDIDT_TCP_EDC_STALL_PATTERN_3_4                                                               0x00a6
13592 #define ixDIDT_TCP_EDC_STALL_PATTERN_5_6                                                               0x00a7
13593 #define ixDIDT_TCP_EDC_STALL_PATTERN_7                                                                 0x00a8
13594 #define ixDIDT_TCP_EDC_TIMER_PERIOD                                                                    0x00a9
13595 #define ixDIDT_TCP_THROTTLE_CTRL                                                                       0x00aa
13596 #define ixDIDT_TCP_EDC_STALL_DELAY_1                                                                   0x00ab
13597 #define ixDIDT_TCP_EDC_STALL_DELAY_2                                                                   0x00ac
13598 #define ixDIDT_TCP_EDC_STALL_DELAY_3                                                                   0x00ad
13599 #define ixDIDT_TCP_EDC_STATUS                                                                          0x00af
13600 #define ixDIDT_TCP_EDC_OVERFLOW                                                                        0x00b0
13601 #define ixDIDT_TCP_EDC_ROLLING_POWER_DELTA                                                             0x00b1
13602 #define ixDIDT_TCP_EDC_PCC_PERF_COUNTER                                                                0x00b2
13603 #define ixDIDT_SQ_STALL_EVENT_COUNTER                                                                  0x00c0
13604 #define ixDIDT_DB_STALL_EVENT_COUNTER                                                                  0x00c1
13605 #define ixDIDT_TD_STALL_EVENT_COUNTER                                                                  0x00c2
13606 #define ixDIDT_TCP_STALL_EVENT_COUNTER                                                                 0x00c3
13607 
13608 
13609 #endif
13610