1/* 2 * New-style TCG opcode generator for i386 instructions 3 * 4 * Copyright (c) 2022 Red Hat, Inc. 5 * 6 * Author: Paolo Bonzini <pbonzini@redhat.com> 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2.1 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22/* 23 * Sometimes, knowing what the backend has can produce better code. 24 * The exact opcode to check depends on 32- vs. 64-bit. 25 */ 26#ifdef TARGET_X86_64 27#define INDEX_op_extract2_tl INDEX_op_extract2_i64 28#else 29#define INDEX_op_extract2_tl INDEX_op_extract2_i32 30#endif 31 32#define MMX_OFFSET(reg) \ 33 ({ assert((reg) >= 0 && (reg) <= 7); \ 34 offsetof(CPUX86State, fpregs[reg].mmx); }) 35 36#define ZMM_OFFSET(reg) \ 37 ({ assert((reg) >= 0 && (reg) <= 15); \ 38 offsetof(CPUX86State, xmm_regs[reg]); }) 39 40typedef void (*SSEFunc_i_ep)(TCGv_i32 val, TCGv_ptr env, TCGv_ptr reg); 41typedef void (*SSEFunc_l_ep)(TCGv_i64 val, TCGv_ptr env, TCGv_ptr reg); 42typedef void (*SSEFunc_0_epp)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b); 43typedef void (*SSEFunc_0_eppp)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, 44 TCGv_ptr reg_c); 45typedef void (*SSEFunc_0_epppp)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, 46 TCGv_ptr reg_c, TCGv_ptr reg_d); 47typedef void (*SSEFunc_0_eppi)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, 48 TCGv_i32 val); 49typedef void (*SSEFunc_0_epppi)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, 50 TCGv_ptr reg_c, TCGv_i32 val); 51typedef void (*SSEFunc_0_ppi)(TCGv_ptr reg_a, TCGv_ptr reg_b, TCGv_i32 val); 52typedef void (*SSEFunc_0_pppi)(TCGv_ptr reg_a, TCGv_ptr reg_b, TCGv_ptr reg_c, 53 TCGv_i32 val); 54typedef void (*SSEFunc_0_eppt)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, 55 TCGv val); 56typedef void (*SSEFunc_0_epppti)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, 57 TCGv_ptr reg_c, TCGv a0, TCGv_i32 scale); 58typedef void (*SSEFunc_0_eppppi)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, 59 TCGv_ptr reg_c, TCGv_ptr reg_d, TCGv_i32 flags); 60typedef void (*SSEFunc_0_eppppii)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b, 61 TCGv_ptr reg_c, TCGv_ptr reg_d, TCGv_i32 even, 62 TCGv_i32 odd); 63 64static void gen_JMP_m(DisasContext *s, X86DecodedInsn *decode); 65static void gen_JMP(DisasContext *s, X86DecodedInsn *decode); 66 67static inline TCGv_i32 tcg_constant8u_i32(uint8_t val) 68{ 69 return tcg_constant_i32(val); 70} 71 72static void gen_NM_exception(DisasContext *s) 73{ 74 gen_exception(s, EXCP07_PREX); 75} 76 77static void gen_lea_modrm(DisasContext *s, X86DecodedInsn *decode) 78{ 79 AddressParts *mem = &decode->mem; 80 TCGv ea; 81 82 ea = gen_lea_modrm_1(s, *mem, decode->e.vex_class == 12); 83 if (decode->e.special == X86_SPECIAL_BitTest) { 84 MemOp ot = decode->op[1].ot; 85 int poslen = 8 << ot; 86 int opn = decode->op[2].n; 87 TCGv ofs = tcg_temp_new(); 88 89 /* Extract memory displacement from the second operand. */ 90 assert(decode->op[2].unit == X86_OP_INT && decode->op[2].ot != MO_8); 91 tcg_gen_sextract_tl(ofs, cpu_regs[opn], 3, poslen - 3); 92 tcg_gen_andi_tl(ofs, ofs, -1 << ot); 93 tcg_gen_add_tl(s->A0, ea, ofs); 94 ea = s->A0; 95 } 96 97 gen_lea_v_seg(s, ea, mem->def_seg, s->override); 98} 99 100static inline int mmx_offset(MemOp ot) 101{ 102 switch (ot) { 103 case MO_8: 104 return offsetof(MMXReg, MMX_B(0)); 105 case MO_16: 106 return offsetof(MMXReg, MMX_W(0)); 107 case MO_32: 108 return offsetof(MMXReg, MMX_L(0)); 109 case MO_64: 110 return offsetof(MMXReg, MMX_Q(0)); 111 default: 112 g_assert_not_reached(); 113 } 114} 115 116static inline int xmm_offset(MemOp ot) 117{ 118 switch (ot) { 119 case MO_8: 120 return offsetof(ZMMReg, ZMM_B(0)); 121 case MO_16: 122 return offsetof(ZMMReg, ZMM_W(0)); 123 case MO_32: 124 return offsetof(ZMMReg, ZMM_L(0)); 125 case MO_64: 126 return offsetof(ZMMReg, ZMM_Q(0)); 127 case MO_128: 128 return offsetof(ZMMReg, ZMM_X(0)); 129 case MO_256: 130 return offsetof(ZMMReg, ZMM_Y(0)); 131 default: 132 g_assert_not_reached(); 133 } 134} 135 136static int vector_reg_offset(X86DecodedOp *op) 137{ 138 assert(op->unit == X86_OP_MMX || op->unit == X86_OP_SSE); 139 140 if (op->unit == X86_OP_MMX) { 141 return op->offset - mmx_offset(op->ot); 142 } else { 143 return op->offset - xmm_offset(op->ot); 144 } 145} 146 147static int vector_elem_offset(X86DecodedOp *op, MemOp ot, int n) 148{ 149 int base_ofs = vector_reg_offset(op); 150 switch(ot) { 151 case MO_8: 152 if (op->unit == X86_OP_MMX) { 153 return base_ofs + offsetof(MMXReg, MMX_B(n)); 154 } else { 155 return base_ofs + offsetof(ZMMReg, ZMM_B(n)); 156 } 157 case MO_16: 158 if (op->unit == X86_OP_MMX) { 159 return base_ofs + offsetof(MMXReg, MMX_W(n)); 160 } else { 161 return base_ofs + offsetof(ZMMReg, ZMM_W(n)); 162 } 163 case MO_32: 164 if (op->unit == X86_OP_MMX) { 165 return base_ofs + offsetof(MMXReg, MMX_L(n)); 166 } else { 167 return base_ofs + offsetof(ZMMReg, ZMM_L(n)); 168 } 169 case MO_64: 170 if (op->unit == X86_OP_MMX) { 171 return base_ofs; 172 } else { 173 return base_ofs + offsetof(ZMMReg, ZMM_Q(n)); 174 } 175 case MO_128: 176 assert(op->unit == X86_OP_SSE); 177 return base_ofs + offsetof(ZMMReg, ZMM_X(n)); 178 case MO_256: 179 assert(op->unit == X86_OP_SSE); 180 return base_ofs + offsetof(ZMMReg, ZMM_Y(n)); 181 default: 182 g_assert_not_reached(); 183 } 184} 185 186static void compute_mmx_offset(X86DecodedOp *op) 187{ 188 if (!op->has_ea) { 189 op->offset = MMX_OFFSET(op->n) + mmx_offset(op->ot); 190 } else { 191 op->offset = offsetof(CPUX86State, mmx_t0) + mmx_offset(op->ot); 192 } 193} 194 195static void compute_xmm_offset(X86DecodedOp *op) 196{ 197 if (!op->has_ea) { 198 op->offset = ZMM_OFFSET(op->n) + xmm_offset(op->ot); 199 } else { 200 op->offset = offsetof(CPUX86State, xmm_t0) + xmm_offset(op->ot); 201 } 202} 203 204static void gen_load_sse(DisasContext *s, TCGv temp, MemOp ot, int dest_ofs, bool aligned) 205{ 206 switch(ot) { 207 case MO_8: 208 gen_op_ld_v(s, MO_8, temp, s->A0); 209 tcg_gen_st8_tl(temp, tcg_env, dest_ofs); 210 break; 211 case MO_16: 212 gen_op_ld_v(s, MO_16, temp, s->A0); 213 tcg_gen_st16_tl(temp, tcg_env, dest_ofs); 214 break; 215 case MO_32: 216 gen_op_ld_v(s, MO_32, temp, s->A0); 217 tcg_gen_st32_tl(temp, tcg_env, dest_ofs); 218 break; 219 case MO_64: 220 gen_ldq_env_A0(s, dest_ofs); 221 break; 222 case MO_128: 223 gen_ldo_env_A0(s, dest_ofs, aligned); 224 break; 225 case MO_256: 226 gen_ldy_env_A0(s, dest_ofs, aligned); 227 break; 228 default: 229 g_assert_not_reached(); 230 } 231} 232 233static bool sse_needs_alignment(DisasContext *s, X86DecodedInsn *decode, MemOp ot) 234{ 235 switch (decode->e.vex_class) { 236 case 2: 237 case 4: 238 if ((s->prefix & PREFIX_VEX) || 239 decode->e.vex_special == X86_VEX_SSEUnaligned) { 240 /* MOST legacy SSE instructions require aligned memory operands, but not all. */ 241 return false; 242 } 243 /* fall through */ 244 case 1: 245 return ot >= MO_128; 246 247 default: 248 return false; 249 } 250} 251 252static void gen_load(DisasContext *s, X86DecodedInsn *decode, int opn, TCGv v) 253{ 254 X86DecodedOp *op = &decode->op[opn]; 255 256 switch (op->unit) { 257 case X86_OP_SKIP: 258 return; 259 case X86_OP_SEG: 260 tcg_gen_ld32u_tl(v, tcg_env, 261 offsetof(CPUX86State,segs[op->n].selector)); 262 break; 263#ifndef CONFIG_USER_ONLY 264 case X86_OP_CR: 265 if (op->n == 8) { 266 translator_io_start(&s->base); 267 gen_helper_read_cr8(v, tcg_env); 268 } else { 269 tcg_gen_ld_tl(v, tcg_env, offsetof(CPUX86State, cr[op->n])); 270 } 271 break; 272 case X86_OP_DR: 273 /* CR4.DE tested in the helper. */ 274 gen_helper_get_dr(v, tcg_env, tcg_constant_i32(op->n)); 275 break; 276#endif 277 case X86_OP_INT: 278 if (op->has_ea) { 279 if (v == s->T0 && decode->e.special == X86_SPECIAL_SExtT0) { 280 gen_op_ld_v(s, op->ot | MO_SIGN, v, s->A0); 281 } else { 282 gen_op_ld_v(s, op->ot, v, s->A0); 283 } 284 285 } else if (op->ot < MO_TL && v == s->T0 && 286 (decode->e.special == X86_SPECIAL_SExtT0 || 287 decode->e.special == X86_SPECIAL_ZExtT0)) { 288 if (op->ot == MO_8 && byte_reg_is_xH(s, op->n)) { 289 if (decode->e.special == X86_SPECIAL_SExtT0) { 290 tcg_gen_sextract_tl(v, cpu_regs[op->n - 4], 8, 8); 291 } else { 292 tcg_gen_extract_tl(v, cpu_regs[op->n - 4], 8, 8); 293 } 294 } else { 295 if (decode->e.special == X86_SPECIAL_SExtT0) { 296 tcg_gen_ext_tl(v, cpu_regs[op->n], op->ot | MO_SIGN); 297 } else { 298 tcg_gen_ext_tl(v, cpu_regs[op->n], op->ot); 299 } 300 } 301 302 } else { 303 gen_op_mov_v_reg(s, op->ot, v, op->n); 304 } 305 break; 306 case X86_OP_IMM: 307 tcg_gen_movi_tl(v, op->imm); 308 break; 309 310 case X86_OP_MMX: 311 compute_mmx_offset(op); 312 goto load_vector; 313 314 case X86_OP_SSE: 315 compute_xmm_offset(op); 316 load_vector: 317 if (op->has_ea) { 318 bool aligned = sse_needs_alignment(s, decode, op->ot); 319 gen_load_sse(s, v, op->ot, op->offset, aligned); 320 } 321 break; 322 323 default: 324 g_assert_not_reached(); 325 } 326} 327 328static TCGv_ptr op_ptr(X86DecodedInsn *decode, int opn) 329{ 330 X86DecodedOp *op = &decode->op[opn]; 331 332 assert(op->unit == X86_OP_MMX || op->unit == X86_OP_SSE); 333 if (op->v_ptr) { 334 return op->v_ptr; 335 } 336 op->v_ptr = tcg_temp_new_ptr(); 337 338 /* The temporary points to the MMXReg or ZMMReg. */ 339 tcg_gen_addi_ptr(op->v_ptr, tcg_env, vector_reg_offset(op)); 340 return op->v_ptr; 341} 342 343#define OP_PTR0 op_ptr(decode, 0) 344#define OP_PTR1 op_ptr(decode, 1) 345#define OP_PTR2 op_ptr(decode, 2) 346 347static void gen_writeback(DisasContext *s, X86DecodedInsn *decode, int opn, TCGv v) 348{ 349 X86DecodedOp *op = &decode->op[opn]; 350 switch (op->unit) { 351 case X86_OP_SKIP: 352 break; 353 case X86_OP_SEG: 354 /* Note that gen_movl_seg takes care of interrupt shadow and TF. */ 355 gen_movl_seg(s, op->n, v, op->n == R_SS); 356 break; 357 case X86_OP_INT: 358 if (op->has_ea) { 359 gen_op_st_v(s, op->ot, v, s->A0); 360 } else { 361 gen_op_mov_reg_v(s, op->ot, op->n, v); 362 } 363 break; 364 case X86_OP_MMX: 365 break; 366 case X86_OP_SSE: 367 if (!op->has_ea && (s->prefix & PREFIX_VEX) && op->ot <= MO_128) { 368 tcg_gen_gvec_dup_imm(MO_64, 369 offsetof(CPUX86State, xmm_regs[op->n].ZMM_X(1)), 370 16, 16, 0); 371 } 372 break; 373#ifndef CONFIG_USER_ONLY 374 case X86_OP_CR: 375 if (op->n == 8) { 376 translator_io_start(&s->base); 377 } 378 gen_helper_write_crN(tcg_env, tcg_constant_i32(op->n), v); 379 s->base.is_jmp = DISAS_EOB_NEXT; 380 break; 381 case X86_OP_DR: 382 /* CR4.DE tested in the helper. */ 383 gen_helper_set_dr(tcg_env, tcg_constant_i32(op->n), v); 384 s->base.is_jmp = DISAS_EOB_NEXT; 385 break; 386#endif 387 default: 388 g_assert_not_reached(); 389 } 390 op->unit = X86_OP_SKIP; 391} 392 393static inline int vector_len(DisasContext *s, X86DecodedInsn *decode) 394{ 395 if (decode->e.special == X86_SPECIAL_MMX && 396 !(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) { 397 return 8; 398 } 399 return s->vex_l ? 32 : 16; 400} 401 402static void prepare_update1_cc(X86DecodedInsn *decode, DisasContext *s, CCOp op) 403{ 404 decode->cc_dst = s->T0; 405 decode->cc_op = op; 406} 407 408static void prepare_update2_cc(X86DecodedInsn *decode, DisasContext *s, CCOp op) 409{ 410 decode->cc_src = s->T1; 411 decode->cc_dst = s->T0; 412 decode->cc_op = op; 413} 414 415static void prepare_update_cc_incdec(X86DecodedInsn *decode, DisasContext *s, CCOp op) 416{ 417 gen_compute_eflags_c(s, s->T1); 418 prepare_update2_cc(decode, s, op); 419} 420 421static void prepare_update3_cc(X86DecodedInsn *decode, DisasContext *s, CCOp op, TCGv reg) 422{ 423 decode->cc_src2 = reg; 424 decode->cc_src = s->T1; 425 decode->cc_dst = s->T0; 426 decode->cc_op = op; 427} 428 429/* Set up decode->cc_* to modify CF while keeping other flags unchanged. */ 430static void prepare_update_cf(X86DecodedInsn *decode, DisasContext *s, TCGv cf) 431{ 432 switch (s->cc_op) { 433 case CC_OP_ADOX: 434 case CC_OP_ADCOX: 435 decode->cc_src2 = cpu_cc_src2; 436 decode->cc_src = cpu_cc_src; 437 decode->cc_op = CC_OP_ADCOX; 438 break; 439 440 case CC_OP_EFLAGS: 441 case CC_OP_ADCX: 442 decode->cc_src = cpu_cc_src; 443 decode->cc_op = CC_OP_ADCX; 444 break; 445 446 default: 447 decode->cc_src = tcg_temp_new(); 448 gen_mov_eflags(s, decode->cc_src); 449 decode->cc_op = CC_OP_ADCX; 450 break; 451 } 452 decode->cc_dst = cf; 453} 454 455static void gen_store_sse(DisasContext *s, X86DecodedInsn *decode, int src_ofs) 456{ 457 MemOp ot = decode->op[0].ot; 458 int vec_len = vector_len(s, decode); 459 bool aligned = sse_needs_alignment(s, decode, ot); 460 461 if (!decode->op[0].has_ea) { 462 tcg_gen_gvec_mov(MO_64, decode->op[0].offset, src_ofs, vec_len, vec_len); 463 return; 464 } 465 466 switch (ot) { 467 case MO_64: 468 gen_stq_env_A0(s, src_ofs); 469 break; 470 case MO_128: 471 gen_sto_env_A0(s, src_ofs, aligned); 472 break; 473 case MO_256: 474 gen_sty_env_A0(s, src_ofs, aligned); 475 break; 476 default: 477 g_assert_not_reached(); 478 } 479} 480 481static void gen_helper_pavgusb(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b) 482{ 483 gen_helper_pavgb_mmx(env, reg_a, reg_a, reg_b); 484} 485 486#define FN_3DNOW_MOVE ((SSEFunc_0_epp) (uintptr_t) 1) 487static const SSEFunc_0_epp fns_3dnow[] = { 488 [0x0c] = gen_helper_pi2fw, 489 [0x0d] = gen_helper_pi2fd, 490 [0x1c] = gen_helper_pf2iw, 491 [0x1d] = gen_helper_pf2id, 492 [0x8a] = gen_helper_pfnacc, 493 [0x8e] = gen_helper_pfpnacc, 494 [0x90] = gen_helper_pfcmpge, 495 [0x94] = gen_helper_pfmin, 496 [0x96] = gen_helper_pfrcp, 497 [0x97] = gen_helper_pfrsqrt, 498 [0x9a] = gen_helper_pfsub, 499 [0x9e] = gen_helper_pfadd, 500 [0xa0] = gen_helper_pfcmpgt, 501 [0xa4] = gen_helper_pfmax, 502 [0xa6] = FN_3DNOW_MOVE, /* PFRCPIT1; no need to actually increase precision */ 503 [0xa7] = FN_3DNOW_MOVE, /* PFRSQIT1 */ 504 [0xb6] = FN_3DNOW_MOVE, /* PFRCPIT2 */ 505 [0xaa] = gen_helper_pfsubr, 506 [0xae] = gen_helper_pfacc, 507 [0xb0] = gen_helper_pfcmpeq, 508 [0xb4] = gen_helper_pfmul, 509 [0xb7] = gen_helper_pmulhrw_mmx, 510 [0xbb] = gen_helper_pswapd, 511 [0xbf] = gen_helper_pavgusb, 512}; 513 514static void gen_3dnow(DisasContext *s, X86DecodedInsn *decode) 515{ 516 uint8_t b = decode->immediate; 517 SSEFunc_0_epp fn = b < ARRAY_SIZE(fns_3dnow) ? fns_3dnow[b] : NULL; 518 519 if (!fn) { 520 gen_illegal_opcode(s); 521 return; 522 } 523 if (s->flags & HF_TS_MASK) { 524 gen_NM_exception(s); 525 return; 526 } 527 if (s->flags & HF_EM_MASK) { 528 gen_illegal_opcode(s); 529 return; 530 } 531 532 gen_helper_enter_mmx(tcg_env); 533 if (fn == FN_3DNOW_MOVE) { 534 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset); 535 tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset); 536 } else { 537 fn(tcg_env, OP_PTR0, OP_PTR1); 538 } 539} 540 541/* 542 * 00 = v*ps Vps, Hps, Wpd 543 * 66 = v*pd Vpd, Hpd, Wps 544 * f3 = v*ss Vss, Hss, Wps 545 * f2 = v*sd Vsd, Hsd, Wps 546 */ 547static inline void gen_unary_fp_sse(DisasContext *s, X86DecodedInsn *decode, 548 SSEFunc_0_epp pd_xmm, SSEFunc_0_epp ps_xmm, 549 SSEFunc_0_epp pd_ymm, SSEFunc_0_epp ps_ymm, 550 SSEFunc_0_eppp sd, SSEFunc_0_eppp ss) 551{ 552 if ((s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) { 553 SSEFunc_0_eppp fn = s->prefix & PREFIX_REPZ ? ss : sd; 554 if (!fn) { 555 gen_illegal_opcode(s); 556 return; 557 } 558 fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 559 } else { 560 SSEFunc_0_epp ps, pd, fn; 561 ps = s->vex_l ? ps_ymm : ps_xmm; 562 pd = s->vex_l ? pd_ymm : pd_xmm; 563 fn = s->prefix & PREFIX_DATA ? pd : ps; 564 if (!fn) { 565 gen_illegal_opcode(s); 566 return; 567 } 568 fn(tcg_env, OP_PTR0, OP_PTR2); 569 } 570} 571#define UNARY_FP_SSE(uname, lname) \ 572static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 573{ \ 574 gen_unary_fp_sse(s, decode, \ 575 gen_helper_##lname##pd_xmm, \ 576 gen_helper_##lname##ps_xmm, \ 577 gen_helper_##lname##pd_ymm, \ 578 gen_helper_##lname##ps_ymm, \ 579 gen_helper_##lname##sd, \ 580 gen_helper_##lname##ss); \ 581} 582UNARY_FP_SSE(VSQRT, sqrt) 583 584/* 585 * 00 = v*ps Vps, Hps, Wpd 586 * 66 = v*pd Vpd, Hpd, Wps 587 * f3 = v*ss Vss, Hss, Wps 588 * f2 = v*sd Vsd, Hsd, Wps 589 */ 590static inline void gen_fp_sse(DisasContext *s, X86DecodedInsn *decode, 591 SSEFunc_0_eppp pd_xmm, SSEFunc_0_eppp ps_xmm, 592 SSEFunc_0_eppp pd_ymm, SSEFunc_0_eppp ps_ymm, 593 SSEFunc_0_eppp sd, SSEFunc_0_eppp ss) 594{ 595 SSEFunc_0_eppp ps, pd, fn; 596 if ((s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) { 597 fn = s->prefix & PREFIX_REPZ ? ss : sd; 598 } else { 599 ps = s->vex_l ? ps_ymm : ps_xmm; 600 pd = s->vex_l ? pd_ymm : pd_xmm; 601 fn = s->prefix & PREFIX_DATA ? pd : ps; 602 } 603 if (fn) { 604 fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 605 } else { 606 gen_illegal_opcode(s); 607 } 608} 609 610#define FP_SSE(uname, lname) \ 611static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 612{ \ 613 gen_fp_sse(s, decode, \ 614 gen_helper_##lname##pd_xmm, \ 615 gen_helper_##lname##ps_xmm, \ 616 gen_helper_##lname##pd_ymm, \ 617 gen_helper_##lname##ps_ymm, \ 618 gen_helper_##lname##sd, \ 619 gen_helper_##lname##ss); \ 620} 621FP_SSE(VADD, add) 622FP_SSE(VMUL, mul) 623FP_SSE(VSUB, sub) 624FP_SSE(VMIN, min) 625FP_SSE(VDIV, div) 626FP_SSE(VMAX, max) 627 628#define FMA_SSE_PACKED(uname, ptr0, ptr1, ptr2, even, odd) \ 629static void gen_##uname##Px(DisasContext *s, X86DecodedInsn *decode) \ 630{ \ 631 SSEFunc_0_eppppii xmm = s->vex_w ? gen_helper_fma4pd_xmm : gen_helper_fma4ps_xmm; \ 632 SSEFunc_0_eppppii ymm = s->vex_w ? gen_helper_fma4pd_ymm : gen_helper_fma4ps_ymm; \ 633 SSEFunc_0_eppppii fn = s->vex_l ? ymm : xmm; \ 634 \ 635 fn(tcg_env, OP_PTR0, ptr0, ptr1, ptr2, \ 636 tcg_constant_i32(even), \ 637 tcg_constant_i32((even) ^ (odd))); \ 638} 639 640#define FMA_SSE(uname, ptr0, ptr1, ptr2, flags) \ 641FMA_SSE_PACKED(uname, ptr0, ptr1, ptr2, flags, flags) \ 642static void gen_##uname##Sx(DisasContext *s, X86DecodedInsn *decode) \ 643{ \ 644 SSEFunc_0_eppppi fn = s->vex_w ? gen_helper_fma4sd : gen_helper_fma4ss; \ 645 \ 646 fn(tcg_env, OP_PTR0, ptr0, ptr1, ptr2, \ 647 tcg_constant_i32(flags)); \ 648} \ 649 650FMA_SSE(VFMADD231, OP_PTR1, OP_PTR2, OP_PTR0, 0) 651FMA_SSE(VFMADD213, OP_PTR1, OP_PTR0, OP_PTR2, 0) 652FMA_SSE(VFMADD132, OP_PTR0, OP_PTR2, OP_PTR1, 0) 653 654FMA_SSE(VFNMADD231, OP_PTR1, OP_PTR2, OP_PTR0, float_muladd_negate_product) 655FMA_SSE(VFNMADD213, OP_PTR1, OP_PTR0, OP_PTR2, float_muladd_negate_product) 656FMA_SSE(VFNMADD132, OP_PTR0, OP_PTR2, OP_PTR1, float_muladd_negate_product) 657 658FMA_SSE(VFMSUB231, OP_PTR1, OP_PTR2, OP_PTR0, float_muladd_negate_c) 659FMA_SSE(VFMSUB213, OP_PTR1, OP_PTR0, OP_PTR2, float_muladd_negate_c) 660FMA_SSE(VFMSUB132, OP_PTR0, OP_PTR2, OP_PTR1, float_muladd_negate_c) 661 662FMA_SSE(VFNMSUB231, OP_PTR1, OP_PTR2, OP_PTR0, float_muladd_negate_c|float_muladd_negate_product) 663FMA_SSE(VFNMSUB213, OP_PTR1, OP_PTR0, OP_PTR2, float_muladd_negate_c|float_muladd_negate_product) 664FMA_SSE(VFNMSUB132, OP_PTR0, OP_PTR2, OP_PTR1, float_muladd_negate_c|float_muladd_negate_product) 665 666FMA_SSE_PACKED(VFMADDSUB231, OP_PTR1, OP_PTR2, OP_PTR0, float_muladd_negate_c, 0) 667FMA_SSE_PACKED(VFMADDSUB213, OP_PTR1, OP_PTR0, OP_PTR2, float_muladd_negate_c, 0) 668FMA_SSE_PACKED(VFMADDSUB132, OP_PTR0, OP_PTR2, OP_PTR1, float_muladd_negate_c, 0) 669 670FMA_SSE_PACKED(VFMSUBADD231, OP_PTR1, OP_PTR2, OP_PTR0, 0, float_muladd_negate_c) 671FMA_SSE_PACKED(VFMSUBADD213, OP_PTR1, OP_PTR0, OP_PTR2, 0, float_muladd_negate_c) 672FMA_SSE_PACKED(VFMSUBADD132, OP_PTR0, OP_PTR2, OP_PTR1, 0, float_muladd_negate_c) 673 674#define FP_UNPACK_SSE(uname, lname) \ 675static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 676{ \ 677 /* PS maps to the DQ integer instruction, PD maps to QDQ. */ \ 678 gen_fp_sse(s, decode, \ 679 gen_helper_##lname##qdq_xmm, \ 680 gen_helper_##lname##dq_xmm, \ 681 gen_helper_##lname##qdq_ymm, \ 682 gen_helper_##lname##dq_ymm, \ 683 NULL, NULL); \ 684} 685FP_UNPACK_SSE(VUNPCKLPx, punpckl) 686FP_UNPACK_SSE(VUNPCKHPx, punpckh) 687 688/* 689 * 00 = v*ps Vps, Wpd 690 * f3 = v*ss Vss, Wps 691 */ 692static inline void gen_unary_fp32_sse(DisasContext *s, X86DecodedInsn *decode, 693 SSEFunc_0_epp ps_xmm, 694 SSEFunc_0_epp ps_ymm, 695 SSEFunc_0_eppp ss) 696{ 697 if ((s->prefix & (PREFIX_DATA | PREFIX_REPNZ)) != 0) { 698 goto illegal_op; 699 } else if (s->prefix & PREFIX_REPZ) { 700 if (!ss) { 701 goto illegal_op; 702 } 703 ss(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 704 } else { 705 SSEFunc_0_epp fn = s->vex_l ? ps_ymm : ps_xmm; 706 if (!fn) { 707 goto illegal_op; 708 } 709 fn(tcg_env, OP_PTR0, OP_PTR2); 710 } 711 return; 712 713illegal_op: 714 gen_illegal_opcode(s); 715} 716#define UNARY_FP32_SSE(uname, lname) \ 717static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 718{ \ 719 gen_unary_fp32_sse(s, decode, \ 720 gen_helper_##lname##ps_xmm, \ 721 gen_helper_##lname##ps_ymm, \ 722 gen_helper_##lname##ss); \ 723} 724UNARY_FP32_SSE(VRSQRT, rsqrt) 725UNARY_FP32_SSE(VRCP, rcp) 726 727/* 728 * 66 = v*pd Vpd, Hpd, Wpd 729 * f2 = v*ps Vps, Hps, Wps 730 */ 731static inline void gen_horizontal_fp_sse(DisasContext *s, X86DecodedInsn *decode, 732 SSEFunc_0_eppp pd_xmm, SSEFunc_0_eppp ps_xmm, 733 SSEFunc_0_eppp pd_ymm, SSEFunc_0_eppp ps_ymm) 734{ 735 SSEFunc_0_eppp ps, pd, fn; 736 ps = s->vex_l ? ps_ymm : ps_xmm; 737 pd = s->vex_l ? pd_ymm : pd_xmm; 738 fn = s->prefix & PREFIX_DATA ? pd : ps; 739 fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 740} 741#define HORIZONTAL_FP_SSE(uname, lname) \ 742static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 743{ \ 744 gen_horizontal_fp_sse(s, decode, \ 745 gen_helper_##lname##pd_xmm, gen_helper_##lname##ps_xmm, \ 746 gen_helper_##lname##pd_ymm, gen_helper_##lname##ps_ymm); \ 747} 748HORIZONTAL_FP_SSE(VHADD, hadd) 749HORIZONTAL_FP_SSE(VHSUB, hsub) 750HORIZONTAL_FP_SSE(VADDSUB, addsub) 751 752static inline void gen_ternary_sse(DisasContext *s, X86DecodedInsn *decode, 753 int op3, SSEFunc_0_epppp xmm, SSEFunc_0_epppp ymm) 754{ 755 SSEFunc_0_epppp fn = s->vex_l ? ymm : xmm; 756 TCGv_ptr ptr3 = tcg_temp_new_ptr(); 757 758 /* The format of the fourth input is Lx */ 759 tcg_gen_addi_ptr(ptr3, tcg_env, ZMM_OFFSET(op3)); 760 fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, ptr3); 761} 762#define TERNARY_SSE(uname, uvname, lname) \ 763static void gen_##uvname(DisasContext *s, X86DecodedInsn *decode) \ 764{ \ 765 gen_ternary_sse(s, decode, (uint8_t)decode->immediate >> 4, \ 766 gen_helper_##lname##_xmm, gen_helper_##lname##_ymm); \ 767} \ 768static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 769{ \ 770 gen_ternary_sse(s, decode, 0, \ 771 gen_helper_##lname##_xmm, gen_helper_##lname##_ymm); \ 772} 773TERNARY_SSE(BLENDVPS, VBLENDVPS, blendvps) 774TERNARY_SSE(BLENDVPD, VBLENDVPD, blendvpd) 775TERNARY_SSE(PBLENDVB, VPBLENDVB, pblendvb) 776 777static inline void gen_binary_imm_sse(DisasContext *s, X86DecodedInsn *decode, 778 SSEFunc_0_epppi xmm, SSEFunc_0_epppi ymm) 779{ 780 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 781 if (!s->vex_l) { 782 xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); 783 } else { 784 ymm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); 785 } 786} 787 788#define BINARY_IMM_SSE(uname, lname) \ 789static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 790{ \ 791 gen_binary_imm_sse(s, decode, \ 792 gen_helper_##lname##_xmm, \ 793 gen_helper_##lname##_ymm); \ 794} 795 796BINARY_IMM_SSE(VBLENDPD, blendpd) 797BINARY_IMM_SSE(VBLENDPS, blendps) 798BINARY_IMM_SSE(VPBLENDW, pblendw) 799BINARY_IMM_SSE(VDDPS, dpps) 800#define gen_helper_dppd_ymm NULL 801BINARY_IMM_SSE(VDDPD, dppd) 802BINARY_IMM_SSE(VMPSADBW, mpsadbw) 803BINARY_IMM_SSE(PCLMULQDQ, pclmulqdq) 804 805 806#define UNARY_INT_GVEC(uname, func, ...) \ 807static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 808{ \ 809 int vec_len = vector_len(s, decode); \ 810 \ 811 func(__VA_ARGS__, decode->op[0].offset, \ 812 decode->op[2].offset, vec_len, vec_len); \ 813} 814UNARY_INT_GVEC(PABSB, tcg_gen_gvec_abs, MO_8) 815UNARY_INT_GVEC(PABSW, tcg_gen_gvec_abs, MO_16) 816UNARY_INT_GVEC(PABSD, tcg_gen_gvec_abs, MO_32) 817UNARY_INT_GVEC(VBROADCASTx128, tcg_gen_gvec_dup_mem, MO_128) 818UNARY_INT_GVEC(VPBROADCASTB, tcg_gen_gvec_dup_mem, MO_8) 819UNARY_INT_GVEC(VPBROADCASTW, tcg_gen_gvec_dup_mem, MO_16) 820UNARY_INT_GVEC(VPBROADCASTD, tcg_gen_gvec_dup_mem, MO_32) 821UNARY_INT_GVEC(VPBROADCASTQ, tcg_gen_gvec_dup_mem, MO_64) 822 823 824#define BINARY_INT_GVEC(uname, func, ...) \ 825static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 826{ \ 827 int vec_len = vector_len(s, decode); \ 828 \ 829 func(__VA_ARGS__, \ 830 decode->op[0].offset, decode->op[1].offset, \ 831 decode->op[2].offset, vec_len, vec_len); \ 832} 833 834BINARY_INT_GVEC(PADDB, tcg_gen_gvec_add, MO_8) 835BINARY_INT_GVEC(PADDW, tcg_gen_gvec_add, MO_16) 836BINARY_INT_GVEC(PADDD, tcg_gen_gvec_add, MO_32) 837BINARY_INT_GVEC(PADDQ, tcg_gen_gvec_add, MO_64) 838BINARY_INT_GVEC(PADDSB, tcg_gen_gvec_ssadd, MO_8) 839BINARY_INT_GVEC(PADDSW, tcg_gen_gvec_ssadd, MO_16) 840BINARY_INT_GVEC(PADDUSB, tcg_gen_gvec_usadd, MO_8) 841BINARY_INT_GVEC(PADDUSW, tcg_gen_gvec_usadd, MO_16) 842BINARY_INT_GVEC(PAND, tcg_gen_gvec_and, MO_64) 843BINARY_INT_GVEC(PCMPEQB, tcg_gen_gvec_cmp, TCG_COND_EQ, MO_8) 844BINARY_INT_GVEC(PCMPEQD, tcg_gen_gvec_cmp, TCG_COND_EQ, MO_32) 845BINARY_INT_GVEC(PCMPEQW, tcg_gen_gvec_cmp, TCG_COND_EQ, MO_16) 846BINARY_INT_GVEC(PCMPEQQ, tcg_gen_gvec_cmp, TCG_COND_EQ, MO_64) 847BINARY_INT_GVEC(PCMPGTB, tcg_gen_gvec_cmp, TCG_COND_GT, MO_8) 848BINARY_INT_GVEC(PCMPGTW, tcg_gen_gvec_cmp, TCG_COND_GT, MO_16) 849BINARY_INT_GVEC(PCMPGTD, tcg_gen_gvec_cmp, TCG_COND_GT, MO_32) 850BINARY_INT_GVEC(PCMPGTQ, tcg_gen_gvec_cmp, TCG_COND_GT, MO_64) 851BINARY_INT_GVEC(PMAXSB, tcg_gen_gvec_smax, MO_8) 852BINARY_INT_GVEC(PMAXSW, tcg_gen_gvec_smax, MO_16) 853BINARY_INT_GVEC(PMAXSD, tcg_gen_gvec_smax, MO_32) 854BINARY_INT_GVEC(PMAXUB, tcg_gen_gvec_umax, MO_8) 855BINARY_INT_GVEC(PMAXUW, tcg_gen_gvec_umax, MO_16) 856BINARY_INT_GVEC(PMAXUD, tcg_gen_gvec_umax, MO_32) 857BINARY_INT_GVEC(PMINSB, tcg_gen_gvec_smin, MO_8) 858BINARY_INT_GVEC(PMINSW, tcg_gen_gvec_smin, MO_16) 859BINARY_INT_GVEC(PMINSD, tcg_gen_gvec_smin, MO_32) 860BINARY_INT_GVEC(PMINUB, tcg_gen_gvec_umin, MO_8) 861BINARY_INT_GVEC(PMINUW, tcg_gen_gvec_umin, MO_16) 862BINARY_INT_GVEC(PMINUD, tcg_gen_gvec_umin, MO_32) 863BINARY_INT_GVEC(PMULLW, tcg_gen_gvec_mul, MO_16) 864BINARY_INT_GVEC(PMULLD, tcg_gen_gvec_mul, MO_32) 865BINARY_INT_GVEC(POR, tcg_gen_gvec_or, MO_64) 866BINARY_INT_GVEC(PSUBB, tcg_gen_gvec_sub, MO_8) 867BINARY_INT_GVEC(PSUBW, tcg_gen_gvec_sub, MO_16) 868BINARY_INT_GVEC(PSUBD, tcg_gen_gvec_sub, MO_32) 869BINARY_INT_GVEC(PSUBQ, tcg_gen_gvec_sub, MO_64) 870BINARY_INT_GVEC(PSUBSB, tcg_gen_gvec_sssub, MO_8) 871BINARY_INT_GVEC(PSUBSW, tcg_gen_gvec_sssub, MO_16) 872BINARY_INT_GVEC(PSUBUSB, tcg_gen_gvec_ussub, MO_8) 873BINARY_INT_GVEC(PSUBUSW, tcg_gen_gvec_ussub, MO_16) 874BINARY_INT_GVEC(PXOR, tcg_gen_gvec_xor, MO_64) 875 876 877/* 878 * 00 = p* Pq, Qq (if mmx not NULL; no VEX) 879 * 66 = vp* Vx, Hx, Wx 880 * 881 * These are really the same encoding, because 1) V is the same as P when VEX.V 882 * is not present 2) P and Q are the same as H and W apart from MM/XMM 883 */ 884static inline void gen_binary_int_sse(DisasContext *s, X86DecodedInsn *decode, 885 SSEFunc_0_eppp mmx, SSEFunc_0_eppp xmm, SSEFunc_0_eppp ymm) 886{ 887 assert(!!mmx == !!(decode->e.special == X86_SPECIAL_MMX)); 888 889 if (mmx && (s->prefix & PREFIX_VEX) && !(s->prefix & PREFIX_DATA)) { 890 /* VEX encoding is not applicable to MMX instructions. */ 891 gen_illegal_opcode(s); 892 return; 893 } 894 if (!(s->prefix & PREFIX_DATA)) { 895 mmx(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 896 } else if (!s->vex_l) { 897 xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 898 } else { 899 ymm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 900 } 901} 902 903 904#define BINARY_INT_MMX(uname, lname) \ 905static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 906{ \ 907 gen_binary_int_sse(s, decode, \ 908 gen_helper_##lname##_mmx, \ 909 gen_helper_##lname##_xmm, \ 910 gen_helper_##lname##_ymm); \ 911} 912BINARY_INT_MMX(PUNPCKLBW, punpcklbw) 913BINARY_INT_MMX(PUNPCKLWD, punpcklwd) 914BINARY_INT_MMX(PUNPCKLDQ, punpckldq) 915BINARY_INT_MMX(PACKSSWB, packsswb) 916BINARY_INT_MMX(PACKUSWB, packuswb) 917BINARY_INT_MMX(PUNPCKHBW, punpckhbw) 918BINARY_INT_MMX(PUNPCKHWD, punpckhwd) 919BINARY_INT_MMX(PUNPCKHDQ, punpckhdq) 920BINARY_INT_MMX(PACKSSDW, packssdw) 921 922BINARY_INT_MMX(PAVGB, pavgb) 923BINARY_INT_MMX(PAVGW, pavgw) 924BINARY_INT_MMX(PMADDWD, pmaddwd) 925BINARY_INT_MMX(PMULHUW, pmulhuw) 926BINARY_INT_MMX(PMULHW, pmulhw) 927BINARY_INT_MMX(PMULUDQ, pmuludq) 928BINARY_INT_MMX(PSADBW, psadbw) 929 930BINARY_INT_MMX(PSLLW_r, psllw) 931BINARY_INT_MMX(PSLLD_r, pslld) 932BINARY_INT_MMX(PSLLQ_r, psllq) 933BINARY_INT_MMX(PSRLW_r, psrlw) 934BINARY_INT_MMX(PSRLD_r, psrld) 935BINARY_INT_MMX(PSRLQ_r, psrlq) 936BINARY_INT_MMX(PSRAW_r, psraw) 937BINARY_INT_MMX(PSRAD_r, psrad) 938 939BINARY_INT_MMX(PHADDW, phaddw) 940BINARY_INT_MMX(PHADDSW, phaddsw) 941BINARY_INT_MMX(PHADDD, phaddd) 942BINARY_INT_MMX(PHSUBW, phsubw) 943BINARY_INT_MMX(PHSUBSW, phsubsw) 944BINARY_INT_MMX(PHSUBD, phsubd) 945BINARY_INT_MMX(PMADDUBSW, pmaddubsw) 946BINARY_INT_MMX(PSHUFB, pshufb) 947BINARY_INT_MMX(PSIGNB, psignb) 948BINARY_INT_MMX(PSIGNW, psignw) 949BINARY_INT_MMX(PSIGND, psignd) 950BINARY_INT_MMX(PMULHRSW, pmulhrsw) 951 952/* Instructions with no MMX equivalent. */ 953#define BINARY_INT_SSE(uname, lname) \ 954static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 955{ \ 956 gen_binary_int_sse(s, decode, \ 957 NULL, \ 958 gen_helper_##lname##_xmm, \ 959 gen_helper_##lname##_ymm); \ 960} 961 962/* Instructions with no MMX equivalent. */ 963BINARY_INT_SSE(PUNPCKLQDQ, punpcklqdq) 964BINARY_INT_SSE(PUNPCKHQDQ, punpckhqdq) 965BINARY_INT_SSE(VPACKUSDW, packusdw) 966BINARY_INT_SSE(VPERMILPS, vpermilps) 967BINARY_INT_SSE(VPERMILPD, vpermilpd) 968BINARY_INT_SSE(VMASKMOVPS, vpmaskmovd) 969BINARY_INT_SSE(VMASKMOVPD, vpmaskmovq) 970 971BINARY_INT_SSE(PMULDQ, pmuldq) 972 973BINARY_INT_SSE(VAESDEC, aesdec) 974BINARY_INT_SSE(VAESDECLAST, aesdeclast) 975BINARY_INT_SSE(VAESENC, aesenc) 976BINARY_INT_SSE(VAESENCLAST, aesenclast) 977 978#define UNARY_CMP_SSE(uname, lname) \ 979static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 980{ \ 981 if (!s->vex_l) { \ 982 gen_helper_##lname##_xmm(tcg_env, OP_PTR1, OP_PTR2); \ 983 } else { \ 984 gen_helper_##lname##_ymm(tcg_env, OP_PTR1, OP_PTR2); \ 985 } \ 986 assume_cc_op(s, CC_OP_EFLAGS); \ 987} 988UNARY_CMP_SSE(VPTEST, ptest) 989UNARY_CMP_SSE(VTESTPS, vtestps) 990UNARY_CMP_SSE(VTESTPD, vtestpd) 991 992static inline void gen_unary_int_sse(DisasContext *s, X86DecodedInsn *decode, 993 SSEFunc_0_epp xmm, SSEFunc_0_epp ymm) 994{ 995 if (!s->vex_l) { 996 xmm(tcg_env, OP_PTR0, OP_PTR2); 997 } else { 998 ymm(tcg_env, OP_PTR0, OP_PTR2); 999 } 1000} 1001 1002#define UNARY_INT_SSE(uname, lname) \ 1003static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 1004{ \ 1005 gen_unary_int_sse(s, decode, \ 1006 gen_helper_##lname##_xmm, \ 1007 gen_helper_##lname##_ymm); \ 1008} 1009 1010UNARY_INT_SSE(VPMOVSXBW, pmovsxbw) 1011UNARY_INT_SSE(VPMOVSXBD, pmovsxbd) 1012UNARY_INT_SSE(VPMOVSXBQ, pmovsxbq) 1013UNARY_INT_SSE(VPMOVSXWD, pmovsxwd) 1014UNARY_INT_SSE(VPMOVSXWQ, pmovsxwq) 1015UNARY_INT_SSE(VPMOVSXDQ, pmovsxdq) 1016 1017UNARY_INT_SSE(VPMOVZXBW, pmovzxbw) 1018UNARY_INT_SSE(VPMOVZXBD, pmovzxbd) 1019UNARY_INT_SSE(VPMOVZXBQ, pmovzxbq) 1020UNARY_INT_SSE(VPMOVZXWD, pmovzxwd) 1021UNARY_INT_SSE(VPMOVZXWQ, pmovzxwq) 1022UNARY_INT_SSE(VPMOVZXDQ, pmovzxdq) 1023 1024UNARY_INT_SSE(VMOVSLDUP, pmovsldup) 1025UNARY_INT_SSE(VMOVSHDUP, pmovshdup) 1026UNARY_INT_SSE(VMOVDDUP, pmovdldup) 1027 1028UNARY_INT_SSE(VCVTDQ2PD, cvtdq2pd) 1029UNARY_INT_SSE(VCVTPD2DQ, cvtpd2dq) 1030UNARY_INT_SSE(VCVTTPD2DQ, cvttpd2dq) 1031UNARY_INT_SSE(VCVTDQ2PS, cvtdq2ps) 1032UNARY_INT_SSE(VCVTPS2DQ, cvtps2dq) 1033UNARY_INT_SSE(VCVTTPS2DQ, cvttps2dq) 1034UNARY_INT_SSE(VCVTPH2PS, cvtph2ps) 1035 1036 1037static inline void gen_unary_imm_sse(DisasContext *s, X86DecodedInsn *decode, 1038 SSEFunc_0_ppi xmm, SSEFunc_0_ppi ymm) 1039{ 1040 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 1041 if (!s->vex_l) { 1042 xmm(OP_PTR0, OP_PTR1, imm); 1043 } else { 1044 ymm(OP_PTR0, OP_PTR1, imm); 1045 } 1046} 1047 1048#define UNARY_IMM_SSE(uname, lname) \ 1049static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 1050{ \ 1051 gen_unary_imm_sse(s, decode, \ 1052 gen_helper_##lname##_xmm, \ 1053 gen_helper_##lname##_ymm); \ 1054} 1055 1056UNARY_IMM_SSE(PSHUFD, pshufd) 1057UNARY_IMM_SSE(PSHUFHW, pshufhw) 1058UNARY_IMM_SSE(PSHUFLW, pshuflw) 1059#define gen_helper_vpermq_xmm NULL 1060UNARY_IMM_SSE(VPERMQ, vpermq) 1061UNARY_IMM_SSE(VPERMILPS_i, vpermilps_imm) 1062UNARY_IMM_SSE(VPERMILPD_i, vpermilpd_imm) 1063 1064static inline void gen_unary_imm_fp_sse(DisasContext *s, X86DecodedInsn *decode, 1065 SSEFunc_0_eppi xmm, SSEFunc_0_eppi ymm) 1066{ 1067 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 1068 if (!s->vex_l) { 1069 xmm(tcg_env, OP_PTR0, OP_PTR1, imm); 1070 } else { 1071 ymm(tcg_env, OP_PTR0, OP_PTR1, imm); 1072 } 1073} 1074 1075#define UNARY_IMM_FP_SSE(uname, lname) \ 1076static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 1077{ \ 1078 gen_unary_imm_fp_sse(s, decode, \ 1079 gen_helper_##lname##_xmm, \ 1080 gen_helper_##lname##_ymm); \ 1081} 1082 1083UNARY_IMM_FP_SSE(VROUNDPS, roundps) 1084UNARY_IMM_FP_SSE(VROUNDPD, roundpd) 1085 1086static inline void gen_vexw_avx(DisasContext *s, X86DecodedInsn *decode, 1087 SSEFunc_0_eppp d_xmm, SSEFunc_0_eppp q_xmm, 1088 SSEFunc_0_eppp d_ymm, SSEFunc_0_eppp q_ymm) 1089{ 1090 SSEFunc_0_eppp d = s->vex_l ? d_ymm : d_xmm; 1091 SSEFunc_0_eppp q = s->vex_l ? q_ymm : q_xmm; 1092 SSEFunc_0_eppp fn = s->vex_w ? q : d; 1093 fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 1094} 1095 1096/* VEX.W affects whether to operate on 32- or 64-bit elements. */ 1097#define VEXW_AVX(uname, lname) \ 1098static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 1099{ \ 1100 gen_vexw_avx(s, decode, \ 1101 gen_helper_##lname##d_xmm, gen_helper_##lname##q_xmm, \ 1102 gen_helper_##lname##d_ymm, gen_helper_##lname##q_ymm); \ 1103} 1104VEXW_AVX(VPSLLV, vpsllv) 1105VEXW_AVX(VPSRLV, vpsrlv) 1106VEXW_AVX(VPSRAV, vpsrav) 1107VEXW_AVX(VPMASKMOV, vpmaskmov) 1108 1109/* Same as above, but with extra arguments to the helper. */ 1110static inline void gen_vsib_avx(DisasContext *s, X86DecodedInsn *decode, 1111 SSEFunc_0_epppti d_xmm, SSEFunc_0_epppti q_xmm, 1112 SSEFunc_0_epppti d_ymm, SSEFunc_0_epppti q_ymm) 1113{ 1114 SSEFunc_0_epppti d = s->vex_l ? d_ymm : d_xmm; 1115 SSEFunc_0_epppti q = s->vex_l ? q_ymm : q_xmm; 1116 SSEFunc_0_epppti fn = s->vex_w ? q : d; 1117 TCGv_i32 scale = tcg_constant_i32(decode->mem.scale); 1118 TCGv_ptr index = tcg_temp_new_ptr(); 1119 1120 /* Pass third input as (index, base, scale) */ 1121 tcg_gen_addi_ptr(index, tcg_env, ZMM_OFFSET(decode->mem.index)); 1122 fn(tcg_env, OP_PTR0, OP_PTR1, index, s->A0, scale); 1123 1124 /* 1125 * There are two output operands, so zero OP1's high 128 bits 1126 * in the VEX.128 case. 1127 */ 1128 if (!s->vex_l) { 1129 int ymmh_ofs = vector_elem_offset(&decode->op[1], MO_128, 1); 1130 tcg_gen_gvec_dup_imm(MO_64, ymmh_ofs, 16, 16, 0); 1131 } 1132} 1133#define VSIB_AVX(uname, lname) \ 1134static void gen_##uname(DisasContext *s, X86DecodedInsn *decode) \ 1135{ \ 1136 gen_vsib_avx(s, decode, \ 1137 gen_helper_##lname##d_xmm, gen_helper_##lname##q_xmm, \ 1138 gen_helper_##lname##d_ymm, gen_helper_##lname##q_ymm); \ 1139} 1140VSIB_AVX(VPGATHERD, vpgatherd) 1141VSIB_AVX(VPGATHERQ, vpgatherq) 1142 1143static void gen_AAA(DisasContext *s, X86DecodedInsn *decode) 1144{ 1145 gen_update_cc_op(s); 1146 gen_helper_aaa(tcg_env); 1147 assume_cc_op(s, CC_OP_EFLAGS); 1148} 1149 1150static void gen_AAD(DisasContext *s, X86DecodedInsn *decode) 1151{ 1152 gen_helper_aad(s->T0, s->T0, s->T1); 1153 prepare_update1_cc(decode, s, CC_OP_LOGICB); 1154} 1155 1156static void gen_AAM(DisasContext *s, X86DecodedInsn *decode) 1157{ 1158 if (decode->immediate == 0) { 1159 gen_exception(s, EXCP00_DIVZ); 1160 } else { 1161 gen_helper_aam(s->T0, s->T0, s->T1); 1162 prepare_update1_cc(decode, s, CC_OP_LOGICB); 1163 } 1164} 1165 1166static void gen_AAS(DisasContext *s, X86DecodedInsn *decode) 1167{ 1168 gen_update_cc_op(s); 1169 gen_helper_aas(tcg_env); 1170 assume_cc_op(s, CC_OP_EFLAGS); 1171} 1172 1173static void gen_ADC(DisasContext *s, X86DecodedInsn *decode) 1174{ 1175 MemOp ot = decode->op[1].ot; 1176 TCGv c_in = tcg_temp_new(); 1177 1178 gen_compute_eflags_c(s, c_in); 1179 if (s->prefix & PREFIX_LOCK) { 1180 tcg_gen_add_tl(s->T0, c_in, s->T1); 1181 tcg_gen_atomic_add_fetch_tl(s->T0, s->A0, s->T0, 1182 s->mem_index, ot | MO_LE); 1183 } else { 1184 tcg_gen_add_tl(s->T0, s->T0, s->T1); 1185 tcg_gen_add_tl(s->T0, s->T0, c_in); 1186 } 1187 prepare_update3_cc(decode, s, CC_OP_ADCB + ot, c_in); 1188} 1189 1190static void gen_ADCOX(DisasContext *s, X86DecodedInsn *decode, int cc_op) 1191{ 1192 MemOp ot = decode->op[0].ot; 1193 TCGv carry_in = NULL; 1194 TCGv *carry_out = (cc_op == CC_OP_ADCX ? &decode->cc_dst : &decode->cc_src2); 1195 TCGv zero; 1196 1197 decode->cc_op = cc_op; 1198 *carry_out = tcg_temp_new(); 1199 if (CC_OP_HAS_EFLAGS(s->cc_op)) { 1200 decode->cc_src = cpu_cc_src; 1201 1202 /* Re-use the carry-out from a previous round? */ 1203 if (s->cc_op == cc_op || s->cc_op == CC_OP_ADCOX) { 1204 carry_in = (cc_op == CC_OP_ADCX ? cpu_cc_dst : cpu_cc_src2); 1205 } 1206 1207 /* Preserve the opposite carry from previous rounds? */ 1208 if (s->cc_op != cc_op && s->cc_op != CC_OP_EFLAGS) { 1209 decode->cc_op = CC_OP_ADCOX; 1210 if (carry_out == &decode->cc_dst) { 1211 decode->cc_src2 = cpu_cc_src2; 1212 } else { 1213 decode->cc_dst = cpu_cc_dst; 1214 } 1215 } 1216 } else { 1217 decode->cc_src = tcg_temp_new(); 1218 gen_mov_eflags(s, decode->cc_src); 1219 } 1220 1221 if (!carry_in) { 1222 /* Get carry_in out of EFLAGS. */ 1223 carry_in = tcg_temp_new(); 1224 tcg_gen_extract_tl(carry_in, decode->cc_src, 1225 ctz32(cc_op == CC_OP_ADCX ? CC_C : CC_O), 1); 1226 } 1227 1228 switch (ot) { 1229#ifdef TARGET_X86_64 1230 case MO_32: 1231 /* If TL is 64-bit just do everything in 64-bit arithmetic. */ 1232 tcg_gen_ext32u_tl(s->T0, s->T0); 1233 tcg_gen_ext32u_tl(s->T1, s->T1); 1234 tcg_gen_add_i64(s->T0, s->T0, s->T1); 1235 tcg_gen_add_i64(s->T0, s->T0, carry_in); 1236 tcg_gen_shri_i64(*carry_out, s->T0, 32); 1237 break; 1238#endif 1239 default: 1240 zero = tcg_constant_tl(0); 1241 tcg_gen_add2_tl(s->T0, *carry_out, s->T0, zero, carry_in, zero); 1242 tcg_gen_add2_tl(s->T0, *carry_out, s->T0, *carry_out, s->T1, zero); 1243 break; 1244 } 1245} 1246 1247static void gen_ADCX(DisasContext *s, X86DecodedInsn *decode) 1248{ 1249 gen_ADCOX(s, decode, CC_OP_ADCX); 1250} 1251 1252static void gen_ADD(DisasContext *s, X86DecodedInsn *decode) 1253{ 1254 MemOp ot = decode->op[1].ot; 1255 1256 if (s->prefix & PREFIX_LOCK) { 1257 tcg_gen_atomic_add_fetch_tl(s->T0, s->A0, s->T1, 1258 s->mem_index, ot | MO_LE); 1259 } else { 1260 tcg_gen_add_tl(s->T0, s->T0, s->T1); 1261 } 1262 prepare_update2_cc(decode, s, CC_OP_ADDB + ot); 1263} 1264 1265static void gen_ADOX(DisasContext *s, X86DecodedInsn *decode) 1266{ 1267 gen_ADCOX(s, decode, CC_OP_ADOX); 1268} 1269 1270static void gen_AND(DisasContext *s, X86DecodedInsn *decode) 1271{ 1272 MemOp ot = decode->op[1].ot; 1273 1274 if (s->prefix & PREFIX_LOCK) { 1275 tcg_gen_atomic_and_fetch_tl(s->T0, s->A0, s->T1, 1276 s->mem_index, ot | MO_LE); 1277 } else { 1278 tcg_gen_and_tl(s->T0, s->T0, s->T1); 1279 } 1280 prepare_update1_cc(decode, s, CC_OP_LOGICB + ot); 1281} 1282 1283static void gen_ANDN(DisasContext *s, X86DecodedInsn *decode) 1284{ 1285 MemOp ot = decode->op[0].ot; 1286 1287 tcg_gen_andc_tl(s->T0, s->T1, s->T0); 1288 prepare_update1_cc(decode, s, CC_OP_LOGICB + ot); 1289} 1290 1291static void gen_ARPL(DisasContext *s, X86DecodedInsn *decode) 1292{ 1293 TCGv zf = tcg_temp_new(); 1294 TCGv flags = tcg_temp_new(); 1295 1296 gen_mov_eflags(s, flags); 1297 1298 /* Compute adjusted DST in T1, merging in SRC[RPL]. */ 1299 tcg_gen_deposit_tl(s->T1, s->T0, s->T1, 0, 2); 1300 1301 /* Z flag set if DST[RPL] < SRC[RPL] */ 1302 tcg_gen_setcond_tl(TCG_COND_LTU, zf, s->T0, s->T1); 1303 tcg_gen_deposit_tl(flags, flags, zf, ctz32(CC_Z), 1); 1304 1305 /* Place maximum RPL in DST */ 1306 tcg_gen_umax_tl(s->T0, s->T0, s->T1); 1307 1308 decode->cc_src = flags; 1309 decode->cc_op = CC_OP_EFLAGS; 1310} 1311 1312static void gen_BEXTR(DisasContext *s, X86DecodedInsn *decode) 1313{ 1314 MemOp ot = decode->op[0].ot; 1315 TCGv bound = tcg_constant_tl(ot == MO_64 ? 63 : 31); 1316 TCGv zero = tcg_constant_tl(0); 1317 TCGv mone = tcg_constant_tl(-1); 1318 1319 /* 1320 * Extract START, and shift the operand. 1321 * Shifts larger than operand size get zeros. 1322 */ 1323 tcg_gen_ext8u_tl(s->A0, s->T1); 1324 tcg_gen_shr_tl(s->T0, s->T0, s->A0); 1325 1326 tcg_gen_movcond_tl(TCG_COND_LEU, s->T0, s->A0, bound, s->T0, zero); 1327 1328 /* 1329 * Extract the LEN into an inverse mask. Lengths larger than 1330 * operand size get all zeros, length 0 gets all ones. 1331 */ 1332 tcg_gen_extract_tl(s->A0, s->T1, 8, 8); 1333 tcg_gen_shl_tl(s->T1, mone, s->A0); 1334 tcg_gen_movcond_tl(TCG_COND_LEU, s->T1, s->A0, bound, s->T1, zero); 1335 tcg_gen_andc_tl(s->T0, s->T0, s->T1); 1336 1337 prepare_update1_cc(decode, s, CC_OP_LOGICB + ot); 1338} 1339 1340static void gen_BLSI(DisasContext *s, X86DecodedInsn *decode) 1341{ 1342 MemOp ot = decode->op[0].ot; 1343 1344 /* input in T1, which is ready for prepare_update2_cc */ 1345 tcg_gen_neg_tl(s->T0, s->T1); 1346 tcg_gen_and_tl(s->T0, s->T0, s->T1); 1347 prepare_update2_cc(decode, s, CC_OP_BLSIB + ot); 1348} 1349 1350static void gen_BLSMSK(DisasContext *s, X86DecodedInsn *decode) 1351{ 1352 MemOp ot = decode->op[0].ot; 1353 1354 /* input in T1, which is ready for prepare_update2_cc */ 1355 tcg_gen_subi_tl(s->T0, s->T1, 1); 1356 tcg_gen_xor_tl(s->T0, s->T0, s->T1); 1357 prepare_update2_cc(decode, s, CC_OP_BMILGB + ot); 1358} 1359 1360static void gen_BLSR(DisasContext *s, X86DecodedInsn *decode) 1361{ 1362 MemOp ot = decode->op[0].ot; 1363 1364 /* input in T1, which is ready for prepare_update2_cc */ 1365 tcg_gen_subi_tl(s->T0, s->T1, 1); 1366 tcg_gen_and_tl(s->T0, s->T0, s->T1); 1367 prepare_update2_cc(decode, s, CC_OP_BMILGB + ot); 1368} 1369 1370static void gen_BOUND(DisasContext *s, X86DecodedInsn *decode) 1371{ 1372 TCGv_i32 op = tcg_temp_new_i32(); 1373 tcg_gen_trunc_tl_i32(op, s->T0); 1374 if (decode->op[1].ot == MO_16) { 1375 gen_helper_boundw(tcg_env, s->A0, op); 1376 } else { 1377 gen_helper_boundl(tcg_env, s->A0, op); 1378 } 1379} 1380 1381/* Non-standard convention - on entry T0 is zero-extended input, T1 is the output. */ 1382static void gen_BSF(DisasContext *s, X86DecodedInsn *decode) 1383{ 1384 MemOp ot = decode->op[0].ot; 1385 1386 /* Only the Z bit is defined and it is related to the input. */ 1387 decode->cc_dst = tcg_temp_new(); 1388 decode->cc_op = CC_OP_LOGICB + ot; 1389 tcg_gen_mov_tl(decode->cc_dst, s->T0); 1390 1391 /* 1392 * The manual says that the output is undefined when the 1393 * input is zero, but real hardware leaves it unchanged, and 1394 * real programs appear to depend on that. Accomplish this 1395 * by passing the output as the value to return upon zero. 1396 */ 1397 tcg_gen_ctz_tl(s->T0, s->T0, s->T1); 1398} 1399 1400/* Non-standard convention - on entry T0 is zero-extended input, T1 is the output. */ 1401static void gen_BSR(DisasContext *s, X86DecodedInsn *decode) 1402{ 1403 MemOp ot = decode->op[0].ot; 1404 1405 /* Only the Z bit is defined and it is related to the input. */ 1406 decode->cc_dst = tcg_temp_new(); 1407 decode->cc_op = CC_OP_LOGICB + ot; 1408 tcg_gen_mov_tl(decode->cc_dst, s->T0); 1409 1410 /* 1411 * The manual says that the output is undefined when the 1412 * input is zero, but real hardware leaves it unchanged, and 1413 * real programs appear to depend on that. Accomplish this 1414 * by passing the output as the value to return upon zero. 1415 * Plus, return the bit index of the first 1 bit. 1416 */ 1417 tcg_gen_xori_tl(s->T1, s->T1, TARGET_LONG_BITS - 1); 1418 tcg_gen_clz_tl(s->T0, s->T0, s->T1); 1419 tcg_gen_xori_tl(s->T0, s->T0, TARGET_LONG_BITS - 1); 1420} 1421 1422static void gen_BSWAP(DisasContext *s, X86DecodedInsn *decode) 1423{ 1424#ifdef TARGET_X86_64 1425 if (s->dflag == MO_64) { 1426 tcg_gen_bswap64_i64(s->T0, s->T0); 1427 return; 1428 } 1429#endif 1430 tcg_gen_bswap32_tl(s->T0, s->T0, TCG_BSWAP_OZ); 1431} 1432 1433static TCGv gen_bt_mask(DisasContext *s, X86DecodedInsn *decode) 1434{ 1435 MemOp ot = decode->op[1].ot; 1436 TCGv mask = tcg_temp_new(); 1437 1438 tcg_gen_andi_tl(s->T1, s->T1, (8 << ot) - 1); 1439 tcg_gen_shl_tl(mask, tcg_constant_tl(1), s->T1); 1440 return mask; 1441} 1442 1443/* Expects truncated bit index in COUNT, 1 << COUNT in MASK. */ 1444static void gen_bt_flags(DisasContext *s, X86DecodedInsn *decode, TCGv src, 1445 TCGv count, TCGv mask) 1446{ 1447 TCGv cf; 1448 1449 /* 1450 * C is the result of the test, Z is unchanged, and the others 1451 * are all undefined. 1452 */ 1453 if (s->cc_op == CC_OP_DYNAMIC || CC_OP_HAS_EFLAGS(s->cc_op)) { 1454 /* Generate EFLAGS and replace the C bit. */ 1455 cf = tcg_temp_new(); 1456 tcg_gen_setcond_tl(TCG_COND_TSTNE, cf, src, mask); 1457 prepare_update_cf(decode, s, cf); 1458 } else { 1459 /* 1460 * Z was going to be computed from the non-zero status of CC_DST. 1461 * We can get that same Z value (and the new C value) by leaving 1462 * CC_DST alone, setting CC_SRC, and using a CC_OP_SAR of the 1463 * same width. 1464 */ 1465 decode->cc_src = tcg_temp_new(); 1466 decode->cc_dst = cpu_cc_dst; 1467 decode->cc_op = CC_OP_SARB + cc_op_size(s->cc_op); 1468 tcg_gen_shr_tl(decode->cc_src, src, count); 1469 } 1470} 1471 1472static void gen_BT(DisasContext *s, X86DecodedInsn *decode) 1473{ 1474 TCGv count = s->T1; 1475 TCGv mask; 1476 1477 /* 1478 * Try to ensure that the rhs of the TSTNE condition is a constant (and a 1479 * power of two), as that is more readily available on most TCG backends. 1480 * 1481 * For immediate bit number gen_bt_mask()'s output is already a constant; 1482 * for register bit number, shift the source right and check bit 0. 1483 */ 1484 if (decode->e.op2 == X86_TYPE_I) { 1485 mask = gen_bt_mask(s, decode); 1486 } else { 1487 MemOp ot = decode->op[1].ot; 1488 1489 tcg_gen_andi_tl(s->T1, s->T1, (8 << ot) - 1); 1490 tcg_gen_shr_tl(s->T0, s->T0, s->T1); 1491 1492 count = tcg_constant_tl(0); 1493 mask = tcg_constant_tl(1); 1494 } 1495 gen_bt_flags(s, decode, s->T0, count, mask); 1496} 1497 1498static void gen_BTC(DisasContext *s, X86DecodedInsn *decode) 1499{ 1500 MemOp ot = decode->op[0].ot; 1501 TCGv old = tcg_temp_new(); 1502 TCGv mask = gen_bt_mask(s, decode); 1503 1504 if (s->prefix & PREFIX_LOCK) { 1505 tcg_gen_atomic_fetch_xor_tl(old, s->A0, mask, s->mem_index, ot | MO_LE); 1506 } else { 1507 tcg_gen_mov_tl(old, s->T0); 1508 tcg_gen_xor_tl(s->T0, s->T0, mask); 1509 } 1510 1511 gen_bt_flags(s, decode, old, s->T1, mask); 1512} 1513 1514static void gen_BTR(DisasContext *s, X86DecodedInsn *decode) 1515{ 1516 MemOp ot = decode->op[0].ot; 1517 TCGv old = tcg_temp_new(); 1518 TCGv mask = gen_bt_mask(s, decode); 1519 1520 if (s->prefix & PREFIX_LOCK) { 1521 TCGv maskc = tcg_temp_new(); 1522 tcg_gen_not_tl(maskc, mask); 1523 tcg_gen_atomic_fetch_and_tl(old, s->A0, maskc, s->mem_index, ot | MO_LE); 1524 } else { 1525 tcg_gen_mov_tl(old, s->T0); 1526 tcg_gen_andc_tl(s->T0, s->T0, mask); 1527 } 1528 1529 gen_bt_flags(s, decode, old, s->T1, mask); 1530} 1531 1532static void gen_BTS(DisasContext *s, X86DecodedInsn *decode) 1533{ 1534 MemOp ot = decode->op[0].ot; 1535 TCGv old = tcg_temp_new(); 1536 TCGv mask = gen_bt_mask(s, decode); 1537 1538 if (s->prefix & PREFIX_LOCK) { 1539 tcg_gen_atomic_fetch_or_tl(old, s->A0, mask, s->mem_index, ot | MO_LE); 1540 } else { 1541 tcg_gen_mov_tl(old, s->T0); 1542 tcg_gen_or_tl(s->T0, s->T0, mask); 1543 } 1544 1545 gen_bt_flags(s, decode, old, s->T1, mask); 1546} 1547 1548static void gen_BZHI(DisasContext *s, X86DecodedInsn *decode) 1549{ 1550 MemOp ot = decode->op[0].ot; 1551 TCGv bound = tcg_constant_tl(ot == MO_64 ? 63 : 31); 1552 TCGv zero = tcg_constant_tl(0); 1553 TCGv mone = tcg_constant_tl(-1); 1554 1555 tcg_gen_ext8u_tl(s->T1, s->T1); 1556 1557 tcg_gen_shl_tl(s->A0, mone, s->T1); 1558 tcg_gen_movcond_tl(TCG_COND_LEU, s->A0, s->T1, bound, s->A0, zero); 1559 tcg_gen_andc_tl(s->T0, s->T0, s->A0); 1560 /* 1561 * Note that since we're using BMILG (in order to get O 1562 * cleared) we need to store the inverse into C. 1563 */ 1564 tcg_gen_setcond_tl(TCG_COND_LEU, s->T1, s->T1, bound); 1565 prepare_update2_cc(decode, s, CC_OP_BMILGB + ot); 1566} 1567 1568static void gen_CALL(DisasContext *s, X86DecodedInsn *decode) 1569{ 1570 gen_push_v(s, eip_next_tl(s)); 1571 gen_JMP(s, decode); 1572} 1573 1574static void gen_CALL_m(DisasContext *s, X86DecodedInsn *decode) 1575{ 1576 gen_push_v(s, eip_next_tl(s)); 1577 gen_JMP_m(s, decode); 1578} 1579 1580static void gen_CALLF(DisasContext *s, X86DecodedInsn *decode) 1581{ 1582 gen_far_call(s); 1583} 1584 1585static void gen_CALLF_m(DisasContext *s, X86DecodedInsn *decode) 1586{ 1587 MemOp ot = decode->op[1].ot; 1588 1589 gen_op_ld_v(s, ot, s->T0, s->A0); 1590 gen_add_A0_im(s, 1 << ot); 1591 gen_op_ld_v(s, MO_16, s->T1, s->A0); 1592 gen_far_call(s); 1593} 1594 1595static void gen_CBW(DisasContext *s, X86DecodedInsn *decode) 1596{ 1597 MemOp src_ot = decode->op[0].ot - 1; 1598 1599 tcg_gen_ext_tl(s->T0, s->T0, src_ot | MO_SIGN); 1600} 1601 1602static void gen_CLC(DisasContext *s, X86DecodedInsn *decode) 1603{ 1604 gen_compute_eflags(s); 1605 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C); 1606} 1607 1608static void gen_CLD(DisasContext *s, X86DecodedInsn *decode) 1609{ 1610 tcg_gen_st_i32(tcg_constant_i32(1), tcg_env, offsetof(CPUX86State, df)); 1611} 1612 1613static void gen_CLI(DisasContext *s, X86DecodedInsn *decode) 1614{ 1615 gen_reset_eflags(s, IF_MASK); 1616} 1617 1618static void gen_CLTS(DisasContext *s, X86DecodedInsn *decode) 1619{ 1620 gen_helper_clts(tcg_env); 1621 /* abort block because static cpu state changed */ 1622 s->base.is_jmp = DISAS_EOB_NEXT; 1623} 1624 1625static void gen_CMC(DisasContext *s, X86DecodedInsn *decode) 1626{ 1627 gen_compute_eflags(s); 1628 tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C); 1629} 1630 1631static void gen_CMOVcc(DisasContext *s, X86DecodedInsn *decode) 1632{ 1633 gen_cmovcc(s, decode->b & 0xf, s->T0, s->T1); 1634} 1635 1636static void gen_CMPccXADD(DisasContext *s, X86DecodedInsn *decode) 1637{ 1638 TCGLabel *label_top = gen_new_label(); 1639 TCGLabel *label_bottom = gen_new_label(); 1640 TCGv oldv = tcg_temp_new(); 1641 TCGv newv = tcg_temp_new(); 1642 TCGv cmpv = tcg_temp_new(); 1643 TCGCond cond; 1644 1645 TCGv cmp_lhs, cmp_rhs; 1646 MemOp ot, ot_full; 1647 1648 int jcc_op = (decode->b >> 1) & 7; 1649 static const TCGCond cond_table[8] = { 1650 [JCC_O] = TCG_COND_LT, /* test sign bit by comparing against 0 */ 1651 [JCC_B] = TCG_COND_LTU, 1652 [JCC_Z] = TCG_COND_EQ, 1653 [JCC_BE] = TCG_COND_LEU, 1654 [JCC_S] = TCG_COND_LT, /* test sign bit by comparing against 0 */ 1655 [JCC_P] = TCG_COND_TSTEQ, /* even parity - tests low bit of popcount */ 1656 [JCC_L] = TCG_COND_LT, 1657 [JCC_LE] = TCG_COND_LE, 1658 }; 1659 1660 cond = cond_table[jcc_op]; 1661 if (decode->b & 1) { 1662 cond = tcg_invert_cond(cond); 1663 } 1664 1665 ot = decode->op[0].ot; 1666 ot_full = ot | MO_LE; 1667 if (jcc_op >= JCC_S) { 1668 /* 1669 * Sign-extend values before subtracting for S, P (zero/sign extension 1670 * does not matter there) L, LE and their inverses. 1671 */ 1672 ot_full |= MO_SIGN; 1673 } 1674 1675 /* 1676 * cmpv will be moved to cc_src *after* cpu_regs[] is written back, so use 1677 * tcg_gen_ext_tl instead of gen_ext_tl. 1678 */ 1679 tcg_gen_ext_tl(cmpv, cpu_regs[decode->op[1].n], ot_full); 1680 1681 /* 1682 * Cmpxchg loop starts here. 1683 * - s->T1: addition operand (from decoder) 1684 * - s->A0: dest address (from decoder) 1685 * - s->cc_srcT: memory operand (lhs for comparison) 1686 * - cmpv: rhs for comparison 1687 */ 1688 gen_set_label(label_top); 1689 gen_op_ld_v(s, ot_full, s->cc_srcT, s->A0); 1690 tcg_gen_sub_tl(s->T0, s->cc_srcT, cmpv); 1691 1692 /* Compute the comparison result by hand, to avoid clobbering cc_*. */ 1693 switch (jcc_op) { 1694 case JCC_O: 1695 /* (src1 ^ src2) & (src1 ^ dst). newv is only used here for a moment */ 1696 tcg_gen_xor_tl(newv, s->cc_srcT, s->T0); 1697 tcg_gen_xor_tl(s->tmp0, s->cc_srcT, cmpv); 1698 tcg_gen_and_tl(s->tmp0, s->tmp0, newv); 1699 tcg_gen_sextract_tl(s->tmp0, s->tmp0, 0, 8 << ot); 1700 cmp_lhs = s->tmp0, cmp_rhs = tcg_constant_tl(0); 1701 break; 1702 1703 case JCC_P: 1704 tcg_gen_ext8u_tl(s->tmp0, s->T0); 1705 tcg_gen_ctpop_tl(s->tmp0, s->tmp0); 1706 cmp_lhs = s->tmp0, cmp_rhs = tcg_constant_tl(1); 1707 break; 1708 1709 case JCC_S: 1710 tcg_gen_sextract_tl(s->tmp0, s->T0, 0, 8 << ot); 1711 cmp_lhs = s->tmp0, cmp_rhs = tcg_constant_tl(0); 1712 break; 1713 1714 default: 1715 cmp_lhs = s->cc_srcT, cmp_rhs = cmpv; 1716 break; 1717 } 1718 1719 /* Compute new value: if condition does not hold, just store back s->cc_srcT */ 1720 tcg_gen_add_tl(newv, s->cc_srcT, s->T1); 1721 tcg_gen_movcond_tl(cond, newv, cmp_lhs, cmp_rhs, newv, s->cc_srcT); 1722 tcg_gen_atomic_cmpxchg_tl(oldv, s->A0, s->cc_srcT, newv, s->mem_index, ot_full); 1723 1724 /* Exit unconditionally if cmpxchg succeeded. */ 1725 tcg_gen_brcond_tl(TCG_COND_EQ, oldv, s->cc_srcT, label_bottom); 1726 1727 /* Try again if there was actually a store to make. */ 1728 tcg_gen_brcond_tl(cond, cmp_lhs, cmp_rhs, label_top); 1729 gen_set_label(label_bottom); 1730 1731 /* Store old value to registers only after a successful store. */ 1732 gen_writeback(s, decode, 1, s->cc_srcT); 1733 1734 decode->cc_dst = s->T0; 1735 decode->cc_src = cmpv; 1736 decode->cc_op = CC_OP_SUBB + ot; 1737} 1738 1739static void gen_CMPS(DisasContext *s, X86DecodedInsn *decode) 1740{ 1741 MemOp ot = decode->op[2].ot; 1742 gen_repz_nz(s, ot, gen_cmps); 1743} 1744 1745static void gen_CMPXCHG(DisasContext *s, X86DecodedInsn *decode) 1746{ 1747 MemOp ot = decode->op[2].ot; 1748 TCGv cmpv = tcg_temp_new(); 1749 TCGv oldv = tcg_temp_new(); 1750 TCGv newv = tcg_temp_new(); 1751 TCGv dest; 1752 1753 tcg_gen_ext_tl(cmpv, cpu_regs[R_EAX], ot); 1754 tcg_gen_ext_tl(newv, s->T1, ot); 1755 if (s->prefix & PREFIX_LOCK) { 1756 tcg_gen_atomic_cmpxchg_tl(oldv, s->A0, cmpv, newv, 1757 s->mem_index, ot | MO_LE); 1758 } else { 1759 tcg_gen_ext_tl(oldv, s->T0, ot); 1760 if (decode->op[0].has_ea) { 1761 /* 1762 * Perform an unconditional store cycle like physical cpu; 1763 * must be before changing accumulator to ensure 1764 * idempotency if the store faults and the instruction 1765 * is restarted 1766 */ 1767 tcg_gen_movcond_tl(TCG_COND_EQ, newv, oldv, cmpv, newv, oldv); 1768 gen_op_st_v(s, ot, newv, s->A0); 1769 } else { 1770 /* 1771 * Unlike the memory case, where "the destination operand receives 1772 * a write cycle without regard to the result of the comparison", 1773 * rm must not be touched altogether if the write fails, including 1774 * not zero-extending it on 64-bit processors. So, precompute 1775 * the result of a successful writeback and perform the movcond 1776 * directly on cpu_regs. In case rm is part of RAX, note that this 1777 * movcond and the one below are mutually exclusive is executed. 1778 */ 1779 dest = gen_op_deposit_reg_v(s, ot, decode->op[0].n, newv, newv); 1780 tcg_gen_movcond_tl(TCG_COND_EQ, dest, oldv, cmpv, newv, dest); 1781 } 1782 decode->op[0].unit = X86_OP_SKIP; 1783 } 1784 1785 /* Write RAX only if the cmpxchg fails. */ 1786 dest = gen_op_deposit_reg_v(s, ot, R_EAX, s->T0, oldv); 1787 tcg_gen_movcond_tl(TCG_COND_NE, dest, oldv, cmpv, s->T0, dest); 1788 1789 tcg_gen_mov_tl(s->cc_srcT, cmpv); 1790 tcg_gen_sub_tl(cmpv, cmpv, oldv); 1791 decode->cc_dst = cmpv; 1792 decode->cc_src = oldv; 1793 decode->cc_op = CC_OP_SUBB + ot; 1794} 1795 1796static void gen_CMPXCHG16B(DisasContext *s, X86DecodedInsn *decode) 1797{ 1798#ifdef TARGET_X86_64 1799 MemOp mop = MO_TE | MO_128 | MO_ALIGN; 1800 TCGv_i64 t0, t1; 1801 TCGv_i128 cmp, val; 1802 1803 cmp = tcg_temp_new_i128(); 1804 val = tcg_temp_new_i128(); 1805 tcg_gen_concat_i64_i128(cmp, cpu_regs[R_EAX], cpu_regs[R_EDX]); 1806 tcg_gen_concat_i64_i128(val, cpu_regs[R_EBX], cpu_regs[R_ECX]); 1807 1808 /* Only require atomic with LOCK; non-parallel handled in generator. */ 1809 if (s->prefix & PREFIX_LOCK) { 1810 tcg_gen_atomic_cmpxchg_i128(val, s->A0, cmp, val, s->mem_index, mop); 1811 } else { 1812 tcg_gen_nonatomic_cmpxchg_i128(val, s->A0, cmp, val, s->mem_index, mop); 1813 } 1814 1815 tcg_gen_extr_i128_i64(s->T0, s->T1, val); 1816 1817 /* Determine success after the fact. */ 1818 t0 = tcg_temp_new_i64(); 1819 t1 = tcg_temp_new_i64(); 1820 tcg_gen_xor_i64(t0, s->T0, cpu_regs[R_EAX]); 1821 tcg_gen_xor_i64(t1, s->T1, cpu_regs[R_EDX]); 1822 tcg_gen_or_i64(t0, t0, t1); 1823 1824 /* Update Z. */ 1825 gen_compute_eflags(s); 1826 tcg_gen_setcondi_i64(TCG_COND_EQ, t0, t0, 0); 1827 tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, t0, ctz32(CC_Z), 1); 1828 1829 /* 1830 * Extract the result values for the register pair. We may do this 1831 * unconditionally, because on success (Z=1), the old value matches 1832 * the previous value in RDX:RAX. 1833 */ 1834 tcg_gen_mov_i64(cpu_regs[R_EAX], s->T0); 1835 tcg_gen_mov_i64(cpu_regs[R_EDX], s->T1); 1836#else 1837 abort(); 1838#endif 1839} 1840 1841static void gen_CMPXCHG8B(DisasContext *s, X86DecodedInsn *decode) 1842{ 1843 TCGv_i64 cmp, val, old; 1844 TCGv Z; 1845 1846 cmp = tcg_temp_new_i64(); 1847 val = tcg_temp_new_i64(); 1848 old = tcg_temp_new_i64(); 1849 1850 /* Construct the comparison values from the register pair. */ 1851 tcg_gen_concat_tl_i64(cmp, cpu_regs[R_EAX], cpu_regs[R_EDX]); 1852 tcg_gen_concat_tl_i64(val, cpu_regs[R_EBX], cpu_regs[R_ECX]); 1853 1854 /* Only require atomic with LOCK; non-parallel handled in generator. */ 1855 if (s->prefix & PREFIX_LOCK) { 1856 tcg_gen_atomic_cmpxchg_i64(old, s->A0, cmp, val, s->mem_index, MO_TEUQ); 1857 } else { 1858 tcg_gen_nonatomic_cmpxchg_i64(old, s->A0, cmp, val, 1859 s->mem_index, MO_TEUQ); 1860 } 1861 1862 /* Set tmp0 to match the required value of Z. */ 1863 tcg_gen_setcond_i64(TCG_COND_EQ, cmp, old, cmp); 1864 Z = tcg_temp_new(); 1865 tcg_gen_trunc_i64_tl(Z, cmp); 1866 1867 /* 1868 * Extract the result values for the register pair. 1869 * For 32-bit, we may do this unconditionally, because on success (Z=1), 1870 * the old value matches the previous value in EDX:EAX. For x86_64, 1871 * the store must be conditional, because we must leave the source 1872 * registers unchanged on success, and zero-extend the writeback 1873 * on failure (Z=0). 1874 */ 1875 if (TARGET_LONG_BITS == 32) { 1876 tcg_gen_extr_i64_tl(cpu_regs[R_EAX], cpu_regs[R_EDX], old); 1877 } else { 1878 TCGv zero = tcg_constant_tl(0); 1879 1880 tcg_gen_extr_i64_tl(s->T0, s->T1, old); 1881 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_regs[R_EAX], Z, zero, 1882 s->T0, cpu_regs[R_EAX]); 1883 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_regs[R_EDX], Z, zero, 1884 s->T1, cpu_regs[R_EDX]); 1885 } 1886 1887 /* Update Z. */ 1888 gen_compute_eflags(s); 1889 tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, Z, ctz32(CC_Z), 1); 1890} 1891 1892static void gen_CPUID(DisasContext *s, X86DecodedInsn *decode) 1893{ 1894 gen_update_cc_op(s); 1895 gen_update_eip_cur(s); 1896 gen_helper_cpuid(tcg_env); 1897} 1898 1899static void gen_CRC32(DisasContext *s, X86DecodedInsn *decode) 1900{ 1901 MemOp ot = decode->op[2].ot; 1902 1903 tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); 1904 gen_helper_crc32(s->T0, s->tmp2_i32, s->T1, tcg_constant_i32(8 << ot)); 1905} 1906 1907static void gen_CVTPI2Px(DisasContext *s, X86DecodedInsn *decode) 1908{ 1909 gen_helper_enter_mmx(tcg_env); 1910 if (s->prefix & PREFIX_DATA) { 1911 gen_helper_cvtpi2pd(tcg_env, OP_PTR0, OP_PTR2); 1912 } else { 1913 gen_helper_cvtpi2ps(tcg_env, OP_PTR0, OP_PTR2); 1914 } 1915} 1916 1917static void gen_CVTPx2PI(DisasContext *s, X86DecodedInsn *decode) 1918{ 1919 gen_helper_enter_mmx(tcg_env); 1920 if (s->prefix & PREFIX_DATA) { 1921 gen_helper_cvtpd2pi(tcg_env, OP_PTR0, OP_PTR2); 1922 } else { 1923 gen_helper_cvtps2pi(tcg_env, OP_PTR0, OP_PTR2); 1924 } 1925} 1926 1927static void gen_CVTTPx2PI(DisasContext *s, X86DecodedInsn *decode) 1928{ 1929 gen_helper_enter_mmx(tcg_env); 1930 if (s->prefix & PREFIX_DATA) { 1931 gen_helper_cvttpd2pi(tcg_env, OP_PTR0, OP_PTR2); 1932 } else { 1933 gen_helper_cvttps2pi(tcg_env, OP_PTR0, OP_PTR2); 1934 } 1935} 1936 1937static void gen_CWD(DisasContext *s, X86DecodedInsn *decode) 1938{ 1939 int shift = 8 << decode->op[0].ot; 1940 1941 tcg_gen_sextract_tl(s->T0, s->T0, shift - 1, 1); 1942} 1943 1944static void gen_DAA(DisasContext *s, X86DecodedInsn *decode) 1945{ 1946 gen_update_cc_op(s); 1947 gen_helper_daa(tcg_env); 1948 assume_cc_op(s, CC_OP_EFLAGS); 1949} 1950 1951static void gen_DAS(DisasContext *s, X86DecodedInsn *decode) 1952{ 1953 gen_update_cc_op(s); 1954 gen_helper_das(tcg_env); 1955 assume_cc_op(s, CC_OP_EFLAGS); 1956} 1957 1958static void gen_DEC(DisasContext *s, X86DecodedInsn *decode) 1959{ 1960 MemOp ot = decode->op[1].ot; 1961 1962 tcg_gen_movi_tl(s->T1, -1); 1963 if (s->prefix & PREFIX_LOCK) { 1964 tcg_gen_atomic_add_fetch_tl(s->T0, s->A0, s->T1, 1965 s->mem_index, ot | MO_LE); 1966 } else { 1967 tcg_gen_add_tl(s->T0, s->T0, s->T1); 1968 } 1969 prepare_update_cc_incdec(decode, s, CC_OP_DECB + ot); 1970} 1971 1972static void gen_DIV(DisasContext *s, X86DecodedInsn *decode) 1973{ 1974 MemOp ot = decode->op[1].ot; 1975 1976 switch(ot) { 1977 case MO_8: 1978 gen_helper_divb_AL(tcg_env, s->T0); 1979 break; 1980 case MO_16: 1981 gen_helper_divw_AX(tcg_env, s->T0); 1982 break; 1983 default: 1984 case MO_32: 1985 gen_helper_divl_EAX(tcg_env, s->T0); 1986 break; 1987#ifdef TARGET_X86_64 1988 case MO_64: 1989 gen_helper_divq_EAX(tcg_env, s->T0); 1990 break; 1991#endif 1992 } 1993} 1994 1995static void gen_EMMS(DisasContext *s, X86DecodedInsn *decode) 1996{ 1997 gen_helper_emms(tcg_env); 1998} 1999 2000static void gen_ENTER(DisasContext *s, X86DecodedInsn *decode) 2001{ 2002 gen_enter(s, decode->op[1].imm, decode->op[2].imm); 2003} 2004 2005static void gen_EXTRQ_i(DisasContext *s, X86DecodedInsn *decode) 2006{ 2007 TCGv_i32 length = tcg_constant_i32(decode->immediate & 63); 2008 TCGv_i32 index = tcg_constant_i32((decode->immediate >> 8) & 63); 2009 2010 gen_helper_extrq_i(tcg_env, OP_PTR0, index, length); 2011} 2012 2013static void gen_EXTRQ_r(DisasContext *s, X86DecodedInsn *decode) 2014{ 2015 gen_helper_extrq_r(tcg_env, OP_PTR0, OP_PTR2); 2016} 2017 2018static void gen_FXRSTOR(DisasContext *s, X86DecodedInsn *decode) 2019{ 2020 if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) { 2021 gen_NM_exception(s); 2022 } else { 2023 gen_helper_fxrstor(tcg_env, s->A0); 2024 } 2025} 2026 2027static void gen_FXSAVE(DisasContext *s, X86DecodedInsn *decode) 2028{ 2029 if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) { 2030 gen_NM_exception(s); 2031 } else { 2032 gen_helper_fxsave(tcg_env, s->A0); 2033 } 2034} 2035 2036static void gen_HLT(DisasContext *s, X86DecodedInsn *decode) 2037{ 2038#ifdef CONFIG_SYSTEM_ONLY 2039 gen_update_cc_op(s); 2040 gen_update_eip_next(s); 2041 gen_helper_hlt(tcg_env); 2042 s->base.is_jmp = DISAS_NORETURN; 2043#endif 2044} 2045 2046static void gen_IDIV(DisasContext *s, X86DecodedInsn *decode) 2047{ 2048 MemOp ot = decode->op[1].ot; 2049 2050 switch(ot) { 2051 case MO_8: 2052 gen_helper_idivb_AL(tcg_env, s->T0); 2053 break; 2054 case MO_16: 2055 gen_helper_idivw_AX(tcg_env, s->T0); 2056 break; 2057 default: 2058 case MO_32: 2059 gen_helper_idivl_EAX(tcg_env, s->T0); 2060 break; 2061#ifdef TARGET_X86_64 2062 case MO_64: 2063 gen_helper_idivq_EAX(tcg_env, s->T0); 2064 break; 2065#endif 2066 } 2067} 2068 2069static void gen_IMUL3(DisasContext *s, X86DecodedInsn *decode) 2070{ 2071 MemOp ot = decode->op[0].ot; 2072 TCGv cc_src_rhs; 2073 2074 switch (ot) { 2075 case MO_16: 2076 /* s->T0 already sign-extended */ 2077 tcg_gen_ext16s_tl(s->T1, s->T1); 2078 tcg_gen_mul_tl(s->T0, s->T0, s->T1); 2079 /* Compare the full result to the extension of the truncated result. */ 2080 tcg_gen_ext16s_tl(s->T1, s->T0); 2081 cc_src_rhs = s->T0; 2082 break; 2083 2084 case MO_32: 2085#ifdef TARGET_X86_64 2086 if (TCG_TARGET_REG_BITS == 64) { 2087 /* 2088 * This produces fewer TCG ops, and better code if flags are needed, 2089 * but it requires a 64-bit multiply even if they are not. Use it 2090 * only if the target has 64-bits registers. 2091 * 2092 * s->T0 is already sign-extended. 2093 */ 2094 tcg_gen_ext32s_tl(s->T1, s->T1); 2095 tcg_gen_mul_tl(s->T0, s->T0, s->T1); 2096 /* Compare the full result to the extension of the truncated result. */ 2097 tcg_gen_ext32s_tl(s->T1, s->T0); 2098 cc_src_rhs = s->T0; 2099 } else { 2100 /* Variant that only needs a 32-bit widening multiply. */ 2101 TCGv_i32 hi = tcg_temp_new_i32(); 2102 TCGv_i32 lo = tcg_temp_new_i32(); 2103 tcg_gen_trunc_tl_i32(lo, s->T0); 2104 tcg_gen_trunc_tl_i32(hi, s->T1); 2105 tcg_gen_muls2_i32(lo, hi, lo, hi); 2106 tcg_gen_extu_i32_tl(s->T0, lo); 2107 2108 cc_src_rhs = tcg_temp_new(); 2109 tcg_gen_extu_i32_tl(cc_src_rhs, hi); 2110 /* Compare the high part to the sign bit of the truncated result */ 2111 tcg_gen_sari_i32(lo, lo, 31); 2112 tcg_gen_extu_i32_tl(s->T1, lo); 2113 } 2114 break; 2115 2116 case MO_64: 2117#endif 2118 cc_src_rhs = tcg_temp_new(); 2119 tcg_gen_muls2_tl(s->T0, cc_src_rhs, s->T0, s->T1); 2120 /* Compare the high part to the sign bit of the truncated result */ 2121 tcg_gen_sari_tl(s->T1, s->T0, TARGET_LONG_BITS - 1); 2122 break; 2123 2124 default: 2125 g_assert_not_reached(); 2126 } 2127 2128 tcg_gen_sub_tl(s->T1, s->T1, cc_src_rhs); 2129 prepare_update2_cc(decode, s, CC_OP_MULB + ot); 2130} 2131 2132static void gen_IMUL(DisasContext *s, X86DecodedInsn *decode) 2133{ 2134 MemOp ot = decode->op[1].ot; 2135 TCGv cc_src_rhs; 2136 2137 switch (ot) { 2138 case MO_8: 2139 /* s->T0 already sign-extended */ 2140 tcg_gen_ext8s_tl(s->T1, s->T1); 2141 tcg_gen_mul_tl(s->T0, s->T0, s->T1); 2142 gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0); 2143 /* Compare the full result to the extension of the truncated result. */ 2144 tcg_gen_ext8s_tl(s->T1, s->T0); 2145 cc_src_rhs = s->T0; 2146 break; 2147 2148 case MO_16: 2149 /* s->T0 already sign-extended */ 2150 tcg_gen_ext16s_tl(s->T1, s->T1); 2151 tcg_gen_mul_tl(s->T0, s->T0, s->T1); 2152 gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0); 2153 tcg_gen_shri_tl(s->T1, s->T0, 16); 2154 gen_op_mov_reg_v(s, MO_16, R_EDX, s->T1); 2155 /* Compare the full result to the extension of the truncated result. */ 2156 tcg_gen_ext16s_tl(s->T1, s->T0); 2157 cc_src_rhs = s->T0; 2158 break; 2159 2160 case MO_32: 2161#ifdef TARGET_X86_64 2162 /* s->T0 already sign-extended */ 2163 tcg_gen_ext32s_tl(s->T1, s->T1); 2164 tcg_gen_mul_tl(s->T0, s->T0, s->T1); 2165 tcg_gen_ext32u_tl(cpu_regs[R_EAX], s->T0); 2166 tcg_gen_shri_tl(cpu_regs[R_EDX], s->T0, 32); 2167 /* Compare the full result to the extension of the truncated result. */ 2168 tcg_gen_ext32s_tl(s->T1, s->T0); 2169 cc_src_rhs = s->T0; 2170 break; 2171 2172 case MO_64: 2173#endif 2174 tcg_gen_muls2_tl(s->T0, cpu_regs[R_EDX], s->T0, s->T1); 2175 tcg_gen_mov_tl(cpu_regs[R_EAX], s->T0); 2176 2177 /* Compare the high part to the sign bit of the truncated result */ 2178 tcg_gen_negsetcondi_tl(TCG_COND_LT, s->T1, s->T0, 0); 2179 cc_src_rhs = cpu_regs[R_EDX]; 2180 break; 2181 2182 default: 2183 g_assert_not_reached(); 2184 } 2185 2186 tcg_gen_sub_tl(s->T1, s->T1, cc_src_rhs); 2187 prepare_update2_cc(decode, s, CC_OP_MULB + ot); 2188} 2189 2190static void gen_IN(DisasContext *s, X86DecodedInsn *decode) 2191{ 2192 MemOp ot = decode->op[0].ot; 2193 TCGv_i32 port = tcg_temp_new_i32(); 2194 2195 tcg_gen_trunc_tl_i32(port, s->T0); 2196 tcg_gen_ext16u_i32(port, port); 2197 if (!gen_check_io(s, ot, port, SVM_IOIO_TYPE_MASK)) { 2198 return; 2199 } 2200 translator_io_start(&s->base); 2201 gen_helper_in_func(ot, s->T0, port); 2202 gen_writeback(s, decode, 0, s->T0); 2203 gen_bpt_io(s, port, ot); 2204} 2205 2206static void gen_INC(DisasContext *s, X86DecodedInsn *decode) 2207{ 2208 MemOp ot = decode->op[1].ot; 2209 2210 tcg_gen_movi_tl(s->T1, 1); 2211 if (s->prefix & PREFIX_LOCK) { 2212 tcg_gen_atomic_add_fetch_tl(s->T0, s->A0, s->T1, 2213 s->mem_index, ot | MO_LE); 2214 } else { 2215 tcg_gen_add_tl(s->T0, s->T0, s->T1); 2216 } 2217 prepare_update_cc_incdec(decode, s, CC_OP_INCB + ot); 2218} 2219 2220static void gen_INS(DisasContext *s, X86DecodedInsn *decode) 2221{ 2222 MemOp ot = decode->op[1].ot; 2223 TCGv_i32 port = tcg_temp_new_i32(); 2224 2225 tcg_gen_trunc_tl_i32(port, s->T1); 2226 tcg_gen_ext16u_i32(port, port); 2227 if (!gen_check_io(s, ot, port, 2228 SVM_IOIO_TYPE_MASK | SVM_IOIO_STR_MASK)) { 2229 return; 2230 } 2231 2232 translator_io_start(&s->base); 2233 gen_repz(s, ot, gen_ins); 2234} 2235 2236static void gen_INSERTQ_i(DisasContext *s, X86DecodedInsn *decode) 2237{ 2238 TCGv_i32 length = tcg_constant_i32(decode->immediate & 63); 2239 TCGv_i32 index = tcg_constant_i32((decode->immediate >> 8) & 63); 2240 2241 gen_helper_insertq_i(tcg_env, OP_PTR0, OP_PTR1, index, length); 2242} 2243 2244static void gen_INSERTQ_r(DisasContext *s, X86DecodedInsn *decode) 2245{ 2246 gen_helper_insertq_r(tcg_env, OP_PTR0, OP_PTR2); 2247} 2248 2249static void gen_INT(DisasContext *s, X86DecodedInsn *decode) 2250{ 2251 gen_interrupt(s, decode->immediate); 2252} 2253 2254static void gen_INT1(DisasContext *s, X86DecodedInsn *decode) 2255{ 2256 gen_update_cc_op(s); 2257 gen_update_eip_next(s); 2258 gen_helper_icebp(tcg_env); 2259 s->base.is_jmp = DISAS_NORETURN; 2260} 2261 2262static void gen_INT3(DisasContext *s, X86DecodedInsn *decode) 2263{ 2264 gen_interrupt(s, EXCP03_INT3); 2265} 2266 2267static void gen_INTO(DisasContext *s, X86DecodedInsn *decode) 2268{ 2269 gen_update_cc_op(s); 2270 gen_update_eip_cur(s); 2271 gen_helper_into(tcg_env, cur_insn_len_i32(s)); 2272} 2273 2274static void gen_IRET(DisasContext *s, X86DecodedInsn *decode) 2275{ 2276 if (!PE(s) || VM86(s)) { 2277 gen_helper_iret_real(tcg_env, tcg_constant_i32(s->dflag - 1)); 2278 } else { 2279 gen_helper_iret_protected(tcg_env, tcg_constant_i32(s->dflag - 1), 2280 eip_next_i32(s)); 2281 } 2282 assume_cc_op(s, CC_OP_EFLAGS); 2283 s->base.is_jmp = DISAS_EOB_ONLY; 2284} 2285 2286static void gen_Jcc(DisasContext *s, X86DecodedInsn *decode) 2287{ 2288 TCGLabel *taken = gen_new_label(); 2289 2290 gen_bnd_jmp(s); 2291 gen_jcc(s, decode->b & 0xf, taken); 2292 gen_conditional_jump_labels(s, decode->immediate, NULL, taken); 2293} 2294 2295static void gen_JCXZ(DisasContext *s, X86DecodedInsn *decode) 2296{ 2297 TCGLabel *taken = gen_new_label(); 2298 2299 gen_update_cc_op(s); 2300 gen_op_jz_ecx(s, taken); 2301 gen_conditional_jump_labels(s, decode->immediate, NULL, taken); 2302} 2303 2304static void gen_JMP(DisasContext *s, X86DecodedInsn *decode) 2305{ 2306 gen_update_cc_op(s); 2307 gen_jmp_rel(s, s->dflag, decode->immediate, 0); 2308} 2309 2310static void gen_JMP_m(DisasContext *s, X86DecodedInsn *decode) 2311{ 2312 gen_op_jmp_v(s, s->T0); 2313 gen_bnd_jmp(s); 2314 s->base.is_jmp = DISAS_JUMP; 2315} 2316 2317static void gen_JMPF(DisasContext *s, X86DecodedInsn *decode) 2318{ 2319 gen_far_jmp(s); 2320} 2321 2322static void gen_JMPF_m(DisasContext *s, X86DecodedInsn *decode) 2323{ 2324 MemOp ot = decode->op[1].ot; 2325 2326 gen_op_ld_v(s, ot, s->T0, s->A0); 2327 gen_add_A0_im(s, 1 << ot); 2328 gen_op_ld_v(s, MO_16, s->T1, s->A0); 2329 gen_far_jmp(s); 2330} 2331 2332static void gen_LAHF(DisasContext *s, X86DecodedInsn *decode) 2333{ 2334 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) { 2335 return gen_illegal_opcode(s); 2336 } 2337 gen_compute_eflags(s); 2338 /* Note: gen_compute_eflags() only gives the condition codes */ 2339 tcg_gen_ori_tl(s->T0, cpu_cc_src, 0x02); 2340 tcg_gen_deposit_tl(cpu_regs[R_EAX], cpu_regs[R_EAX], s->T0, 8, 8); 2341} 2342 2343static void gen_LAR(DisasContext *s, X86DecodedInsn *decode) 2344{ 2345 MemOp ot = decode->op[0].ot; 2346 TCGv result = tcg_temp_new(); 2347 TCGv dest; 2348 2349 gen_compute_eflags(s); 2350 gen_update_cc_op(s); 2351 gen_helper_lar(result, tcg_env, s->T0); 2352 2353 /* Perform writeback here to skip it if ZF=0. */ 2354 decode->op[0].unit = X86_OP_SKIP; 2355 dest = gen_op_deposit_reg_v(s, ot, decode->op[0].n, result, result); 2356 tcg_gen_movcond_tl(TCG_COND_TSTNE, dest, cpu_cc_src, tcg_constant_tl(CC_Z), 2357 result, dest); 2358} 2359 2360static void gen_LDMXCSR(DisasContext *s, X86DecodedInsn *decode) 2361{ 2362 tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); 2363 gen_helper_ldmxcsr(tcg_env, s->tmp2_i32); 2364} 2365 2366static void gen_lxx_seg(DisasContext *s, X86DecodedInsn *decode, int seg) 2367{ 2368 MemOp ot = decode->op[0].ot; 2369 2370 /* Offset already in s->T0. */ 2371 gen_add_A0_im(s, 1 << ot); 2372 gen_op_ld_v(s, MO_16, s->T1, s->A0); 2373 2374 /* load the segment here to handle exceptions properly */ 2375 gen_movl_seg(s, seg, s->T1, false); 2376} 2377 2378static void gen_LDS(DisasContext *s, X86DecodedInsn *decode) 2379{ 2380 gen_lxx_seg(s, decode, R_DS); 2381} 2382 2383static void gen_LEA(DisasContext *s, X86DecodedInsn *decode) 2384{ 2385 TCGv ea = gen_lea_modrm_1(s, decode->mem, false); 2386 gen_lea_v_seg_dest(s, s->aflag, s->T0, ea, -1, -1); 2387} 2388 2389static void gen_LEAVE(DisasContext *s, X86DecodedInsn *decode) 2390{ 2391 gen_leave(s); 2392} 2393 2394static void gen_LES(DisasContext *s, X86DecodedInsn *decode) 2395{ 2396 gen_lxx_seg(s, decode, R_ES); 2397} 2398 2399static void gen_LFENCE(DisasContext *s, X86DecodedInsn *decode) 2400{ 2401 tcg_gen_mb(TCG_MO_LD_LD | TCG_BAR_SC); 2402} 2403 2404static void gen_LFS(DisasContext *s, X86DecodedInsn *decode) 2405{ 2406 gen_lxx_seg(s, decode, R_FS); 2407} 2408 2409static void gen_LGS(DisasContext *s, X86DecodedInsn *decode) 2410{ 2411 gen_lxx_seg(s, decode, R_GS); 2412} 2413 2414static void gen_LODS(DisasContext *s, X86DecodedInsn *decode) 2415{ 2416 MemOp ot = decode->op[1].ot; 2417 gen_repz(s, ot, gen_lods); 2418} 2419 2420static void gen_LOOP(DisasContext *s, X86DecodedInsn *decode) 2421{ 2422 TCGLabel *taken = gen_new_label(); 2423 2424 gen_update_cc_op(s); 2425 gen_op_add_reg_im(s, s->aflag, R_ECX, -1); 2426 gen_op_jnz_ecx(s, taken); 2427 gen_conditional_jump_labels(s, decode->immediate, NULL, taken); 2428} 2429 2430static void gen_LOOPE(DisasContext *s, X86DecodedInsn *decode) 2431{ 2432 TCGLabel *taken = gen_new_label(); 2433 TCGLabel *not_taken = gen_new_label(); 2434 2435 gen_update_cc_op(s); 2436 gen_op_add_reg_im(s, s->aflag, R_ECX, -1); 2437 gen_op_jz_ecx(s, not_taken); 2438 gen_jcc(s, (JCC_Z << 1), taken); /* jz taken */ 2439 gen_conditional_jump_labels(s, decode->immediate, not_taken, taken); 2440} 2441 2442static void gen_LOOPNE(DisasContext *s, X86DecodedInsn *decode) 2443{ 2444 TCGLabel *taken = gen_new_label(); 2445 TCGLabel *not_taken = gen_new_label(); 2446 2447 gen_update_cc_op(s); 2448 gen_op_add_reg_im(s, s->aflag, R_ECX, -1); 2449 gen_op_jz_ecx(s, not_taken); 2450 gen_jcc(s, (JCC_Z << 1) | 1, taken); /* jnz taken */ 2451 gen_conditional_jump_labels(s, decode->immediate, not_taken, taken); 2452} 2453 2454static void gen_LSL(DisasContext *s, X86DecodedInsn *decode) 2455{ 2456 MemOp ot = decode->op[0].ot; 2457 TCGv result = tcg_temp_new(); 2458 TCGv dest; 2459 2460 gen_compute_eflags(s); 2461 gen_update_cc_op(s); 2462 gen_helper_lsl(result, tcg_env, s->T0); 2463 2464 /* Perform writeback here to skip it if ZF=0. */ 2465 decode->op[0].unit = X86_OP_SKIP; 2466 dest = gen_op_deposit_reg_v(s, ot, decode->op[0].n, result, result); 2467 tcg_gen_movcond_tl(TCG_COND_TSTNE, dest, cpu_cc_src, tcg_constant_tl(CC_Z), 2468 result, dest); 2469} 2470 2471static void gen_LSS(DisasContext *s, X86DecodedInsn *decode) 2472{ 2473 gen_lxx_seg(s, decode, R_SS); 2474} 2475 2476static void gen_LZCNT(DisasContext *s, X86DecodedInsn *decode) 2477{ 2478 MemOp ot = decode->op[0].ot; 2479 2480 /* C bit (cc_src) is defined related to the input. */ 2481 decode->cc_src = tcg_temp_new(); 2482 decode->cc_dst = s->T0; 2483 decode->cc_op = CC_OP_BMILGB + ot; 2484 tcg_gen_mov_tl(decode->cc_src, s->T0); 2485 2486 /* 2487 * Reduce the target_ulong result by the number of zeros that 2488 * we expect to find at the top. 2489 */ 2490 tcg_gen_clzi_tl(s->T0, s->T0, TARGET_LONG_BITS); 2491 tcg_gen_subi_tl(s->T0, s->T0, TARGET_LONG_BITS - (8 << ot)); 2492} 2493 2494static void gen_MFENCE(DisasContext *s, X86DecodedInsn *decode) 2495{ 2496 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); 2497} 2498 2499static void gen_MOV(DisasContext *s, X86DecodedInsn *decode) 2500{ 2501 /* nothing to do! */ 2502} 2503#define gen_NOP gen_MOV 2504 2505static void gen_MASKMOV(DisasContext *s, X86DecodedInsn *decode) 2506{ 2507 gen_lea_v_seg(s, cpu_regs[R_EDI], R_DS, s->override); 2508 2509 if (s->prefix & PREFIX_DATA) { 2510 gen_helper_maskmov_xmm(tcg_env, OP_PTR1, OP_PTR2, s->A0); 2511 } else { 2512 gen_helper_maskmov_mmx(tcg_env, OP_PTR1, OP_PTR2, s->A0); 2513 } 2514} 2515 2516static void gen_MOVBE(DisasContext *s, X86DecodedInsn *decode) 2517{ 2518 MemOp ot = decode->op[0].ot; 2519 2520 /* M operand type does not load/store */ 2521 if (decode->e.op0 == X86_TYPE_M) { 2522 tcg_gen_qemu_st_tl(s->T0, s->A0, s->mem_index, ot | MO_BE); 2523 } else { 2524 tcg_gen_qemu_ld_tl(s->T0, s->A0, s->mem_index, ot | MO_BE); 2525 } 2526} 2527 2528static void gen_MOVD_from(DisasContext *s, X86DecodedInsn *decode) 2529{ 2530 MemOp ot = decode->op[2].ot; 2531 2532 switch (ot) { 2533 case MO_32: 2534#ifdef TARGET_X86_64 2535 tcg_gen_ld32u_tl(s->T0, tcg_env, decode->op[2].offset); 2536 break; 2537 case MO_64: 2538#endif 2539 tcg_gen_ld_tl(s->T0, tcg_env, decode->op[2].offset); 2540 break; 2541 default: 2542 abort(); 2543 } 2544} 2545 2546static void gen_MOVD_to(DisasContext *s, X86DecodedInsn *decode) 2547{ 2548 MemOp ot = decode->op[2].ot; 2549 int vec_len = vector_len(s, decode); 2550 int lo_ofs = vector_elem_offset(&decode->op[0], ot, 0); 2551 2552 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 2553 2554 switch (ot) { 2555 case MO_32: 2556#ifdef TARGET_X86_64 2557 tcg_gen_st32_tl(s->T1, tcg_env, lo_ofs); 2558 break; 2559 case MO_64: 2560#endif 2561 tcg_gen_st_tl(s->T1, tcg_env, lo_ofs); 2562 break; 2563 default: 2564 g_assert_not_reached(); 2565 } 2566} 2567 2568static void gen_MOVDQ(DisasContext *s, X86DecodedInsn *decode) 2569{ 2570 gen_store_sse(s, decode, decode->op[2].offset); 2571} 2572 2573static void gen_MOVMSK(DisasContext *s, X86DecodedInsn *decode) 2574{ 2575 typeof(gen_helper_movmskps_ymm) *ps, *pd, *fn; 2576 ps = s->vex_l ? gen_helper_movmskps_ymm : gen_helper_movmskps_xmm; 2577 pd = s->vex_l ? gen_helper_movmskpd_ymm : gen_helper_movmskpd_xmm; 2578 fn = s->prefix & PREFIX_DATA ? pd : ps; 2579 fn(s->tmp2_i32, tcg_env, OP_PTR2); 2580 tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32); 2581} 2582 2583static void gen_MOVQ(DisasContext *s, X86DecodedInsn *decode) 2584{ 2585 int vec_len = vector_len(s, decode); 2586 int lo_ofs = vector_elem_offset(&decode->op[0], MO_64, 0); 2587 2588 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset); 2589 if (decode->op[0].has_ea) { 2590 tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEUQ); 2591 } else { 2592 /* 2593 * tcg_gen_gvec_dup_i64(MO_64, op0.offset, 8, vec_len, s->tmp1_64) would 2594 * seem to work, but it does not on big-endian platforms; the cleared parts 2595 * are always at higher addresses, but cross-endian emulation inverts the 2596 * byte order so that the cleared parts need to be at *lower* addresses. 2597 * Because oprsz is 8, we see this here even for SSE; but more in general, 2598 * it disqualifies using oprsz < maxsz to emulate VEX128. 2599 */ 2600 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 2601 tcg_gen_st_i64(s->tmp1_i64, tcg_env, lo_ofs); 2602 } 2603} 2604 2605static void gen_MOVq_dq(DisasContext *s, X86DecodedInsn *decode) 2606{ 2607 gen_helper_enter_mmx(tcg_env); 2608 /* Otherwise the same as any other movq. */ 2609 return gen_MOVQ(s, decode); 2610} 2611 2612static void gen_MOVS(DisasContext *s, X86DecodedInsn *decode) 2613{ 2614 MemOp ot = decode->op[2].ot; 2615 gen_repz(s, ot, gen_movs); 2616} 2617 2618static void gen_MUL(DisasContext *s, X86DecodedInsn *decode) 2619{ 2620 MemOp ot = decode->op[1].ot; 2621 2622 switch (ot) { 2623 case MO_8: 2624 /* s->T0 already zero-extended */ 2625 tcg_gen_ext8u_tl(s->T1, s->T1); 2626 tcg_gen_mul_tl(s->T0, s->T0, s->T1); 2627 gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0); 2628 tcg_gen_andi_tl(s->T1, s->T0, 0xff00); 2629 decode->cc_dst = s->T0; 2630 decode->cc_src = s->T1; 2631 break; 2632 2633 case MO_16: 2634 /* s->T0 already zero-extended */ 2635 tcg_gen_ext16u_tl(s->T1, s->T1); 2636 tcg_gen_mul_tl(s->T0, s->T0, s->T1); 2637 gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0); 2638 tcg_gen_shri_tl(s->T1, s->T0, 16); 2639 gen_op_mov_reg_v(s, MO_16, R_EDX, s->T1); 2640 decode->cc_dst = s->T0; 2641 decode->cc_src = s->T1; 2642 break; 2643 2644 case MO_32: 2645#ifdef TARGET_X86_64 2646 /* s->T0 already zero-extended */ 2647 tcg_gen_ext32u_tl(s->T1, s->T1); 2648 tcg_gen_mul_tl(s->T0, s->T0, s->T1); 2649 tcg_gen_ext32u_tl(cpu_regs[R_EAX], s->T0); 2650 tcg_gen_shri_tl(cpu_regs[R_EDX], s->T0, 32); 2651 decode->cc_dst = cpu_regs[R_EAX]; 2652 decode->cc_src = cpu_regs[R_EDX]; 2653 break; 2654 2655 case MO_64: 2656#endif 2657 tcg_gen_mulu2_tl(cpu_regs[R_EAX], cpu_regs[R_EDX], s->T0, s->T1); 2658 decode->cc_dst = cpu_regs[R_EAX]; 2659 decode->cc_src = cpu_regs[R_EDX]; 2660 break; 2661 2662 default: 2663 g_assert_not_reached(); 2664 } 2665 2666 decode->cc_op = CC_OP_MULB + ot; 2667} 2668 2669static void gen_MULX(DisasContext *s, X86DecodedInsn *decode) 2670{ 2671 MemOp ot = decode->op[0].ot; 2672 2673 /* low part of result in VEX.vvvv, high in MODRM */ 2674 switch (ot) { 2675 case MO_32: 2676#ifdef TARGET_X86_64 2677 tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); 2678 tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1); 2679 tcg_gen_mulu2_i32(s->tmp2_i32, s->tmp3_i32, 2680 s->tmp2_i32, s->tmp3_i32); 2681 tcg_gen_extu_i32_tl(cpu_regs[s->vex_v], s->tmp2_i32); 2682 tcg_gen_extu_i32_tl(s->T0, s->tmp3_i32); 2683 break; 2684 2685 case MO_64: 2686#endif 2687 tcg_gen_mulu2_tl(cpu_regs[s->vex_v], s->T0, s->T0, s->T1); 2688 break; 2689 2690 default: 2691 g_assert_not_reached(); 2692 } 2693} 2694 2695static void gen_NEG(DisasContext *s, X86DecodedInsn *decode) 2696{ 2697 MemOp ot = decode->op[0].ot; 2698 TCGv oldv = tcg_temp_new(); 2699 2700 if (s->prefix & PREFIX_LOCK) { 2701 TCGv newv = tcg_temp_new(); 2702 TCGv cmpv = tcg_temp_new(); 2703 TCGLabel *label1 = gen_new_label(); 2704 2705 gen_set_label(label1); 2706 gen_op_ld_v(s, ot, oldv, s->A0); 2707 tcg_gen_neg_tl(newv, oldv); 2708 tcg_gen_atomic_cmpxchg_tl(cmpv, s->A0, oldv, newv, 2709 s->mem_index, ot | MO_LE); 2710 tcg_gen_brcond_tl(TCG_COND_NE, oldv, cmpv, label1); 2711 } else { 2712 tcg_gen_mov_tl(oldv, s->T0); 2713 } 2714 tcg_gen_neg_tl(s->T0, oldv); 2715 2716 decode->cc_dst = s->T0; 2717 decode->cc_src = oldv; 2718 tcg_gen_movi_tl(s->cc_srcT, 0); 2719 decode->cc_op = CC_OP_SUBB + ot; 2720} 2721 2722static void gen_NOT(DisasContext *s, X86DecodedInsn *decode) 2723{ 2724 MemOp ot = decode->op[0].ot; 2725 2726 if (s->prefix & PREFIX_LOCK) { 2727 tcg_gen_movi_tl(s->T0, ~0); 2728 tcg_gen_atomic_xor_fetch_tl(s->T0, s->A0, s->T0, 2729 s->mem_index, ot | MO_LE); 2730 } else { 2731 tcg_gen_not_tl(s->T0, s->T0); 2732 } 2733} 2734 2735static void gen_OR(DisasContext *s, X86DecodedInsn *decode) 2736{ 2737 MemOp ot = decode->op[1].ot; 2738 2739 if (s->prefix & PREFIX_LOCK) { 2740 tcg_gen_atomic_or_fetch_tl(s->T0, s->A0, s->T1, 2741 s->mem_index, ot | MO_LE); 2742 } else { 2743 tcg_gen_or_tl(s->T0, s->T0, s->T1); 2744 } 2745 prepare_update1_cc(decode, s, CC_OP_LOGICB + ot); 2746} 2747 2748static void gen_OUT(DisasContext *s, X86DecodedInsn *decode) 2749{ 2750 MemOp ot = decode->op[1].ot; 2751 TCGv_i32 port = tcg_temp_new_i32(); 2752 TCGv_i32 value = tcg_temp_new_i32(); 2753 2754 tcg_gen_trunc_tl_i32(port, s->T1); 2755 tcg_gen_ext16u_i32(port, port); 2756 if (!gen_check_io(s, ot, port, 0)) { 2757 return; 2758 } 2759 tcg_gen_trunc_tl_i32(value, s->T0); 2760 translator_io_start(&s->base); 2761 gen_helper_out_func(ot, port, value); 2762 gen_bpt_io(s, port, ot); 2763} 2764 2765static void gen_OUTS(DisasContext *s, X86DecodedInsn *decode) 2766{ 2767 MemOp ot = decode->op[1].ot; 2768 TCGv_i32 port = tcg_temp_new_i32(); 2769 2770 tcg_gen_trunc_tl_i32(port, s->T1); 2771 tcg_gen_ext16u_i32(port, port); 2772 if (!gen_check_io(s, ot, port, SVM_IOIO_STR_MASK)) { 2773 return; 2774 } 2775 2776 translator_io_start(&s->base); 2777 gen_repz(s, ot, gen_outs); 2778} 2779 2780static void gen_PALIGNR(DisasContext *s, X86DecodedInsn *decode) 2781{ 2782 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 2783 if (!(s->prefix & PREFIX_DATA)) { 2784 gen_helper_palignr_mmx(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); 2785 } else if (!s->vex_l) { 2786 gen_helper_palignr_xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); 2787 } else { 2788 gen_helper_palignr_ymm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); 2789 } 2790} 2791 2792static void gen_PANDN(DisasContext *s, X86DecodedInsn *decode) 2793{ 2794 int vec_len = vector_len(s, decode); 2795 2796 /* Careful, operand order is reversed! */ 2797 tcg_gen_gvec_andc(MO_64, 2798 decode->op[0].offset, decode->op[2].offset, 2799 decode->op[1].offset, vec_len, vec_len); 2800} 2801 2802static void gen_PAUSE(DisasContext *s, X86DecodedInsn *decode) 2803{ 2804 gen_update_cc_op(s); 2805 gen_update_eip_next(s); 2806 gen_helper_pause(tcg_env); 2807 s->base.is_jmp = DISAS_NORETURN; 2808} 2809 2810static void gen_PCMPESTRI(DisasContext *s, X86DecodedInsn *decode) 2811{ 2812 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 2813 gen_helper_pcmpestri_xmm(tcg_env, OP_PTR1, OP_PTR2, imm); 2814 assume_cc_op(s, CC_OP_EFLAGS); 2815} 2816 2817static void gen_PCMPESTRM(DisasContext *s, X86DecodedInsn *decode) 2818{ 2819 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 2820 gen_helper_pcmpestrm_xmm(tcg_env, OP_PTR1, OP_PTR2, imm); 2821 assume_cc_op(s, CC_OP_EFLAGS); 2822 if ((s->prefix & PREFIX_VEX) && !s->vex_l) { 2823 tcg_gen_gvec_dup_imm(MO_64, offsetof(CPUX86State, xmm_regs[0].ZMM_X(1)), 2824 16, 16, 0); 2825 } 2826} 2827 2828static void gen_PCMPISTRI(DisasContext *s, X86DecodedInsn *decode) 2829{ 2830 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 2831 gen_helper_pcmpistri_xmm(tcg_env, OP_PTR1, OP_PTR2, imm); 2832 assume_cc_op(s, CC_OP_EFLAGS); 2833} 2834 2835static void gen_PCMPISTRM(DisasContext *s, X86DecodedInsn *decode) 2836{ 2837 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 2838 gen_helper_pcmpistrm_xmm(tcg_env, OP_PTR1, OP_PTR2, imm); 2839 assume_cc_op(s, CC_OP_EFLAGS); 2840 if ((s->prefix & PREFIX_VEX) && !s->vex_l) { 2841 tcg_gen_gvec_dup_imm(MO_64, offsetof(CPUX86State, xmm_regs[0].ZMM_X(1)), 2842 16, 16, 0); 2843 } 2844} 2845 2846static void gen_PDEP(DisasContext *s, X86DecodedInsn *decode) 2847{ 2848 gen_helper_pdep(s->T0, s->T0, s->T1); 2849} 2850 2851static void gen_PEXT(DisasContext *s, X86DecodedInsn *decode) 2852{ 2853 gen_helper_pext(s->T0, s->T0, s->T1); 2854} 2855 2856static inline void gen_pextr(DisasContext *s, X86DecodedInsn *decode, MemOp ot) 2857{ 2858 int vec_len = vector_len(s, decode); 2859 int mask = (vec_len >> ot) - 1; 2860 int val = decode->immediate & mask; 2861 2862 switch (ot) { 2863 case MO_8: 2864 tcg_gen_ld8u_tl(s->T0, tcg_env, vector_elem_offset(&decode->op[1], ot, val)); 2865 break; 2866 case MO_16: 2867 tcg_gen_ld16u_tl(s->T0, tcg_env, vector_elem_offset(&decode->op[1], ot, val)); 2868 break; 2869 case MO_32: 2870#ifdef TARGET_X86_64 2871 tcg_gen_ld32u_tl(s->T0, tcg_env, vector_elem_offset(&decode->op[1], ot, val)); 2872 break; 2873 case MO_64: 2874#endif 2875 tcg_gen_ld_tl(s->T0, tcg_env, vector_elem_offset(&decode->op[1], ot, val)); 2876 break; 2877 default: 2878 abort(); 2879 } 2880} 2881 2882static void gen_PEXTRB(DisasContext *s, X86DecodedInsn *decode) 2883{ 2884 gen_pextr(s, decode, MO_8); 2885} 2886 2887static void gen_PEXTRW(DisasContext *s, X86DecodedInsn *decode) 2888{ 2889 gen_pextr(s, decode, MO_16); 2890} 2891 2892static void gen_PEXTR(DisasContext *s, X86DecodedInsn *decode) 2893{ 2894 MemOp ot = decode->op[0].ot; 2895 gen_pextr(s, decode, ot); 2896} 2897 2898static inline void gen_pinsr(DisasContext *s, X86DecodedInsn *decode, MemOp ot) 2899{ 2900 int vec_len = vector_len(s, decode); 2901 int mask = (vec_len >> ot) - 1; 2902 int val = decode->immediate & mask; 2903 2904 if (decode->op[1].offset != decode->op[0].offset) { 2905 assert(vec_len == 16); 2906 gen_store_sse(s, decode, decode->op[1].offset); 2907 } 2908 2909 switch (ot) { 2910 case MO_8: 2911 tcg_gen_st8_tl(s->T1, tcg_env, vector_elem_offset(&decode->op[0], ot, val)); 2912 break; 2913 case MO_16: 2914 tcg_gen_st16_tl(s->T1, tcg_env, vector_elem_offset(&decode->op[0], ot, val)); 2915 break; 2916 case MO_32: 2917#ifdef TARGET_X86_64 2918 tcg_gen_st32_tl(s->T1, tcg_env, vector_elem_offset(&decode->op[0], ot, val)); 2919 break; 2920 case MO_64: 2921#endif 2922 tcg_gen_st_tl(s->T1, tcg_env, vector_elem_offset(&decode->op[0], ot, val)); 2923 break; 2924 default: 2925 abort(); 2926 } 2927} 2928 2929static void gen_PINSRB(DisasContext *s, X86DecodedInsn *decode) 2930{ 2931 gen_pinsr(s, decode, MO_8); 2932} 2933 2934static void gen_PINSRW(DisasContext *s, X86DecodedInsn *decode) 2935{ 2936 gen_pinsr(s, decode, MO_16); 2937} 2938 2939static void gen_PINSR(DisasContext *s, X86DecodedInsn *decode) 2940{ 2941 gen_pinsr(s, decode, decode->op[2].ot); 2942} 2943 2944static void gen_pmovmskb_i64(TCGv_i64 d, TCGv_i64 s) 2945{ 2946 TCGv_i64 t = tcg_temp_new_i64(); 2947 2948 tcg_gen_andi_i64(d, s, 0x8080808080808080ull); 2949 2950 /* 2951 * After each shift+or pair: 2952 * 0: a.......b.......c.......d.......e.......f.......g.......h....... 2953 * 7: ab......bc......cd......de......ef......fg......gh......h....... 2954 * 14: abcd....bcde....cdef....defg....efgh....fgh.....gh......h....... 2955 * 28: abcdefghbcdefgh.cdefgh..defgh...efgh....fgh.....gh......h....... 2956 * The result is left in the high bits of the word. 2957 */ 2958 tcg_gen_shli_i64(t, d, 7); 2959 tcg_gen_or_i64(d, d, t); 2960 tcg_gen_shli_i64(t, d, 14); 2961 tcg_gen_or_i64(d, d, t); 2962 tcg_gen_shli_i64(t, d, 28); 2963 tcg_gen_or_i64(d, d, t); 2964} 2965 2966static void gen_pmovmskb_vec(unsigned vece, TCGv_vec d, TCGv_vec s) 2967{ 2968 TCGv_vec t = tcg_temp_new_vec_matching(d); 2969 TCGv_vec m = tcg_constant_vec_matching(d, MO_8, 0x80); 2970 2971 /* See above */ 2972 tcg_gen_and_vec(vece, d, s, m); 2973 tcg_gen_shli_vec(vece, t, d, 7); 2974 tcg_gen_or_vec(vece, d, d, t); 2975 tcg_gen_shli_vec(vece, t, d, 14); 2976 tcg_gen_or_vec(vece, d, d, t); 2977 tcg_gen_shli_vec(vece, t, d, 28); 2978 tcg_gen_or_vec(vece, d, d, t); 2979} 2980 2981static void gen_PMOVMSKB(DisasContext *s, X86DecodedInsn *decode) 2982{ 2983 static const TCGOpcode vecop_list[] = { INDEX_op_shli_vec, 0 }; 2984 static const GVecGen2 g = { 2985 .fni8 = gen_pmovmskb_i64, 2986 .fniv = gen_pmovmskb_vec, 2987 .opt_opc = vecop_list, 2988 .vece = MO_64, 2989 .prefer_i64 = TCG_TARGET_REG_BITS == 64 2990 }; 2991 MemOp ot = decode->op[2].ot; 2992 int vec_len = vector_len(s, decode); 2993 TCGv t = tcg_temp_new(); 2994 2995 tcg_gen_gvec_2(offsetof(CPUX86State, xmm_t0) + xmm_offset(ot), decode->op[2].offset, 2996 vec_len, vec_len, &g); 2997 tcg_gen_ld8u_tl(s->T0, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_B(vec_len - 1))); 2998 while (vec_len > 8) { 2999 vec_len -= 8; 3000 if (tcg_op_supported(INDEX_op_extract2_tl, TCG_TYPE_TL, 0)) { 3001 /* 3002 * Load the next byte of the result into the high byte of T. 3003 * TCG does a similar expansion of deposit to shl+extract2; by 3004 * loading the whole word, the shift left is avoided. 3005 */ 3006#ifdef TARGET_X86_64 3007 tcg_gen_ld_tl(t, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_Q((vec_len - 1) / 8))); 3008#else 3009 tcg_gen_ld_tl(t, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_L((vec_len - 1) / 4))); 3010#endif 3011 3012 tcg_gen_extract2_tl(s->T0, t, s->T0, TARGET_LONG_BITS - 8); 3013 } else { 3014 /* 3015 * The _previous_ value is deposited into bits 8 and higher of t. Because 3016 * those bits are known to be zero after ld8u, this becomes a shift+or 3017 * if deposit is not available. 3018 */ 3019 tcg_gen_ld8u_tl(t, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_B(vec_len - 1))); 3020 tcg_gen_deposit_tl(s->T0, t, s->T0, 8, TARGET_LONG_BITS - 8); 3021 } 3022 } 3023} 3024 3025static void gen_POP(DisasContext *s, X86DecodedInsn *decode) 3026{ 3027 X86DecodedOp *op = &decode->op[0]; 3028 MemOp ot = gen_pop_T0(s); 3029 3030 assert(ot >= op->ot); 3031 if (op->has_ea || op->unit == X86_OP_SEG) { 3032 /* NOTE: order is important for MMU exceptions */ 3033 gen_writeback(s, decode, 0, s->T0); 3034 } 3035 3036 /* NOTE: writing back registers after update is important for pop %sp */ 3037 gen_pop_update(s, ot); 3038} 3039 3040static void gen_POPA(DisasContext *s, X86DecodedInsn *decode) 3041{ 3042 gen_popa(s); 3043} 3044 3045static void gen_POPCNT(DisasContext *s, X86DecodedInsn *decode) 3046{ 3047 decode->cc_dst = tcg_temp_new(); 3048 decode->cc_op = CC_OP_POPCNT; 3049 3050 tcg_gen_mov_tl(decode->cc_dst, s->T0); 3051 tcg_gen_ctpop_tl(s->T0, s->T0); 3052} 3053 3054static void gen_POPF(DisasContext *s, X86DecodedInsn *decode) 3055{ 3056 MemOp ot; 3057 int mask = TF_MASK | AC_MASK | ID_MASK | NT_MASK; 3058 3059 if (CPL(s) == 0) { 3060 mask |= IF_MASK | IOPL_MASK; 3061 } else if (CPL(s) <= IOPL(s)) { 3062 mask |= IF_MASK; 3063 } 3064 if (s->dflag == MO_16) { 3065 mask &= 0xffff; 3066 } 3067 3068 ot = gen_pop_T0(s); 3069 gen_helper_write_eflags(tcg_env, s->T0, tcg_constant_i32(mask)); 3070 gen_pop_update(s, ot); 3071 set_cc_op(s, CC_OP_EFLAGS); 3072 /* abort translation because TF/AC flag may change */ 3073 s->base.is_jmp = DISAS_EOB_NEXT; 3074} 3075 3076static void gen_PSHUFW(DisasContext *s, X86DecodedInsn *decode) 3077{ 3078 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 3079 gen_helper_pshufw_mmx(OP_PTR0, OP_PTR1, imm); 3080} 3081 3082static void gen_PSRLW_i(DisasContext *s, X86DecodedInsn *decode) 3083{ 3084 int vec_len = vector_len(s, decode); 3085 3086 if (decode->immediate >= 16) { 3087 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 3088 } else { 3089 tcg_gen_gvec_shri(MO_16, 3090 decode->op[0].offset, decode->op[1].offset, 3091 decode->immediate, vec_len, vec_len); 3092 } 3093} 3094 3095static void gen_PSLLW_i(DisasContext *s, X86DecodedInsn *decode) 3096{ 3097 int vec_len = vector_len(s, decode); 3098 3099 if (decode->immediate >= 16) { 3100 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 3101 } else { 3102 tcg_gen_gvec_shli(MO_16, 3103 decode->op[0].offset, decode->op[1].offset, 3104 decode->immediate, vec_len, vec_len); 3105 } 3106} 3107 3108static void gen_PSRAW_i(DisasContext *s, X86DecodedInsn *decode) 3109{ 3110 int vec_len = vector_len(s, decode); 3111 3112 if (decode->immediate >= 16) { 3113 decode->immediate = 15; 3114 } 3115 tcg_gen_gvec_sari(MO_16, 3116 decode->op[0].offset, decode->op[1].offset, 3117 decode->immediate, vec_len, vec_len); 3118} 3119 3120static void gen_PSRLD_i(DisasContext *s, X86DecodedInsn *decode) 3121{ 3122 int vec_len = vector_len(s, decode); 3123 3124 if (decode->immediate >= 32) { 3125 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 3126 } else { 3127 tcg_gen_gvec_shri(MO_32, 3128 decode->op[0].offset, decode->op[1].offset, 3129 decode->immediate, vec_len, vec_len); 3130 } 3131} 3132 3133static void gen_PSLLD_i(DisasContext *s, X86DecodedInsn *decode) 3134{ 3135 int vec_len = vector_len(s, decode); 3136 3137 if (decode->immediate >= 32) { 3138 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 3139 } else { 3140 tcg_gen_gvec_shli(MO_32, 3141 decode->op[0].offset, decode->op[1].offset, 3142 decode->immediate, vec_len, vec_len); 3143 } 3144} 3145 3146static void gen_PSRAD_i(DisasContext *s, X86DecodedInsn *decode) 3147{ 3148 int vec_len = vector_len(s, decode); 3149 3150 if (decode->immediate >= 32) { 3151 decode->immediate = 31; 3152 } 3153 tcg_gen_gvec_sari(MO_32, 3154 decode->op[0].offset, decode->op[1].offset, 3155 decode->immediate, vec_len, vec_len); 3156} 3157 3158static void gen_PSRLQ_i(DisasContext *s, X86DecodedInsn *decode) 3159{ 3160 int vec_len = vector_len(s, decode); 3161 3162 if (decode->immediate >= 64) { 3163 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 3164 } else { 3165 tcg_gen_gvec_shri(MO_64, 3166 decode->op[0].offset, decode->op[1].offset, 3167 decode->immediate, vec_len, vec_len); 3168 } 3169} 3170 3171static void gen_PSLLQ_i(DisasContext *s, X86DecodedInsn *decode) 3172{ 3173 int vec_len = vector_len(s, decode); 3174 3175 if (decode->immediate >= 64) { 3176 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 3177 } else { 3178 tcg_gen_gvec_shli(MO_64, 3179 decode->op[0].offset, decode->op[1].offset, 3180 decode->immediate, vec_len, vec_len); 3181 } 3182} 3183 3184static TCGv_ptr make_imm8u_xmm_vec(uint8_t imm, int vec_len) 3185{ 3186 MemOp ot = vec_len == 16 ? MO_128 : MO_256; 3187 TCGv_i32 imm_v = tcg_constant8u_i32(imm); 3188 TCGv_ptr ptr = tcg_temp_new_ptr(); 3189 3190 tcg_gen_gvec_dup_imm(MO_64, offsetof(CPUX86State, xmm_t0) + xmm_offset(ot), 3191 vec_len, vec_len, 0); 3192 3193 tcg_gen_addi_ptr(ptr, tcg_env, offsetof(CPUX86State, xmm_t0)); 3194 tcg_gen_st_i32(imm_v, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_L(0))); 3195 return ptr; 3196} 3197 3198static void gen_PSRLDQ_i(DisasContext *s, X86DecodedInsn *decode) 3199{ 3200 int vec_len = vector_len(s, decode); 3201 TCGv_ptr imm_vec = make_imm8u_xmm_vec(decode->immediate, vec_len); 3202 3203 if (s->vex_l) { 3204 gen_helper_psrldq_ymm(tcg_env, OP_PTR0, OP_PTR1, imm_vec); 3205 } else { 3206 gen_helper_psrldq_xmm(tcg_env, OP_PTR0, OP_PTR1, imm_vec); 3207 } 3208} 3209 3210static void gen_PSLLDQ_i(DisasContext *s, X86DecodedInsn *decode) 3211{ 3212 int vec_len = vector_len(s, decode); 3213 TCGv_ptr imm_vec = make_imm8u_xmm_vec(decode->immediate, vec_len); 3214 3215 if (s->vex_l) { 3216 gen_helper_pslldq_ymm(tcg_env, OP_PTR0, OP_PTR1, imm_vec); 3217 } else { 3218 gen_helper_pslldq_xmm(tcg_env, OP_PTR0, OP_PTR1, imm_vec); 3219 } 3220} 3221 3222static void gen_PUSH(DisasContext *s, X86DecodedInsn *decode) 3223{ 3224 gen_push_v(s, s->T0); 3225} 3226 3227static void gen_PUSHA(DisasContext *s, X86DecodedInsn *decode) 3228{ 3229 gen_pusha(s); 3230} 3231 3232static void gen_PUSHF(DisasContext *s, X86DecodedInsn *decode) 3233{ 3234 gen_update_cc_op(s); 3235 gen_helper_read_eflags(s->T0, tcg_env); 3236 gen_push_v(s, s->T0); 3237} 3238 3239static MemOp gen_shift_count(DisasContext *s, X86DecodedInsn *decode, 3240 bool *can_be_zero, TCGv *count, int unit) 3241{ 3242 MemOp ot = decode->op[0].ot; 3243 int mask = (ot <= MO_32 ? 0x1f : 0x3f); 3244 3245 *can_be_zero = false; 3246 switch (unit) { 3247 case X86_OP_INT: 3248 *count = tcg_temp_new(); 3249 tcg_gen_andi_tl(*count, cpu_regs[R_ECX], mask); 3250 *can_be_zero = true; 3251 break; 3252 3253 case X86_OP_IMM: 3254 if ((decode->immediate & mask) == 0) { 3255 *count = NULL; 3256 break; 3257 } 3258 *count = tcg_temp_new(); 3259 tcg_gen_movi_tl(*count, decode->immediate & mask); 3260 break; 3261 3262 case X86_OP_SKIP: 3263 *count = tcg_temp_new(); 3264 tcg_gen_movi_tl(*count, 1); 3265 break; 3266 3267 default: 3268 g_assert_not_reached(); 3269 } 3270 3271 return ot; 3272} 3273 3274/* 3275 * Compute existing flags in decode->cc_src, for gen_* functions that wants 3276 * to set the cc_op set to CC_OP_ADCOX. In particular, this allows rotate 3277 * operations to compute the carry in decode->cc_dst and the overflow in 3278 * decode->cc_src2. 3279 * 3280 * If need_flags is true, decode->cc_dst and decode->cc_src2 are preloaded 3281 * with the value of CF and OF before the instruction, so that it is possible 3282 * to keep the flags unmodified. 3283 * 3284 * Return true if carry could be made available cheaply as a 1-bit value in 3285 * decode->cc_dst (trying a bit harder if want_carry is true). If false is 3286 * returned, decode->cc_dst is uninitialized and the carry is only available 3287 * as bit 0 of decode->cc_src. 3288 */ 3289static bool gen_eflags_adcox(DisasContext *s, X86DecodedInsn *decode, bool want_carry, bool need_flags) 3290{ 3291 bool got_cf = false; 3292 bool got_of = false; 3293 3294 decode->cc_dst = tcg_temp_new(); 3295 decode->cc_src = tcg_temp_new(); 3296 decode->cc_src2 = tcg_temp_new(); 3297 decode->cc_op = CC_OP_ADCOX; 3298 3299 /* A lot more cc_ops could be "optimized" to avoid the extracts at 3300 * the end (INC/DEC, BMILG, MUL), but they are all really unlikely 3301 * to be followed by rotations within the same basic block. 3302 */ 3303 switch (s->cc_op) { 3304 case CC_OP_ADCOX: 3305 /* No need to compute the full EFLAGS, CF/OF are already isolated. */ 3306 tcg_gen_mov_tl(decode->cc_src, cpu_cc_src); 3307 if (need_flags) { 3308 tcg_gen_mov_tl(decode->cc_src2, cpu_cc_src2); 3309 got_of = true; 3310 } 3311 if (want_carry || need_flags) { 3312 tcg_gen_mov_tl(decode->cc_dst, cpu_cc_dst); 3313 got_cf = true; 3314 } 3315 break; 3316 3317 case CC_OP_LOGICB ... CC_OP_LOGICQ: 3318 /* CF and OF are zero, do it just because it's easy. */ 3319 gen_mov_eflags(s, decode->cc_src); 3320 if (need_flags) { 3321 tcg_gen_movi_tl(decode->cc_src2, 0); 3322 got_of = true; 3323 } 3324 if (want_carry || need_flags) { 3325 tcg_gen_movi_tl(decode->cc_dst, 0); 3326 got_cf = true; 3327 } 3328 break; 3329 3330 case CC_OP_SARB ... CC_OP_SARQ: 3331 /* 3332 * SHR/RCR/SHR/RCR/... is a relatively common occurrence of RCR. 3333 * By computing CF without using eflags, the calls to cc_compute_all 3334 * can be eliminated as dead code (except for the last RCR). 3335 */ 3336 if (want_carry || need_flags) { 3337 tcg_gen_andi_tl(decode->cc_dst, cpu_cc_src, 1); 3338 got_cf = true; 3339 } 3340 gen_mov_eflags(s, decode->cc_src); 3341 break; 3342 3343 case CC_OP_SHLB ... CC_OP_SHLQ: 3344 /* 3345 * Likewise for SHL/RCL/SHL/RCL/... but, if CF is not in the sign 3346 * bit, we might as well fish CF out of EFLAGS and save a shift. 3347 */ 3348 if (want_carry && (!need_flags || s->cc_op == CC_OP_SHLB + MO_TL)) { 3349 MemOp size = cc_op_size(s->cc_op); 3350 tcg_gen_shri_tl(decode->cc_dst, cpu_cc_src, (8 << size) - 1); 3351 got_cf = true; 3352 } 3353 gen_mov_eflags(s, decode->cc_src); 3354 break; 3355 3356 default: 3357 gen_mov_eflags(s, decode->cc_src); 3358 break; 3359 } 3360 3361 if (need_flags) { 3362 /* If the flags could be left unmodified, always load them. */ 3363 if (!got_of) { 3364 tcg_gen_extract_tl(decode->cc_src2, decode->cc_src, ctz32(CC_O), 1); 3365 got_of = true; 3366 } 3367 if (!got_cf) { 3368 tcg_gen_extract_tl(decode->cc_dst, decode->cc_src, ctz32(CC_C), 1); 3369 got_cf = true; 3370 } 3371 } 3372 return got_cf; 3373} 3374 3375static void gen_rot_overflow(X86DecodedInsn *decode, TCGv result, TCGv old, 3376 bool can_be_zero, TCGv count) 3377{ 3378 MemOp ot = decode->op[0].ot; 3379 TCGv temp = can_be_zero ? tcg_temp_new() : decode->cc_src2; 3380 3381 tcg_gen_xor_tl(temp, old, result); 3382 tcg_gen_extract_tl(temp, temp, (8 << ot) - 1, 1); 3383 if (can_be_zero) { 3384 tcg_gen_movcond_tl(TCG_COND_EQ, decode->cc_src2, count, tcg_constant_tl(0), 3385 decode->cc_src2, temp); 3386 } 3387} 3388 3389/* 3390 * RCx operations are invariant modulo 8*operand_size+1. For 8 and 16-bit operands, 3391 * this is less than 0x1f (the mask applied by gen_shift_count) so reduce further. 3392 */ 3393static void gen_rotc_mod(MemOp ot, TCGv count) 3394{ 3395 TCGv temp; 3396 3397 switch (ot) { 3398 case MO_8: 3399 temp = tcg_temp_new(); 3400 tcg_gen_subi_tl(temp, count, 18); 3401 tcg_gen_movcond_tl(TCG_COND_GE, count, temp, tcg_constant_tl(0), temp, count); 3402 tcg_gen_subi_tl(temp, count, 9); 3403 tcg_gen_movcond_tl(TCG_COND_GE, count, temp, tcg_constant_tl(0), temp, count); 3404 break; 3405 3406 case MO_16: 3407 temp = tcg_temp_new(); 3408 tcg_gen_subi_tl(temp, count, 17); 3409 tcg_gen_movcond_tl(TCG_COND_GE, count, temp, tcg_constant_tl(0), temp, count); 3410 break; 3411 3412 default: 3413 break; 3414 } 3415} 3416 3417/* 3418 * The idea here is that the bit to the right of the new bit 0 is the 3419 * new carry, and the bit to the right of the old bit 0 is the old carry. 3420 * Just like a regular rotation, the result of the rotation is composed 3421 * from a right shifted part and a left shifted part of s->T0. The new carry 3422 * is extracted from the right-shifted portion, and the old carry is 3423 * inserted at the end of the left-shifted portion. 3424 * 3425 * Because of the separate shifts involving the carry, gen_RCL and gen_RCR 3426 * mostly operate on count-1. This also comes in handy when computing 3427 * length - count, because (length-1) - (count-1) can be computed with 3428 * a XOR, and that is commutative unlike subtraction. 3429 */ 3430static void gen_RCL(DisasContext *s, X86DecodedInsn *decode) 3431{ 3432 bool have_1bit_cin, can_be_zero; 3433 TCGv count; 3434 TCGLabel *zero_label = NULL; 3435 MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); 3436 TCGv low, high, low_count; 3437 3438 if (!count) { 3439 return; 3440 } 3441 3442 low = tcg_temp_new(); 3443 high = tcg_temp_new(); 3444 low_count = tcg_temp_new(); 3445 3446 gen_rotc_mod(ot, count); 3447 have_1bit_cin = gen_eflags_adcox(s, decode, true, can_be_zero); 3448 if (can_be_zero) { 3449 zero_label = gen_new_label(); 3450 tcg_gen_brcondi_tl(TCG_COND_EQ, count, 0, zero_label); 3451 } 3452 3453 /* Compute high part, including incoming carry. */ 3454 if (!have_1bit_cin || tcg_op_deposit_valid(TCG_TYPE_TL, 1, TARGET_LONG_BITS - 1)) { 3455 /* high = (T0 << 1) | cin */ 3456 TCGv cin = have_1bit_cin ? decode->cc_dst : decode->cc_src; 3457 tcg_gen_deposit_tl(high, cin, s->T0, 1, TARGET_LONG_BITS - 1); 3458 } else { 3459 /* Same as above but without deposit; cin in cc_dst. */ 3460 tcg_gen_add_tl(high, s->T0, decode->cc_dst); 3461 tcg_gen_add_tl(high, high, s->T0); 3462 } 3463 tcg_gen_subi_tl(count, count, 1); 3464 tcg_gen_shl_tl(high, high, count); 3465 3466 /* Compute low part and outgoing carry, incoming s->T0 is zero extended */ 3467 tcg_gen_xori_tl(low_count, count, (8 << ot) - 1); /* LENGTH - 1 - (count - 1) */ 3468 tcg_gen_shr_tl(low, s->T0, low_count); 3469 tcg_gen_andi_tl(decode->cc_dst, low, 1); 3470 tcg_gen_shri_tl(low, low, 1); 3471 3472 /* Compute result and outgoing overflow */ 3473 tcg_gen_mov_tl(decode->cc_src2, s->T0); 3474 tcg_gen_or_tl(s->T0, low, high); 3475 gen_rot_overflow(decode, s->T0, decode->cc_src2, false, NULL); 3476 3477 if (zero_label) { 3478 gen_set_label(zero_label); 3479 } 3480} 3481 3482static void gen_RCR(DisasContext *s, X86DecodedInsn *decode) 3483{ 3484 bool have_1bit_cin, can_be_zero; 3485 TCGv count; 3486 TCGLabel *zero_label = NULL; 3487 MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); 3488 TCGv low, high, high_count; 3489 3490 if (!count) { 3491 return; 3492 } 3493 3494 low = tcg_temp_new(); 3495 high = tcg_temp_new(); 3496 high_count = tcg_temp_new(); 3497 3498 gen_rotc_mod(ot, count); 3499 have_1bit_cin = gen_eflags_adcox(s, decode, true, can_be_zero); 3500 if (can_be_zero) { 3501 zero_label = gen_new_label(); 3502 tcg_gen_brcondi_tl(TCG_COND_EQ, count, 0, zero_label); 3503 } 3504 3505 /* Save incoming carry into high, it will be shifted later. */ 3506 if (!have_1bit_cin || tcg_op_deposit_valid(TCG_TYPE_TL, 1, TARGET_LONG_BITS - 1)) { 3507 TCGv cin = have_1bit_cin ? decode->cc_dst : decode->cc_src; 3508 tcg_gen_deposit_tl(high, cin, s->T0, 1, TARGET_LONG_BITS - 1); 3509 } else { 3510 /* Same as above but without deposit; cin in cc_dst. */ 3511 tcg_gen_add_tl(high, s->T0, decode->cc_dst); 3512 tcg_gen_add_tl(high, high, s->T0); 3513 } 3514 3515 /* Compute low part and outgoing carry, incoming s->T0 is zero extended */ 3516 tcg_gen_subi_tl(count, count, 1); 3517 tcg_gen_shr_tl(low, s->T0, count); 3518 tcg_gen_andi_tl(decode->cc_dst, low, 1); 3519 tcg_gen_shri_tl(low, low, 1); 3520 3521 /* Move high part to the right position */ 3522 tcg_gen_xori_tl(high_count, count, (8 << ot) - 1); /* LENGTH - 1 - (count - 1) */ 3523 tcg_gen_shl_tl(high, high, high_count); 3524 3525 /* Compute result and outgoing overflow */ 3526 tcg_gen_mov_tl(decode->cc_src2, s->T0); 3527 tcg_gen_or_tl(s->T0, low, high); 3528 gen_rot_overflow(decode, s->T0, decode->cc_src2, false, NULL); 3529 3530 if (zero_label) { 3531 gen_set_label(zero_label); 3532 } 3533} 3534 3535#ifdef CONFIG_USER_ONLY 3536static void gen_unreachable(DisasContext *s, X86DecodedInsn *decode) 3537{ 3538 g_assert_not_reached(); 3539} 3540#endif 3541 3542#ifndef CONFIG_USER_ONLY 3543static void gen_RDMSR(DisasContext *s, X86DecodedInsn *decode) 3544{ 3545 gen_update_cc_op(s); 3546 gen_update_eip_cur(s); 3547 gen_helper_rdmsr(tcg_env); 3548} 3549#else 3550#define gen_RDMSR gen_unreachable 3551#endif 3552 3553static void gen_RDPMC(DisasContext *s, X86DecodedInsn *decode) 3554{ 3555 gen_update_cc_op(s); 3556 gen_update_eip_cur(s); 3557 translator_io_start(&s->base); 3558 gen_helper_rdpmc(tcg_env); 3559 s->base.is_jmp = DISAS_NORETURN; 3560} 3561 3562static void gen_RDTSC(DisasContext *s, X86DecodedInsn *decode) 3563{ 3564 gen_update_cc_op(s); 3565 gen_update_eip_cur(s); 3566 translator_io_start(&s->base); 3567 gen_helper_rdtsc(tcg_env); 3568} 3569 3570static void gen_RDxxBASE(DisasContext *s, X86DecodedInsn *decode) 3571{ 3572 TCGv base = cpu_seg_base[s->modrm & 8 ? R_GS : R_FS]; 3573 3574 /* Preserve hflags bits by testing CR4 at runtime. */ 3575 gen_helper_cr4_testbit(tcg_env, tcg_constant_i32(CR4_FSGSBASE_MASK)); 3576 tcg_gen_mov_tl(s->T0, base); 3577} 3578 3579static void gen_RET(DisasContext *s, X86DecodedInsn *decode) 3580{ 3581 int16_t adjust = decode->e.op1 == X86_TYPE_I ? decode->immediate : 0; 3582 3583 MemOp ot = gen_pop_T0(s); 3584 gen_stack_update(s, adjust + (1 << ot)); 3585 gen_op_jmp_v(s, s->T0); 3586 gen_bnd_jmp(s); 3587 s->base.is_jmp = DISAS_JUMP; 3588} 3589 3590static void gen_RETF(DisasContext *s, X86DecodedInsn *decode) 3591{ 3592 int16_t adjust = decode->e.op1 == X86_TYPE_I ? decode->immediate : 0; 3593 3594 if (!PE(s) || VM86(s)) { 3595 gen_lea_ss_ofs(s, s->A0, cpu_regs[R_ESP], 0); 3596 /* pop offset */ 3597 gen_op_ld_v(s, s->dflag, s->T0, s->A0); 3598 /* NOTE: keeping EIP updated is not a problem in case of 3599 exception */ 3600 gen_op_jmp_v(s, s->T0); 3601 /* pop selector */ 3602 gen_add_A0_im(s, 1 << s->dflag); 3603 gen_op_ld_v(s, s->dflag, s->T0, s->A0); 3604 gen_op_movl_seg_real(s, R_CS, s->T0); 3605 /* add stack offset */ 3606 gen_stack_update(s, adjust + (2 << s->dflag)); 3607 } else { 3608 gen_update_cc_op(s); 3609 gen_update_eip_cur(s); 3610 gen_helper_lret_protected(tcg_env, tcg_constant_i32(s->dflag - 1), 3611 tcg_constant_i32(adjust)); 3612 } 3613 s->base.is_jmp = DISAS_EOB_ONLY; 3614} 3615 3616/* 3617 * Return non-NULL if a 32-bit rotate works, after possibly replicating the input. 3618 * The input has already been zero-extended upon operand decode. 3619 */ 3620static TCGv_i32 gen_rot_replicate(MemOp ot, TCGv in) 3621{ 3622 TCGv_i32 temp; 3623 switch (ot) { 3624 case MO_8: 3625 temp = tcg_temp_new_i32(); 3626 tcg_gen_trunc_tl_i32(temp, in); 3627 tcg_gen_muli_i32(temp, temp, 0x01010101); 3628 return temp; 3629 3630 case MO_16: 3631 temp = tcg_temp_new_i32(); 3632 tcg_gen_trunc_tl_i32(temp, in); 3633 tcg_gen_deposit_i32(temp, temp, temp, 16, 16); 3634 return temp; 3635 3636#ifdef TARGET_X86_64 3637 case MO_32: 3638 temp = tcg_temp_new_i32(); 3639 tcg_gen_trunc_tl_i32(temp, in); 3640 return temp; 3641#endif 3642 3643 default: 3644 return NULL; 3645 } 3646} 3647 3648static void gen_rot_carry(X86DecodedInsn *decode, TCGv result, 3649 bool can_be_zero, TCGv count, int bit) 3650{ 3651 if (!can_be_zero) { 3652 tcg_gen_extract_tl(decode->cc_dst, result, bit, 1); 3653 } else { 3654 TCGv temp = tcg_temp_new(); 3655 tcg_gen_extract_tl(temp, result, bit, 1); 3656 tcg_gen_movcond_tl(TCG_COND_EQ, decode->cc_dst, count, tcg_constant_tl(0), 3657 decode->cc_dst, temp); 3658 } 3659} 3660 3661static void gen_ROL(DisasContext *s, X86DecodedInsn *decode) 3662{ 3663 bool can_be_zero; 3664 TCGv count; 3665 MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); 3666 TCGv_i32 temp32, count32; 3667 TCGv old = tcg_temp_new(); 3668 3669 if (!count) { 3670 return; 3671 } 3672 3673 gen_eflags_adcox(s, decode, false, can_be_zero); 3674 tcg_gen_mov_tl(old, s->T0); 3675 temp32 = gen_rot_replicate(ot, s->T0); 3676 if (temp32) { 3677 count32 = tcg_temp_new_i32(); 3678 tcg_gen_trunc_tl_i32(count32, count); 3679 tcg_gen_rotl_i32(temp32, temp32, count32); 3680 /* Zero extend to facilitate later optimization. */ 3681 tcg_gen_extu_i32_tl(s->T0, temp32); 3682 } else { 3683 tcg_gen_rotl_tl(s->T0, s->T0, count); 3684 } 3685 gen_rot_carry(decode, s->T0, can_be_zero, count, 0); 3686 gen_rot_overflow(decode, s->T0, old, can_be_zero, count); 3687} 3688 3689static void gen_ROR(DisasContext *s, X86DecodedInsn *decode) 3690{ 3691 bool can_be_zero; 3692 TCGv count; 3693 MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); 3694 TCGv_i32 temp32, count32; 3695 TCGv old = tcg_temp_new(); 3696 3697 if (!count) { 3698 return; 3699 } 3700 3701 gen_eflags_adcox(s, decode, false, can_be_zero); 3702 tcg_gen_mov_tl(old, s->T0); 3703 temp32 = gen_rot_replicate(ot, s->T0); 3704 if (temp32) { 3705 count32 = tcg_temp_new_i32(); 3706 tcg_gen_trunc_tl_i32(count32, count); 3707 tcg_gen_rotr_i32(temp32, temp32, count32); 3708 /* Zero extend to facilitate later optimization. */ 3709 tcg_gen_extu_i32_tl(s->T0, temp32); 3710 gen_rot_carry(decode, s->T0, can_be_zero, count, 31); 3711 } else { 3712 tcg_gen_rotr_tl(s->T0, s->T0, count); 3713 gen_rot_carry(decode, s->T0, can_be_zero, count, TARGET_LONG_BITS - 1); 3714 } 3715 gen_rot_overflow(decode, s->T0, old, can_be_zero, count); 3716} 3717 3718static void gen_RORX(DisasContext *s, X86DecodedInsn *decode) 3719{ 3720 MemOp ot = decode->op[0].ot; 3721 int mask = ot == MO_64 ? 63 : 31; 3722 int b = decode->immediate & mask; 3723 3724 switch (ot) { 3725 case MO_32: 3726#ifdef TARGET_X86_64 3727 tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); 3728 tcg_gen_rotri_i32(s->tmp2_i32, s->tmp2_i32, b); 3729 tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32); 3730 break; 3731 3732 case MO_64: 3733#endif 3734 tcg_gen_rotri_tl(s->T0, s->T0, b); 3735 break; 3736 3737 default: 3738 g_assert_not_reached(); 3739 } 3740} 3741 3742#ifndef CONFIG_USER_ONLY 3743static void gen_RSM(DisasContext *s, X86DecodedInsn *decode) 3744{ 3745 gen_helper_rsm(tcg_env); 3746 assume_cc_op(s, CC_OP_EFLAGS); 3747 s->base.is_jmp = DISAS_EOB_ONLY; 3748} 3749#else 3750#define gen_RSM gen_UD 3751#endif 3752 3753static void gen_SAHF(DisasContext *s, X86DecodedInsn *decode) 3754{ 3755 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) { 3756 return gen_illegal_opcode(s); 3757 } 3758 tcg_gen_shri_tl(s->T0, cpu_regs[R_EAX], 8); 3759 gen_compute_eflags(s); 3760 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O); 3761 tcg_gen_andi_tl(s->T0, s->T0, CC_S | CC_Z | CC_A | CC_P | CC_C); 3762 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, s->T0); 3763} 3764 3765static void gen_SALC(DisasContext *s, X86DecodedInsn *decode) 3766{ 3767 gen_compute_eflags_c(s, s->T0); 3768 tcg_gen_neg_tl(s->T0, s->T0); 3769} 3770 3771static void gen_shift_dynamic_flags(DisasContext *s, X86DecodedInsn *decode, TCGv count, CCOp cc_op) 3772{ 3773 TCGv_i32 count32 = tcg_temp_new_i32(); 3774 TCGv_i32 old_cc_op; 3775 3776 decode->cc_op = CC_OP_DYNAMIC; 3777 decode->cc_op_dynamic = tcg_temp_new_i32(); 3778 3779 assert(decode->cc_dst == s->T0); 3780 if (cc_op_live(s->cc_op) & USES_CC_DST) { 3781 decode->cc_dst = tcg_temp_new(); 3782 tcg_gen_movcond_tl(TCG_COND_EQ, decode->cc_dst, count, tcg_constant_tl(0), 3783 cpu_cc_dst, s->T0); 3784 } 3785 3786 if (cc_op_live(s->cc_op) & USES_CC_SRC) { 3787 tcg_gen_movcond_tl(TCG_COND_EQ, decode->cc_src, count, tcg_constant_tl(0), 3788 cpu_cc_src, decode->cc_src); 3789 } 3790 3791 tcg_gen_trunc_tl_i32(count32, count); 3792 if (s->cc_op == CC_OP_DYNAMIC) { 3793 old_cc_op = cpu_cc_op; 3794 } else { 3795 old_cc_op = tcg_constant_i32(s->cc_op); 3796 } 3797 tcg_gen_movcond_i32(TCG_COND_EQ, decode->cc_op_dynamic, count32, tcg_constant_i32(0), 3798 old_cc_op, tcg_constant_i32(cc_op)); 3799} 3800 3801static void gen_SAR(DisasContext *s, X86DecodedInsn *decode) 3802{ 3803 bool can_be_zero; 3804 TCGv count; 3805 MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); 3806 3807 if (!count) { 3808 return; 3809 } 3810 3811 decode->cc_dst = s->T0; 3812 decode->cc_src = tcg_temp_new(); 3813 tcg_gen_subi_tl(decode->cc_src, count, 1); 3814 tcg_gen_sar_tl(decode->cc_src, s->T0, decode->cc_src); 3815 tcg_gen_sar_tl(s->T0, s->T0, count); 3816 if (can_be_zero) { 3817 gen_shift_dynamic_flags(s, decode, count, CC_OP_SARB + ot); 3818 } else { 3819 decode->cc_op = CC_OP_SARB + ot; 3820 } 3821} 3822 3823static void gen_SARX(DisasContext *s, X86DecodedInsn *decode) 3824{ 3825 MemOp ot = decode->op[0].ot; 3826 int mask; 3827 3828 mask = ot == MO_64 ? 63 : 31; 3829 tcg_gen_andi_tl(s->T1, s->T1, mask); 3830 tcg_gen_sar_tl(s->T0, s->T0, s->T1); 3831} 3832 3833static void gen_SBB(DisasContext *s, X86DecodedInsn *decode) 3834{ 3835 MemOp ot = decode->op[0].ot; 3836 TCGv c_in = tcg_temp_new(); 3837 3838 gen_compute_eflags_c(s, c_in); 3839 if (s->prefix & PREFIX_LOCK) { 3840 tcg_gen_add_tl(s->T0, s->T1, c_in); 3841 tcg_gen_neg_tl(s->T0, s->T0); 3842 tcg_gen_atomic_add_fetch_tl(s->T0, s->A0, s->T0, 3843 s->mem_index, ot | MO_LE); 3844 } else { 3845 /* 3846 * TODO: SBB reg, reg could use gen_prepare_eflags_c followed by 3847 * negsetcond, and CC_OP_SUBB as the cc_op. 3848 */ 3849 tcg_gen_sub_tl(s->T0, s->T0, s->T1); 3850 tcg_gen_sub_tl(s->T0, s->T0, c_in); 3851 } 3852 prepare_update3_cc(decode, s, CC_OP_SBBB + ot, c_in); 3853} 3854 3855static void gen_SCAS(DisasContext *s, X86DecodedInsn *decode) 3856{ 3857 MemOp ot = decode->op[2].ot; 3858 gen_repz_nz(s, ot, gen_scas); 3859} 3860 3861static void gen_SETcc(DisasContext *s, X86DecodedInsn *decode) 3862{ 3863 gen_setcc(s, decode->b & 0xf, s->T0); 3864} 3865 3866static void gen_SFENCE(DisasContext *s, X86DecodedInsn *decode) 3867{ 3868 tcg_gen_mb(TCG_MO_ST_ST | TCG_BAR_SC); 3869} 3870 3871static void gen_SHA1NEXTE(DisasContext *s, X86DecodedInsn *decode) 3872{ 3873 gen_helper_sha1nexte(OP_PTR0, OP_PTR1, OP_PTR2); 3874} 3875 3876static void gen_SHA1MSG1(DisasContext *s, X86DecodedInsn *decode) 3877{ 3878 gen_helper_sha1msg1(OP_PTR0, OP_PTR1, OP_PTR2); 3879} 3880 3881static void gen_SHA1MSG2(DisasContext *s, X86DecodedInsn *decode) 3882{ 3883 gen_helper_sha1msg2(OP_PTR0, OP_PTR1, OP_PTR2); 3884} 3885 3886static void gen_SHA1RNDS4(DisasContext *s, X86DecodedInsn *decode) 3887{ 3888 switch(decode->immediate & 3) { 3889 case 0: 3890 gen_helper_sha1rnds4_f0(OP_PTR0, OP_PTR0, OP_PTR1); 3891 break; 3892 case 1: 3893 gen_helper_sha1rnds4_f1(OP_PTR0, OP_PTR0, OP_PTR1); 3894 break; 3895 case 2: 3896 gen_helper_sha1rnds4_f2(OP_PTR0, OP_PTR0, OP_PTR1); 3897 break; 3898 case 3: 3899 gen_helper_sha1rnds4_f3(OP_PTR0, OP_PTR0, OP_PTR1); 3900 break; 3901 } 3902} 3903 3904static void gen_SHA256MSG1(DisasContext *s, X86DecodedInsn *decode) 3905{ 3906 gen_helper_sha256msg1(OP_PTR0, OP_PTR1, OP_PTR2); 3907} 3908 3909static void gen_SHA256MSG2(DisasContext *s, X86DecodedInsn *decode) 3910{ 3911 gen_helper_sha256msg2(OP_PTR0, OP_PTR1, OP_PTR2); 3912} 3913 3914static void gen_SHA256RNDS2(DisasContext *s, X86DecodedInsn *decode) 3915{ 3916 TCGv_i32 wk0 = tcg_temp_new_i32(); 3917 TCGv_i32 wk1 = tcg_temp_new_i32(); 3918 3919 tcg_gen_ld_i32(wk0, tcg_env, ZMM_OFFSET(0) + offsetof(ZMMReg, ZMM_L(0))); 3920 tcg_gen_ld_i32(wk1, tcg_env, ZMM_OFFSET(0) + offsetof(ZMMReg, ZMM_L(1))); 3921 3922 gen_helper_sha256rnds2(OP_PTR0, OP_PTR1, OP_PTR2, wk0, wk1); 3923} 3924 3925static void gen_SHL(DisasContext *s, X86DecodedInsn *decode) 3926{ 3927 bool can_be_zero; 3928 TCGv count; 3929 MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); 3930 3931 if (!count) { 3932 return; 3933 } 3934 3935 decode->cc_dst = s->T0; 3936 decode->cc_src = tcg_temp_new(); 3937 tcg_gen_subi_tl(decode->cc_src, count, 1); 3938 tcg_gen_shl_tl(decode->cc_src, s->T0, decode->cc_src); 3939 tcg_gen_shl_tl(s->T0, s->T0, count); 3940 if (can_be_zero) { 3941 gen_shift_dynamic_flags(s, decode, count, CC_OP_SHLB + ot); 3942 } else { 3943 decode->cc_op = CC_OP_SHLB + ot; 3944 } 3945} 3946 3947static void gen_SHLD(DisasContext *s, X86DecodedInsn *decode) 3948{ 3949 bool can_be_zero; 3950 TCGv count; 3951 int unit = decode->e.op3 == X86_TYPE_I ? X86_OP_IMM : X86_OP_INT; 3952 MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, unit); 3953 3954 if (!count) { 3955 return; 3956 } 3957 3958 decode->cc_dst = s->T0; 3959 decode->cc_src = s->tmp0; 3960 gen_shiftd_rm_T1(s, ot, false, count); 3961 if (can_be_zero) { 3962 gen_shift_dynamic_flags(s, decode, count, CC_OP_SHLB + ot); 3963 } else { 3964 decode->cc_op = CC_OP_SHLB + ot; 3965 } 3966} 3967 3968static void gen_SHLX(DisasContext *s, X86DecodedInsn *decode) 3969{ 3970 MemOp ot = decode->op[0].ot; 3971 int mask; 3972 3973 mask = ot == MO_64 ? 63 : 31; 3974 tcg_gen_andi_tl(s->T1, s->T1, mask); 3975 tcg_gen_shl_tl(s->T0, s->T0, s->T1); 3976} 3977 3978static void gen_SHR(DisasContext *s, X86DecodedInsn *decode) 3979{ 3980 bool can_be_zero; 3981 TCGv count; 3982 MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); 3983 3984 if (!count) { 3985 return; 3986 } 3987 3988 decode->cc_dst = s->T0; 3989 decode->cc_src = tcg_temp_new(); 3990 tcg_gen_subi_tl(decode->cc_src, count, 1); 3991 tcg_gen_shr_tl(decode->cc_src, s->T0, decode->cc_src); 3992 tcg_gen_shr_tl(s->T0, s->T0, count); 3993 if (can_be_zero) { 3994 gen_shift_dynamic_flags(s, decode, count, CC_OP_SARB + ot); 3995 } else { 3996 decode->cc_op = CC_OP_SARB + ot; 3997 } 3998} 3999 4000static void gen_SHRD(DisasContext *s, X86DecodedInsn *decode) 4001{ 4002 bool can_be_zero; 4003 TCGv count; 4004 int unit = decode->e.op3 == X86_TYPE_I ? X86_OP_IMM : X86_OP_INT; 4005 MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, unit); 4006 4007 if (!count) { 4008 return; 4009 } 4010 4011 decode->cc_dst = s->T0; 4012 decode->cc_src = s->tmp0; 4013 gen_shiftd_rm_T1(s, ot, true, count); 4014 if (can_be_zero) { 4015 gen_shift_dynamic_flags(s, decode, count, CC_OP_SARB + ot); 4016 } else { 4017 decode->cc_op = CC_OP_SARB + ot; 4018 } 4019} 4020 4021static void gen_SHRX(DisasContext *s, X86DecodedInsn *decode) 4022{ 4023 MemOp ot = decode->op[0].ot; 4024 int mask; 4025 4026 mask = ot == MO_64 ? 63 : 31; 4027 tcg_gen_andi_tl(s->T1, s->T1, mask); 4028 tcg_gen_shr_tl(s->T0, s->T0, s->T1); 4029} 4030 4031static void gen_STC(DisasContext *s, X86DecodedInsn *decode) 4032{ 4033 gen_compute_eflags(s); 4034 tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C); 4035} 4036 4037static void gen_STD(DisasContext *s, X86DecodedInsn *decode) 4038{ 4039 tcg_gen_st_i32(tcg_constant_i32(-1), tcg_env, offsetof(CPUX86State, df)); 4040} 4041 4042static void gen_STI(DisasContext *s, X86DecodedInsn *decode) 4043{ 4044 gen_set_eflags(s, IF_MASK); 4045 s->base.is_jmp = DISAS_EOB_INHIBIT_IRQ; 4046} 4047 4048static void gen_VAESKEYGEN(DisasContext *s, X86DecodedInsn *decode) 4049{ 4050 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 4051 assert(!s->vex_l); 4052 gen_helper_aeskeygenassist_xmm(tcg_env, OP_PTR0, OP_PTR1, imm); 4053} 4054 4055static void gen_STMXCSR(DisasContext *s, X86DecodedInsn *decode) 4056{ 4057 gen_helper_update_mxcsr(tcg_env); 4058 tcg_gen_ld32u_tl(s->T0, tcg_env, offsetof(CPUX86State, mxcsr)); 4059} 4060 4061static void gen_STOS(DisasContext *s, X86DecodedInsn *decode) 4062{ 4063 MemOp ot = decode->op[1].ot; 4064 gen_repz(s, ot, gen_stos); 4065} 4066 4067static void gen_SUB(DisasContext *s, X86DecodedInsn *decode) 4068{ 4069 MemOp ot = decode->op[1].ot; 4070 4071 if (s->prefix & PREFIX_LOCK) { 4072 tcg_gen_neg_tl(s->T0, s->T1); 4073 tcg_gen_atomic_fetch_add_tl(s->cc_srcT, s->A0, s->T0, 4074 s->mem_index, ot | MO_LE); 4075 tcg_gen_sub_tl(s->T0, s->cc_srcT, s->T1); 4076 } else { 4077 tcg_gen_mov_tl(s->cc_srcT, s->T0); 4078 tcg_gen_sub_tl(s->T0, s->T0, s->T1); 4079 } 4080 prepare_update2_cc(decode, s, CC_OP_SUBB + ot); 4081} 4082 4083static void gen_SYSCALL(DisasContext *s, X86DecodedInsn *decode) 4084{ 4085 gen_update_cc_op(s); 4086 gen_update_eip_cur(s); 4087 gen_helper_syscall(tcg_env, cur_insn_len_i32(s)); 4088 if (LMA(s)) { 4089 assume_cc_op(s, CC_OP_EFLAGS); 4090 } 4091 4092 /* 4093 * TF handling for the syscall insn is different. The TF bit is checked 4094 * after the syscall insn completes. This allows #DB to not be 4095 * generated after one has entered CPL0 if TF is set in FMASK. 4096 */ 4097 s->base.is_jmp = DISAS_EOB_RECHECK_TF; 4098} 4099 4100static void gen_SYSENTER(DisasContext *s, X86DecodedInsn *decode) 4101{ 4102 gen_helper_sysenter(tcg_env); 4103 s->base.is_jmp = DISAS_EOB_ONLY; 4104} 4105 4106static void gen_SYSEXIT(DisasContext *s, X86DecodedInsn *decode) 4107{ 4108 gen_helper_sysexit(tcg_env, tcg_constant_i32(s->dflag - 1)); 4109 s->base.is_jmp = DISAS_EOB_ONLY; 4110} 4111 4112static void gen_SYSRET(DisasContext *s, X86DecodedInsn *decode) 4113{ 4114 gen_helper_sysret(tcg_env, tcg_constant_i32(s->dflag - 1)); 4115 if (LMA(s)) { 4116 assume_cc_op(s, CC_OP_EFLAGS); 4117 } 4118 4119 /* 4120 * TF handling for the sysret insn is different. The TF bit is checked 4121 * after the sysret insn completes. This allows #DB to be 4122 * generated "as if" the syscall insn in userspace has just 4123 * completed. 4124 */ 4125 s->base.is_jmp = DISAS_EOB_RECHECK_TF; 4126} 4127 4128static void gen_TZCNT(DisasContext *s, X86DecodedInsn *decode) 4129{ 4130 MemOp ot = decode->op[0].ot; 4131 4132 /* C bit (cc_src) is defined related to the input. */ 4133 decode->cc_src = tcg_temp_new(); 4134 decode->cc_dst = s->T0; 4135 decode->cc_op = CC_OP_BMILGB + ot; 4136 tcg_gen_mov_tl(decode->cc_src, s->T0); 4137 4138 /* A zero input returns the operand size. */ 4139 tcg_gen_ctzi_tl(s->T0, s->T0, 8 << ot); 4140} 4141 4142static void gen_UD(DisasContext *s, X86DecodedInsn *decode) 4143{ 4144 gen_illegal_opcode(s); 4145} 4146 4147static void gen_VAESIMC(DisasContext *s, X86DecodedInsn *decode) 4148{ 4149 assert(!s->vex_l); 4150 gen_helper_aesimc_xmm(tcg_env, OP_PTR0, OP_PTR2); 4151} 4152 4153/* 4154 * 00 = v*ps Vps, Hps, Wpd 4155 * 66 = v*pd Vpd, Hpd, Wps 4156 * f3 = v*ss Vss, Hss, Wps 4157 * f2 = v*sd Vsd, Hsd, Wps 4158 */ 4159#define SSE_CMP(x) { \ 4160 gen_helper_ ## x ## ps ## _xmm, gen_helper_ ## x ## pd ## _xmm, \ 4161 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, \ 4162 gen_helper_ ## x ## ps ## _ymm, gen_helper_ ## x ## pd ## _ymm} 4163static const SSEFunc_0_eppp gen_helper_cmp_funcs[32][6] = { 4164 SSE_CMP(cmpeq), 4165 SSE_CMP(cmplt), 4166 SSE_CMP(cmple), 4167 SSE_CMP(cmpunord), 4168 SSE_CMP(cmpneq), 4169 SSE_CMP(cmpnlt), 4170 SSE_CMP(cmpnle), 4171 SSE_CMP(cmpord), 4172 4173 SSE_CMP(cmpequ), 4174 SSE_CMP(cmpnge), 4175 SSE_CMP(cmpngt), 4176 SSE_CMP(cmpfalse), 4177 SSE_CMP(cmpnequ), 4178 SSE_CMP(cmpge), 4179 SSE_CMP(cmpgt), 4180 SSE_CMP(cmptrue), 4181 4182 SSE_CMP(cmpeqs), 4183 SSE_CMP(cmpltq), 4184 SSE_CMP(cmpleq), 4185 SSE_CMP(cmpunords), 4186 SSE_CMP(cmpneqq), 4187 SSE_CMP(cmpnltq), 4188 SSE_CMP(cmpnleq), 4189 SSE_CMP(cmpords), 4190 4191 SSE_CMP(cmpequs), 4192 SSE_CMP(cmpngeq), 4193 SSE_CMP(cmpngtq), 4194 SSE_CMP(cmpfalses), 4195 SSE_CMP(cmpnequs), 4196 SSE_CMP(cmpgeq), 4197 SSE_CMP(cmpgtq), 4198 SSE_CMP(cmptrues), 4199}; 4200#undef SSE_CMP 4201 4202static void gen_VCMP(DisasContext *s, X86DecodedInsn *decode) 4203{ 4204 int index = decode->immediate & (s->prefix & PREFIX_VEX ? 31 : 7); 4205 int b = 4206 s->prefix & PREFIX_REPZ ? 2 /* ss */ : 4207 s->prefix & PREFIX_REPNZ ? 3 /* sd */ : 4208 !!(s->prefix & PREFIX_DATA) /* pd */ + (s->vex_l << 2); 4209 4210 gen_helper_cmp_funcs[index][b](tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 4211} 4212 4213static void gen_VCOMI(DisasContext *s, X86DecodedInsn *decode) 4214{ 4215 SSEFunc_0_epp fn; 4216 fn = s->prefix & PREFIX_DATA ? gen_helper_comisd : gen_helper_comiss; 4217 fn(tcg_env, OP_PTR1, OP_PTR2); 4218 assume_cc_op(s, CC_OP_EFLAGS); 4219} 4220 4221static void gen_VCVTPD2PS(DisasContext *s, X86DecodedInsn *decode) 4222{ 4223 if (s->vex_l) { 4224 gen_helper_cvtpd2ps_ymm(tcg_env, OP_PTR0, OP_PTR2); 4225 } else { 4226 gen_helper_cvtpd2ps_xmm(tcg_env, OP_PTR0, OP_PTR2); 4227 } 4228} 4229 4230static void gen_VCVTPS2PD(DisasContext *s, X86DecodedInsn *decode) 4231{ 4232 if (s->vex_l) { 4233 gen_helper_cvtps2pd_ymm(tcg_env, OP_PTR0, OP_PTR2); 4234 } else { 4235 gen_helper_cvtps2pd_xmm(tcg_env, OP_PTR0, OP_PTR2); 4236 } 4237} 4238 4239static void gen_VCVTPS2PH(DisasContext *s, X86DecodedInsn *decode) 4240{ 4241 gen_unary_imm_fp_sse(s, decode, 4242 gen_helper_cvtps2ph_xmm, 4243 gen_helper_cvtps2ph_ymm); 4244 /* 4245 * VCVTPS2PH is the only instruction that performs an operation on a 4246 * register source and then *stores* into memory. 4247 */ 4248 if (decode->op[0].has_ea) { 4249 gen_store_sse(s, decode, decode->op[0].offset); 4250 } 4251} 4252 4253static void gen_VCVTSD2SS(DisasContext *s, X86DecodedInsn *decode) 4254{ 4255 gen_helper_cvtsd2ss(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 4256} 4257 4258static void gen_VCVTSS2SD(DisasContext *s, X86DecodedInsn *decode) 4259{ 4260 gen_helper_cvtss2sd(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); 4261} 4262 4263static void gen_VCVTSI2Sx(DisasContext *s, X86DecodedInsn *decode) 4264{ 4265 int vec_len = vector_len(s, decode); 4266 TCGv_i32 in; 4267 4268 tcg_gen_gvec_mov(MO_64, decode->op[0].offset, decode->op[1].offset, vec_len, vec_len); 4269 4270#ifdef TARGET_X86_64 4271 MemOp ot = decode->op[2].ot; 4272 if (ot == MO_64) { 4273 if (s->prefix & PREFIX_REPNZ) { 4274 gen_helper_cvtsq2sd(tcg_env, OP_PTR0, s->T1); 4275 } else { 4276 gen_helper_cvtsq2ss(tcg_env, OP_PTR0, s->T1); 4277 } 4278 return; 4279 } 4280 in = s->tmp2_i32; 4281 tcg_gen_trunc_tl_i32(in, s->T1); 4282#else 4283 in = s->T1; 4284#endif 4285 4286 if (s->prefix & PREFIX_REPNZ) { 4287 gen_helper_cvtsi2sd(tcg_env, OP_PTR0, in); 4288 } else { 4289 gen_helper_cvtsi2ss(tcg_env, OP_PTR0, in); 4290 } 4291} 4292 4293static inline void gen_VCVTtSx2SI(DisasContext *s, X86DecodedInsn *decode, 4294 SSEFunc_i_ep ss2si, SSEFunc_l_ep ss2sq, 4295 SSEFunc_i_ep sd2si, SSEFunc_l_ep sd2sq) 4296{ 4297 TCGv_i32 out; 4298 4299#ifdef TARGET_X86_64 4300 MemOp ot = decode->op[0].ot; 4301 if (ot == MO_64) { 4302 if (s->prefix & PREFIX_REPNZ) { 4303 sd2sq(s->T0, tcg_env, OP_PTR2); 4304 } else { 4305 ss2sq(s->T0, tcg_env, OP_PTR2); 4306 } 4307 return; 4308 } 4309 4310 out = s->tmp2_i32; 4311#else 4312 out = s->T0; 4313#endif 4314 if (s->prefix & PREFIX_REPNZ) { 4315 sd2si(out, tcg_env, OP_PTR2); 4316 } else { 4317 ss2si(out, tcg_env, OP_PTR2); 4318 } 4319#ifdef TARGET_X86_64 4320 tcg_gen_extu_i32_tl(s->T0, out); 4321#endif 4322} 4323 4324#ifndef TARGET_X86_64 4325#define gen_helper_cvtss2sq NULL 4326#define gen_helper_cvtsd2sq NULL 4327#define gen_helper_cvttss2sq NULL 4328#define gen_helper_cvttsd2sq NULL 4329#endif 4330 4331static void gen_VCVTSx2SI(DisasContext *s, X86DecodedInsn *decode) 4332{ 4333 gen_VCVTtSx2SI(s, decode, 4334 gen_helper_cvtss2si, gen_helper_cvtss2sq, 4335 gen_helper_cvtsd2si, gen_helper_cvtsd2sq); 4336} 4337 4338static void gen_VCVTTSx2SI(DisasContext *s, X86DecodedInsn *decode) 4339{ 4340 gen_VCVTtSx2SI(s, decode, 4341 gen_helper_cvttss2si, gen_helper_cvttss2sq, 4342 gen_helper_cvttsd2si, gen_helper_cvttsd2sq); 4343} 4344 4345static void gen_VEXTRACTx128(DisasContext *s, X86DecodedInsn *decode) 4346{ 4347 int mask = decode->immediate & 1; 4348 int src_ofs = vector_elem_offset(&decode->op[1], MO_128, mask); 4349 if (decode->op[0].has_ea) { 4350 /* VEX-only instruction, no alignment requirements. */ 4351 gen_sto_env_A0(s, src_ofs, false); 4352 } else { 4353 tcg_gen_gvec_mov(MO_64, decode->op[0].offset, src_ofs, 16, 16); 4354 } 4355} 4356 4357static void gen_VEXTRACTPS(DisasContext *s, X86DecodedInsn *decode) 4358{ 4359 gen_pextr(s, decode, MO_32); 4360} 4361 4362static void gen_vinsertps(DisasContext *s, X86DecodedInsn *decode) 4363{ 4364 int val = decode->immediate; 4365 int dest_word = (val >> 4) & 3; 4366 int new_mask = (val & 15) | (1 << dest_word); 4367 int vec_len = 16; 4368 4369 assert(!s->vex_l); 4370 4371 if (new_mask == 15) { 4372 /* All zeroes except possibly for the inserted element */ 4373 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 4374 } else if (decode->op[1].offset != decode->op[0].offset) { 4375 gen_store_sse(s, decode, decode->op[1].offset); 4376 } 4377 4378 if (new_mask != (val & 15)) { 4379 tcg_gen_st_i32(s->tmp2_i32, tcg_env, 4380 vector_elem_offset(&decode->op[0], MO_32, dest_word)); 4381 } 4382 4383 if (new_mask != 15) { 4384 TCGv_i32 zero = tcg_constant_i32(0); /* float32_zero */ 4385 int i; 4386 for (i = 0; i < 4; i++) { 4387 if ((val >> i) & 1) { 4388 tcg_gen_st_i32(zero, tcg_env, 4389 vector_elem_offset(&decode->op[0], MO_32, i)); 4390 } 4391 } 4392 } 4393} 4394 4395static void gen_VINSERTPS_r(DisasContext *s, X86DecodedInsn *decode) 4396{ 4397 int val = decode->immediate; 4398 tcg_gen_ld_i32(s->tmp2_i32, tcg_env, 4399 vector_elem_offset(&decode->op[2], MO_32, (val >> 6) & 3)); 4400 gen_vinsertps(s, decode); 4401} 4402 4403static void gen_VINSERTPS_m(DisasContext *s, X86DecodedInsn *decode) 4404{ 4405 tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUL); 4406 gen_vinsertps(s, decode); 4407} 4408 4409static void gen_VINSERTx128(DisasContext *s, X86DecodedInsn *decode) 4410{ 4411 int mask = decode->immediate & 1; 4412 tcg_gen_gvec_mov(MO_64, 4413 decode->op[0].offset + offsetof(YMMReg, YMM_X(mask)), 4414 decode->op[2].offset + offsetof(YMMReg, YMM_X(0)), 16, 16); 4415 tcg_gen_gvec_mov(MO_64, 4416 decode->op[0].offset + offsetof(YMMReg, YMM_X(!mask)), 4417 decode->op[1].offset + offsetof(YMMReg, YMM_X(!mask)), 16, 16); 4418} 4419 4420static inline void gen_maskmov(DisasContext *s, X86DecodedInsn *decode, 4421 SSEFunc_0_eppt xmm, SSEFunc_0_eppt ymm) 4422{ 4423 if (!s->vex_l) { 4424 xmm(tcg_env, OP_PTR2, OP_PTR1, s->A0); 4425 } else { 4426 ymm(tcg_env, OP_PTR2, OP_PTR1, s->A0); 4427 } 4428} 4429 4430static void gen_VMASKMOVPD_st(DisasContext *s, X86DecodedInsn *decode) 4431{ 4432 gen_maskmov(s, decode, gen_helper_vpmaskmovq_st_xmm, gen_helper_vpmaskmovq_st_ymm); 4433} 4434 4435static void gen_VMASKMOVPS_st(DisasContext *s, X86DecodedInsn *decode) 4436{ 4437 gen_maskmov(s, decode, gen_helper_vpmaskmovd_st_xmm, gen_helper_vpmaskmovd_st_ymm); 4438} 4439 4440static void gen_VMOVHPx_ld(DisasContext *s, X86DecodedInsn *decode) 4441{ 4442 gen_ldq_env_A0(s, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1))); 4443 if (decode->op[0].offset != decode->op[1].offset) { 4444 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(0))); 4445 tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0))); 4446 } 4447} 4448 4449static void gen_VMOVHPx_st(DisasContext *s, X86DecodedInsn *decode) 4450{ 4451 gen_stq_env_A0(s, decode->op[2].offset + offsetof(XMMReg, XMM_Q(1))); 4452} 4453 4454static void gen_VMOVHPx(DisasContext *s, X86DecodedInsn *decode) 4455{ 4456 if (decode->op[0].offset != decode->op[2].offset) { 4457 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset + offsetof(XMMReg, XMM_Q(1))); 4458 tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1))); 4459 } 4460 if (decode->op[0].offset != decode->op[1].offset) { 4461 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(0))); 4462 tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0))); 4463 } 4464} 4465 4466static void gen_VMOVHLPS(DisasContext *s, X86DecodedInsn *decode) 4467{ 4468 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset + offsetof(XMMReg, XMM_Q(1))); 4469 tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0))); 4470 if (decode->op[0].offset != decode->op[1].offset) { 4471 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(1))); 4472 tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1))); 4473 } 4474} 4475 4476static void gen_VMOVLHPS(DisasContext *s, X86DecodedInsn *decode) 4477{ 4478 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset); 4479 tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1))); 4480 if (decode->op[0].offset != decode->op[1].offset) { 4481 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset + offsetof(XMMReg, XMM_Q(0))); 4482 tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0))); 4483 } 4484} 4485 4486/* 4487 * Note that MOVLPx supports 256-bit operation unlike MOVHLPx, MOVLHPx, MOXHPx. 4488 * Use a gvec move to move everything above the bottom 64 bits. 4489 */ 4490 4491static void gen_VMOVLPx(DisasContext *s, X86DecodedInsn *decode) 4492{ 4493 int vec_len = vector_len(s, decode); 4494 4495 tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset + offsetof(XMMReg, XMM_Q(0))); 4496 tcg_gen_gvec_mov(MO_64, decode->op[0].offset, decode->op[1].offset, vec_len, vec_len); 4497 tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(XMMReg, XMM_Q(0))); 4498} 4499 4500static void gen_VMOVLPx_ld(DisasContext *s, X86DecodedInsn *decode) 4501{ 4502 int vec_len = vector_len(s, decode); 4503 4504 tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEUQ); 4505 tcg_gen_gvec_mov(MO_64, decode->op[0].offset, decode->op[1].offset, vec_len, vec_len); 4506 tcg_gen_st_i64(s->tmp1_i64, OP_PTR0, offsetof(ZMMReg, ZMM_Q(0))); 4507} 4508 4509static void gen_VMOVLPx_st(DisasContext *s, X86DecodedInsn *decode) 4510{ 4511 tcg_gen_ld_i64(s->tmp1_i64, OP_PTR2, offsetof(ZMMReg, ZMM_Q(0))); 4512 tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEUQ); 4513} 4514 4515static void gen_VMOVSD_ld(DisasContext *s, X86DecodedInsn *decode) 4516{ 4517 TCGv_i64 zero = tcg_constant_i64(0); 4518 4519 tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEUQ); 4520 tcg_gen_st_i64(zero, OP_PTR0, offsetof(ZMMReg, ZMM_Q(1))); 4521 tcg_gen_st_i64(s->tmp1_i64, OP_PTR0, offsetof(ZMMReg, ZMM_Q(0))); 4522} 4523 4524static void gen_VMOVSS(DisasContext *s, X86DecodedInsn *decode) 4525{ 4526 int vec_len = vector_len(s, decode); 4527 4528 tcg_gen_ld_i32(s->tmp2_i32, OP_PTR2, offsetof(ZMMReg, ZMM_L(0))); 4529 tcg_gen_gvec_mov(MO_64, decode->op[0].offset, decode->op[1].offset, vec_len, vec_len); 4530 tcg_gen_st_i32(s->tmp2_i32, OP_PTR0, offsetof(ZMMReg, ZMM_L(0))); 4531} 4532 4533static void gen_VMOVSS_ld(DisasContext *s, X86DecodedInsn *decode) 4534{ 4535 int vec_len = vector_len(s, decode); 4536 4537 tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUL); 4538 tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0); 4539 tcg_gen_st_i32(s->tmp2_i32, OP_PTR0, offsetof(ZMMReg, ZMM_L(0))); 4540} 4541 4542static void gen_VMOVSS_st(DisasContext *s, X86DecodedInsn *decode) 4543{ 4544 tcg_gen_ld_i32(s->tmp2_i32, OP_PTR2, offsetof(ZMMReg, ZMM_L(0))); 4545 tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUL); 4546} 4547 4548static void gen_VPMASKMOV_st(DisasContext *s, X86DecodedInsn *decode) 4549{ 4550 if (s->vex_w) { 4551 gen_VMASKMOVPD_st(s, decode); 4552 } else { 4553 gen_VMASKMOVPS_st(s, decode); 4554 } 4555} 4556 4557static void gen_VPERMD(DisasContext *s, X86DecodedInsn *decode) 4558{ 4559 assert(s->vex_l); 4560 gen_helper_vpermd_ymm(OP_PTR0, OP_PTR1, OP_PTR2); 4561} 4562 4563static void gen_VPERM2x128(DisasContext *s, X86DecodedInsn *decode) 4564{ 4565 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 4566 assert(s->vex_l); 4567 gen_helper_vpermdq_ymm(OP_PTR0, OP_PTR1, OP_PTR2, imm); 4568} 4569 4570static void gen_VPHMINPOSUW(DisasContext *s, X86DecodedInsn *decode) 4571{ 4572 assert(!s->vex_l); 4573 gen_helper_phminposuw_xmm(tcg_env, OP_PTR0, OP_PTR2); 4574} 4575 4576static void gen_VROUNDSD(DisasContext *s, X86DecodedInsn *decode) 4577{ 4578 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 4579 assert(!s->vex_l); 4580 gen_helper_roundsd_xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); 4581} 4582 4583static void gen_VROUNDSS(DisasContext *s, X86DecodedInsn *decode) 4584{ 4585 TCGv_i32 imm = tcg_constant8u_i32(decode->immediate); 4586 assert(!s->vex_l); 4587 gen_helper_roundss_xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); 4588} 4589 4590static void gen_VSHUF(DisasContext *s, X86DecodedInsn *decode) 4591{ 4592 TCGv_i32 imm = tcg_constant_i32(decode->immediate); 4593 SSEFunc_0_pppi ps, pd, fn; 4594 ps = s->vex_l ? gen_helper_shufps_ymm : gen_helper_shufps_xmm; 4595 pd = s->vex_l ? gen_helper_shufpd_ymm : gen_helper_shufpd_xmm; 4596 fn = s->prefix & PREFIX_DATA ? pd : ps; 4597 fn(OP_PTR0, OP_PTR1, OP_PTR2, imm); 4598} 4599 4600static void gen_VUCOMI(DisasContext *s, X86DecodedInsn *decode) 4601{ 4602 SSEFunc_0_epp fn; 4603 fn = s->prefix & PREFIX_DATA ? gen_helper_ucomisd : gen_helper_ucomiss; 4604 fn(tcg_env, OP_PTR1, OP_PTR2); 4605 assume_cc_op(s, CC_OP_EFLAGS); 4606} 4607 4608static void gen_VZEROALL(DisasContext *s, X86DecodedInsn *decode) 4609{ 4610 TCGv_ptr ptr = tcg_temp_new_ptr(); 4611 4612 tcg_gen_addi_ptr(ptr, tcg_env, offsetof(CPUX86State, xmm_regs)); 4613 gen_helper_memset(ptr, ptr, tcg_constant_i32(0), 4614 tcg_constant_ptr(CPU_NB_REGS * sizeof(ZMMReg))); 4615} 4616 4617static void gen_VZEROUPPER(DisasContext *s, X86DecodedInsn *decode) 4618{ 4619 int i; 4620 4621 for (i = 0; i < CPU_NB_REGS; i++) { 4622 int offset = offsetof(CPUX86State, xmm_regs[i].ZMM_X(1)); 4623 tcg_gen_gvec_dup_imm(MO_64, offset, 16, 16, 0); 4624 } 4625} 4626 4627static void gen_WAIT(DisasContext *s, X86DecodedInsn *decode) 4628{ 4629 if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) == (HF_MP_MASK | HF_TS_MASK)) { 4630 gen_NM_exception(s); 4631 } else { 4632 /* needs to be treated as I/O because of ferr_irq */ 4633 translator_io_start(&s->base); 4634 gen_helper_fwait(tcg_env); 4635 } 4636} 4637 4638#ifndef CONFIG_USER_ONLY 4639static void gen_WRMSR(DisasContext *s, X86DecodedInsn *decode) 4640{ 4641 gen_update_cc_op(s); 4642 gen_update_eip_cur(s); 4643 gen_helper_wrmsr(tcg_env); 4644 s->base.is_jmp = DISAS_EOB_NEXT; 4645} 4646#else 4647#define gen_WRMSR gen_unreachable 4648#endif 4649 4650static void gen_WRxxBASE(DisasContext *s, X86DecodedInsn *decode) 4651{ 4652 TCGv base = cpu_seg_base[s->modrm & 8 ? R_GS : R_FS]; 4653 4654 /* Preserve hflags bits by testing CR4 at runtime. */ 4655 gen_helper_cr4_testbit(tcg_env, tcg_constant_i32(CR4_FSGSBASE_MASK)); 4656 tcg_gen_mov_tl(base, s->T0); 4657} 4658 4659static void gen_XADD(DisasContext *s, X86DecodedInsn *decode) 4660{ 4661 MemOp ot = decode->op[1].ot; 4662 4663 decode->cc_dst = tcg_temp_new(); 4664 decode->cc_src = s->T1; 4665 decode->cc_op = CC_OP_ADDB + ot; 4666 4667 if (s->prefix & PREFIX_LOCK) { 4668 tcg_gen_atomic_fetch_add_tl(s->T0, s->A0, s->T1, s->mem_index, ot | MO_LE); 4669 tcg_gen_add_tl(decode->cc_dst, s->T0, s->T1); 4670 } else { 4671 tcg_gen_add_tl(decode->cc_dst, s->T0, s->T1); 4672 /* 4673 * NOTE: writing memory first is important for MMU exceptions, 4674 * but "new result" wins for XADD AX, AX. 4675 */ 4676 gen_writeback(s, decode, 0, decode->cc_dst); 4677 } 4678 if (decode->op[0].has_ea || decode->op[2].n != decode->op[0].n) { 4679 gen_writeback(s, decode, 2, s->T0); 4680 } 4681} 4682 4683static void gen_XCHG(DisasContext *s, X86DecodedInsn *decode) 4684{ 4685 if (s->prefix & PREFIX_LOCK) { 4686 tcg_gen_atomic_xchg_tl(s->T0, s->A0, s->T1, 4687 s->mem_index, decode->op[0].ot | MO_LE); 4688 /* now store old value into register operand */ 4689 gen_op_mov_reg_v(s, decode->op[2].ot, decode->op[2].n, s->T0); 4690 } else { 4691 /* move destination value into source operand, source preserved in T1 */ 4692 gen_op_mov_reg_v(s, decode->op[2].ot, decode->op[2].n, s->T0); 4693 tcg_gen_mov_tl(s->T0, s->T1); 4694 } 4695} 4696 4697static void gen_XLAT(DisasContext *s, X86DecodedInsn *decode) 4698{ 4699 /* AL is already zero-extended into s->T0. */ 4700 tcg_gen_add_tl(s->A0, cpu_regs[R_EBX], s->T0); 4701 gen_lea_v_seg(s, s->A0, R_DS, s->override); 4702 gen_op_ld_v(s, MO_8, s->T0, s->A0); 4703} 4704 4705static void gen_XOR(DisasContext *s, X86DecodedInsn *decode) 4706{ 4707 /* special case XOR reg, reg */ 4708 if (decode->op[1].unit == X86_OP_INT && 4709 decode->op[2].unit == X86_OP_INT && 4710 decode->op[1].n == decode->op[2].n) { 4711 tcg_gen_movi_tl(s->T0, 0); 4712 decode->cc_op = CC_OP_EFLAGS; 4713 decode->cc_src = tcg_constant_tl(CC_Z | CC_P); 4714 } else { 4715 MemOp ot = decode->op[1].ot; 4716 4717 if (s->prefix & PREFIX_LOCK) { 4718 tcg_gen_atomic_xor_fetch_tl(s->T0, s->A0, s->T1, 4719 s->mem_index, ot | MO_LE); 4720 } else { 4721 tcg_gen_xor_tl(s->T0, s->T0, s->T1); 4722 } 4723 prepare_update1_cc(decode, s, CC_OP_LOGICB + ot); 4724 } 4725} 4726 4727static void gen_XRSTOR(DisasContext *s, X86DecodedInsn *decode) 4728{ 4729 TCGv_i64 features = tcg_temp_new_i64(); 4730 4731 tcg_gen_concat_tl_i64(features, cpu_regs[R_EAX], cpu_regs[R_EDX]); 4732 gen_helper_xrstor(tcg_env, s->A0, features); 4733 if (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_MPX) { 4734 /* 4735 * XRSTOR is how MPX is enabled, which changes how 4736 * we translate. Thus we need to end the TB. 4737 */ 4738 s->base.is_jmp = DISAS_EOB_NEXT; 4739 } 4740} 4741 4742static void gen_XSAVE(DisasContext *s, X86DecodedInsn *decode) 4743{ 4744 TCGv_i64 features = tcg_temp_new_i64(); 4745 4746 tcg_gen_concat_tl_i64(features, cpu_regs[R_EAX], cpu_regs[R_EDX]); 4747 gen_helper_xsave(tcg_env, s->A0, features); 4748} 4749 4750static void gen_XSAVEOPT(DisasContext *s, X86DecodedInsn *decode) 4751{ 4752 TCGv_i64 features = tcg_temp_new_i64(); 4753 4754 tcg_gen_concat_tl_i64(features, cpu_regs[R_EAX], cpu_regs[R_EDX]); 4755 gen_helper_xsave(tcg_env, s->A0, features); 4756} 4757