1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * dwc3-xilinx.c - Xilinx DWC3 controller specific glue driver
4 *
5 * Authors: Manish Narani <manish.narani@xilinx.com>
6 * Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
7 */
8
9 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/clk.h>
13 #include <linux/of.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/of_platform.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/reset.h>
20 #include <linux/of_address.h>
21 #include <linux/delay.h>
22 #include <linux/firmware/xlnx-zynqmp.h>
23 #include <linux/io.h>
24
25 #include <linux/phy/phy.h>
26
27 /* USB phy reset mask register */
28 #define XLNX_USB_PHY_RST_EN 0x001C
29 #define XLNX_PHY_RST_MASK 0x1
30
31 /* Xilinx USB 3.0 IP Register */
32 #define XLNX_USB_TRAFFIC_ROUTE_CONFIG 0x005C
33 #define XLNX_USB_TRAFFIC_ROUTE_FPD 0x1
34
35 /* Versal USB Reset ID */
36 #define VERSAL_USB_RESET_ID 0xC104036
37
38 #define XLNX_USB_FPD_PIPE_CLK 0x7c
39 #define PIPE_CLK_DESELECT 1
40 #define PIPE_CLK_SELECT 0
41 #define XLNX_USB_FPD_POWER_PRSNT 0x80
42 #define FPD_POWER_PRSNT_OPTION BIT(0)
43
44 struct dwc3_xlnx {
45 int num_clocks;
46 struct clk_bulk_data *clks;
47 struct device *dev;
48 void __iomem *regs;
49 int (*pltfm_init)(struct dwc3_xlnx *data);
50 struct phy *usb3_phy;
51 };
52
dwc3_xlnx_mask_phy_rst(struct dwc3_xlnx * priv_data,bool mask)53 static void dwc3_xlnx_mask_phy_rst(struct dwc3_xlnx *priv_data, bool mask)
54 {
55 u32 reg;
56
57 /*
58 * Enable or disable ULPI PHY reset from USB Controller.
59 * This does not actually reset the phy, but just controls
60 * whether USB controller can or cannot reset ULPI PHY.
61 */
62 reg = readl(priv_data->regs + XLNX_USB_PHY_RST_EN);
63
64 if (mask)
65 reg &= ~XLNX_PHY_RST_MASK;
66 else
67 reg |= XLNX_PHY_RST_MASK;
68
69 writel(reg, priv_data->regs + XLNX_USB_PHY_RST_EN);
70 }
71
dwc3_xlnx_init_versal(struct dwc3_xlnx * priv_data)72 static int dwc3_xlnx_init_versal(struct dwc3_xlnx *priv_data)
73 {
74 struct device *dev = priv_data->dev;
75 int ret;
76
77 dwc3_xlnx_mask_phy_rst(priv_data, false);
78
79 /* Assert and De-assert reset */
80 ret = zynqmp_pm_reset_assert(VERSAL_USB_RESET_ID,
81 PM_RESET_ACTION_ASSERT);
82 if (ret < 0) {
83 dev_err_probe(dev, ret, "failed to assert Reset\n");
84 return ret;
85 }
86
87 ret = zynqmp_pm_reset_assert(VERSAL_USB_RESET_ID,
88 PM_RESET_ACTION_RELEASE);
89 if (ret < 0) {
90 dev_err_probe(dev, ret, "failed to De-assert Reset\n");
91 return ret;
92 }
93
94 dwc3_xlnx_mask_phy_rst(priv_data, true);
95
96 return 0;
97 }
98
dwc3_xlnx_init_zynqmp(struct dwc3_xlnx * priv_data)99 static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data)
100 {
101 struct device *dev = priv_data->dev;
102 struct reset_control *crst, *hibrst, *apbrst;
103 struct gpio_desc *reset_gpio;
104 int ret = 0;
105 u32 reg;
106
107 priv_data->usb3_phy = devm_phy_optional_get(dev, "usb3-phy");
108 if (IS_ERR(priv_data->usb3_phy)) {
109 ret = PTR_ERR(priv_data->usb3_phy);
110 dev_err_probe(dev, ret,
111 "failed to get USB3 PHY\n");
112 goto err;
113 }
114
115 /*
116 * The following core resets are not required unless a USB3 PHY
117 * is used, and the subsequent register settings are not required
118 * unless a core reset is performed (they should be set properly
119 * by the first-stage boot loader, but may be reverted by a core
120 * reset). They may also break the configuration if USB3 is actually
121 * in use but the usb3-phy entry is missing from the device tree.
122 * Therefore, skip these operations in this case.
123 */
124 if (!priv_data->usb3_phy) {
125 /* Deselect the PIPE Clock Select bit in FPD PIPE Clock register */
126 writel(PIPE_CLK_DESELECT, priv_data->regs + XLNX_USB_FPD_PIPE_CLK);
127 goto skip_usb3_phy;
128 }
129
130 crst = devm_reset_control_get_exclusive(dev, "usb_crst");
131 if (IS_ERR(crst)) {
132 ret = PTR_ERR(crst);
133 dev_err_probe(dev, ret,
134 "failed to get core reset signal\n");
135 goto err;
136 }
137
138 hibrst = devm_reset_control_get_exclusive(dev, "usb_hibrst");
139 if (IS_ERR(hibrst)) {
140 ret = PTR_ERR(hibrst);
141 dev_err_probe(dev, ret,
142 "failed to get hibernation reset signal\n");
143 goto err;
144 }
145
146 apbrst = devm_reset_control_get_exclusive(dev, "usb_apbrst");
147 if (IS_ERR(apbrst)) {
148 ret = PTR_ERR(apbrst);
149 dev_err_probe(dev, ret,
150 "failed to get APB reset signal\n");
151 goto err;
152 }
153
154 ret = reset_control_assert(crst);
155 if (ret < 0) {
156 dev_err(dev, "Failed to assert core reset\n");
157 goto err;
158 }
159
160 ret = reset_control_assert(hibrst);
161 if (ret < 0) {
162 dev_err(dev, "Failed to assert hibernation reset\n");
163 goto err;
164 }
165
166 ret = reset_control_assert(apbrst);
167 if (ret < 0) {
168 dev_err(dev, "Failed to assert APB reset\n");
169 goto err;
170 }
171
172 ret = phy_init(priv_data->usb3_phy);
173 if (ret < 0) {
174 phy_exit(priv_data->usb3_phy);
175 goto err;
176 }
177
178 ret = reset_control_deassert(apbrst);
179 if (ret < 0) {
180 dev_err(dev, "Failed to release APB reset\n");
181 goto err;
182 }
183
184 /* Set PIPE Power Present signal in FPD Power Present Register*/
185 writel(FPD_POWER_PRSNT_OPTION, priv_data->regs + XLNX_USB_FPD_POWER_PRSNT);
186
187 /* Set the PIPE Clock Select bit in FPD PIPE Clock register */
188 writel(PIPE_CLK_SELECT, priv_data->regs + XLNX_USB_FPD_PIPE_CLK);
189
190 ret = reset_control_deassert(crst);
191 if (ret < 0) {
192 dev_err(dev, "Failed to release core reset\n");
193 goto err;
194 }
195
196 ret = reset_control_deassert(hibrst);
197 if (ret < 0) {
198 dev_err(dev, "Failed to release hibernation reset\n");
199 goto err;
200 }
201
202 ret = phy_power_on(priv_data->usb3_phy);
203 if (ret < 0) {
204 phy_exit(priv_data->usb3_phy);
205 goto err;
206 }
207
208 skip_usb3_phy:
209 /* ulpi reset via gpio-modepin or gpio-framework driver */
210 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
211 if (IS_ERR(reset_gpio)) {
212 return dev_err_probe(dev, PTR_ERR(reset_gpio),
213 "Failed to request reset GPIO\n");
214 }
215
216 if (reset_gpio) {
217 usleep_range(5000, 10000);
218 gpiod_set_value_cansleep(reset_gpio, 0);
219 usleep_range(5000, 10000);
220 }
221
222 /*
223 * This routes the USB DMA traffic to go through FPD path instead
224 * of reaching DDR directly. This traffic routing is needed to
225 * make SMMU and CCI work with USB DMA.
226 */
227 if (of_dma_is_coherent(dev->of_node) || device_iommu_mapped(dev)) {
228 reg = readl(priv_data->regs + XLNX_USB_TRAFFIC_ROUTE_CONFIG);
229 reg |= XLNX_USB_TRAFFIC_ROUTE_FPD;
230 writel(reg, priv_data->regs + XLNX_USB_TRAFFIC_ROUTE_CONFIG);
231 }
232
233 err:
234 return ret;
235 }
236
237 static const struct of_device_id dwc3_xlnx_of_match[] = {
238 {
239 .compatible = "xlnx,zynqmp-dwc3",
240 .data = &dwc3_xlnx_init_zynqmp,
241 },
242 {
243 .compatible = "xlnx,versal-dwc3",
244 .data = &dwc3_xlnx_init_versal,
245 },
246 { /* Sentinel */ }
247 };
248 MODULE_DEVICE_TABLE(of, dwc3_xlnx_of_match);
249
dwc3_xlnx_probe(struct platform_device * pdev)250 static int dwc3_xlnx_probe(struct platform_device *pdev)
251 {
252 struct dwc3_xlnx *priv_data;
253 struct device *dev = &pdev->dev;
254 struct device_node *np = dev->of_node;
255 const struct of_device_id *match;
256 void __iomem *regs;
257 int ret;
258
259 priv_data = devm_kzalloc(dev, sizeof(*priv_data), GFP_KERNEL);
260 if (!priv_data)
261 return -ENOMEM;
262
263 regs = devm_platform_ioremap_resource(pdev, 0);
264 if (IS_ERR(regs)) {
265 ret = PTR_ERR(regs);
266 dev_err_probe(dev, ret, "failed to map registers\n");
267 return ret;
268 }
269
270 match = of_match_node(dwc3_xlnx_of_match, pdev->dev.of_node);
271
272 priv_data->pltfm_init = match->data;
273 priv_data->regs = regs;
274 priv_data->dev = dev;
275
276 platform_set_drvdata(pdev, priv_data);
277
278 ret = devm_clk_bulk_get_all(priv_data->dev, &priv_data->clks);
279 if (ret < 0)
280 return ret;
281
282 priv_data->num_clocks = ret;
283
284 ret = clk_bulk_prepare_enable(priv_data->num_clocks, priv_data->clks);
285 if (ret)
286 return ret;
287
288 ret = priv_data->pltfm_init(priv_data);
289 if (ret)
290 goto err_clk_put;
291
292 ret = of_platform_populate(np, NULL, NULL, dev);
293 if (ret)
294 goto err_clk_put;
295
296 pm_runtime_set_active(dev);
297 pm_runtime_enable(dev);
298 pm_suspend_ignore_children(dev, false);
299 pm_runtime_get_sync(dev);
300
301 return 0;
302
303 err_clk_put:
304 clk_bulk_disable_unprepare(priv_data->num_clocks, priv_data->clks);
305
306 return ret;
307 }
308
dwc3_xlnx_remove(struct platform_device * pdev)309 static void dwc3_xlnx_remove(struct platform_device *pdev)
310 {
311 struct dwc3_xlnx *priv_data = platform_get_drvdata(pdev);
312 struct device *dev = &pdev->dev;
313
314 of_platform_depopulate(dev);
315
316 clk_bulk_disable_unprepare(priv_data->num_clocks, priv_data->clks);
317 priv_data->num_clocks = 0;
318
319 pm_runtime_disable(dev);
320 pm_runtime_put_noidle(dev);
321 pm_runtime_set_suspended(dev);
322 }
323
dwc3_xlnx_runtime_suspend(struct device * dev)324 static int __maybe_unused dwc3_xlnx_runtime_suspend(struct device *dev)
325 {
326 struct dwc3_xlnx *priv_data = dev_get_drvdata(dev);
327
328 clk_bulk_disable(priv_data->num_clocks, priv_data->clks);
329
330 return 0;
331 }
332
dwc3_xlnx_runtime_resume(struct device * dev)333 static int __maybe_unused dwc3_xlnx_runtime_resume(struct device *dev)
334 {
335 struct dwc3_xlnx *priv_data = dev_get_drvdata(dev);
336
337 return clk_bulk_enable(priv_data->num_clocks, priv_data->clks);
338 }
339
dwc3_xlnx_runtime_idle(struct device * dev)340 static int __maybe_unused dwc3_xlnx_runtime_idle(struct device *dev)
341 {
342 pm_runtime_mark_last_busy(dev);
343 pm_runtime_autosuspend(dev);
344
345 return 0;
346 }
347
dwc3_xlnx_suspend(struct device * dev)348 static int __maybe_unused dwc3_xlnx_suspend(struct device *dev)
349 {
350 struct dwc3_xlnx *priv_data = dev_get_drvdata(dev);
351
352 phy_exit(priv_data->usb3_phy);
353
354 /* Disable the clocks */
355 clk_bulk_disable(priv_data->num_clocks, priv_data->clks);
356
357 return 0;
358 }
359
dwc3_xlnx_resume(struct device * dev)360 static int __maybe_unused dwc3_xlnx_resume(struct device *dev)
361 {
362 struct dwc3_xlnx *priv_data = dev_get_drvdata(dev);
363 int ret;
364
365 ret = clk_bulk_enable(priv_data->num_clocks, priv_data->clks);
366 if (ret)
367 return ret;
368
369 ret = phy_init(priv_data->usb3_phy);
370 if (ret < 0)
371 return ret;
372
373 ret = phy_power_on(priv_data->usb3_phy);
374 if (ret < 0) {
375 phy_exit(priv_data->usb3_phy);
376 return ret;
377 }
378
379 return 0;
380 }
381
382 static const struct dev_pm_ops dwc3_xlnx_dev_pm_ops = {
383 SET_SYSTEM_SLEEP_PM_OPS(dwc3_xlnx_suspend, dwc3_xlnx_resume)
384 SET_RUNTIME_PM_OPS(dwc3_xlnx_runtime_suspend,
385 dwc3_xlnx_runtime_resume, dwc3_xlnx_runtime_idle)
386 };
387
388 static struct platform_driver dwc3_xlnx_driver = {
389 .probe = dwc3_xlnx_probe,
390 .remove_new = dwc3_xlnx_remove,
391 .driver = {
392 .name = "dwc3-xilinx",
393 .of_match_table = dwc3_xlnx_of_match,
394 .pm = &dwc3_xlnx_dev_pm_ops,
395 },
396 };
397
398 module_platform_driver(dwc3_xlnx_driver);
399
400 MODULE_LICENSE("GPL v2");
401 MODULE_DESCRIPTION("Xilinx DWC3 controller specific glue driver");
402 MODULE_AUTHOR("Manish Narani <manish.narani@xilinx.com>");
403 MODULE_AUTHOR("Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>");
404