1 // SPDX-License-Identifier: (GPL-2.0)
2 /*
3 * Microchip CoreSPI SPI controller driver
4 *
5 * Copyright (c) 2018-2022 Microchip Technology Inc. and its subsidiaries
6 *
7 * Author: Daire McNamara <daire.mcnamara@microchip.com>
8 * Author: Conor Dooley <conor.dooley@microchip.com>
9 *
10 */
11
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/err.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/platform_device.h>
21 #include <linux/spi/spi.h>
22
23 #define MAX_LEN (0xffff)
24 #define MAX_CS (1)
25 #define DEFAULT_FRAMESIZE (8)
26 #define FIFO_DEPTH (32)
27 #define CLK_GEN_MODE1_MAX (255)
28 #define CLK_GEN_MODE0_MAX (15)
29 #define CLK_GEN_MIN (0)
30 #define MODE_X_MASK_SHIFT (24)
31
32 #define CONTROL_ENABLE BIT(0)
33 #define CONTROL_MASTER BIT(1)
34 #define CONTROL_RX_DATA_INT BIT(4)
35 #define CONTROL_TX_DATA_INT BIT(5)
36 #define CONTROL_RX_OVER_INT BIT(6)
37 #define CONTROL_TX_UNDER_INT BIT(7)
38 #define CONTROL_SPO BIT(24)
39 #define CONTROL_SPH BIT(25)
40 #define CONTROL_SPS BIT(26)
41 #define CONTROL_FRAMEURUN BIT(27)
42 #define CONTROL_CLKMODE BIT(28)
43 #define CONTROL_BIGFIFO BIT(29)
44 #define CONTROL_OENOFF BIT(30)
45 #define CONTROL_RESET BIT(31)
46
47 #define CONTROL_MODE_MASK GENMASK(3, 2)
48 #define MOTOROLA_MODE (0)
49 #define CONTROL_FRAMECNT_MASK GENMASK(23, 8)
50 #define CONTROL_FRAMECNT_SHIFT (8)
51
52 #define STATUS_ACTIVE BIT(14)
53 #define STATUS_SSEL BIT(13)
54 #define STATUS_FRAMESTART BIT(12)
55 #define STATUS_TXFIFO_EMPTY_NEXT_READ BIT(11)
56 #define STATUS_TXFIFO_EMPTY BIT(10)
57 #define STATUS_TXFIFO_FULL_NEXT_WRITE BIT(9)
58 #define STATUS_TXFIFO_FULL BIT(8)
59 #define STATUS_RXFIFO_EMPTY_NEXT_READ BIT(7)
60 #define STATUS_RXFIFO_EMPTY BIT(6)
61 #define STATUS_RXFIFO_FULL_NEXT_WRITE BIT(5)
62 #define STATUS_RXFIFO_FULL BIT(4)
63 #define STATUS_TX_UNDERRUN BIT(3)
64 #define STATUS_RX_OVERFLOW BIT(2)
65 #define STATUS_RXDAT_RXED BIT(1)
66 #define STATUS_TXDAT_SENT BIT(0)
67
68 #define INT_TXDONE BIT(0)
69 #define INT_RXRDY BIT(1)
70 #define INT_RX_CHANNEL_OVERFLOW BIT(2)
71 #define INT_TX_CHANNEL_UNDERRUN BIT(3)
72
73 #define INT_ENABLE_MASK (CONTROL_RX_DATA_INT | CONTROL_TX_DATA_INT | \
74 CONTROL_RX_OVER_INT | CONTROL_TX_UNDER_INT)
75
76 #define REG_CONTROL (0x00)
77 #define REG_FRAME_SIZE (0x04)
78 #define FRAME_SIZE_MASK GENMASK(5, 0)
79 #define REG_STATUS (0x08)
80 #define REG_INT_CLEAR (0x0c)
81 #define REG_RX_DATA (0x10)
82 #define REG_TX_DATA (0x14)
83 #define REG_CLK_GEN (0x18)
84 #define REG_SLAVE_SELECT (0x1c)
85 #define SSEL_MASK GENMASK(7, 0)
86 #define SSEL_DIRECT BIT(8)
87 #define SSELOUT_SHIFT 9
88 #define SSELOUT BIT(SSELOUT_SHIFT)
89 #define REG_MIS (0x20)
90 #define REG_RIS (0x24)
91 #define REG_CONTROL2 (0x28)
92 #define REG_COMMAND (0x2c)
93 #define COMMAND_CLRFRAMECNT BIT(4)
94 #define COMMAND_TXFIFORST BIT(3)
95 #define COMMAND_RXFIFORST BIT(2)
96 #define REG_PKTSIZE (0x30)
97 #define REG_CMD_SIZE (0x34)
98 #define REG_HWSTATUS (0x38)
99 #define REG_STAT8 (0x3c)
100 #define REG_CTRL2 (0x48)
101 #define REG_FRAMESUP (0x50)
102
103 struct mchp_corespi {
104 void __iomem *regs;
105 struct clk *clk;
106 const u8 *tx_buf;
107 u8 *rx_buf;
108 u32 clk_gen; /* divider for spi output clock generated by the controller */
109 u32 clk_mode;
110 u32 pending_slave_select;
111 int irq;
112 int tx_len;
113 int rx_len;
114 int pending;
115 };
116
mchp_corespi_read(struct mchp_corespi * spi,unsigned int reg)117 static inline u32 mchp_corespi_read(struct mchp_corespi *spi, unsigned int reg)
118 {
119 return readl(spi->regs + reg);
120 }
121
mchp_corespi_write(struct mchp_corespi * spi,unsigned int reg,u32 val)122 static inline void mchp_corespi_write(struct mchp_corespi *spi, unsigned int reg, u32 val)
123 {
124 writel(val, spi->regs + reg);
125 }
126
mchp_corespi_disable(struct mchp_corespi * spi)127 static inline void mchp_corespi_disable(struct mchp_corespi *spi)
128 {
129 u32 control = mchp_corespi_read(spi, REG_CONTROL);
130
131 control &= ~CONTROL_ENABLE;
132
133 mchp_corespi_write(spi, REG_CONTROL, control);
134 }
135
mchp_corespi_read_fifo(struct mchp_corespi * spi)136 static inline void mchp_corespi_read_fifo(struct mchp_corespi *spi)
137 {
138 u8 data;
139 int fifo_max, i = 0;
140
141 fifo_max = min(spi->rx_len, FIFO_DEPTH);
142
143 while ((i < fifo_max) && !(mchp_corespi_read(spi, REG_STATUS) & STATUS_RXFIFO_EMPTY)) {
144 data = mchp_corespi_read(spi, REG_RX_DATA);
145
146 if (spi->rx_buf)
147 *spi->rx_buf++ = data;
148 i++;
149 }
150 spi->rx_len -= i;
151 spi->pending -= i;
152 }
153
mchp_corespi_enable_ints(struct mchp_corespi * spi)154 static void mchp_corespi_enable_ints(struct mchp_corespi *spi)
155 {
156 u32 control = mchp_corespi_read(spi, REG_CONTROL);
157
158 control |= INT_ENABLE_MASK;
159 mchp_corespi_write(spi, REG_CONTROL, control);
160 }
161
mchp_corespi_disable_ints(struct mchp_corespi * spi)162 static void mchp_corespi_disable_ints(struct mchp_corespi *spi)
163 {
164 u32 control = mchp_corespi_read(spi, REG_CONTROL);
165
166 control &= ~INT_ENABLE_MASK;
167 mchp_corespi_write(spi, REG_CONTROL, control);
168 }
169
mchp_corespi_set_xfer_size(struct mchp_corespi * spi,int len)170 static inline void mchp_corespi_set_xfer_size(struct mchp_corespi *spi, int len)
171 {
172 u32 control;
173 u32 lenpart;
174 u32 frames = mchp_corespi_read(spi, REG_FRAMESUP);
175
176 /*
177 * Writing to FRAMECNT in REG_CONTROL will reset the frame count, taking
178 * a shortcut requires an explicit clear.
179 */
180 if (frames == len) {
181 mchp_corespi_write(spi, REG_COMMAND, COMMAND_CLRFRAMECNT);
182 return;
183 }
184
185 /*
186 * The lower 16 bits of the frame count are stored in the control reg
187 * for legacy reasons, but the upper 16 written to a different register:
188 * FRAMESUP. While both the upper and lower bits can be *READ* from the
189 * FRAMESUP register, writing to the lower 16 bits is (supposedly) a NOP.
190 *
191 * The driver used to disable the controller while modifying the frame
192 * count, and mask off the lower 16 bits of len while writing to
193 * FRAMES_UP. When the driver was changed to disable the controller as
194 * infrequently as possible, it was discovered that the logic of
195 * lenpart = len & 0xffff_0000
196 * write(REG_FRAMESUP, lenpart)
197 * would actually write zeros into the lower 16 bits on an mpfs250t-es,
198 * despite documentation stating these bits were read-only.
199 * Writing len unmasked into FRAMES_UP ensures those bits aren't zeroed
200 * on an mpfs250t-es and will be a NOP for the lower 16 bits on hardware
201 * that matches the documentation.
202 */
203 lenpart = len & 0xffff;
204 control = mchp_corespi_read(spi, REG_CONTROL);
205 control &= ~CONTROL_FRAMECNT_MASK;
206 control |= lenpart << CONTROL_FRAMECNT_SHIFT;
207 mchp_corespi_write(spi, REG_CONTROL, control);
208 mchp_corespi_write(spi, REG_FRAMESUP, len);
209 }
210
mchp_corespi_write_fifo(struct mchp_corespi * spi)211 static inline void mchp_corespi_write_fifo(struct mchp_corespi *spi)
212 {
213 u8 byte;
214 int fifo_max, i = 0;
215
216 fifo_max = min(spi->tx_len, FIFO_DEPTH);
217 mchp_corespi_set_xfer_size(spi, fifo_max);
218
219 while ((i < fifo_max) && !(mchp_corespi_read(spi, REG_STATUS) & STATUS_TXFIFO_FULL)) {
220 byte = spi->tx_buf ? *spi->tx_buf++ : 0xaa;
221 mchp_corespi_write(spi, REG_TX_DATA, byte);
222 i++;
223 }
224
225 spi->tx_len -= i;
226 spi->pending += i;
227 }
228
mchp_corespi_set_framesize(struct mchp_corespi * spi,int bt)229 static inline void mchp_corespi_set_framesize(struct mchp_corespi *spi, int bt)
230 {
231 u32 frame_size = mchp_corespi_read(spi, REG_FRAME_SIZE);
232 u32 control;
233
234 if ((frame_size & FRAME_SIZE_MASK) == bt)
235 return;
236
237 /*
238 * Disable the SPI controller. Writes to the frame size have
239 * no effect when the controller is enabled.
240 */
241 control = mchp_corespi_read(spi, REG_CONTROL);
242 control &= ~CONTROL_ENABLE;
243 mchp_corespi_write(spi, REG_CONTROL, control);
244
245 mchp_corespi_write(spi, REG_FRAME_SIZE, bt);
246
247 control |= CONTROL_ENABLE;
248 mchp_corespi_write(spi, REG_CONTROL, control);
249 }
250
mchp_corespi_set_cs(struct spi_device * spi,bool disable)251 static void mchp_corespi_set_cs(struct spi_device *spi, bool disable)
252 {
253 u32 reg;
254 struct mchp_corespi *corespi = spi_controller_get_devdata(spi->controller);
255
256 reg = mchp_corespi_read(corespi, REG_SLAVE_SELECT);
257 reg &= ~BIT(spi_get_chipselect(spi, 0));
258 reg |= !disable << spi_get_chipselect(spi, 0);
259 corespi->pending_slave_select = reg;
260
261 /*
262 * Only deassert chip select immediately. Writing to some registers
263 * requires the controller to be disabled, which results in the
264 * output pins being tristated and can cause the SCLK and MOSI lines
265 * to transition. Therefore asserting the chip select is deferred
266 * until just before writing to the TX FIFO, to ensure the device
267 * doesn't see any spurious clock transitions whilst CS is enabled.
268 */
269 if (((spi->mode & SPI_CS_HIGH) == 0) == disable)
270 mchp_corespi_write(corespi, REG_SLAVE_SELECT, reg);
271 }
272
mchp_corespi_setup(struct spi_device * spi)273 static int mchp_corespi_setup(struct spi_device *spi)
274 {
275 struct mchp_corespi *corespi = spi_controller_get_devdata(spi->controller);
276 u32 reg;
277
278 /*
279 * Active high targets need to be specifically set to their inactive
280 * states during probe by adding them to the "control group" & thus
281 * driving their select line low.
282 */
283 if (spi->mode & SPI_CS_HIGH) {
284 reg = mchp_corespi_read(corespi, REG_SLAVE_SELECT);
285 reg |= BIT(spi_get_chipselect(spi, 0));
286 corespi->pending_slave_select = reg;
287 mchp_corespi_write(corespi, REG_SLAVE_SELECT, reg);
288 }
289 return 0;
290 }
291
mchp_corespi_init(struct spi_controller * host,struct mchp_corespi * spi)292 static void mchp_corespi_init(struct spi_controller *host, struct mchp_corespi *spi)
293 {
294 unsigned long clk_hz;
295 u32 control = mchp_corespi_read(spi, REG_CONTROL);
296
297 control &= ~CONTROL_ENABLE;
298 mchp_corespi_write(spi, REG_CONTROL, control);
299
300 control |= CONTROL_MASTER;
301 control &= ~CONTROL_MODE_MASK;
302 control |= MOTOROLA_MODE;
303
304 /*
305 * The controller must be configured so that it doesn't remove Chip
306 * Select until the entire message has been transferred, even if at
307 * some points TX FIFO becomes empty.
308 *
309 * BIGFIFO mode is also enabled, which sets the fifo depth to 32 frames
310 * for the 8 bit transfers that this driver uses.
311 */
312 control |= CONTROL_SPS | CONTROL_BIGFIFO;
313
314 mchp_corespi_write(spi, REG_CONTROL, control);
315
316 mchp_corespi_set_framesize(spi, DEFAULT_FRAMESIZE);
317
318 /* max. possible spi clock rate is the apb clock rate */
319 clk_hz = clk_get_rate(spi->clk);
320 host->max_speed_hz = clk_hz;
321
322 mchp_corespi_enable_ints(spi);
323
324 /*
325 * It is required to enable direct mode, otherwise control over the chip
326 * select is relinquished to the hardware. SSELOUT is enabled too so we
327 * can deal with active high targets.
328 */
329 spi->pending_slave_select = SSELOUT | SSEL_DIRECT;
330 mchp_corespi_write(spi, REG_SLAVE_SELECT, spi->pending_slave_select);
331
332 control = mchp_corespi_read(spi, REG_CONTROL);
333
334 control &= ~CONTROL_RESET;
335 control |= CONTROL_ENABLE;
336
337 mchp_corespi_write(spi, REG_CONTROL, control);
338 }
339
mchp_corespi_set_clk_gen(struct mchp_corespi * spi)340 static inline void mchp_corespi_set_clk_gen(struct mchp_corespi *spi)
341 {
342 u32 control;
343
344 control = mchp_corespi_read(spi, REG_CONTROL);
345 if (spi->clk_mode)
346 control |= CONTROL_CLKMODE;
347 else
348 control &= ~CONTROL_CLKMODE;
349
350 mchp_corespi_write(spi, REG_CLK_GEN, spi->clk_gen);
351 mchp_corespi_write(spi, REG_CONTROL, control);
352 }
353
mchp_corespi_set_mode(struct mchp_corespi * spi,unsigned int mode)354 static inline void mchp_corespi_set_mode(struct mchp_corespi *spi, unsigned int mode)
355 {
356 u32 mode_val;
357 u32 control = mchp_corespi_read(spi, REG_CONTROL);
358
359 switch (mode & SPI_MODE_X_MASK) {
360 case SPI_MODE_0:
361 mode_val = 0;
362 break;
363 case SPI_MODE_1:
364 mode_val = CONTROL_SPH;
365 break;
366 case SPI_MODE_2:
367 mode_val = CONTROL_SPO;
368 break;
369 case SPI_MODE_3:
370 mode_val = CONTROL_SPH | CONTROL_SPO;
371 break;
372 }
373
374 /*
375 * Disable the SPI controller. Writes to the frame protocol have
376 * no effect when the controller is enabled.
377 */
378
379 control &= ~CONTROL_ENABLE;
380 mchp_corespi_write(spi, REG_CONTROL, control);
381
382 control &= ~(SPI_MODE_X_MASK << MODE_X_MASK_SHIFT);
383 control |= mode_val;
384
385 mchp_corespi_write(spi, REG_CONTROL, control);
386
387 control |= CONTROL_ENABLE;
388 mchp_corespi_write(spi, REG_CONTROL, control);
389 }
390
mchp_corespi_interrupt(int irq,void * dev_id)391 static irqreturn_t mchp_corespi_interrupt(int irq, void *dev_id)
392 {
393 struct spi_controller *host = dev_id;
394 struct mchp_corespi *spi = spi_controller_get_devdata(host);
395 u32 intfield = mchp_corespi_read(spi, REG_MIS) & 0xf;
396 bool finalise = false;
397
398 /* Interrupt line may be shared and not for us at all */
399 if (intfield == 0)
400 return IRQ_NONE;
401
402 if (intfield & INT_TXDONE)
403 mchp_corespi_write(spi, REG_INT_CLEAR, INT_TXDONE);
404
405 if (intfield & INT_RXRDY) {
406 mchp_corespi_write(spi, REG_INT_CLEAR, INT_RXRDY);
407
408 if (spi->rx_len)
409 mchp_corespi_read_fifo(spi);
410 }
411
412 if (!spi->rx_len && !spi->tx_len)
413 finalise = true;
414
415 if (intfield & INT_RX_CHANNEL_OVERFLOW) {
416 mchp_corespi_write(spi, REG_INT_CLEAR, INT_RX_CHANNEL_OVERFLOW);
417 finalise = true;
418 dev_err(&host->dev,
419 "%s: RX OVERFLOW: rxlen: %d, txlen: %d\n", __func__,
420 spi->rx_len, spi->tx_len);
421 }
422
423 if (intfield & INT_TX_CHANNEL_UNDERRUN) {
424 mchp_corespi_write(spi, REG_INT_CLEAR, INT_TX_CHANNEL_UNDERRUN);
425 finalise = true;
426 dev_err(&host->dev,
427 "%s: TX UNDERFLOW: rxlen: %d, txlen: %d\n", __func__,
428 spi->rx_len, spi->tx_len);
429 }
430
431 if (finalise)
432 spi_finalize_current_transfer(host);
433
434 return IRQ_HANDLED;
435 }
436
mchp_corespi_calculate_clkgen(struct mchp_corespi * spi,unsigned long target_hz)437 static int mchp_corespi_calculate_clkgen(struct mchp_corespi *spi,
438 unsigned long target_hz)
439 {
440 unsigned long clk_hz, spi_hz, clk_gen;
441
442 clk_hz = clk_get_rate(spi->clk);
443 if (!clk_hz)
444 return -EINVAL;
445 spi_hz = min(target_hz, clk_hz);
446
447 /*
448 * There are two possible clock modes for the controller generated
449 * clock's division ratio:
450 * CLK_MODE = 0: 1 / (2^(CLK_GEN + 1)) where CLK_GEN = 0 to 15.
451 * CLK_MODE = 1: 1 / (2 * CLK_GEN + 1) where CLK_GEN = 0 to 255.
452 * First try mode 1, fall back to 0 and if we have tried both modes and
453 * we /still/ can't get a good setting, we then throw the toys out of
454 * the pram and give up
455 * clk_gen is the register name for the clock divider on MPFS.
456 */
457 clk_gen = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1;
458 if (clk_gen > CLK_GEN_MODE1_MAX || clk_gen <= CLK_GEN_MIN) {
459 clk_gen = DIV_ROUND_UP(clk_hz, spi_hz);
460 clk_gen = fls(clk_gen) - 1;
461
462 if (clk_gen > CLK_GEN_MODE0_MAX)
463 return -EINVAL;
464
465 spi->clk_mode = 0;
466 } else {
467 spi->clk_mode = 1;
468 }
469
470 spi->clk_gen = clk_gen;
471 return 0;
472 }
473
mchp_corespi_transfer_one(struct spi_controller * host,struct spi_device * spi_dev,struct spi_transfer * xfer)474 static int mchp_corespi_transfer_one(struct spi_controller *host,
475 struct spi_device *spi_dev,
476 struct spi_transfer *xfer)
477 {
478 struct mchp_corespi *spi = spi_controller_get_devdata(host);
479 int ret;
480
481 ret = mchp_corespi_calculate_clkgen(spi, (unsigned long)xfer->speed_hz);
482 if (ret) {
483 dev_err(&host->dev, "failed to set clk_gen for target %u Hz\n", xfer->speed_hz);
484 return ret;
485 }
486
487 mchp_corespi_set_clk_gen(spi);
488
489 spi->tx_buf = xfer->tx_buf;
490 spi->rx_buf = xfer->rx_buf;
491 spi->tx_len = xfer->len;
492 spi->rx_len = xfer->len;
493 spi->pending = 0;
494
495 mchp_corespi_set_xfer_size(spi, (spi->tx_len > FIFO_DEPTH)
496 ? FIFO_DEPTH : spi->tx_len);
497
498 mchp_corespi_write(spi, REG_COMMAND, COMMAND_RXFIFORST | COMMAND_TXFIFORST);
499
500 mchp_corespi_write(spi, REG_SLAVE_SELECT, spi->pending_slave_select);
501
502 while (spi->tx_len)
503 mchp_corespi_write_fifo(spi);
504
505 return 1;
506 }
507
mchp_corespi_prepare_message(struct spi_controller * host,struct spi_message * msg)508 static int mchp_corespi_prepare_message(struct spi_controller *host,
509 struct spi_message *msg)
510 {
511 struct spi_device *spi_dev = msg->spi;
512 struct mchp_corespi *spi = spi_controller_get_devdata(host);
513
514 mchp_corespi_set_framesize(spi, DEFAULT_FRAMESIZE);
515 mchp_corespi_set_mode(spi, spi_dev->mode);
516
517 return 0;
518 }
519
mchp_corespi_probe(struct platform_device * pdev)520 static int mchp_corespi_probe(struct platform_device *pdev)
521 {
522 struct spi_controller *host;
523 struct mchp_corespi *spi;
524 struct resource *res;
525 u32 num_cs;
526 int ret = 0;
527
528 host = devm_spi_alloc_host(&pdev->dev, sizeof(*spi));
529 if (!host)
530 return dev_err_probe(&pdev->dev, -ENOMEM,
531 "unable to allocate host for SPI controller\n");
532
533 platform_set_drvdata(pdev, host);
534
535 if (of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs))
536 num_cs = MAX_CS;
537
538 host->num_chipselect = num_cs;
539 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
540 host->setup = mchp_corespi_setup;
541 host->bits_per_word_mask = SPI_BPW_MASK(8);
542 host->transfer_one = mchp_corespi_transfer_one;
543 host->prepare_message = mchp_corespi_prepare_message;
544 host->set_cs = mchp_corespi_set_cs;
545 host->dev.of_node = pdev->dev.of_node;
546
547 spi = spi_controller_get_devdata(host);
548
549 spi->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
550 if (IS_ERR(spi->regs))
551 return PTR_ERR(spi->regs);
552
553 spi->irq = platform_get_irq(pdev, 0);
554 if (spi->irq < 0)
555 return spi->irq;
556
557 ret = devm_request_irq(&pdev->dev, spi->irq, mchp_corespi_interrupt,
558 IRQF_SHARED, dev_name(&pdev->dev), host);
559 if (ret)
560 return dev_err_probe(&pdev->dev, ret,
561 "could not request irq\n");
562
563 spi->clk = devm_clk_get(&pdev->dev, NULL);
564 if (IS_ERR(spi->clk))
565 return dev_err_probe(&pdev->dev, PTR_ERR(spi->clk),
566 "could not get clk\n");
567
568 ret = clk_prepare_enable(spi->clk);
569 if (ret)
570 return dev_err_probe(&pdev->dev, ret,
571 "failed to enable clock\n");
572
573 mchp_corespi_init(host, spi);
574
575 ret = devm_spi_register_controller(&pdev->dev, host);
576 if (ret) {
577 mchp_corespi_disable(spi);
578 clk_disable_unprepare(spi->clk);
579 return dev_err_probe(&pdev->dev, ret,
580 "unable to register host for SPI controller\n");
581 }
582
583 dev_info(&pdev->dev, "Registered SPI controller %d\n", host->bus_num);
584
585 return 0;
586 }
587
mchp_corespi_remove(struct platform_device * pdev)588 static void mchp_corespi_remove(struct platform_device *pdev)
589 {
590 struct spi_controller *host = platform_get_drvdata(pdev);
591 struct mchp_corespi *spi = spi_controller_get_devdata(host);
592
593 mchp_corespi_disable_ints(spi);
594 clk_disable_unprepare(spi->clk);
595 mchp_corespi_disable(spi);
596 }
597
598 #define MICROCHIP_SPI_PM_OPS (NULL)
599
600 /*
601 * Platform driver data structure
602 */
603
604 #if defined(CONFIG_OF)
605 static const struct of_device_id mchp_corespi_dt_ids[] = {
606 { .compatible = "microchip,mpfs-spi" },
607 { /* sentinel */ }
608 };
609 MODULE_DEVICE_TABLE(of, mchp_corespi_dt_ids);
610 #endif
611
612 static struct platform_driver mchp_corespi_driver = {
613 .probe = mchp_corespi_probe,
614 .driver = {
615 .name = "microchip-corespi",
616 .pm = MICROCHIP_SPI_PM_OPS,
617 .of_match_table = of_match_ptr(mchp_corespi_dt_ids),
618 },
619 .remove_new = mchp_corespi_remove,
620 };
621 module_platform_driver(mchp_corespi_driver);
622 MODULE_DESCRIPTION("Microchip coreSPI SPI controller driver");
623 MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>");
624 MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
625 MODULE_LICENSE("GPL");
626