1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * PolarFire SoC (MPFS) Peripheral Clock Reset Controller
4 *
5 * Author: Conor Dooley <conor.dooley@microchip.com>
6 * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries.
7 *
8 */
9 #include <linux/auxiliary_bus.h>
10 #include <linux/delay.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/platform_device.h>
14 #include <linux/reset-controller.h>
15 #include <dt-bindings/clock/microchip,mpfs-clock.h>
16 #include <soc/microchip/mpfs.h>
17
18 /*
19 * The ENVM reset is the lowest bit in the register & I am using the CLK_FOO
20 * defines in the dt to make things easier to configure - so this is accounting
21 * for the offset of 3 there.
22 */
23 #define MPFS_PERIPH_OFFSET CLK_ENVM
24 #define MPFS_NUM_RESETS 30u
25 #define MPFS_SLEEP_MIN_US 100
26 #define MPFS_SLEEP_MAX_US 200
27
28 /* block concurrent access to the soft reset register */
29 static DEFINE_SPINLOCK(mpfs_reset_lock);
30
31 /*
32 * Peripheral clock resets
33 */
34
mpfs_assert(struct reset_controller_dev * rcdev,unsigned long id)35 static int mpfs_assert(struct reset_controller_dev *rcdev, unsigned long id)
36 {
37 unsigned long flags;
38 u32 reg;
39
40 spin_lock_irqsave(&mpfs_reset_lock, flags);
41
42 reg = mpfs_reset_read(rcdev->dev);
43 reg |= BIT(id);
44 mpfs_reset_write(rcdev->dev, reg);
45
46 spin_unlock_irqrestore(&mpfs_reset_lock, flags);
47
48 return 0;
49 }
50
mpfs_deassert(struct reset_controller_dev * rcdev,unsigned long id)51 static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long id)
52 {
53 unsigned long flags;
54 u32 reg;
55
56 spin_lock_irqsave(&mpfs_reset_lock, flags);
57
58 reg = mpfs_reset_read(rcdev->dev);
59 reg &= ~BIT(id);
60 mpfs_reset_write(rcdev->dev, reg);
61
62 spin_unlock_irqrestore(&mpfs_reset_lock, flags);
63
64 return 0;
65 }
66
mpfs_status(struct reset_controller_dev * rcdev,unsigned long id)67 static int mpfs_status(struct reset_controller_dev *rcdev, unsigned long id)
68 {
69 u32 reg = mpfs_reset_read(rcdev->dev);
70
71 /*
72 * It is safe to return here as MPFS_NUM_RESETS makes sure the sign bit
73 * is never hit.
74 */
75 return (reg & BIT(id));
76 }
77
mpfs_reset(struct reset_controller_dev * rcdev,unsigned long id)78 static int mpfs_reset(struct reset_controller_dev *rcdev, unsigned long id)
79 {
80 mpfs_assert(rcdev, id);
81
82 usleep_range(MPFS_SLEEP_MIN_US, MPFS_SLEEP_MAX_US);
83
84 mpfs_deassert(rcdev, id);
85
86 return 0;
87 }
88
89 static const struct reset_control_ops mpfs_reset_ops = {
90 .reset = mpfs_reset,
91 .assert = mpfs_assert,
92 .deassert = mpfs_deassert,
93 .status = mpfs_status,
94 };
95
mpfs_reset_xlate(struct reset_controller_dev * rcdev,const struct of_phandle_args * reset_spec)96 static int mpfs_reset_xlate(struct reset_controller_dev *rcdev,
97 const struct of_phandle_args *reset_spec)
98 {
99 unsigned int index = reset_spec->args[0];
100
101 /*
102 * CLK_RESERVED does not map to a clock, but it does map to a reset,
103 * so it has to be accounted for here. It is the reset for the fabric,
104 * so if this reset gets called - do not reset it.
105 */
106 if (index == CLK_RESERVED) {
107 dev_err(rcdev->dev, "Resetting the fabric is not supported\n");
108 return -EINVAL;
109 }
110
111 if (index < MPFS_PERIPH_OFFSET || index >= (MPFS_PERIPH_OFFSET + rcdev->nr_resets)) {
112 dev_err(rcdev->dev, "Invalid reset index %u\n", index);
113 return -EINVAL;
114 }
115
116 return index - MPFS_PERIPH_OFFSET;
117 }
118
mpfs_reset_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)119 static int mpfs_reset_probe(struct auxiliary_device *adev,
120 const struct auxiliary_device_id *id)
121 {
122 struct device *dev = &adev->dev;
123 struct reset_controller_dev *rcdev;
124
125 rcdev = devm_kzalloc(dev, sizeof(*rcdev), GFP_KERNEL);
126 if (!rcdev)
127 return -ENOMEM;
128
129 rcdev->dev = dev;
130 rcdev->dev->parent = dev->parent;
131 rcdev->ops = &mpfs_reset_ops;
132 rcdev->of_node = dev->parent->of_node;
133 rcdev->of_reset_n_cells = 1;
134 rcdev->of_xlate = mpfs_reset_xlate;
135 rcdev->nr_resets = MPFS_NUM_RESETS;
136
137 return devm_reset_controller_register(dev, rcdev);
138 }
139
140 static const struct auxiliary_device_id mpfs_reset_ids[] = {
141 {
142 .name = "clk_mpfs.reset-mpfs",
143 },
144 { }
145 };
146 MODULE_DEVICE_TABLE(auxiliary, mpfs_reset_ids);
147
148 static struct auxiliary_driver mpfs_reset_driver = {
149 .probe = mpfs_reset_probe,
150 .id_table = mpfs_reset_ids,
151 };
152
153 module_auxiliary_driver(mpfs_reset_driver);
154
155 MODULE_DESCRIPTION("Microchip PolarFire SoC Reset Driver");
156 MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
157 MODULE_IMPORT_NS(MCHP_CLK_MPFS);
158