1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef DAL_DC_314_SMU_H_ 28 #define DAL_DC_314_SMU_H_ 29 30 #include "smu13_driver_if_v13_0_4.h" 31 32 typedef enum { 33 WCK_RATIO_1_1 = 0, // DDR5, Wck:ck is always 1:1; 34 WCK_RATIO_1_2, 35 WCK_RATIO_1_4, 36 WCK_RATIO_MAX 37 } WCK_RATIO_e; 38 39 typedef struct { 40 uint32_t FClk; 41 uint32_t MemClk; 42 uint32_t Voltage; 43 uint8_t WckRatio; 44 uint8_t Spare[3]; 45 } DfPstateTable314_t; 46 47 //Freq in MHz 48 //Voltage in milli volts with 2 fractional bits 49 typedef struct { 50 uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS]; 51 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS]; 52 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS]; 53 uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS]; 54 uint32_t VClocks[NUM_VCN_DPM_LEVELS]; 55 uint32_t DClocks[NUM_VCN_DPM_LEVELS]; 56 uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS]; 57 DfPstateTable314_t DfPstateTable[NUM_DF_PSTATE_LEVELS]; 58 59 uint8_t NumDcfClkLevelsEnabled; 60 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk 61 uint8_t NumSocClkLevelsEnabled; 62 uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk 63 uint8_t NumDfPstatesEnabled; 64 uint8_t spare[3]; 65 66 uint32_t MinGfxClk; 67 uint32_t MaxGfxClk; 68 } DpmClocks314_t; 69 70 struct dcn314_watermarks { 71 // Watermarks 72 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; 73 uint32_t MmHubPadding[7]; // SMU internal use 74 }; 75 76 struct dcn314_smu_dpm_clks { 77 DpmClocks314_t *dpm_clks; 78 union large_integer mc_address; 79 }; 80 81 struct display_idle_optimization { 82 unsigned int df_request_disabled : 1; 83 unsigned int phy_ref_clk_off : 1; 84 unsigned int s0i2_rdy : 1; 85 unsigned int reserved : 29; 86 }; 87 88 union display_idle_optimization_u { 89 struct display_idle_optimization idle_info; 90 uint32_t data; 91 }; 92 93 int dcn314_smu_get_smu_version(struct clk_mgr_internal *clk_mgr); 94 int dcn314_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz); 95 int dcn314_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr); 96 int dcn314_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz); 97 int dcn314_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz); 98 int dcn314_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz); 99 void dcn314_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info); 100 void dcn314_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable); 101 void dcn314_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr); 102 void dcn314_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high); 103 void dcn314_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low); 104 void dcn314_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr); 105 void dcn314_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr); 106 107 void dcn314_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support); 108 void dcn314_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable); 109 110 #endif /* DAL_DC_314_SMU_H_ */ 111