1/* Xtensa configuration-specific ISA information. 2 Copyright 2003, 2004, 2005 Free Software Foundation, Inc. 3 4 This file is part of BFD, the Binary File Descriptor library. 5 6 This program is free software; you can redistribute it and/or 7 modify it under the terms of the GNU General Public License as 8 published by the Free Software Foundation; either version 2 of the 9 License, or (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, see 18 <https://www.gnu.org/licenses/>. */ 19 20#include "qemu/osdep.h" 21#include "xtensa-isa.h" 22#include "xtensa-isa-internal.h" 23 24 25/* Sysregs. */ 26 27static xtensa_sysreg_internal sysregs[] = { 28 { "LBEG", 0, 0 }, 29 { "LEND", 1, 0 }, 30 { "LCOUNT", 2, 0 }, 31 { "PTEVADDR", 83, 0 }, 32 { "DDR", 104, 0 }, 33 { "176", 176, 0 }, 34 { "208", 208, 0 }, 35 { "INTERRUPT", 226, 0 }, 36 { "INTCLEAR", 227, 0 }, 37 { "CCOUNT", 234, 0 }, 38 { "PRID", 235, 0 }, 39 { "ICOUNT", 236, 0 }, 40 { "CCOMPARE0", 240, 0 }, 41 { "CCOMPARE1", 241, 0 }, 42 { "CCOMPARE2", 242, 0 }, 43 { "EPC1", 177, 0 }, 44 { "EPC2", 178, 0 }, 45 { "EPC3", 179, 0 }, 46 { "EPC4", 180, 0 }, 47 { "EXCSAVE1", 209, 0 }, 48 { "EXCSAVE2", 210, 0 }, 49 { "EXCSAVE3", 211, 0 }, 50 { "EXCSAVE4", 212, 0 }, 51 { "EPS2", 194, 0 }, 52 { "EPS3", 195, 0 }, 53 { "EPS4", 196, 0 }, 54 { "EXCCAUSE", 232, 0 }, 55 { "DEPC", 192, 0 }, 56 { "EXCVADDR", 238, 0 }, 57 { "WINDOWBASE", 72, 0 }, 58 { "WINDOWSTART", 73, 0 }, 59 { "SAR", 3, 0 }, 60 { "LITBASE", 5, 0 }, 61 { "PS", 230, 0 }, 62 { "MISC0", 244, 0 }, 63 { "MISC1", 245, 0 }, 64 { "INTENABLE", 228, 0 }, 65 { "DBREAKA0", 144, 0 }, 66 { "DBREAKC0", 160, 0 }, 67 { "DBREAKA1", 145, 0 }, 68 { "DBREAKC1", 161, 0 }, 69 { "IBREAKA0", 128, 0 }, 70 { "IBREAKA1", 129, 0 }, 71 { "IBREAKENABLE", 96, 0 }, 72 { "ICOUNTLEVEL", 237, 0 }, 73 { "DEBUGCAUSE", 233, 0 }, 74 { "RASID", 90, 0 }, 75 { "ITLBCFG", 91, 0 }, 76 { "DTLBCFG", 92, 0 } 77}; 78 79#define NUM_SYSREGS 49 80#define MAX_SPECIAL_REG 245 81#define MAX_USER_REG 0 82 83 84/* Processor states. */ 85 86static xtensa_state_internal states[] = { 87 { "LCOUNT", 32, 0 }, 88 { "PC", 32, 0 }, 89 { "ICOUNT", 32, 0 }, 90 { "DDR", 32, 0 }, 91 { "INTERRUPT", 17, 0 }, 92 { "CCOUNT", 32, 0 }, 93 { "XTSYNC", 1, 0 }, 94 { "EPC1", 32, 0 }, 95 { "EPC2", 32, 0 }, 96 { "EPC3", 32, 0 }, 97 { "EPC4", 32, 0 }, 98 { "EXCSAVE1", 32, 0 }, 99 { "EXCSAVE2", 32, 0 }, 100 { "EXCSAVE3", 32, 0 }, 101 { "EXCSAVE4", 32, 0 }, 102 { "EPS2", 15, 0 }, 103 { "EPS3", 15, 0 }, 104 { "EPS4", 15, 0 }, 105 { "EXCCAUSE", 6, 0 }, 106 { "PSINTLEVEL", 4, 0 }, 107 { "PSUM", 1, 0 }, 108 { "PSWOE", 1, 0 }, 109 { "PSRING", 2, 0 }, 110 { "PSEXCM", 1, 0 }, 111 { "DEPC", 32, 0 }, 112 { "EXCVADDR", 32, 0 }, 113 { "WindowBase", 4, 0 }, 114 { "WindowStart", 16, 0 }, 115 { "PSCALLINC", 2, 0 }, 116 { "PSOWB", 4, 0 }, 117 { "LBEG", 32, 0 }, 118 { "LEND", 32, 0 }, 119 { "SAR", 6, 0 }, 120 { "LITBADDR", 20, 0 }, 121 { "LITBEN", 1, 0 }, 122 { "MISC0", 32, 0 }, 123 { "MISC1", 32, 0 }, 124 { "InOCDMode", 1, 0 }, 125 { "INTENABLE", 17, 0 }, 126 { "DBREAKA0", 32, 0 }, 127 { "DBREAKC0", 8, 0 }, 128 { "DBREAKA1", 32, 0 }, 129 { "DBREAKC1", 8, 0 }, 130 { "IBREAKA0", 32, 0 }, 131 { "IBREAKA1", 32, 0 }, 132 { "IBREAKENABLE", 2, 0 }, 133 { "ICOUNTLEVEL", 4, 0 }, 134 { "DEBUGCAUSE", 6, 0 }, 135 { "DBNUM", 4, 0 }, 136 { "CCOMPARE0", 32, 0 }, 137 { "CCOMPARE1", 32, 0 }, 138 { "CCOMPARE2", 32, 0 }, 139 { "ASID3", 8, 0 }, 140 { "ASID2", 8, 0 }, 141 { "ASID1", 8, 0 }, 142 { "INSTPGSZID4", 2, 0 }, 143 { "DATAPGSZID4", 2, 0 }, 144 { "PTBASE", 10, 0 } 145}; 146 147#define NUM_STATES 58 148 149/* Macros for xtensa_state numbers (for use in iclasses because the 150 state numbers are not available when the iclass table is generated). */ 151 152#define STATE_LCOUNT 0 153#define STATE_PC 1 154#define STATE_ICOUNT 2 155#define STATE_DDR 3 156#define STATE_INTERRUPT 4 157#define STATE_CCOUNT 5 158#define STATE_XTSYNC 6 159#define STATE_EPC1 7 160#define STATE_EPC2 8 161#define STATE_EPC3 9 162#define STATE_EPC4 10 163#define STATE_EXCSAVE1 11 164#define STATE_EXCSAVE2 12 165#define STATE_EXCSAVE3 13 166#define STATE_EXCSAVE4 14 167#define STATE_EPS2 15 168#define STATE_EPS3 16 169#define STATE_EPS4 17 170#define STATE_EXCCAUSE 18 171#define STATE_PSINTLEVEL 19 172#define STATE_PSUM 20 173#define STATE_PSWOE 21 174#define STATE_PSRING 22 175#define STATE_PSEXCM 23 176#define STATE_DEPC 24 177#define STATE_EXCVADDR 25 178#define STATE_WindowBase 26 179#define STATE_WindowStart 27 180#define STATE_PSCALLINC 28 181#define STATE_PSOWB 29 182#define STATE_LBEG 30 183#define STATE_LEND 31 184#define STATE_SAR 32 185#define STATE_LITBADDR 33 186#define STATE_LITBEN 34 187#define STATE_MISC0 35 188#define STATE_MISC1 36 189#define STATE_InOCDMode 37 190#define STATE_INTENABLE 38 191#define STATE_DBREAKA0 39 192#define STATE_DBREAKC0 40 193#define STATE_DBREAKA1 41 194#define STATE_DBREAKC1 42 195#define STATE_IBREAKA0 43 196#define STATE_IBREAKA1 44 197#define STATE_IBREAKENABLE 45 198#define STATE_ICOUNTLEVEL 46 199#define STATE_DEBUGCAUSE 47 200#define STATE_DBNUM 48 201#define STATE_CCOMPARE0 49 202#define STATE_CCOMPARE1 50 203#define STATE_CCOMPARE2 51 204#define STATE_ASID3 52 205#define STATE_ASID2 53 206#define STATE_ASID1 54 207#define STATE_INSTPGSZID4 55 208#define STATE_DATAPGSZID4 56 209#define STATE_PTBASE 57 210 211 212/* Field definitions. */ 213 214static unsigned 215Field_t_Slot_inst_get (const xtensa_insnbuf insn) 216{ 217 unsigned tie_t = 0; 218 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); 219 return tie_t; 220} 221 222static void 223Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 224{ 225 uint32 tie_t; 226 tie_t = (val << 28) >> 28; 227 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); 228} 229 230static unsigned 231Field_s_Slot_inst_get (const xtensa_insnbuf insn) 232{ 233 unsigned tie_t = 0; 234 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 235 return tie_t; 236} 237 238static void 239Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 240{ 241 uint32 tie_t; 242 tie_t = (val << 28) >> 28; 243 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 244} 245 246static unsigned 247Field_r_Slot_inst_get (const xtensa_insnbuf insn) 248{ 249 unsigned tie_t = 0; 250 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 251 return tie_t; 252} 253 254static void 255Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 256{ 257 uint32 tie_t; 258 tie_t = (val << 28) >> 28; 259 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 260} 261 262static unsigned 263Field_op2_Slot_inst_get (const xtensa_insnbuf insn) 264{ 265 unsigned tie_t = 0; 266 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 267 return tie_t; 268} 269 270static void 271Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 272{ 273 uint32 tie_t; 274 tie_t = (val << 28) >> 28; 275 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 276} 277 278static unsigned 279Field_op1_Slot_inst_get (const xtensa_insnbuf insn) 280{ 281 unsigned tie_t = 0; 282 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 283 return tie_t; 284} 285 286static void 287Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 288{ 289 uint32 tie_t; 290 tie_t = (val << 28) >> 28; 291 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 292} 293 294static unsigned 295Field_op0_Slot_inst_get (const xtensa_insnbuf insn) 296{ 297 unsigned tie_t = 0; 298 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); 299 return tie_t; 300} 301 302static void 303Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 304{ 305 uint32 tie_t; 306 tie_t = (val << 28) >> 28; 307 insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); 308} 309 310static unsigned 311Field_n_Slot_inst_get (const xtensa_insnbuf insn) 312{ 313 unsigned tie_t = 0; 314 tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); 315 return tie_t; 316} 317 318static void 319Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 320{ 321 uint32 tie_t; 322 tie_t = (val << 30) >> 30; 323 insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); 324} 325 326static unsigned 327Field_m_Slot_inst_get (const xtensa_insnbuf insn) 328{ 329 unsigned tie_t = 0; 330 tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); 331 return tie_t; 332} 333 334static void 335Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 336{ 337 uint32 tie_t; 338 tie_t = (val << 30) >> 30; 339 insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); 340} 341 342static unsigned 343Field_sr_Slot_inst_get (const xtensa_insnbuf insn) 344{ 345 unsigned tie_t = 0; 346 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 347 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 348 return tie_t; 349} 350 351static void 352Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 353{ 354 uint32 tie_t; 355 tie_t = (val << 28) >> 28; 356 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 357 tie_t = (val << 24) >> 28; 358 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 359} 360 361static unsigned 362Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) 363{ 364 unsigned tie_t = 0; 365 tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); 366 return tie_t; 367} 368 369static void 370Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 371{ 372 uint32 tie_t; 373 tie_t = (val << 29) >> 29; 374 insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); 375} 376 377static unsigned 378Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) 379{ 380 unsigned tie_t = 0; 381 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 382 return tie_t; 383} 384 385static void 386Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 387{ 388 uint32 tie_t; 389 tie_t = (val << 28) >> 28; 390 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 391} 392 393static unsigned 394Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) 395{ 396 unsigned tie_t = 0; 397 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 398 return tie_t; 399} 400 401static void 402Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 403{ 404 uint32 tie_t; 405 tie_t = (val << 28) >> 28; 406 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 407} 408 409static unsigned 410Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) 411{ 412 unsigned tie_t = 0; 413 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 414 return tie_t; 415} 416 417static void 418Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 419{ 420 uint32 tie_t; 421 tie_t = (val << 28) >> 28; 422 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 423} 424 425static unsigned 426Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) 427{ 428 unsigned tie_t = 0; 429 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 430 return tie_t; 431} 432 433static void 434Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 435{ 436 uint32 tie_t; 437 tie_t = (val << 28) >> 28; 438 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 439} 440 441static unsigned 442Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) 443{ 444 unsigned tie_t = 0; 445 tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); 446 return tie_t; 447} 448 449static void 450Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 451{ 452 uint32 tie_t; 453 tie_t = (val << 31) >> 31; 454 insn[0] = (insn[0] & ~0x400) | (tie_t << 10); 455} 456 457static unsigned 458Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) 459{ 460 unsigned tie_t = 0; 461 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); 462 return tie_t; 463} 464 465static void 466Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 467{ 468 uint32 tie_t; 469 tie_t = (val << 31) >> 31; 470 insn[0] = (insn[0] & ~0x800) | (tie_t << 11); 471} 472 473static unsigned 474Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) 475{ 476 unsigned tie_t = 0; 477 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 478 return tie_t; 479} 480 481static void 482Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 483{ 484 uint32 tie_t; 485 tie_t = (val << 28) >> 28; 486 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 487} 488 489static unsigned 490Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) 491{ 492 unsigned tie_t = 0; 493 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 494 return tie_t; 495} 496 497static void 498Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 499{ 500 uint32 tie_t; 501 tie_t = (val << 28) >> 28; 502 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 503} 504 505static unsigned 506Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) 507{ 508 unsigned tie_t = 0; 509 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); 510 return tie_t; 511} 512 513static void 514Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 515{ 516 uint32 tie_t; 517 tie_t = (val << 31) >> 31; 518 insn[0] = (insn[0] & ~0x100) | (tie_t << 8); 519} 520 521static unsigned 522Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) 523{ 524 unsigned tie_t = 0; 525 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); 526 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); 527 return tie_t; 528} 529 530static void 531Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 532{ 533 uint32 tie_t; 534 tie_t = (val << 28) >> 28; 535 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); 536 tie_t = (val << 27) >> 31; 537 insn[0] = (insn[0] & ~0x100) | (tie_t << 8); 538} 539 540static unsigned 541Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) 542{ 543 unsigned tie_t = 0; 544 tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); 545 return tie_t; 546} 547 548static void 549Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 550{ 551 uint32 tie_t; 552 tie_t = (val << 20) >> 20; 553 insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); 554} 555 556static unsigned 557Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) 558{ 559 unsigned tie_t = 0; 560 tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); 561 return tie_t; 562} 563 564static void 565Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 566{ 567 uint32 tie_t; 568 tie_t = (val << 24) >> 24; 569 insn[0] = (insn[0] & ~0xff) | (tie_t << 0); 570} 571 572static unsigned 573Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) 574{ 575 unsigned tie_t = 0; 576 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 577 return tie_t; 578} 579 580static void 581Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 582{ 583 uint32 tie_t; 584 tie_t = (val << 28) >> 28; 585 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 586} 587 588static unsigned 589Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) 590{ 591 unsigned tie_t = 0; 592 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 593 tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); 594 return tie_t; 595} 596 597static void 598Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 599{ 600 uint32 tie_t; 601 tie_t = (val << 24) >> 24; 602 insn[0] = (insn[0] & ~0xff) | (tie_t << 0); 603 tie_t = (val << 20) >> 28; 604 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 605} 606 607static unsigned 608Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) 609{ 610 unsigned tie_t = 0; 611 tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16); 612 return tie_t; 613} 614 615static void 616Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 617{ 618 uint32 tie_t; 619 tie_t = (val << 16) >> 16; 620 insn[0] = (insn[0] & ~0xffff) | (tie_t << 0); 621} 622 623static unsigned 624Field_offset_Slot_inst_get (const xtensa_insnbuf insn) 625{ 626 unsigned tie_t = 0; 627 tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); 628 return tie_t; 629} 630 631static void 632Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 633{ 634 uint32 tie_t; 635 tie_t = (val << 14) >> 14; 636 insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); 637} 638 639static unsigned 640Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) 641{ 642 unsigned tie_t = 0; 643 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 644 return tie_t; 645} 646 647static void 648Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 649{ 650 uint32 tie_t; 651 tie_t = (val << 28) >> 28; 652 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 653} 654 655static unsigned 656Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) 657{ 658 unsigned tie_t = 0; 659 tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); 660 return tie_t; 661} 662 663static void 664Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 665{ 666 uint32 tie_t; 667 tie_t = (val << 31) >> 31; 668 insn[0] = (insn[0] & ~0x1) | (tie_t << 0); 669} 670 671static unsigned 672Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) 673{ 674 unsigned tie_t = 0; 675 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); 676 return tie_t; 677} 678 679static void 680Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 681{ 682 uint32 tie_t; 683 tie_t = (val << 31) >> 31; 684 insn[0] = (insn[0] & ~0x10) | (tie_t << 4); 685} 686 687static unsigned 688Field_sae_Slot_inst_get (const xtensa_insnbuf insn) 689{ 690 unsigned tie_t = 0; 691 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); 692 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 693 return tie_t; 694} 695 696static void 697Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 698{ 699 uint32 tie_t; 700 tie_t = (val << 28) >> 28; 701 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 702 tie_t = (val << 27) >> 31; 703 insn[0] = (insn[0] & ~0x10) | (tie_t << 4); 704} 705 706static unsigned 707Field_sal_Slot_inst_get (const xtensa_insnbuf insn) 708{ 709 unsigned tie_t = 0; 710 tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); 711 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); 712 return tie_t; 713} 714 715static void 716Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 717{ 718 uint32 tie_t; 719 tie_t = (val << 28) >> 28; 720 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); 721 tie_t = (val << 27) >> 31; 722 insn[0] = (insn[0] & ~0x1) | (tie_t << 0); 723} 724 725static unsigned 726Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) 727{ 728 unsigned tie_t = 0; 729 tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); 730 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 731 return tie_t; 732} 733 734static void 735Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 736{ 737 uint32 tie_t; 738 tie_t = (val << 28) >> 28; 739 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 740 tie_t = (val << 27) >> 31; 741 insn[0] = (insn[0] & ~0x1) | (tie_t << 0); 742} 743 744static unsigned 745Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) 746{ 747 unsigned tie_t = 0; 748 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); 749 return tie_t; 750} 751 752static void 753Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 754{ 755 uint32 tie_t; 756 tie_t = (val << 31) >> 31; 757 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); 758} 759 760static unsigned 761Field_sas_Slot_inst_get (const xtensa_insnbuf insn) 762{ 763 unsigned tie_t = 0; 764 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); 765 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 766 return tie_t; 767} 768 769static void 770Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 771{ 772 uint32 tie_t; 773 tie_t = (val << 28) >> 28; 774 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 775 tie_t = (val << 27) >> 31; 776 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); 777} 778 779static unsigned 780Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) 781{ 782 unsigned tie_t = 0; 783 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 784 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 785 return tie_t; 786} 787 788static void 789Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 790{ 791 uint32 tie_t; 792 tie_t = (val << 28) >> 28; 793 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 794 tie_t = (val << 24) >> 28; 795 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 796} 797 798static unsigned 799Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) 800{ 801 unsigned tie_t = 0; 802 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 803 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 804 return tie_t; 805} 806 807static void 808Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 809{ 810 uint32 tie_t; 811 tie_t = (val << 28) >> 28; 812 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 813 tie_t = (val << 24) >> 28; 814 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 815} 816 817static unsigned 818Field_st_Slot_inst_get (const xtensa_insnbuf insn) 819{ 820 unsigned tie_t = 0; 821 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 822 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); 823 return tie_t; 824} 825 826static void 827Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 828{ 829 uint32 tie_t; 830 tie_t = (val << 28) >> 28; 831 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); 832 tie_t = (val << 24) >> 28; 833 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 834} 835 836static unsigned 837Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) 838{ 839 unsigned tie_t = 0; 840 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 841 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 842 return tie_t; 843} 844 845static void 846Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 847{ 848 uint32 tie_t; 849 tie_t = (val << 28) >> 28; 850 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 851 tie_t = (val << 24) >> 28; 852 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 853} 854 855static unsigned 856Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) 857{ 858 unsigned tie_t = 0; 859 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 860 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 861 return tie_t; 862} 863 864static void 865Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 866{ 867 uint32 tie_t; 868 tie_t = (val << 28) >> 28; 869 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 870 tie_t = (val << 24) >> 28; 871 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 872} 873 874static unsigned 875Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) 876{ 877 unsigned tie_t = 0; 878 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 879 return tie_t; 880} 881 882static void 883Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 884{ 885 uint32 tie_t; 886 tie_t = (val << 28) >> 28; 887 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 888} 889 890static unsigned 891Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) 892{ 893 unsigned tie_t = 0; 894 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 895 return tie_t; 896} 897 898static void 899Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 900{ 901 uint32 tie_t; 902 tie_t = (val << 28) >> 28; 903 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 904} 905 906static unsigned 907Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) 908{ 909 unsigned tie_t = 0; 910 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 911 return tie_t; 912} 913 914static void 915Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 916{ 917 uint32 tie_t; 918 tie_t = (val << 28) >> 28; 919 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 920} 921 922static unsigned 923Field_mn_Slot_inst_get (const xtensa_insnbuf insn) 924{ 925 unsigned tie_t = 0; 926 tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); 927 tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); 928 return tie_t; 929} 930 931static void 932Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 933{ 934 uint32 tie_t; 935 tie_t = (val << 30) >> 30; 936 insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); 937 tie_t = (val << 28) >> 30; 938 insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); 939} 940 941static unsigned 942Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) 943{ 944 unsigned tie_t = 0; 945 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); 946 return tie_t; 947} 948 949static void 950Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 951{ 952 uint32 tie_t; 953 tie_t = (val << 31) >> 31; 954 insn[0] = (insn[0] & ~0x800) | (tie_t << 11); 955} 956 957static unsigned 958Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) 959{ 960 unsigned tie_t = 0; 961 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 962 return tie_t; 963} 964 965static void 966Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 967{ 968 uint32 tie_t; 969 tie_t = (val << 28) >> 28; 970 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 971} 972 973static unsigned 974Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) 975{ 976 unsigned tie_t = 0; 977 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 978 return tie_t; 979} 980 981static void 982Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 983{ 984 uint32 tie_t; 985 tie_t = (val << 28) >> 28; 986 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 987} 988 989static unsigned 990Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) 991{ 992 unsigned tie_t = 0; 993 tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); 994 return tie_t; 995} 996 997static void 998Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 999{ 1000 uint32 tie_t; 1001 tie_t = (val << 30) >> 30; 1002 insn[0] = (insn[0] & ~0x300) | (tie_t << 8); 1003} 1004 1005static unsigned 1006Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) 1007{ 1008 unsigned tie_t = 0; 1009 tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); 1010 return tie_t; 1011} 1012 1013static void 1014Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1015{ 1016 uint32 tie_t; 1017 tie_t = (val << 30) >> 30; 1018 insn[0] = (insn[0] & ~0x300) | (tie_t << 8); 1019} 1020 1021static unsigned 1022Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) 1023{ 1024 unsigned tie_t = 0; 1025 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 1026 return tie_t; 1027} 1028 1029static void 1030Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1031{ 1032 uint32 tie_t; 1033 tie_t = (val << 28) >> 28; 1034 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 1035} 1036 1037static unsigned 1038Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) 1039{ 1040 unsigned tie_t = 0; 1041 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 1042 return tie_t; 1043} 1044 1045static void 1046Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1047{ 1048 uint32 tie_t; 1049 tie_t = (val << 28) >> 28; 1050 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 1051} 1052 1053static unsigned 1054Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) 1055{ 1056 unsigned tie_t = 0; 1057 tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); 1058 return tie_t; 1059} 1060 1061static void 1062Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1063{ 1064 uint32 tie_t; 1065 tie_t = (val << 29) >> 29; 1066 insn[0] = (insn[0] & ~0x700) | (tie_t << 8); 1067} 1068 1069static unsigned 1070Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) 1071{ 1072 unsigned tie_t = 0; 1073 tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); 1074 return tie_t; 1075} 1076 1077static void 1078Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1079{ 1080 uint32 tie_t; 1081 tie_t = (val << 29) >> 29; 1082 insn[0] = (insn[0] & ~0x700) | (tie_t << 8); 1083} 1084 1085static unsigned 1086Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) 1087{ 1088 unsigned tie_t = 0; 1089 tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); 1090 return tie_t; 1091} 1092 1093static void 1094Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1095{ 1096 uint32 tie_t; 1097 tie_t = (val << 31) >> 31; 1098 insn[0] = (insn[0] & ~0x400) | (tie_t << 10); 1099} 1100 1101static unsigned 1102Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) 1103{ 1104 unsigned tie_t = 0; 1105 tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); 1106 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 1107 return tie_t; 1108} 1109 1110static void 1111Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1112{ 1113 uint32 tie_t; 1114 tie_t = (val << 28) >> 28; 1115 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 1116 tie_t = (val << 26) >> 30; 1117 insn[0] = (insn[0] & ~0x300) | (tie_t << 8); 1118} 1119 1120static unsigned 1121Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) 1122{ 1123 unsigned tie_t = 0; 1124 tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); 1125 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 1126 return tie_t; 1127} 1128 1129static void 1130Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1131{ 1132 uint32 tie_t; 1133 tie_t = (val << 28) >> 28; 1134 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 1135 tie_t = (val << 26) >> 30; 1136 insn[0] = (insn[0] & ~0x300) | (tie_t << 8); 1137} 1138 1139static unsigned 1140Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) 1141{ 1142 unsigned tie_t = 0; 1143 tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); 1144 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 1145 return tie_t; 1146} 1147 1148static void 1149Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1150{ 1151 uint32 tie_t; 1152 tie_t = (val << 28) >> 28; 1153 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 1154 tie_t = (val << 25) >> 29; 1155 insn[0] = (insn[0] & ~0x700) | (tie_t << 8); 1156} 1157 1158static unsigned 1159Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) 1160{ 1161 unsigned tie_t = 0; 1162 tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); 1163 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 1164 return tie_t; 1165} 1166 1167static void 1168Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1169{ 1170 uint32 tie_t; 1171 tie_t = (val << 28) >> 28; 1172 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 1173 tie_t = (val << 25) >> 29; 1174 insn[0] = (insn[0] & ~0x700) | (tie_t << 8); 1175} 1176 1177static void 1178Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, 1179 uint32 val ATTRIBUTE_UNUSED) 1180{ 1181 /* Do nothing. */ 1182} 1183 1184static unsigned 1185Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1186{ 1187 return 0; 1188} 1189 1190static unsigned 1191Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1192{ 1193 return 4; 1194} 1195 1196static unsigned 1197Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1198{ 1199 return 8; 1200} 1201 1202static unsigned 1203Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1204{ 1205 return 12; 1206} 1207 1208 1209/* Functional units. */ 1210 1211static xtensa_funcUnit_internal funcUnits[] = { 1212 1213}; 1214 1215 1216/* Register files. */ 1217 1218static xtensa_regfile_internal regfiles[] = { 1219 { "AR", "a", 0, 32, 64 } 1220}; 1221 1222 1223/* Interfaces. */ 1224 1225static xtensa_interface_internal interfaces[] = { 1226 1227}; 1228 1229 1230/* Constant tables. */ 1231 1232/* constant table ai4c */ 1233static const unsigned CONST_TBL_ai4c_0[] = { 1234 0xffffffff, 1235 0x1, 1236 0x2, 1237 0x3, 1238 0x4, 1239 0x5, 1240 0x6, 1241 0x7, 1242 0x8, 1243 0x9, 1244 0xa, 1245 0xb, 1246 0xc, 1247 0xd, 1248 0xe, 1249 0xf, 1250 0 1251}; 1252 1253/* constant table b4c */ 1254static const unsigned CONST_TBL_b4c_0[] = { 1255 0xffffffff, 1256 0x1, 1257 0x2, 1258 0x3, 1259 0x4, 1260 0x5, 1261 0x6, 1262 0x7, 1263 0x8, 1264 0xa, 1265 0xc, 1266 0x10, 1267 0x20, 1268 0x40, 1269 0x80, 1270 0x100, 1271 0 1272}; 1273 1274/* constant table b4cu */ 1275static const unsigned CONST_TBL_b4cu_0[] = { 1276 0x8000, 1277 0x10000, 1278 0x2, 1279 0x3, 1280 0x4, 1281 0x5, 1282 0x6, 1283 0x7, 1284 0x8, 1285 0xa, 1286 0xc, 1287 0x10, 1288 0x20, 1289 0x40, 1290 0x80, 1291 0x100, 1292 0 1293}; 1294 1295 1296/* Instruction operands. */ 1297 1298static int 1299Operand_soffsetx4_decode (uint32 *valp) 1300{ 1301 unsigned soffsetx4_0, offset_0; 1302 offset_0 = *valp & 0x3ffff; 1303 soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2); 1304 *valp = soffsetx4_0; 1305 return 0; 1306} 1307 1308static int 1309Operand_soffsetx4_encode (uint32 *valp) 1310{ 1311 unsigned offset_0, soffsetx4_0; 1312 soffsetx4_0 = *valp; 1313 offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff; 1314 *valp = offset_0; 1315 return 0; 1316} 1317 1318static int 1319Operand_soffsetx4_ator (uint32 *valp, uint32 pc) 1320{ 1321 *valp -= (pc & ~0x3); 1322 return 0; 1323} 1324 1325static int 1326Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) 1327{ 1328 *valp += (pc & ~0x3); 1329 return 0; 1330} 1331 1332static int 1333Operand_uimm12x8_decode (uint32 *valp) 1334{ 1335 unsigned uimm12x8_0, imm12_0; 1336 imm12_0 = *valp & 0xfff; 1337 uimm12x8_0 = imm12_0 << 3; 1338 *valp = uimm12x8_0; 1339 return 0; 1340} 1341 1342static int 1343Operand_uimm12x8_encode (uint32 *valp) 1344{ 1345 unsigned imm12_0, uimm12x8_0; 1346 uimm12x8_0 = *valp; 1347 imm12_0 = ((uimm12x8_0 >> 3) & 0xfff); 1348 *valp = imm12_0; 1349 return 0; 1350} 1351 1352static int 1353Operand_simm4_decode (uint32 *valp) 1354{ 1355 unsigned simm4_0, mn_0; 1356 mn_0 = *valp & 0xf; 1357 simm4_0 = ((int) mn_0 << 28) >> 28; 1358 *valp = simm4_0; 1359 return 0; 1360} 1361 1362static int 1363Operand_simm4_encode (uint32 *valp) 1364{ 1365 unsigned mn_0, simm4_0; 1366 simm4_0 = *valp; 1367 mn_0 = (simm4_0 & 0xf); 1368 *valp = mn_0; 1369 return 0; 1370} 1371 1372static int 1373Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED) 1374{ 1375 return 0; 1376} 1377 1378static int 1379Operand_arr_encode (uint32 *valp) 1380{ 1381 return (*valp & ~0xf) != 0; 1382} 1383 1384static int 1385Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED) 1386{ 1387 return 0; 1388} 1389 1390static int 1391Operand_ars_encode (uint32 *valp) 1392{ 1393 return (*valp & ~0xf) != 0; 1394} 1395 1396static int 1397Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED) 1398{ 1399 return 0; 1400} 1401 1402static int 1403Operand_art_encode (uint32 *valp) 1404{ 1405 return (*valp & ~0xf) != 0; 1406} 1407 1408static int 1409Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED) 1410{ 1411 return 0; 1412} 1413 1414static int 1415Operand_ar0_encode (uint32 *valp) 1416{ 1417 return (*valp & ~0x3f) != 0; 1418} 1419 1420static int 1421Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED) 1422{ 1423 return 0; 1424} 1425 1426static int 1427Operand_ar4_encode (uint32 *valp) 1428{ 1429 return (*valp & ~0x3f) != 0; 1430} 1431 1432static int 1433Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED) 1434{ 1435 return 0; 1436} 1437 1438static int 1439Operand_ar8_encode (uint32 *valp) 1440{ 1441 return (*valp & ~0x3f) != 0; 1442} 1443 1444static int 1445Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED) 1446{ 1447 return 0; 1448} 1449 1450static int 1451Operand_ar12_encode (uint32 *valp) 1452{ 1453 return (*valp & ~0x3f) != 0; 1454} 1455 1456static int 1457Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) 1458{ 1459 return 0; 1460} 1461 1462static int 1463Operand_ars_entry_encode (uint32 *valp) 1464{ 1465 return (*valp & ~0x3f) != 0; 1466} 1467 1468static int 1469Operand_immrx4_decode (uint32 *valp) 1470{ 1471 unsigned immrx4_0, r_0; 1472 r_0 = *valp & 0xf; 1473 immrx4_0 = ((((0xfffffff)) << 4) | r_0) << 2; 1474 *valp = immrx4_0; 1475 return 0; 1476} 1477 1478static int 1479Operand_immrx4_encode (uint32 *valp) 1480{ 1481 unsigned r_0, immrx4_0; 1482 immrx4_0 = *valp; 1483 r_0 = ((immrx4_0 >> 2) & 0xf); 1484 *valp = r_0; 1485 return 0; 1486} 1487 1488static int 1489Operand_lsi4x4_decode (uint32 *valp) 1490{ 1491 unsigned lsi4x4_0, r_0; 1492 r_0 = *valp & 0xf; 1493 lsi4x4_0 = r_0 << 2; 1494 *valp = lsi4x4_0; 1495 return 0; 1496} 1497 1498static int 1499Operand_lsi4x4_encode (uint32 *valp) 1500{ 1501 unsigned r_0, lsi4x4_0; 1502 lsi4x4_0 = *valp; 1503 r_0 = ((lsi4x4_0 >> 2) & 0xf); 1504 *valp = r_0; 1505 return 0; 1506} 1507 1508static int 1509Operand_simm7_decode (uint32 *valp) 1510{ 1511 unsigned simm7_0, imm7_0; 1512 imm7_0 = *valp & 0x7f; 1513 simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0; 1514 *valp = simm7_0; 1515 return 0; 1516} 1517 1518static int 1519Operand_simm7_encode (uint32 *valp) 1520{ 1521 unsigned imm7_0, simm7_0; 1522 simm7_0 = *valp; 1523 imm7_0 = (simm7_0 & 0x7f); 1524 *valp = imm7_0; 1525 return 0; 1526} 1527 1528static int 1529Operand_uimm6_decode (uint32 *valp) 1530{ 1531 unsigned uimm6_0, imm6_0; 1532 imm6_0 = *valp & 0x3f; 1533 uimm6_0 = 0x4 + ((((0)) << 6) | imm6_0); 1534 *valp = uimm6_0; 1535 return 0; 1536} 1537 1538static int 1539Operand_uimm6_encode (uint32 *valp) 1540{ 1541 unsigned imm6_0, uimm6_0; 1542 uimm6_0 = *valp; 1543 imm6_0 = (uimm6_0 - 0x4) & 0x3f; 1544 *valp = imm6_0; 1545 return 0; 1546} 1547 1548static int 1549Operand_uimm6_ator (uint32 *valp, uint32 pc) 1550{ 1551 *valp -= pc; 1552 return 0; 1553} 1554 1555static int 1556Operand_uimm6_rtoa (uint32 *valp, uint32 pc) 1557{ 1558 *valp += pc; 1559 return 0; 1560} 1561 1562static int 1563Operand_ai4const_decode (uint32 *valp) 1564{ 1565 unsigned ai4const_0, t_0; 1566 t_0 = *valp & 0xf; 1567 ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf]; 1568 *valp = ai4const_0; 1569 return 0; 1570} 1571 1572static int 1573Operand_ai4const_encode (uint32 *valp) 1574{ 1575 unsigned t_0, ai4const_0; 1576 ai4const_0 = *valp; 1577 switch (ai4const_0) 1578 { 1579 case 0xffffffff: t_0 = 0; break; 1580 case 0x1: t_0 = 0x1; break; 1581 case 0x2: t_0 = 0x2; break; 1582 case 0x3: t_0 = 0x3; break; 1583 case 0x4: t_0 = 0x4; break; 1584 case 0x5: t_0 = 0x5; break; 1585 case 0x6: t_0 = 0x6; break; 1586 case 0x7: t_0 = 0x7; break; 1587 case 0x8: t_0 = 0x8; break; 1588 case 0x9: t_0 = 0x9; break; 1589 case 0xa: t_0 = 0xa; break; 1590 case 0xb: t_0 = 0xb; break; 1591 case 0xc: t_0 = 0xc; break; 1592 case 0xd: t_0 = 0xd; break; 1593 case 0xe: t_0 = 0xe; break; 1594 default: t_0 = 0xf; break; 1595 } 1596 *valp = t_0; 1597 return 0; 1598} 1599 1600static int 1601Operand_b4const_decode (uint32 *valp) 1602{ 1603 unsigned b4const_0, r_0; 1604 r_0 = *valp & 0xf; 1605 b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf]; 1606 *valp = b4const_0; 1607 return 0; 1608} 1609 1610static int 1611Operand_b4const_encode (uint32 *valp) 1612{ 1613 unsigned r_0, b4const_0; 1614 b4const_0 = *valp; 1615 switch (b4const_0) 1616 { 1617 case 0xffffffff: r_0 = 0; break; 1618 case 0x1: r_0 = 0x1; break; 1619 case 0x2: r_0 = 0x2; break; 1620 case 0x3: r_0 = 0x3; break; 1621 case 0x4: r_0 = 0x4; break; 1622 case 0x5: r_0 = 0x5; break; 1623 case 0x6: r_0 = 0x6; break; 1624 case 0x7: r_0 = 0x7; break; 1625 case 0x8: r_0 = 0x8; break; 1626 case 0xa: r_0 = 0x9; break; 1627 case 0xc: r_0 = 0xa; break; 1628 case 0x10: r_0 = 0xb; break; 1629 case 0x20: r_0 = 0xc; break; 1630 case 0x40: r_0 = 0xd; break; 1631 case 0x80: r_0 = 0xe; break; 1632 default: r_0 = 0xf; break; 1633 } 1634 *valp = r_0; 1635 return 0; 1636} 1637 1638static int 1639Operand_b4constu_decode (uint32 *valp) 1640{ 1641 unsigned b4constu_0, r_0; 1642 r_0 = *valp & 0xf; 1643 b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf]; 1644 *valp = b4constu_0; 1645 return 0; 1646} 1647 1648static int 1649Operand_b4constu_encode (uint32 *valp) 1650{ 1651 unsigned r_0, b4constu_0; 1652 b4constu_0 = *valp; 1653 switch (b4constu_0) 1654 { 1655 case 0x8000: r_0 = 0; break; 1656 case 0x10000: r_0 = 0x1; break; 1657 case 0x2: r_0 = 0x2; break; 1658 case 0x3: r_0 = 0x3; break; 1659 case 0x4: r_0 = 0x4; break; 1660 case 0x5: r_0 = 0x5; break; 1661 case 0x6: r_0 = 0x6; break; 1662 case 0x7: r_0 = 0x7; break; 1663 case 0x8: r_0 = 0x8; break; 1664 case 0xa: r_0 = 0x9; break; 1665 case 0xc: r_0 = 0xa; break; 1666 case 0x10: r_0 = 0xb; break; 1667 case 0x20: r_0 = 0xc; break; 1668 case 0x40: r_0 = 0xd; break; 1669 case 0x80: r_0 = 0xe; break; 1670 default: r_0 = 0xf; break; 1671 } 1672 *valp = r_0; 1673 return 0; 1674} 1675 1676static int 1677Operand_uimm8_decode (uint32 *valp) 1678{ 1679 unsigned uimm8_0, imm8_0; 1680 imm8_0 = *valp & 0xff; 1681 uimm8_0 = imm8_0; 1682 *valp = uimm8_0; 1683 return 0; 1684} 1685 1686static int 1687Operand_uimm8_encode (uint32 *valp) 1688{ 1689 unsigned imm8_0, uimm8_0; 1690 uimm8_0 = *valp; 1691 imm8_0 = (uimm8_0 & 0xff); 1692 *valp = imm8_0; 1693 return 0; 1694} 1695 1696static int 1697Operand_uimm8x2_decode (uint32 *valp) 1698{ 1699 unsigned uimm8x2_0, imm8_0; 1700 imm8_0 = *valp & 0xff; 1701 uimm8x2_0 = imm8_0 << 1; 1702 *valp = uimm8x2_0; 1703 return 0; 1704} 1705 1706static int 1707Operand_uimm8x2_encode (uint32 *valp) 1708{ 1709 unsigned imm8_0, uimm8x2_0; 1710 uimm8x2_0 = *valp; 1711 imm8_0 = ((uimm8x2_0 >> 1) & 0xff); 1712 *valp = imm8_0; 1713 return 0; 1714} 1715 1716static int 1717Operand_uimm8x4_decode (uint32 *valp) 1718{ 1719 unsigned uimm8x4_0, imm8_0; 1720 imm8_0 = *valp & 0xff; 1721 uimm8x4_0 = imm8_0 << 2; 1722 *valp = uimm8x4_0; 1723 return 0; 1724} 1725 1726static int 1727Operand_uimm8x4_encode (uint32 *valp) 1728{ 1729 unsigned imm8_0, uimm8x4_0; 1730 uimm8x4_0 = *valp; 1731 imm8_0 = ((uimm8x4_0 >> 2) & 0xff); 1732 *valp = imm8_0; 1733 return 0; 1734} 1735 1736static int 1737Operand_uimm4x16_decode (uint32 *valp) 1738{ 1739 unsigned uimm4x16_0, op2_0; 1740 op2_0 = *valp & 0xf; 1741 uimm4x16_0 = op2_0 << 4; 1742 *valp = uimm4x16_0; 1743 return 0; 1744} 1745 1746static int 1747Operand_uimm4x16_encode (uint32 *valp) 1748{ 1749 unsigned op2_0, uimm4x16_0; 1750 uimm4x16_0 = *valp; 1751 op2_0 = ((uimm4x16_0 >> 4) & 0xf); 1752 *valp = op2_0; 1753 return 0; 1754} 1755 1756static int 1757Operand_simm8_decode (uint32 *valp) 1758{ 1759 unsigned simm8_0, imm8_0; 1760 imm8_0 = *valp & 0xff; 1761 simm8_0 = ((int) imm8_0 << 24) >> 24; 1762 *valp = simm8_0; 1763 return 0; 1764} 1765 1766static int 1767Operand_simm8_encode (uint32 *valp) 1768{ 1769 unsigned imm8_0, simm8_0; 1770 simm8_0 = *valp; 1771 imm8_0 = (simm8_0 & 0xff); 1772 *valp = imm8_0; 1773 return 0; 1774} 1775 1776static int 1777Operand_simm8x256_decode (uint32 *valp) 1778{ 1779 unsigned simm8x256_0, imm8_0; 1780 imm8_0 = *valp & 0xff; 1781 simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8; 1782 *valp = simm8x256_0; 1783 return 0; 1784} 1785 1786static int 1787Operand_simm8x256_encode (uint32 *valp) 1788{ 1789 unsigned imm8_0, simm8x256_0; 1790 simm8x256_0 = *valp; 1791 imm8_0 = ((simm8x256_0 >> 8) & 0xff); 1792 *valp = imm8_0; 1793 return 0; 1794} 1795 1796static int 1797Operand_simm12b_decode (uint32 *valp) 1798{ 1799 unsigned simm12b_0, imm12b_0; 1800 imm12b_0 = *valp & 0xfff; 1801 simm12b_0 = ((int) imm12b_0 << 20) >> 20; 1802 *valp = simm12b_0; 1803 return 0; 1804} 1805 1806static int 1807Operand_simm12b_encode (uint32 *valp) 1808{ 1809 unsigned imm12b_0, simm12b_0; 1810 simm12b_0 = *valp; 1811 imm12b_0 = (simm12b_0 & 0xfff); 1812 *valp = imm12b_0; 1813 return 0; 1814} 1815 1816static int 1817Operand_msalp32_decode (uint32 *valp) 1818{ 1819 unsigned msalp32_0, sal_0; 1820 sal_0 = *valp & 0x1f; 1821 msalp32_0 = 0x20 - sal_0; 1822 *valp = msalp32_0; 1823 return 0; 1824} 1825 1826static int 1827Operand_msalp32_encode (uint32 *valp) 1828{ 1829 unsigned sal_0, msalp32_0; 1830 msalp32_0 = *valp; 1831 sal_0 = (0x20 - msalp32_0) & 0x1f; 1832 *valp = sal_0; 1833 return 0; 1834} 1835 1836static int 1837Operand_op2p1_decode (uint32 *valp) 1838{ 1839 unsigned op2p1_0, op2_0; 1840 op2_0 = *valp & 0xf; 1841 op2p1_0 = op2_0 + 0x1; 1842 *valp = op2p1_0; 1843 return 0; 1844} 1845 1846static int 1847Operand_op2p1_encode (uint32 *valp) 1848{ 1849 unsigned op2_0, op2p1_0; 1850 op2p1_0 = *valp; 1851 op2_0 = (op2p1_0 - 0x1) & 0xf; 1852 *valp = op2_0; 1853 return 0; 1854} 1855 1856static int 1857Operand_label8_decode (uint32 *valp) 1858{ 1859 unsigned label8_0, imm8_0; 1860 imm8_0 = *valp & 0xff; 1861 label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24); 1862 *valp = label8_0; 1863 return 0; 1864} 1865 1866static int 1867Operand_label8_encode (uint32 *valp) 1868{ 1869 unsigned imm8_0, label8_0; 1870 label8_0 = *valp; 1871 imm8_0 = (label8_0 - 0x4) & 0xff; 1872 *valp = imm8_0; 1873 return 0; 1874} 1875 1876static int 1877Operand_label8_ator (uint32 *valp, uint32 pc) 1878{ 1879 *valp -= pc; 1880 return 0; 1881} 1882 1883static int 1884Operand_label8_rtoa (uint32 *valp, uint32 pc) 1885{ 1886 *valp += pc; 1887 return 0; 1888} 1889 1890static int 1891Operand_ulabel8_decode (uint32 *valp) 1892{ 1893 unsigned ulabel8_0, imm8_0; 1894 imm8_0 = *valp & 0xff; 1895 ulabel8_0 = 0x4 + ((((0)) << 8) | imm8_0); 1896 *valp = ulabel8_0; 1897 return 0; 1898} 1899 1900static int 1901Operand_ulabel8_encode (uint32 *valp) 1902{ 1903 unsigned imm8_0, ulabel8_0; 1904 ulabel8_0 = *valp; 1905 imm8_0 = (ulabel8_0 - 0x4) & 0xff; 1906 *valp = imm8_0; 1907 return 0; 1908} 1909 1910static int 1911Operand_ulabel8_ator (uint32 *valp, uint32 pc) 1912{ 1913 *valp -= pc; 1914 return 0; 1915} 1916 1917static int 1918Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) 1919{ 1920 *valp += pc; 1921 return 0; 1922} 1923 1924static int 1925Operand_label12_decode (uint32 *valp) 1926{ 1927 unsigned label12_0, imm12_0; 1928 imm12_0 = *valp & 0xfff; 1929 label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20); 1930 *valp = label12_0; 1931 return 0; 1932} 1933 1934static int 1935Operand_label12_encode (uint32 *valp) 1936{ 1937 unsigned imm12_0, label12_0; 1938 label12_0 = *valp; 1939 imm12_0 = (label12_0 - 0x4) & 0xfff; 1940 *valp = imm12_0; 1941 return 0; 1942} 1943 1944static int 1945Operand_label12_ator (uint32 *valp, uint32 pc) 1946{ 1947 *valp -= pc; 1948 return 0; 1949} 1950 1951static int 1952Operand_label12_rtoa (uint32 *valp, uint32 pc) 1953{ 1954 *valp += pc; 1955 return 0; 1956} 1957 1958static int 1959Operand_soffset_decode (uint32 *valp) 1960{ 1961 unsigned soffset_0, offset_0; 1962 offset_0 = *valp & 0x3ffff; 1963 soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14); 1964 *valp = soffset_0; 1965 return 0; 1966} 1967 1968static int 1969Operand_soffset_encode (uint32 *valp) 1970{ 1971 unsigned offset_0, soffset_0; 1972 soffset_0 = *valp; 1973 offset_0 = (soffset_0 - 0x4) & 0x3ffff; 1974 *valp = offset_0; 1975 return 0; 1976} 1977 1978static int 1979Operand_soffset_ator (uint32 *valp, uint32 pc) 1980{ 1981 *valp -= pc; 1982 return 0; 1983} 1984 1985static int 1986Operand_soffset_rtoa (uint32 *valp, uint32 pc) 1987{ 1988 *valp += pc; 1989 return 0; 1990} 1991 1992static int 1993Operand_uimm16x4_decode (uint32 *valp) 1994{ 1995 unsigned uimm16x4_0, imm16_0; 1996 imm16_0 = *valp & 0xffff; 1997 uimm16x4_0 = ((((0xffff)) << 16) | imm16_0) << 2; 1998 *valp = uimm16x4_0; 1999 return 0; 2000} 2001 2002static int 2003Operand_uimm16x4_encode (uint32 *valp) 2004{ 2005 unsigned imm16_0, uimm16x4_0; 2006 uimm16x4_0 = *valp; 2007 imm16_0 = (uimm16x4_0 >> 2) & 0xffff; 2008 *valp = imm16_0; 2009 return 0; 2010} 2011 2012static int 2013Operand_uimm16x4_ator (uint32 *valp, uint32 pc) 2014{ 2015 *valp -= ((pc + 3) & ~0x3); 2016 return 0; 2017} 2018 2019static int 2020Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) 2021{ 2022 *valp += ((pc + 3) & ~0x3); 2023 return 0; 2024} 2025 2026static int 2027Operand_immt_decode (uint32 *valp) 2028{ 2029 unsigned immt_0, t_0; 2030 t_0 = *valp & 0xf; 2031 immt_0 = t_0; 2032 *valp = immt_0; 2033 return 0; 2034} 2035 2036static int 2037Operand_immt_encode (uint32 *valp) 2038{ 2039 unsigned t_0, immt_0; 2040 immt_0 = *valp; 2041 t_0 = immt_0 & 0xf; 2042 *valp = t_0; 2043 return 0; 2044} 2045 2046static int 2047Operand_imms_decode (uint32 *valp) 2048{ 2049 unsigned imms_0, s_0; 2050 s_0 = *valp & 0xf; 2051 imms_0 = s_0; 2052 *valp = imms_0; 2053 return 0; 2054} 2055 2056static int 2057Operand_imms_encode (uint32 *valp) 2058{ 2059 unsigned s_0, imms_0; 2060 imms_0 = *valp; 2061 s_0 = imms_0 & 0xf; 2062 *valp = s_0; 2063 return 0; 2064} 2065 2066static xtensa_operand_internal operands[] = { 2067 { "soffsetx4", 10, -1, 0, 2068 XTENSA_OPERAND_IS_PCRELATIVE, 2069 Operand_soffsetx4_encode, Operand_soffsetx4_decode, 2070 Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, 2071 { "uimm12x8", 3, -1, 0, 2072 0, 2073 Operand_uimm12x8_encode, Operand_uimm12x8_decode, 2074 0, 0 }, 2075 { "simm4", 26, -1, 0, 2076 0, 2077 Operand_simm4_encode, Operand_simm4_decode, 2078 0, 0 }, 2079 { "arr", 14, 0, 1, 2080 XTENSA_OPERAND_IS_REGISTER, 2081 Operand_arr_encode, Operand_arr_decode, 2082 0, 0 }, 2083 { "ars", 5, 0, 1, 2084 XTENSA_OPERAND_IS_REGISTER, 2085 Operand_ars_encode, Operand_ars_decode, 2086 0, 0 }, 2087 { "*ars_invisible", 5, 0, 1, 2088 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2089 Operand_ars_encode, Operand_ars_decode, 2090 0, 0 }, 2091 { "art", 0, 0, 1, 2092 XTENSA_OPERAND_IS_REGISTER, 2093 Operand_art_encode, Operand_art_decode, 2094 0, 0 }, 2095 { "ar0", 35, 0, 1, 2096 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2097 Operand_ar0_encode, Operand_ar0_decode, 2098 0, 0 }, 2099 { "ar4", 36, 0, 1, 2100 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2101 Operand_ar4_encode, Operand_ar4_decode, 2102 0, 0 }, 2103 { "ar8", 37, 0, 1, 2104 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2105 Operand_ar8_encode, Operand_ar8_decode, 2106 0, 0 }, 2107 { "ar12", 38, 0, 1, 2108 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2109 Operand_ar12_encode, Operand_ar12_decode, 2110 0, 0 }, 2111 { "ars_entry", 5, 0, 1, 2112 XTENSA_OPERAND_IS_REGISTER, 2113 Operand_ars_entry_encode, Operand_ars_entry_decode, 2114 0, 0 }, 2115 { "immrx4", 14, -1, 0, 2116 0, 2117 Operand_immrx4_encode, Operand_immrx4_decode, 2118 0, 0 }, 2119 { "lsi4x4", 14, -1, 0, 2120 0, 2121 Operand_lsi4x4_encode, Operand_lsi4x4_decode, 2122 0, 0 }, 2123 { "simm7", 34, -1, 0, 2124 0, 2125 Operand_simm7_encode, Operand_simm7_decode, 2126 0, 0 }, 2127 { "uimm6", 33, -1, 0, 2128 XTENSA_OPERAND_IS_PCRELATIVE, 2129 Operand_uimm6_encode, Operand_uimm6_decode, 2130 Operand_uimm6_ator, Operand_uimm6_rtoa }, 2131 { "ai4const", 0, -1, 0, 2132 0, 2133 Operand_ai4const_encode, Operand_ai4const_decode, 2134 0, 0 }, 2135 { "b4const", 14, -1, 0, 2136 0, 2137 Operand_b4const_encode, Operand_b4const_decode, 2138 0, 0 }, 2139 { "b4constu", 14, -1, 0, 2140 0, 2141 Operand_b4constu_encode, Operand_b4constu_decode, 2142 0, 0 }, 2143 { "uimm8", 4, -1, 0, 2144 0, 2145 Operand_uimm8_encode, Operand_uimm8_decode, 2146 0, 0 }, 2147 { "uimm8x2", 4, -1, 0, 2148 0, 2149 Operand_uimm8x2_encode, Operand_uimm8x2_decode, 2150 0, 0 }, 2151 { "uimm8x4", 4, -1, 0, 2152 0, 2153 Operand_uimm8x4_encode, Operand_uimm8x4_decode, 2154 0, 0 }, 2155 { "uimm4x16", 13, -1, 0, 2156 0, 2157 Operand_uimm4x16_encode, Operand_uimm4x16_decode, 2158 0, 0 }, 2159 { "simm8", 4, -1, 0, 2160 0, 2161 Operand_simm8_encode, Operand_simm8_decode, 2162 0, 0 }, 2163 { "simm8x256", 4, -1, 0, 2164 0, 2165 Operand_simm8x256_encode, Operand_simm8x256_decode, 2166 0, 0 }, 2167 { "simm12b", 6, -1, 0, 2168 0, 2169 Operand_simm12b_encode, Operand_simm12b_decode, 2170 0, 0 }, 2171 { "msalp32", 18, -1, 0, 2172 0, 2173 Operand_msalp32_encode, Operand_msalp32_decode, 2174 0, 0 }, 2175 { "op2p1", 13, -1, 0, 2176 0, 2177 Operand_op2p1_encode, Operand_op2p1_decode, 2178 0, 0 }, 2179 { "label8", 4, -1, 0, 2180 XTENSA_OPERAND_IS_PCRELATIVE, 2181 Operand_label8_encode, Operand_label8_decode, 2182 Operand_label8_ator, Operand_label8_rtoa }, 2183 { "ulabel8", 4, -1, 0, 2184 XTENSA_OPERAND_IS_PCRELATIVE, 2185 Operand_ulabel8_encode, Operand_ulabel8_decode, 2186 Operand_ulabel8_ator, Operand_ulabel8_rtoa }, 2187 { "label12", 3, -1, 0, 2188 XTENSA_OPERAND_IS_PCRELATIVE, 2189 Operand_label12_encode, Operand_label12_decode, 2190 Operand_label12_ator, Operand_label12_rtoa }, 2191 { "soffset", 10, -1, 0, 2192 XTENSA_OPERAND_IS_PCRELATIVE, 2193 Operand_soffset_encode, Operand_soffset_decode, 2194 Operand_soffset_ator, Operand_soffset_rtoa }, 2195 { "uimm16x4", 7, -1, 0, 2196 XTENSA_OPERAND_IS_PCRELATIVE, 2197 Operand_uimm16x4_encode, Operand_uimm16x4_decode, 2198 Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, 2199 { "immt", 0, -1, 0, 2200 0, 2201 Operand_immt_encode, Operand_immt_decode, 2202 0, 0 }, 2203 { "imms", 5, -1, 0, 2204 0, 2205 Operand_imms_encode, Operand_imms_decode, 2206 0, 0 }, 2207 { "t", 0, -1, 0, 0, 0, 0, 0, 0 }, 2208 { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 }, 2209 { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 }, 2210 { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 }, 2211 { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 }, 2212 { "s", 5, -1, 0, 0, 0, 0, 0, 0 }, 2213 { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 }, 2214 { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 }, 2215 { "m", 8, -1, 0, 0, 0, 0, 0, 0 }, 2216 { "n", 9, -1, 0, 0, 0, 0, 0, 0 }, 2217 { "offset", 10, -1, 0, 0, 0, 0, 0, 0 }, 2218 { "op0", 11, -1, 0, 0, 0, 0, 0, 0 }, 2219 { "op1", 12, -1, 0, 0, 0, 0, 0, 0 }, 2220 { "op2", 13, -1, 0, 0, 0, 0, 0, 0 }, 2221 { "r", 14, -1, 0, 0, 0, 0, 0, 0 }, 2222 { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 }, 2223 { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 }, 2224 { "sae", 17, -1, 0, 0, 0, 0, 0, 0 }, 2225 { "sal", 18, -1, 0, 0, 0, 0, 0, 0 }, 2226 { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 }, 2227 { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 }, 2228 { "sas", 21, -1, 0, 0, 0, 0, 0, 0 }, 2229 { "sr", 22, -1, 0, 0, 0, 0, 0, 0 }, 2230 { "st", 23, -1, 0, 0, 0, 0, 0, 0 }, 2231 { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 }, 2232 { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 }, 2233 { "mn", 26, -1, 0, 0, 0, 0, 0, 0 }, 2234 { "i", 27, -1, 0, 0, 0, 0, 0, 0 }, 2235 { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 }, 2236 { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 }, 2237 { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 }, 2238 { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 }, 2239 { "z", 32, -1, 0, 0, 0, 0, 0, 0 }, 2240 { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 }, 2241 { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 } 2242}; 2243 2244 2245/* Iclass table. */ 2246 2247static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { 2248 { { STATE_PSRING }, 'i' }, 2249 { { STATE_PSEXCM }, 'm' }, 2250 { { STATE_EPC1 }, 'i' } 2251}; 2252 2253static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { 2254 { { STATE_PSEXCM }, 'i' }, 2255 { { STATE_PSRING }, 'i' }, 2256 { { STATE_DEPC }, 'i' } 2257}; 2258 2259static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { 2260 { { 0 /* soffsetx4 */ }, 'i' }, 2261 { { 10 /* ar12 */ }, 'o' } 2262}; 2263 2264static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { 2265 { { STATE_PSCALLINC }, 'o' } 2266}; 2267 2268static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { 2269 { { 0 /* soffsetx4 */ }, 'i' }, 2270 { { 9 /* ar8 */ }, 'o' } 2271}; 2272 2273static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { 2274 { { STATE_PSCALLINC }, 'o' } 2275}; 2276 2277static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { 2278 { { 0 /* soffsetx4 */ }, 'i' }, 2279 { { 8 /* ar4 */ }, 'o' } 2280}; 2281 2282static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { 2283 { { STATE_PSCALLINC }, 'o' } 2284}; 2285 2286static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { 2287 { { 4 /* ars */ }, 'i' }, 2288 { { 10 /* ar12 */ }, 'o' } 2289}; 2290 2291static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { 2292 { { STATE_PSCALLINC }, 'o' } 2293}; 2294 2295static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { 2296 { { 4 /* ars */ }, 'i' }, 2297 { { 9 /* ar8 */ }, 'o' } 2298}; 2299 2300static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { 2301 { { STATE_PSCALLINC }, 'o' } 2302}; 2303 2304static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { 2305 { { 4 /* ars */ }, 'i' }, 2306 { { 8 /* ar4 */ }, 'o' } 2307}; 2308 2309static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { 2310 { { STATE_PSCALLINC }, 'o' } 2311}; 2312 2313static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { 2314 { { 11 /* ars_entry */ }, 's' }, 2315 { { 4 /* ars */ }, 'i' }, 2316 { { 1 /* uimm12x8 */ }, 'i' } 2317}; 2318 2319static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { 2320 { { STATE_PSCALLINC }, 'i' }, 2321 { { STATE_PSEXCM }, 'i' }, 2322 { { STATE_PSWOE }, 'i' }, 2323 { { STATE_WindowBase }, 'm' }, 2324 { { STATE_WindowStart }, 'm' } 2325}; 2326 2327static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { 2328 { { 6 /* art */ }, 'o' }, 2329 { { 4 /* ars */ }, 'i' } 2330}; 2331 2332static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { 2333 { { STATE_WindowBase }, 'i' }, 2334 { { STATE_WindowStart }, 'i' } 2335}; 2336 2337static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { 2338 { { 2 /* simm4 */ }, 'i' } 2339}; 2340 2341static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { 2342 { { STATE_PSEXCM }, 'i' }, 2343 { { STATE_PSRING }, 'i' }, 2344 { { STATE_WindowBase }, 'm' } 2345}; 2346 2347static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { 2348 { { 5 /* *ars_invisible */ }, 'i' } 2349}; 2350 2351static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { 2352 { { STATE_WindowBase }, 'm' }, 2353 { { STATE_WindowStart }, 'm' }, 2354 { { STATE_PSEXCM }, 'i' }, 2355 { { STATE_PSWOE }, 'i' } 2356}; 2357 2358static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { 2359 { { STATE_EPC1 }, 'i' }, 2360 { { STATE_PSEXCM }, 'm' }, 2361 { { STATE_PSRING }, 'i' }, 2362 { { STATE_WindowBase }, 'm' }, 2363 { { STATE_WindowStart }, 'm' }, 2364 { { STATE_PSOWB }, 'i' } 2365}; 2366 2367static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { 2368 { { 6 /* art */ }, 'o' }, 2369 { { 4 /* ars */ }, 'i' }, 2370 { { 12 /* immrx4 */ }, 'i' } 2371}; 2372 2373static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { 2374 { { STATE_PSEXCM }, 'i' }, 2375 { { STATE_PSRING }, 'i' } 2376}; 2377 2378static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { 2379 { { 6 /* art */ }, 'i' }, 2380 { { 4 /* ars */ }, 'i' }, 2381 { { 12 /* immrx4 */ }, 'i' } 2382}; 2383 2384static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { 2385 { { STATE_PSEXCM }, 'i' }, 2386 { { STATE_PSRING }, 'i' } 2387}; 2388 2389static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { 2390 { { 6 /* art */ }, 'o' } 2391}; 2392 2393static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { 2394 { { STATE_PSEXCM }, 'i' }, 2395 { { STATE_PSRING }, 'i' }, 2396 { { STATE_WindowBase }, 'i' } 2397}; 2398 2399static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { 2400 { { 6 /* art */ }, 'i' } 2401}; 2402 2403static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { 2404 { { STATE_PSEXCM }, 'i' }, 2405 { { STATE_PSRING }, 'i' }, 2406 { { STATE_WindowBase }, 'o' } 2407}; 2408 2409static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { 2410 { { 6 /* art */ }, 'm' } 2411}; 2412 2413static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { 2414 { { STATE_PSEXCM }, 'i' }, 2415 { { STATE_PSRING }, 'i' }, 2416 { { STATE_WindowBase }, 'm' } 2417}; 2418 2419static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { 2420 { { 6 /* art */ }, 'o' } 2421}; 2422 2423static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { 2424 { { STATE_PSEXCM }, 'i' }, 2425 { { STATE_PSRING }, 'i' }, 2426 { { STATE_WindowStart }, 'i' } 2427}; 2428 2429static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { 2430 { { 6 /* art */ }, 'i' } 2431}; 2432 2433static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { 2434 { { STATE_PSEXCM }, 'i' }, 2435 { { STATE_PSRING }, 'i' }, 2436 { { STATE_WindowStart }, 'o' } 2437}; 2438 2439static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { 2440 { { 6 /* art */ }, 'm' } 2441}; 2442 2443static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { 2444 { { STATE_PSEXCM }, 'i' }, 2445 { { STATE_PSRING }, 'i' }, 2446 { { STATE_WindowStart }, 'm' } 2447}; 2448 2449static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { 2450 { { 3 /* arr */ }, 'o' }, 2451 { { 4 /* ars */ }, 'i' }, 2452 { { 6 /* art */ }, 'i' } 2453}; 2454 2455static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { 2456 { { 3 /* arr */ }, 'o' }, 2457 { { 4 /* ars */ }, 'i' }, 2458 { { 16 /* ai4const */ }, 'i' } 2459}; 2460 2461static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { 2462 { { 4 /* ars */ }, 'i' }, 2463 { { 15 /* uimm6 */ }, 'i' } 2464}; 2465 2466static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { 2467 { { 6 /* art */ }, 'o' }, 2468 { { 4 /* ars */ }, 'i' }, 2469 { { 13 /* lsi4x4 */ }, 'i' } 2470}; 2471 2472static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { 2473 { { 6 /* art */ }, 'o' }, 2474 { { 4 /* ars */ }, 'i' } 2475}; 2476 2477static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { 2478 { { 4 /* ars */ }, 'o' }, 2479 { { 14 /* simm7 */ }, 'i' } 2480}; 2481 2482static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { 2483 { { 5 /* *ars_invisible */ }, 'i' } 2484}; 2485 2486static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { 2487 { { 6 /* art */ }, 'i' }, 2488 { { 4 /* ars */ }, 'i' }, 2489 { { 13 /* lsi4x4 */ }, 'i' } 2490}; 2491 2492static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { 2493 { { 6 /* art */ }, 'o' }, 2494 { { 4 /* ars */ }, 'i' }, 2495 { { 23 /* simm8 */ }, 'i' } 2496}; 2497 2498static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { 2499 { { 6 /* art */ }, 'o' }, 2500 { { 4 /* ars */ }, 'i' }, 2501 { { 24 /* simm8x256 */ }, 'i' } 2502}; 2503 2504static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { 2505 { { 3 /* arr */ }, 'o' }, 2506 { { 4 /* ars */ }, 'i' }, 2507 { { 6 /* art */ }, 'i' } 2508}; 2509 2510static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { 2511 { { 3 /* arr */ }, 'o' }, 2512 { { 4 /* ars */ }, 'i' }, 2513 { { 6 /* art */ }, 'i' } 2514}; 2515 2516static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { 2517 { { 4 /* ars */ }, 'i' }, 2518 { { 17 /* b4const */ }, 'i' }, 2519 { { 28 /* label8 */ }, 'i' } 2520}; 2521 2522static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { 2523 { { 4 /* ars */ }, 'i' }, 2524 { { 37 /* bbi */ }, 'i' }, 2525 { { 28 /* label8 */ }, 'i' } 2526}; 2527 2528static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { 2529 { { 4 /* ars */ }, 'i' }, 2530 { { 18 /* b4constu */ }, 'i' }, 2531 { { 28 /* label8 */ }, 'i' } 2532}; 2533 2534static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { 2535 { { 4 /* ars */ }, 'i' }, 2536 { { 6 /* art */ }, 'i' }, 2537 { { 28 /* label8 */ }, 'i' } 2538}; 2539 2540static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { 2541 { { 4 /* ars */ }, 'i' }, 2542 { { 30 /* label12 */ }, 'i' } 2543}; 2544 2545static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { 2546 { { 0 /* soffsetx4 */ }, 'i' }, 2547 { { 7 /* ar0 */ }, 'o' } 2548}; 2549 2550static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { 2551 { { 4 /* ars */ }, 'i' }, 2552 { { 7 /* ar0 */ }, 'o' } 2553}; 2554 2555static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { 2556 { { 3 /* arr */ }, 'o' }, 2557 { { 6 /* art */ }, 'i' }, 2558 { { 52 /* sae */ }, 'i' }, 2559 { { 27 /* op2p1 */ }, 'i' } 2560}; 2561 2562static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { 2563 { { 31 /* soffset */ }, 'i' } 2564}; 2565 2566static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { 2567 { { 4 /* ars */ }, 'i' } 2568}; 2569 2570static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { 2571 { { 6 /* art */ }, 'o' }, 2572 { { 4 /* ars */ }, 'i' }, 2573 { { 20 /* uimm8x2 */ }, 'i' } 2574}; 2575 2576static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { 2577 { { 6 /* art */ }, 'o' }, 2578 { { 4 /* ars */ }, 'i' }, 2579 { { 20 /* uimm8x2 */ }, 'i' } 2580}; 2581 2582static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { 2583 { { 6 /* art */ }, 'o' }, 2584 { { 4 /* ars */ }, 'i' }, 2585 { { 21 /* uimm8x4 */ }, 'i' } 2586}; 2587 2588static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { 2589 { { 6 /* art */ }, 'o' }, 2590 { { 32 /* uimm16x4 */ }, 'i' } 2591}; 2592 2593static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = { 2594 { { STATE_LITBADDR }, 'i' }, 2595 { { STATE_LITBEN }, 'i' } 2596}; 2597 2598static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { 2599 { { 6 /* art */ }, 'o' }, 2600 { { 4 /* ars */ }, 'i' }, 2601 { { 19 /* uimm8 */ }, 'i' } 2602}; 2603 2604static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { 2605 { { 4 /* ars */ }, 'i' }, 2606 { { 29 /* ulabel8 */ }, 'i' } 2607}; 2608 2609static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { 2610 { { STATE_LBEG }, 'o' }, 2611 { { STATE_LEND }, 'o' }, 2612 { { STATE_LCOUNT }, 'o' } 2613}; 2614 2615static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { 2616 { { 4 /* ars */ }, 'i' }, 2617 { { 29 /* ulabel8 */ }, 'i' } 2618}; 2619 2620static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { 2621 { { STATE_LBEG }, 'o' }, 2622 { { STATE_LEND }, 'o' }, 2623 { { STATE_LCOUNT }, 'o' } 2624}; 2625 2626static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { 2627 { { 6 /* art */ }, 'o' }, 2628 { { 25 /* simm12b */ }, 'i' } 2629}; 2630 2631static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { 2632 { { 3 /* arr */ }, 'm' }, 2633 { { 4 /* ars */ }, 'i' }, 2634 { { 6 /* art */ }, 'i' } 2635}; 2636 2637static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { 2638 { { 3 /* arr */ }, 'o' }, 2639 { { 6 /* art */ }, 'i' } 2640}; 2641 2642static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { 2643 { { 5 /* *ars_invisible */ }, 'i' } 2644}; 2645 2646static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { 2647 { { 6 /* art */ }, 'i' }, 2648 { { 4 /* ars */ }, 'i' }, 2649 { { 20 /* uimm8x2 */ }, 'i' } 2650}; 2651 2652static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { 2653 { { 6 /* art */ }, 'i' }, 2654 { { 4 /* ars */ }, 'i' }, 2655 { { 21 /* uimm8x4 */ }, 'i' } 2656}; 2657 2658static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { 2659 { { 6 /* art */ }, 'i' }, 2660 { { 4 /* ars */ }, 'i' }, 2661 { { 19 /* uimm8 */ }, 'i' } 2662}; 2663 2664static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { 2665 { { 4 /* ars */ }, 'i' } 2666}; 2667 2668static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { 2669 { { STATE_SAR }, 'o' } 2670}; 2671 2672static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { 2673 { { 56 /* sas */ }, 'i' } 2674}; 2675 2676static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { 2677 { { STATE_SAR }, 'o' } 2678}; 2679 2680static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { 2681 { { 3 /* arr */ }, 'o' }, 2682 { { 4 /* ars */ }, 'i' } 2683}; 2684 2685static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { 2686 { { STATE_SAR }, 'i' } 2687}; 2688 2689static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { 2690 { { 3 /* arr */ }, 'o' }, 2691 { { 4 /* ars */ }, 'i' }, 2692 { { 6 /* art */ }, 'i' } 2693}; 2694 2695static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { 2696 { { STATE_SAR }, 'i' } 2697}; 2698 2699static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { 2700 { { 3 /* arr */ }, 'o' }, 2701 { { 6 /* art */ }, 'i' } 2702}; 2703 2704static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { 2705 { { STATE_SAR }, 'i' } 2706}; 2707 2708static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { 2709 { { 3 /* arr */ }, 'o' }, 2710 { { 4 /* ars */ }, 'i' }, 2711 { { 26 /* msalp32 */ }, 'i' } 2712}; 2713 2714static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { 2715 { { 3 /* arr */ }, 'o' }, 2716 { { 6 /* art */ }, 'i' }, 2717 { { 54 /* sargt */ }, 'i' } 2718}; 2719 2720static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { 2721 { { 3 /* arr */ }, 'o' }, 2722 { { 6 /* art */ }, 'i' }, 2723 { { 40 /* s */ }, 'i' } 2724}; 2725 2726static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { 2727 { { STATE_XTSYNC }, 'i' } 2728}; 2729 2730static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { 2731 { { 6 /* art */ }, 'o' }, 2732 { { 40 /* s */ }, 'i' } 2733}; 2734 2735static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { 2736 { { STATE_PSWOE }, 'i' }, 2737 { { STATE_PSCALLINC }, 'i' }, 2738 { { STATE_PSOWB }, 'i' }, 2739 { { STATE_PSRING }, 'i' }, 2740 { { STATE_PSUM }, 'i' }, 2741 { { STATE_PSEXCM }, 'i' }, 2742 { { STATE_PSINTLEVEL }, 'm' } 2743}; 2744 2745static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { 2746 { { 6 /* art */ }, 'o' } 2747}; 2748 2749static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { 2750 { { STATE_LEND }, 'i' } 2751}; 2752 2753static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { 2754 { { 6 /* art */ }, 'i' } 2755}; 2756 2757static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { 2758 { { STATE_LEND }, 'o' } 2759}; 2760 2761static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { 2762 { { 6 /* art */ }, 'm' } 2763}; 2764 2765static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { 2766 { { STATE_LEND }, 'm' } 2767}; 2768 2769static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { 2770 { { 6 /* art */ }, 'o' } 2771}; 2772 2773static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { 2774 { { STATE_LCOUNT }, 'i' } 2775}; 2776 2777static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { 2778 { { 6 /* art */ }, 'i' } 2779}; 2780 2781static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { 2782 { { STATE_XTSYNC }, 'o' }, 2783 { { STATE_LCOUNT }, 'o' } 2784}; 2785 2786static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { 2787 { { 6 /* art */ }, 'm' } 2788}; 2789 2790static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { 2791 { { STATE_XTSYNC }, 'o' }, 2792 { { STATE_LCOUNT }, 'm' } 2793}; 2794 2795static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { 2796 { { 6 /* art */ }, 'o' } 2797}; 2798 2799static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { 2800 { { STATE_LBEG }, 'i' } 2801}; 2802 2803static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { 2804 { { 6 /* art */ }, 'i' } 2805}; 2806 2807static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { 2808 { { STATE_LBEG }, 'o' } 2809}; 2810 2811static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { 2812 { { 6 /* art */ }, 'm' } 2813}; 2814 2815static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { 2816 { { STATE_LBEG }, 'm' } 2817}; 2818 2819static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { 2820 { { 6 /* art */ }, 'o' } 2821}; 2822 2823static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { 2824 { { STATE_SAR }, 'i' } 2825}; 2826 2827static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { 2828 { { 6 /* art */ }, 'i' } 2829}; 2830 2831static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { 2832 { { STATE_SAR }, 'o' }, 2833 { { STATE_XTSYNC }, 'o' } 2834}; 2835 2836static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { 2837 { { 6 /* art */ }, 'm' } 2838}; 2839 2840static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { 2841 { { STATE_SAR }, 'm' } 2842}; 2843 2844static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { 2845 { { 6 /* art */ }, 'o' } 2846}; 2847 2848static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = { 2849 { { STATE_LITBADDR }, 'i' }, 2850 { { STATE_LITBEN }, 'i' } 2851}; 2852 2853static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { 2854 { { 6 /* art */ }, 'i' } 2855}; 2856 2857static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = { 2858 { { STATE_LITBADDR }, 'o' }, 2859 { { STATE_LITBEN }, 'o' } 2860}; 2861 2862static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { 2863 { { 6 /* art */ }, 'm' } 2864}; 2865 2866static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = { 2867 { { STATE_LITBADDR }, 'm' }, 2868 { { STATE_LITBEN }, 'm' } 2869}; 2870 2871static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = { 2872 { { 6 /* art */ }, 'o' } 2873}; 2874 2875static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = { 2876 { { STATE_PSEXCM }, 'i' }, 2877 { { STATE_PSRING }, 'i' } 2878}; 2879 2880static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = { 2881 { { 6 /* art */ }, 'o' } 2882}; 2883 2884static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = { 2885 { { STATE_PSEXCM }, 'i' }, 2886 { { STATE_PSRING }, 'i' } 2887}; 2888 2889static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { 2890 { { 6 /* art */ }, 'o' } 2891}; 2892 2893static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { 2894 { { STATE_PSWOE }, 'i' }, 2895 { { STATE_PSCALLINC }, 'i' }, 2896 { { STATE_PSOWB }, 'i' }, 2897 { { STATE_PSRING }, 'i' }, 2898 { { STATE_PSUM }, 'i' }, 2899 { { STATE_PSEXCM }, 'i' }, 2900 { { STATE_PSINTLEVEL }, 'i' } 2901}; 2902 2903static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { 2904 { { 6 /* art */ }, 'i' } 2905}; 2906 2907static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { 2908 { { STATE_PSWOE }, 'o' }, 2909 { { STATE_PSCALLINC }, 'o' }, 2910 { { STATE_PSOWB }, 'o' }, 2911 { { STATE_PSRING }, 'm' }, 2912 { { STATE_PSUM }, 'o' }, 2913 { { STATE_PSEXCM }, 'm' }, 2914 { { STATE_PSINTLEVEL }, 'o' } 2915}; 2916 2917static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { 2918 { { 6 /* art */ }, 'm' } 2919}; 2920 2921static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { 2922 { { STATE_PSWOE }, 'm' }, 2923 { { STATE_PSCALLINC }, 'm' }, 2924 { { STATE_PSOWB }, 'm' }, 2925 { { STATE_PSRING }, 'm' }, 2926 { { STATE_PSUM }, 'm' }, 2927 { { STATE_PSEXCM }, 'm' }, 2928 { { STATE_PSINTLEVEL }, 'm' } 2929}; 2930 2931static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { 2932 { { 6 /* art */ }, 'o' } 2933}; 2934 2935static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { 2936 { { STATE_PSEXCM }, 'i' }, 2937 { { STATE_PSRING }, 'i' }, 2938 { { STATE_EPC1 }, 'i' } 2939}; 2940 2941static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { 2942 { { 6 /* art */ }, 'i' } 2943}; 2944 2945static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { 2946 { { STATE_PSEXCM }, 'i' }, 2947 { { STATE_PSRING }, 'i' }, 2948 { { STATE_EPC1 }, 'o' } 2949}; 2950 2951static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { 2952 { { 6 /* art */ }, 'm' } 2953}; 2954 2955static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { 2956 { { STATE_PSEXCM }, 'i' }, 2957 { { STATE_PSRING }, 'i' }, 2958 { { STATE_EPC1 }, 'm' } 2959}; 2960 2961static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { 2962 { { 6 /* art */ }, 'o' } 2963}; 2964 2965static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { 2966 { { STATE_PSEXCM }, 'i' }, 2967 { { STATE_PSRING }, 'i' }, 2968 { { STATE_EXCSAVE1 }, 'i' } 2969}; 2970 2971static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { 2972 { { 6 /* art */ }, 'i' } 2973}; 2974 2975static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { 2976 { { STATE_PSEXCM }, 'i' }, 2977 { { STATE_PSRING }, 'i' }, 2978 { { STATE_EXCSAVE1 }, 'o' } 2979}; 2980 2981static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { 2982 { { 6 /* art */ }, 'm' } 2983}; 2984 2985static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { 2986 { { STATE_PSEXCM }, 'i' }, 2987 { { STATE_PSRING }, 'i' }, 2988 { { STATE_EXCSAVE1 }, 'm' } 2989}; 2990 2991static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { 2992 { { 6 /* art */ }, 'o' } 2993}; 2994 2995static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { 2996 { { STATE_PSEXCM }, 'i' }, 2997 { { STATE_PSRING }, 'i' }, 2998 { { STATE_EPC2 }, 'i' } 2999}; 3000 3001static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { 3002 { { 6 /* art */ }, 'i' } 3003}; 3004 3005static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { 3006 { { STATE_PSEXCM }, 'i' }, 3007 { { STATE_PSRING }, 'i' }, 3008 { { STATE_EPC2 }, 'o' } 3009}; 3010 3011static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { 3012 { { 6 /* art */ }, 'm' } 3013}; 3014 3015static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { 3016 { { STATE_PSEXCM }, 'i' }, 3017 { { STATE_PSRING }, 'i' }, 3018 { { STATE_EPC2 }, 'm' } 3019}; 3020 3021static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { 3022 { { 6 /* art */ }, 'o' } 3023}; 3024 3025static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { 3026 { { STATE_PSEXCM }, 'i' }, 3027 { { STATE_PSRING }, 'i' }, 3028 { { STATE_EXCSAVE2 }, 'i' } 3029}; 3030 3031static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { 3032 { { 6 /* art */ }, 'i' } 3033}; 3034 3035static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { 3036 { { STATE_PSEXCM }, 'i' }, 3037 { { STATE_PSRING }, 'i' }, 3038 { { STATE_EXCSAVE2 }, 'o' } 3039}; 3040 3041static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { 3042 { { 6 /* art */ }, 'm' } 3043}; 3044 3045static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { 3046 { { STATE_PSEXCM }, 'i' }, 3047 { { STATE_PSRING }, 'i' }, 3048 { { STATE_EXCSAVE2 }, 'm' } 3049}; 3050 3051static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { 3052 { { 6 /* art */ }, 'o' } 3053}; 3054 3055static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { 3056 { { STATE_PSEXCM }, 'i' }, 3057 { { STATE_PSRING }, 'i' }, 3058 { { STATE_EPC3 }, 'i' } 3059}; 3060 3061static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { 3062 { { 6 /* art */ }, 'i' } 3063}; 3064 3065static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { 3066 { { STATE_PSEXCM }, 'i' }, 3067 { { STATE_PSRING }, 'i' }, 3068 { { STATE_EPC3 }, 'o' } 3069}; 3070 3071static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { 3072 { { 6 /* art */ }, 'm' } 3073}; 3074 3075static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { 3076 { { STATE_PSEXCM }, 'i' }, 3077 { { STATE_PSRING }, 'i' }, 3078 { { STATE_EPC3 }, 'm' } 3079}; 3080 3081static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { 3082 { { 6 /* art */ }, 'o' } 3083}; 3084 3085static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { 3086 { { STATE_PSEXCM }, 'i' }, 3087 { { STATE_PSRING }, 'i' }, 3088 { { STATE_EXCSAVE3 }, 'i' } 3089}; 3090 3091static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { 3092 { { 6 /* art */ }, 'i' } 3093}; 3094 3095static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { 3096 { { STATE_PSEXCM }, 'i' }, 3097 { { STATE_PSRING }, 'i' }, 3098 { { STATE_EXCSAVE3 }, 'o' } 3099}; 3100 3101static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { 3102 { { 6 /* art */ }, 'm' } 3103}; 3104 3105static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { 3106 { { STATE_PSEXCM }, 'i' }, 3107 { { STATE_PSRING }, 'i' }, 3108 { { STATE_EXCSAVE3 }, 'm' } 3109}; 3110 3111static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { 3112 { { 6 /* art */ }, 'o' } 3113}; 3114 3115static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { 3116 { { STATE_PSEXCM }, 'i' }, 3117 { { STATE_PSRING }, 'i' }, 3118 { { STATE_EPC4 }, 'i' } 3119}; 3120 3121static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { 3122 { { 6 /* art */ }, 'i' } 3123}; 3124 3125static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { 3126 { { STATE_PSEXCM }, 'i' }, 3127 { { STATE_PSRING }, 'i' }, 3128 { { STATE_EPC4 }, 'o' } 3129}; 3130 3131static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { 3132 { { 6 /* art */ }, 'm' } 3133}; 3134 3135static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { 3136 { { STATE_PSEXCM }, 'i' }, 3137 { { STATE_PSRING }, 'i' }, 3138 { { STATE_EPC4 }, 'm' } 3139}; 3140 3141static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { 3142 { { 6 /* art */ }, 'o' } 3143}; 3144 3145static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { 3146 { { STATE_PSEXCM }, 'i' }, 3147 { { STATE_PSRING }, 'i' }, 3148 { { STATE_EXCSAVE4 }, 'i' } 3149}; 3150 3151static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { 3152 { { 6 /* art */ }, 'i' } 3153}; 3154 3155static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { 3156 { { STATE_PSEXCM }, 'i' }, 3157 { { STATE_PSRING }, 'i' }, 3158 { { STATE_EXCSAVE4 }, 'o' } 3159}; 3160 3161static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { 3162 { { 6 /* art */ }, 'm' } 3163}; 3164 3165static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { 3166 { { STATE_PSEXCM }, 'i' }, 3167 { { STATE_PSRING }, 'i' }, 3168 { { STATE_EXCSAVE4 }, 'm' } 3169}; 3170 3171static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { 3172 { { 6 /* art */ }, 'o' } 3173}; 3174 3175static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { 3176 { { STATE_PSEXCM }, 'i' }, 3177 { { STATE_PSRING }, 'i' }, 3178 { { STATE_EPS2 }, 'i' } 3179}; 3180 3181static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { 3182 { { 6 /* art */ }, 'i' } 3183}; 3184 3185static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { 3186 { { STATE_PSEXCM }, 'i' }, 3187 { { STATE_PSRING }, 'i' }, 3188 { { STATE_EPS2 }, 'o' } 3189}; 3190 3191static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { 3192 { { 6 /* art */ }, 'm' } 3193}; 3194 3195static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { 3196 { { STATE_PSEXCM }, 'i' }, 3197 { { STATE_PSRING }, 'i' }, 3198 { { STATE_EPS2 }, 'm' } 3199}; 3200 3201static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { 3202 { { 6 /* art */ }, 'o' } 3203}; 3204 3205static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { 3206 { { STATE_PSEXCM }, 'i' }, 3207 { { STATE_PSRING }, 'i' }, 3208 { { STATE_EPS3 }, 'i' } 3209}; 3210 3211static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { 3212 { { 6 /* art */ }, 'i' } 3213}; 3214 3215static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { 3216 { { STATE_PSEXCM }, 'i' }, 3217 { { STATE_PSRING }, 'i' }, 3218 { { STATE_EPS3 }, 'o' } 3219}; 3220 3221static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { 3222 { { 6 /* art */ }, 'm' } 3223}; 3224 3225static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { 3226 { { STATE_PSEXCM }, 'i' }, 3227 { { STATE_PSRING }, 'i' }, 3228 { { STATE_EPS3 }, 'm' } 3229}; 3230 3231static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { 3232 { { 6 /* art */ }, 'o' } 3233}; 3234 3235static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { 3236 { { STATE_PSEXCM }, 'i' }, 3237 { { STATE_PSRING }, 'i' }, 3238 { { STATE_EPS4 }, 'i' } 3239}; 3240 3241static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { 3242 { { 6 /* art */ }, 'i' } 3243}; 3244 3245static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { 3246 { { STATE_PSEXCM }, 'i' }, 3247 { { STATE_PSRING }, 'i' }, 3248 { { STATE_EPS4 }, 'o' } 3249}; 3250 3251static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { 3252 { { 6 /* art */ }, 'm' } 3253}; 3254 3255static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { 3256 { { STATE_PSEXCM }, 'i' }, 3257 { { STATE_PSRING }, 'i' }, 3258 { { STATE_EPS4 }, 'm' } 3259}; 3260 3261static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { 3262 { { 6 /* art */ }, 'o' } 3263}; 3264 3265static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { 3266 { { STATE_PSEXCM }, 'i' }, 3267 { { STATE_PSRING }, 'i' }, 3268 { { STATE_EXCVADDR }, 'i' } 3269}; 3270 3271static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { 3272 { { 6 /* art */ }, 'i' } 3273}; 3274 3275static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { 3276 { { STATE_PSEXCM }, 'i' }, 3277 { { STATE_PSRING }, 'i' }, 3278 { { STATE_EXCVADDR }, 'o' } 3279}; 3280 3281static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { 3282 { { 6 /* art */ }, 'm' } 3283}; 3284 3285static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { 3286 { { STATE_PSEXCM }, 'i' }, 3287 { { STATE_PSRING }, 'i' }, 3288 { { STATE_EXCVADDR }, 'm' } 3289}; 3290 3291static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { 3292 { { 6 /* art */ }, 'o' } 3293}; 3294 3295static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { 3296 { { STATE_PSEXCM }, 'i' }, 3297 { { STATE_PSRING }, 'i' }, 3298 { { STATE_DEPC }, 'i' } 3299}; 3300 3301static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { 3302 { { 6 /* art */ }, 'i' } 3303}; 3304 3305static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { 3306 { { STATE_PSEXCM }, 'i' }, 3307 { { STATE_PSRING }, 'i' }, 3308 { { STATE_DEPC }, 'o' } 3309}; 3310 3311static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { 3312 { { 6 /* art */ }, 'm' } 3313}; 3314 3315static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { 3316 { { STATE_PSEXCM }, 'i' }, 3317 { { STATE_PSRING }, 'i' }, 3318 { { STATE_DEPC }, 'm' } 3319}; 3320 3321static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { 3322 { { 6 /* art */ }, 'o' } 3323}; 3324 3325static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { 3326 { { STATE_PSEXCM }, 'i' }, 3327 { { STATE_PSRING }, 'i' }, 3328 { { STATE_EXCCAUSE }, 'i' }, 3329 { { STATE_XTSYNC }, 'i' } 3330}; 3331 3332static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { 3333 { { 6 /* art */ }, 'i' } 3334}; 3335 3336static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { 3337 { { STATE_PSEXCM }, 'i' }, 3338 { { STATE_PSRING }, 'i' }, 3339 { { STATE_EXCCAUSE }, 'o' } 3340}; 3341 3342static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { 3343 { { 6 /* art */ }, 'm' } 3344}; 3345 3346static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { 3347 { { STATE_PSEXCM }, 'i' }, 3348 { { STATE_PSRING }, 'i' }, 3349 { { STATE_EXCCAUSE }, 'm' } 3350}; 3351 3352static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { 3353 { { 6 /* art */ }, 'o' } 3354}; 3355 3356static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { 3357 { { STATE_PSEXCM }, 'i' }, 3358 { { STATE_PSRING }, 'i' }, 3359 { { STATE_MISC0 }, 'i' } 3360}; 3361 3362static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { 3363 { { 6 /* art */ }, 'i' } 3364}; 3365 3366static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { 3367 { { STATE_PSEXCM }, 'i' }, 3368 { { STATE_PSRING }, 'i' }, 3369 { { STATE_MISC0 }, 'o' } 3370}; 3371 3372static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { 3373 { { 6 /* art */ }, 'm' } 3374}; 3375 3376static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { 3377 { { STATE_PSEXCM }, 'i' }, 3378 { { STATE_PSRING }, 'i' }, 3379 { { STATE_MISC0 }, 'm' } 3380}; 3381 3382static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { 3383 { { 6 /* art */ }, 'o' } 3384}; 3385 3386static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { 3387 { { STATE_PSEXCM }, 'i' }, 3388 { { STATE_PSRING }, 'i' }, 3389 { { STATE_MISC1 }, 'i' } 3390}; 3391 3392static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { 3393 { { 6 /* art */ }, 'i' } 3394}; 3395 3396static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { 3397 { { STATE_PSEXCM }, 'i' }, 3398 { { STATE_PSRING }, 'i' }, 3399 { { STATE_MISC1 }, 'o' } 3400}; 3401 3402static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { 3403 { { 6 /* art */ }, 'm' } 3404}; 3405 3406static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { 3407 { { STATE_PSEXCM }, 'i' }, 3408 { { STATE_PSRING }, 'i' }, 3409 { { STATE_MISC1 }, 'm' } 3410}; 3411 3412static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { 3413 { { 6 /* art */ }, 'o' } 3414}; 3415 3416static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { 3417 { { STATE_PSEXCM }, 'i' }, 3418 { { STATE_PSRING }, 'i' } 3419}; 3420 3421static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { 3422 { { 40 /* s */ }, 'i' } 3423}; 3424 3425static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { 3426 { { STATE_PSWOE }, 'o' }, 3427 { { STATE_PSCALLINC }, 'o' }, 3428 { { STATE_PSOWB }, 'o' }, 3429 { { STATE_PSRING }, 'm' }, 3430 { { STATE_PSUM }, 'o' }, 3431 { { STATE_PSEXCM }, 'm' }, 3432 { { STATE_PSINTLEVEL }, 'o' }, 3433 { { STATE_EPC1 }, 'i' }, 3434 { { STATE_EPC2 }, 'i' }, 3435 { { STATE_EPC3 }, 'i' }, 3436 { { STATE_EPC4 }, 'i' }, 3437 { { STATE_EPS2 }, 'i' }, 3438 { { STATE_EPS3 }, 'i' }, 3439 { { STATE_EPS4 }, 'i' }, 3440 { { STATE_InOCDMode }, 'm' } 3441}; 3442 3443static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { 3444 { { 40 /* s */ }, 'i' } 3445}; 3446 3447static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { 3448 { { STATE_PSEXCM }, 'i' }, 3449 { { STATE_PSRING }, 'i' }, 3450 { { STATE_PSINTLEVEL }, 'o' } 3451}; 3452 3453static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { 3454 { { 6 /* art */ }, 'o' } 3455}; 3456 3457static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { 3458 { { STATE_PSEXCM }, 'i' }, 3459 { { STATE_PSRING }, 'i' }, 3460 { { STATE_INTERRUPT }, 'i' } 3461}; 3462 3463static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { 3464 { { 6 /* art */ }, 'i' } 3465}; 3466 3467static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { 3468 { { STATE_PSEXCM }, 'i' }, 3469 { { STATE_PSRING }, 'i' }, 3470 { { STATE_XTSYNC }, 'o' }, 3471 { { STATE_INTERRUPT }, 'm' } 3472}; 3473 3474static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { 3475 { { 6 /* art */ }, 'i' } 3476}; 3477 3478static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { 3479 { { STATE_PSEXCM }, 'i' }, 3480 { { STATE_PSRING }, 'i' }, 3481 { { STATE_XTSYNC }, 'o' }, 3482 { { STATE_INTERRUPT }, 'm' } 3483}; 3484 3485static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { 3486 { { 6 /* art */ }, 'o' } 3487}; 3488 3489static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { 3490 { { STATE_PSEXCM }, 'i' }, 3491 { { STATE_PSRING }, 'i' }, 3492 { { STATE_INTENABLE }, 'i' } 3493}; 3494 3495static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { 3496 { { 6 /* art */ }, 'i' } 3497}; 3498 3499static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { 3500 { { STATE_PSEXCM }, 'i' }, 3501 { { STATE_PSRING }, 'i' }, 3502 { { STATE_INTENABLE }, 'o' } 3503}; 3504 3505static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { 3506 { { 6 /* art */ }, 'm' } 3507}; 3508 3509static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { 3510 { { STATE_PSEXCM }, 'i' }, 3511 { { STATE_PSRING }, 'i' }, 3512 { { STATE_INTENABLE }, 'm' } 3513}; 3514 3515static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { 3516 { { 34 /* imms */ }, 'i' }, 3517 { { 33 /* immt */ }, 'i' } 3518}; 3519 3520static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { 3521 { { STATE_PSEXCM }, 'i' }, 3522 { { STATE_PSINTLEVEL }, 'i' } 3523}; 3524 3525static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { 3526 { { 34 /* imms */ }, 'i' } 3527}; 3528 3529static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { 3530 { { STATE_PSEXCM }, 'i' }, 3531 { { STATE_PSINTLEVEL }, 'i' } 3532}; 3533 3534static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { 3535 { { 6 /* art */ }, 'o' } 3536}; 3537 3538static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { 3539 { { STATE_PSEXCM }, 'i' }, 3540 { { STATE_PSRING }, 'i' }, 3541 { { STATE_DBREAKA0 }, 'i' } 3542}; 3543 3544static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { 3545 { { 6 /* art */ }, 'i' } 3546}; 3547 3548static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { 3549 { { STATE_PSEXCM }, 'i' }, 3550 { { STATE_PSRING }, 'i' }, 3551 { { STATE_DBREAKA0 }, 'o' }, 3552 { { STATE_XTSYNC }, 'o' } 3553}; 3554 3555static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { 3556 { { 6 /* art */ }, 'm' } 3557}; 3558 3559static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { 3560 { { STATE_PSEXCM }, 'i' }, 3561 { { STATE_PSRING }, 'i' }, 3562 { { STATE_DBREAKA0 }, 'm' }, 3563 { { STATE_XTSYNC }, 'o' } 3564}; 3565 3566static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { 3567 { { 6 /* art */ }, 'o' } 3568}; 3569 3570static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { 3571 { { STATE_PSEXCM }, 'i' }, 3572 { { STATE_PSRING }, 'i' }, 3573 { { STATE_DBREAKC0 }, 'i' } 3574}; 3575 3576static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { 3577 { { 6 /* art */ }, 'i' } 3578}; 3579 3580static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { 3581 { { STATE_PSEXCM }, 'i' }, 3582 { { STATE_PSRING }, 'i' }, 3583 { { STATE_DBREAKC0 }, 'o' }, 3584 { { STATE_XTSYNC }, 'o' } 3585}; 3586 3587static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { 3588 { { 6 /* art */ }, 'm' } 3589}; 3590 3591static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { 3592 { { STATE_PSEXCM }, 'i' }, 3593 { { STATE_PSRING }, 'i' }, 3594 { { STATE_DBREAKC0 }, 'm' }, 3595 { { STATE_XTSYNC }, 'o' } 3596}; 3597 3598static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { 3599 { { 6 /* art */ }, 'o' } 3600}; 3601 3602static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { 3603 { { STATE_PSEXCM }, 'i' }, 3604 { { STATE_PSRING }, 'i' }, 3605 { { STATE_DBREAKA1 }, 'i' } 3606}; 3607 3608static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { 3609 { { 6 /* art */ }, 'i' } 3610}; 3611 3612static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { 3613 { { STATE_PSEXCM }, 'i' }, 3614 { { STATE_PSRING }, 'i' }, 3615 { { STATE_DBREAKA1 }, 'o' }, 3616 { { STATE_XTSYNC }, 'o' } 3617}; 3618 3619static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { 3620 { { 6 /* art */ }, 'm' } 3621}; 3622 3623static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { 3624 { { STATE_PSEXCM }, 'i' }, 3625 { { STATE_PSRING }, 'i' }, 3626 { { STATE_DBREAKA1 }, 'm' }, 3627 { { STATE_XTSYNC }, 'o' } 3628}; 3629 3630static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { 3631 { { 6 /* art */ }, 'o' } 3632}; 3633 3634static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { 3635 { { STATE_PSEXCM }, 'i' }, 3636 { { STATE_PSRING }, 'i' }, 3637 { { STATE_DBREAKC1 }, 'i' } 3638}; 3639 3640static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { 3641 { { 6 /* art */ }, 'i' } 3642}; 3643 3644static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { 3645 { { STATE_PSEXCM }, 'i' }, 3646 { { STATE_PSRING }, 'i' }, 3647 { { STATE_DBREAKC1 }, 'o' }, 3648 { { STATE_XTSYNC }, 'o' } 3649}; 3650 3651static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { 3652 { { 6 /* art */ }, 'm' } 3653}; 3654 3655static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { 3656 { { STATE_PSEXCM }, 'i' }, 3657 { { STATE_PSRING }, 'i' }, 3658 { { STATE_DBREAKC1 }, 'm' }, 3659 { { STATE_XTSYNC }, 'o' } 3660}; 3661 3662static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { 3663 { { 6 /* art */ }, 'o' } 3664}; 3665 3666static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { 3667 { { STATE_PSEXCM }, 'i' }, 3668 { { STATE_PSRING }, 'i' }, 3669 { { STATE_IBREAKA0 }, 'i' } 3670}; 3671 3672static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { 3673 { { 6 /* art */ }, 'i' } 3674}; 3675 3676static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { 3677 { { STATE_PSEXCM }, 'i' }, 3678 { { STATE_PSRING }, 'i' }, 3679 { { STATE_IBREAKA0 }, 'o' } 3680}; 3681 3682static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { 3683 { { 6 /* art */ }, 'm' } 3684}; 3685 3686static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { 3687 { { STATE_PSEXCM }, 'i' }, 3688 { { STATE_PSRING }, 'i' }, 3689 { { STATE_IBREAKA0 }, 'm' } 3690}; 3691 3692static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { 3693 { { 6 /* art */ }, 'o' } 3694}; 3695 3696static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { 3697 { { STATE_PSEXCM }, 'i' }, 3698 { { STATE_PSRING }, 'i' }, 3699 { { STATE_IBREAKA1 }, 'i' } 3700}; 3701 3702static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { 3703 { { 6 /* art */ }, 'i' } 3704}; 3705 3706static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { 3707 { { STATE_PSEXCM }, 'i' }, 3708 { { STATE_PSRING }, 'i' }, 3709 { { STATE_IBREAKA1 }, 'o' } 3710}; 3711 3712static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { 3713 { { 6 /* art */ }, 'm' } 3714}; 3715 3716static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { 3717 { { STATE_PSEXCM }, 'i' }, 3718 { { STATE_PSRING }, 'i' }, 3719 { { STATE_IBREAKA1 }, 'm' } 3720}; 3721 3722static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { 3723 { { 6 /* art */ }, 'o' } 3724}; 3725 3726static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { 3727 { { STATE_PSEXCM }, 'i' }, 3728 { { STATE_PSRING }, 'i' }, 3729 { { STATE_IBREAKENABLE }, 'i' } 3730}; 3731 3732static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { 3733 { { 6 /* art */ }, 'i' } 3734}; 3735 3736static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { 3737 { { STATE_PSEXCM }, 'i' }, 3738 { { STATE_PSRING }, 'i' }, 3739 { { STATE_IBREAKENABLE }, 'o' } 3740}; 3741 3742static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { 3743 { { 6 /* art */ }, 'm' } 3744}; 3745 3746static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { 3747 { { STATE_PSEXCM }, 'i' }, 3748 { { STATE_PSRING }, 'i' }, 3749 { { STATE_IBREAKENABLE }, 'm' } 3750}; 3751 3752static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { 3753 { { 6 /* art */ }, 'o' } 3754}; 3755 3756static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { 3757 { { STATE_PSEXCM }, 'i' }, 3758 { { STATE_PSRING }, 'i' }, 3759 { { STATE_DEBUGCAUSE }, 'i' }, 3760 { { STATE_DBNUM }, 'i' } 3761}; 3762 3763static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { 3764 { { 6 /* art */ }, 'i' } 3765}; 3766 3767static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { 3768 { { STATE_PSEXCM }, 'i' }, 3769 { { STATE_PSRING }, 'i' }, 3770 { { STATE_DEBUGCAUSE }, 'o' }, 3771 { { STATE_DBNUM }, 'o' } 3772}; 3773 3774static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { 3775 { { 6 /* art */ }, 'm' } 3776}; 3777 3778static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { 3779 { { STATE_PSEXCM }, 'i' }, 3780 { { STATE_PSRING }, 'i' }, 3781 { { STATE_DEBUGCAUSE }, 'm' }, 3782 { { STATE_DBNUM }, 'm' } 3783}; 3784 3785static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { 3786 { { 6 /* art */ }, 'o' } 3787}; 3788 3789static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { 3790 { { STATE_PSEXCM }, 'i' }, 3791 { { STATE_PSRING }, 'i' }, 3792 { { STATE_ICOUNT }, 'i' } 3793}; 3794 3795static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { 3796 { { 6 /* art */ }, 'i' } 3797}; 3798 3799static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { 3800 { { STATE_PSEXCM }, 'i' }, 3801 { { STATE_PSRING }, 'i' }, 3802 { { STATE_XTSYNC }, 'o' }, 3803 { { STATE_ICOUNT }, 'o' } 3804}; 3805 3806static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { 3807 { { 6 /* art */ }, 'm' } 3808}; 3809 3810static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { 3811 { { STATE_PSEXCM }, 'i' }, 3812 { { STATE_PSRING }, 'i' }, 3813 { { STATE_XTSYNC }, 'o' }, 3814 { { STATE_ICOUNT }, 'm' } 3815}; 3816 3817static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { 3818 { { 6 /* art */ }, 'o' } 3819}; 3820 3821static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { 3822 { { STATE_PSEXCM }, 'i' }, 3823 { { STATE_PSRING }, 'i' }, 3824 { { STATE_ICOUNTLEVEL }, 'i' } 3825}; 3826 3827static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { 3828 { { 6 /* art */ }, 'i' } 3829}; 3830 3831static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { 3832 { { STATE_PSEXCM }, 'i' }, 3833 { { STATE_PSRING }, 'i' }, 3834 { { STATE_ICOUNTLEVEL }, 'o' } 3835}; 3836 3837static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { 3838 { { 6 /* art */ }, 'm' } 3839}; 3840 3841static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { 3842 { { STATE_PSEXCM }, 'i' }, 3843 { { STATE_PSRING }, 'i' }, 3844 { { STATE_ICOUNTLEVEL }, 'm' } 3845}; 3846 3847static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { 3848 { { 6 /* art */ }, 'o' } 3849}; 3850 3851static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { 3852 { { STATE_PSEXCM }, 'i' }, 3853 { { STATE_PSRING }, 'i' }, 3854 { { STATE_DDR }, 'i' } 3855}; 3856 3857static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { 3858 { { 6 /* art */ }, 'i' } 3859}; 3860 3861static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { 3862 { { STATE_PSEXCM }, 'i' }, 3863 { { STATE_PSRING }, 'i' }, 3864 { { STATE_XTSYNC }, 'o' }, 3865 { { STATE_DDR }, 'o' } 3866}; 3867 3868static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { 3869 { { 6 /* art */ }, 'm' } 3870}; 3871 3872static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { 3873 { { STATE_PSEXCM }, 'i' }, 3874 { { STATE_PSRING }, 'i' }, 3875 { { STATE_XTSYNC }, 'o' }, 3876 { { STATE_DDR }, 'm' } 3877}; 3878 3879static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { 3880 { { STATE_InOCDMode }, 'm' }, 3881 { { STATE_EPC4 }, 'i' }, 3882 { { STATE_PSWOE }, 'o' }, 3883 { { STATE_PSCALLINC }, 'o' }, 3884 { { STATE_PSOWB }, 'o' }, 3885 { { STATE_PSRING }, 'o' }, 3886 { { STATE_PSUM }, 'o' }, 3887 { { STATE_PSEXCM }, 'o' }, 3888 { { STATE_PSINTLEVEL }, 'o' }, 3889 { { STATE_EPS4 }, 'i' } 3890}; 3891 3892static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { 3893 { { STATE_InOCDMode }, 'm' } 3894}; 3895 3896static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { 3897 { { 6 /* art */ }, 'o' } 3898}; 3899 3900static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { 3901 { { STATE_PSEXCM }, 'i' }, 3902 { { STATE_PSRING }, 'i' }, 3903 { { STATE_CCOUNT }, 'i' } 3904}; 3905 3906static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { 3907 { { 6 /* art */ }, 'i' } 3908}; 3909 3910static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { 3911 { { STATE_PSEXCM }, 'i' }, 3912 { { STATE_PSRING }, 'i' }, 3913 { { STATE_XTSYNC }, 'o' }, 3914 { { STATE_CCOUNT }, 'o' } 3915}; 3916 3917static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { 3918 { { 6 /* art */ }, 'm' } 3919}; 3920 3921static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { 3922 { { STATE_PSEXCM }, 'i' }, 3923 { { STATE_PSRING }, 'i' }, 3924 { { STATE_XTSYNC }, 'o' }, 3925 { { STATE_CCOUNT }, 'm' } 3926}; 3927 3928static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { 3929 { { 6 /* art */ }, 'o' } 3930}; 3931 3932static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { 3933 { { STATE_PSEXCM }, 'i' }, 3934 { { STATE_PSRING }, 'i' }, 3935 { { STATE_CCOMPARE0 }, 'i' } 3936}; 3937 3938static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { 3939 { { 6 /* art */ }, 'i' } 3940}; 3941 3942static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { 3943 { { STATE_PSEXCM }, 'i' }, 3944 { { STATE_PSRING }, 'i' }, 3945 { { STATE_CCOMPARE0 }, 'o' }, 3946 { { STATE_INTERRUPT }, 'm' } 3947}; 3948 3949static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { 3950 { { 6 /* art */ }, 'm' } 3951}; 3952 3953static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { 3954 { { STATE_PSEXCM }, 'i' }, 3955 { { STATE_PSRING }, 'i' }, 3956 { { STATE_CCOMPARE0 }, 'm' }, 3957 { { STATE_INTERRUPT }, 'm' } 3958}; 3959 3960static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { 3961 { { 6 /* art */ }, 'o' } 3962}; 3963 3964static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { 3965 { { STATE_PSEXCM }, 'i' }, 3966 { { STATE_PSRING }, 'i' }, 3967 { { STATE_CCOMPARE1 }, 'i' } 3968}; 3969 3970static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { 3971 { { 6 /* art */ }, 'i' } 3972}; 3973 3974static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { 3975 { { STATE_PSEXCM }, 'i' }, 3976 { { STATE_PSRING }, 'i' }, 3977 { { STATE_CCOMPARE1 }, 'o' }, 3978 { { STATE_INTERRUPT }, 'm' } 3979}; 3980 3981static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { 3982 { { 6 /* art */ }, 'm' } 3983}; 3984 3985static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { 3986 { { STATE_PSEXCM }, 'i' }, 3987 { { STATE_PSRING }, 'i' }, 3988 { { STATE_CCOMPARE1 }, 'm' }, 3989 { { STATE_INTERRUPT }, 'm' } 3990}; 3991 3992static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { 3993 { { 6 /* art */ }, 'o' } 3994}; 3995 3996static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { 3997 { { STATE_PSEXCM }, 'i' }, 3998 { { STATE_PSRING }, 'i' }, 3999 { { STATE_CCOMPARE2 }, 'i' } 4000}; 4001 4002static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { 4003 { { 6 /* art */ }, 'i' } 4004}; 4005 4006static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { 4007 { { STATE_PSEXCM }, 'i' }, 4008 { { STATE_PSRING }, 'i' }, 4009 { { STATE_CCOMPARE2 }, 'o' }, 4010 { { STATE_INTERRUPT }, 'm' } 4011}; 4012 4013static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { 4014 { { 6 /* art */ }, 'm' } 4015}; 4016 4017static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { 4018 { { STATE_PSEXCM }, 'i' }, 4019 { { STATE_PSRING }, 'i' }, 4020 { { STATE_CCOMPARE2 }, 'm' }, 4021 { { STATE_INTERRUPT }, 'm' } 4022}; 4023 4024static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { 4025 { { 4 /* ars */ }, 'i' }, 4026 { { 21 /* uimm8x4 */ }, 'i' } 4027}; 4028 4029static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { 4030 { { 4 /* ars */ }, 'i' }, 4031 { { 21 /* uimm8x4 */ }, 'i' } 4032}; 4033 4034static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { 4035 { { STATE_PSEXCM }, 'i' }, 4036 { { STATE_PSRING }, 'i' } 4037}; 4038 4039static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { 4040 { { 6 /* art */ }, 'o' }, 4041 { { 4 /* ars */ }, 'i' } 4042}; 4043 4044static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { 4045 { { STATE_PSEXCM }, 'i' }, 4046 { { STATE_PSRING }, 'i' } 4047}; 4048 4049static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { 4050 { { 6 /* art */ }, 'i' }, 4051 { { 4 /* ars */ }, 'i' } 4052}; 4053 4054static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { 4055 { { STATE_PSEXCM }, 'i' }, 4056 { { STATE_PSRING }, 'i' } 4057}; 4058 4059static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { 4060 { { 4 /* ars */ }, 'i' }, 4061 { { 21 /* uimm8x4 */ }, 'i' } 4062}; 4063 4064static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { 4065 { { 4 /* ars */ }, 'i' }, 4066 { { 22 /* uimm4x16 */ }, 'i' } 4067}; 4068 4069static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { 4070 { { STATE_PSEXCM }, 'i' }, 4071 { { STATE_PSRING }, 'i' } 4072}; 4073 4074static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { 4075 { { 4 /* ars */ }, 'i' }, 4076 { { 21 /* uimm8x4 */ }, 'i' } 4077}; 4078 4079static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { 4080 { { STATE_PSEXCM }, 'i' }, 4081 { { STATE_PSRING }, 'i' } 4082}; 4083 4084static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { 4085 { { 4 /* ars */ }, 'i' }, 4086 { { 21 /* uimm8x4 */ }, 'i' } 4087}; 4088 4089static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { 4090 { { 6 /* art */ }, 'i' }, 4091 { { 4 /* ars */ }, 'i' } 4092}; 4093 4094static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { 4095 { { STATE_PSEXCM }, 'i' }, 4096 { { STATE_PSRING }, 'i' } 4097}; 4098 4099static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { 4100 { { 6 /* art */ }, 'o' }, 4101 { { 4 /* ars */ }, 'i' } 4102}; 4103 4104static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { 4105 { { STATE_PSEXCM }, 'i' }, 4106 { { STATE_PSRING }, 'i' } 4107}; 4108 4109static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = { 4110 { { 6 /* art */ }, 'i' } 4111}; 4112 4113static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = { 4114 { { STATE_PSEXCM }, 'i' }, 4115 { { STATE_PSRING }, 'i' }, 4116 { { STATE_PTBASE }, 'o' }, 4117 { { STATE_XTSYNC }, 'o' } 4118}; 4119 4120static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = { 4121 { { 6 /* art */ }, 'o' } 4122}; 4123 4124static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = { 4125 { { STATE_PSEXCM }, 'i' }, 4126 { { STATE_PSRING }, 'i' }, 4127 { { STATE_PTBASE }, 'i' }, 4128 { { STATE_EXCVADDR }, 'i' } 4129}; 4130 4131static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = { 4132 { { 6 /* art */ }, 'm' } 4133}; 4134 4135static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = { 4136 { { STATE_PSEXCM }, 'i' }, 4137 { { STATE_PSRING }, 'i' }, 4138 { { STATE_PTBASE }, 'm' }, 4139 { { STATE_EXCVADDR }, 'i' }, 4140 { { STATE_XTSYNC }, 'o' } 4141}; 4142 4143static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = { 4144 { { 6 /* art */ }, 'o' } 4145}; 4146 4147static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = { 4148 { { STATE_PSEXCM }, 'i' }, 4149 { { STATE_PSRING }, 'i' }, 4150 { { STATE_ASID3 }, 'i' }, 4151 { { STATE_ASID2 }, 'i' }, 4152 { { STATE_ASID1 }, 'i' } 4153}; 4154 4155static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = { 4156 { { 6 /* art */ }, 'i' } 4157}; 4158 4159static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = { 4160 { { STATE_XTSYNC }, 'o' }, 4161 { { STATE_PSEXCM }, 'i' }, 4162 { { STATE_PSRING }, 'i' }, 4163 { { STATE_ASID3 }, 'o' }, 4164 { { STATE_ASID2 }, 'o' }, 4165 { { STATE_ASID1 }, 'o' } 4166}; 4167 4168static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = { 4169 { { 6 /* art */ }, 'm' } 4170}; 4171 4172static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = { 4173 { { STATE_XTSYNC }, 'o' }, 4174 { { STATE_PSEXCM }, 'i' }, 4175 { { STATE_PSRING }, 'i' }, 4176 { { STATE_ASID3 }, 'm' }, 4177 { { STATE_ASID2 }, 'm' }, 4178 { { STATE_ASID1 }, 'm' } 4179}; 4180 4181static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = { 4182 { { 6 /* art */ }, 'o' } 4183}; 4184 4185static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = { 4186 { { STATE_PSEXCM }, 'i' }, 4187 { { STATE_PSRING }, 'i' }, 4188 { { STATE_INSTPGSZID4 }, 'i' } 4189}; 4190 4191static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = { 4192 { { 6 /* art */ }, 'i' } 4193}; 4194 4195static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = { 4196 { { STATE_XTSYNC }, 'o' }, 4197 { { STATE_PSEXCM }, 'i' }, 4198 { { STATE_PSRING }, 'i' }, 4199 { { STATE_INSTPGSZID4 }, 'o' } 4200}; 4201 4202static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = { 4203 { { 6 /* art */ }, 'm' } 4204}; 4205 4206static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = { 4207 { { STATE_XTSYNC }, 'o' }, 4208 { { STATE_PSEXCM }, 'i' }, 4209 { { STATE_PSRING }, 'i' }, 4210 { { STATE_INSTPGSZID4 }, 'm' } 4211}; 4212 4213static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = { 4214 { { 6 /* art */ }, 'o' } 4215}; 4216 4217static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = { 4218 { { STATE_PSEXCM }, 'i' }, 4219 { { STATE_PSRING }, 'i' }, 4220 { { STATE_DATAPGSZID4 }, 'i' } 4221}; 4222 4223static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = { 4224 { { 6 /* art */ }, 'i' } 4225}; 4226 4227static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = { 4228 { { STATE_XTSYNC }, 'o' }, 4229 { { STATE_PSEXCM }, 'i' }, 4230 { { STATE_PSRING }, 'i' }, 4231 { { STATE_DATAPGSZID4 }, 'o' } 4232}; 4233 4234static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = { 4235 { { 6 /* art */ }, 'm' } 4236}; 4237 4238static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = { 4239 { { STATE_XTSYNC }, 'o' }, 4240 { { STATE_PSEXCM }, 'i' }, 4241 { { STATE_PSRING }, 'i' }, 4242 { { STATE_DATAPGSZID4 }, 'm' } 4243}; 4244 4245static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { 4246 { { 4 /* ars */ }, 'i' } 4247}; 4248 4249static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { 4250 { { STATE_PSEXCM }, 'i' }, 4251 { { STATE_PSRING }, 'i' }, 4252 { { STATE_XTSYNC }, 'o' } 4253}; 4254 4255static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { 4256 { { 6 /* art */ }, 'o' }, 4257 { { 4 /* ars */ }, 'i' } 4258}; 4259 4260static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = { 4261 { { STATE_PSEXCM }, 'i' }, 4262 { { STATE_PSRING }, 'i' } 4263}; 4264 4265static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { 4266 { { 6 /* art */ }, 'i' }, 4267 { { 4 /* ars */ }, 'i' } 4268}; 4269 4270static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { 4271 { { STATE_PSEXCM }, 'i' }, 4272 { { STATE_PSRING }, 'i' }, 4273 { { STATE_XTSYNC }, 'o' } 4274}; 4275 4276static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { 4277 { { 4 /* ars */ }, 'i' } 4278}; 4279 4280static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = { 4281 { { STATE_PSEXCM }, 'i' }, 4282 { { STATE_PSRING }, 'i' } 4283}; 4284 4285static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { 4286 { { 6 /* art */ }, 'o' }, 4287 { { 4 /* ars */ }, 'i' } 4288}; 4289 4290static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = { 4291 { { STATE_PSEXCM }, 'i' }, 4292 { { STATE_PSRING }, 'i' } 4293}; 4294 4295static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { 4296 { { 6 /* art */ }, 'i' }, 4297 { { 4 /* ars */ }, 'i' } 4298}; 4299 4300static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = { 4301 { { STATE_PSEXCM }, 'i' }, 4302 { { STATE_PSRING }, 'i' } 4303}; 4304 4305static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = { 4306 { { STATE_PTBASE }, 'i' }, 4307 { { STATE_EXCVADDR }, 'i' } 4308}; 4309 4310static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = { 4311 { { STATE_EXCVADDR }, 'i' } 4312}; 4313 4314static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = { 4315 { { STATE_EXCVADDR }, 'i' } 4316}; 4317 4318static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { 4319 { { 6 /* art */ }, 'o' }, 4320 { { 4 /* ars */ }, 'i' } 4321}; 4322 4323static xtensa_iclass_internal iclasses[] = { 4324 { 0, 0 /* xt_iclass_excw */, 4325 0, 0, 0, 0 }, 4326 { 0, 0 /* xt_iclass_rfe */, 4327 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, 4328 { 0, 0 /* xt_iclass_rfde */, 4329 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, 4330 { 0, 0 /* xt_iclass_syscall */, 4331 0, 0, 0, 0 }, 4332 { 0, 0 /* xt_iclass_simcall */, 4333 0, 0, 0, 0 }, 4334 { 2, Iclass_xt_iclass_call12_args, 4335 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, 4336 { 2, Iclass_xt_iclass_call8_args, 4337 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, 4338 { 2, Iclass_xt_iclass_call4_args, 4339 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, 4340 { 2, Iclass_xt_iclass_callx12_args, 4341 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, 4342 { 2, Iclass_xt_iclass_callx8_args, 4343 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, 4344 { 2, Iclass_xt_iclass_callx4_args, 4345 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, 4346 { 3, Iclass_xt_iclass_entry_args, 4347 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, 4348 { 2, Iclass_xt_iclass_movsp_args, 4349 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, 4350 { 1, Iclass_xt_iclass_rotw_args, 4351 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, 4352 { 1, Iclass_xt_iclass_retw_args, 4353 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, 4354 { 0, 0 /* xt_iclass_rfwou */, 4355 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, 4356 { 3, Iclass_xt_iclass_l32e_args, 4357 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, 4358 { 3, Iclass_xt_iclass_s32e_args, 4359 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, 4360 { 1, Iclass_xt_iclass_rsr_windowbase_args, 4361 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, 4362 { 1, Iclass_xt_iclass_wsr_windowbase_args, 4363 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, 4364 { 1, Iclass_xt_iclass_xsr_windowbase_args, 4365 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, 4366 { 1, Iclass_xt_iclass_rsr_windowstart_args, 4367 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, 4368 { 1, Iclass_xt_iclass_wsr_windowstart_args, 4369 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, 4370 { 1, Iclass_xt_iclass_xsr_windowstart_args, 4371 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, 4372 { 3, Iclass_xt_iclass_add_n_args, 4373 0, 0, 0, 0 }, 4374 { 3, Iclass_xt_iclass_addi_n_args, 4375 0, 0, 0, 0 }, 4376 { 2, Iclass_xt_iclass_bz6_args, 4377 0, 0, 0, 0 }, 4378 { 0, 0 /* xt_iclass_ill_n */, 4379 0, 0, 0, 0 }, 4380 { 3, Iclass_xt_iclass_loadi4_args, 4381 0, 0, 0, 0 }, 4382 { 2, Iclass_xt_iclass_mov_n_args, 4383 0, 0, 0, 0 }, 4384 { 2, Iclass_xt_iclass_movi_n_args, 4385 0, 0, 0, 0 }, 4386 { 0, 0 /* xt_iclass_nopn */, 4387 0, 0, 0, 0 }, 4388 { 1, Iclass_xt_iclass_retn_args, 4389 0, 0, 0, 0 }, 4390 { 3, Iclass_xt_iclass_storei4_args, 4391 0, 0, 0, 0 }, 4392 { 3, Iclass_xt_iclass_addi_args, 4393 0, 0, 0, 0 }, 4394 { 3, Iclass_xt_iclass_addmi_args, 4395 0, 0, 0, 0 }, 4396 { 3, Iclass_xt_iclass_addsub_args, 4397 0, 0, 0, 0 }, 4398 { 3, Iclass_xt_iclass_bit_args, 4399 0, 0, 0, 0 }, 4400 { 3, Iclass_xt_iclass_bsi8_args, 4401 0, 0, 0, 0 }, 4402 { 3, Iclass_xt_iclass_bsi8b_args, 4403 0, 0, 0, 0 }, 4404 { 3, Iclass_xt_iclass_bsi8u_args, 4405 0, 0, 0, 0 }, 4406 { 3, Iclass_xt_iclass_bst8_args, 4407 0, 0, 0, 0 }, 4408 { 2, Iclass_xt_iclass_bsz12_args, 4409 0, 0, 0, 0 }, 4410 { 2, Iclass_xt_iclass_call0_args, 4411 0, 0, 0, 0 }, 4412 { 2, Iclass_xt_iclass_callx0_args, 4413 0, 0, 0, 0 }, 4414 { 4, Iclass_xt_iclass_exti_args, 4415 0, 0, 0, 0 }, 4416 { 0, 0 /* xt_iclass_ill */, 4417 0, 0, 0, 0 }, 4418 { 1, Iclass_xt_iclass_jump_args, 4419 0, 0, 0, 0 }, 4420 { 1, Iclass_xt_iclass_jumpx_args, 4421 0, 0, 0, 0 }, 4422 { 3, Iclass_xt_iclass_l16ui_args, 4423 0, 0, 0, 0 }, 4424 { 3, Iclass_xt_iclass_l16si_args, 4425 0, 0, 0, 0 }, 4426 { 3, Iclass_xt_iclass_l32i_args, 4427 0, 0, 0, 0 }, 4428 { 2, Iclass_xt_iclass_l32r_args, 4429 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 }, 4430 { 3, Iclass_xt_iclass_l8i_args, 4431 0, 0, 0, 0 }, 4432 { 2, Iclass_xt_iclass_loop_args, 4433 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, 4434 { 2, Iclass_xt_iclass_loopz_args, 4435 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, 4436 { 2, Iclass_xt_iclass_movi_args, 4437 0, 0, 0, 0 }, 4438 { 3, Iclass_xt_iclass_movz_args, 4439 0, 0, 0, 0 }, 4440 { 2, Iclass_xt_iclass_neg_args, 4441 0, 0, 0, 0 }, 4442 { 0, 0 /* xt_iclass_nop */, 4443 0, 0, 0, 0 }, 4444 { 1, Iclass_xt_iclass_return_args, 4445 0, 0, 0, 0 }, 4446 { 3, Iclass_xt_iclass_s16i_args, 4447 0, 0, 0, 0 }, 4448 { 3, Iclass_xt_iclass_s32i_args, 4449 0, 0, 0, 0 }, 4450 { 3, Iclass_xt_iclass_s8i_args, 4451 0, 0, 0, 0 }, 4452 { 1, Iclass_xt_iclass_sar_args, 4453 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, 4454 { 1, Iclass_xt_iclass_sari_args, 4455 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, 4456 { 2, Iclass_xt_iclass_shifts_args, 4457 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, 4458 { 3, Iclass_xt_iclass_shiftst_args, 4459 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, 4460 { 2, Iclass_xt_iclass_shiftt_args, 4461 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, 4462 { 3, Iclass_xt_iclass_slli_args, 4463 0, 0, 0, 0 }, 4464 { 3, Iclass_xt_iclass_srai_args, 4465 0, 0, 0, 0 }, 4466 { 3, Iclass_xt_iclass_srli_args, 4467 0, 0, 0, 0 }, 4468 { 0, 0 /* xt_iclass_memw */, 4469 0, 0, 0, 0 }, 4470 { 0, 0 /* xt_iclass_extw */, 4471 0, 0, 0, 0 }, 4472 { 0, 0 /* xt_iclass_isync */, 4473 0, 0, 0, 0 }, 4474 { 0, 0 /* xt_iclass_sync */, 4475 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, 4476 { 2, Iclass_xt_iclass_rsil_args, 4477 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, 4478 { 1, Iclass_xt_iclass_rsr_lend_args, 4479 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, 4480 { 1, Iclass_xt_iclass_wsr_lend_args, 4481 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, 4482 { 1, Iclass_xt_iclass_xsr_lend_args, 4483 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, 4484 { 1, Iclass_xt_iclass_rsr_lcount_args, 4485 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, 4486 { 1, Iclass_xt_iclass_wsr_lcount_args, 4487 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, 4488 { 1, Iclass_xt_iclass_xsr_lcount_args, 4489 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, 4490 { 1, Iclass_xt_iclass_rsr_lbeg_args, 4491 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, 4492 { 1, Iclass_xt_iclass_wsr_lbeg_args, 4493 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, 4494 { 1, Iclass_xt_iclass_xsr_lbeg_args, 4495 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, 4496 { 1, Iclass_xt_iclass_rsr_sar_args, 4497 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, 4498 { 1, Iclass_xt_iclass_wsr_sar_args, 4499 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, 4500 { 1, Iclass_xt_iclass_xsr_sar_args, 4501 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, 4502 { 1, Iclass_xt_iclass_rsr_litbase_args, 4503 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 }, 4504 { 1, Iclass_xt_iclass_wsr_litbase_args, 4505 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 }, 4506 { 1, Iclass_xt_iclass_xsr_litbase_args, 4507 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 }, 4508 { 1, Iclass_xt_iclass_rsr_176_args, 4509 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 }, 4510 { 1, Iclass_xt_iclass_rsr_208_args, 4511 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 }, 4512 { 1, Iclass_xt_iclass_rsr_ps_args, 4513 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, 4514 { 1, Iclass_xt_iclass_wsr_ps_args, 4515 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, 4516 { 1, Iclass_xt_iclass_xsr_ps_args, 4517 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, 4518 { 1, Iclass_xt_iclass_rsr_epc1_args, 4519 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, 4520 { 1, Iclass_xt_iclass_wsr_epc1_args, 4521 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, 4522 { 1, Iclass_xt_iclass_xsr_epc1_args, 4523 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, 4524 { 1, Iclass_xt_iclass_rsr_excsave1_args, 4525 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, 4526 { 1, Iclass_xt_iclass_wsr_excsave1_args, 4527 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, 4528 { 1, Iclass_xt_iclass_xsr_excsave1_args, 4529 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, 4530 { 1, Iclass_xt_iclass_rsr_epc2_args, 4531 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, 4532 { 1, Iclass_xt_iclass_wsr_epc2_args, 4533 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, 4534 { 1, Iclass_xt_iclass_xsr_epc2_args, 4535 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, 4536 { 1, Iclass_xt_iclass_rsr_excsave2_args, 4537 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, 4538 { 1, Iclass_xt_iclass_wsr_excsave2_args, 4539 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, 4540 { 1, Iclass_xt_iclass_xsr_excsave2_args, 4541 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, 4542 { 1, Iclass_xt_iclass_rsr_epc3_args, 4543 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, 4544 { 1, Iclass_xt_iclass_wsr_epc3_args, 4545 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, 4546 { 1, Iclass_xt_iclass_xsr_epc3_args, 4547 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, 4548 { 1, Iclass_xt_iclass_rsr_excsave3_args, 4549 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, 4550 { 1, Iclass_xt_iclass_wsr_excsave3_args, 4551 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, 4552 { 1, Iclass_xt_iclass_xsr_excsave3_args, 4553 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, 4554 { 1, Iclass_xt_iclass_rsr_epc4_args, 4555 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, 4556 { 1, Iclass_xt_iclass_wsr_epc4_args, 4557 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, 4558 { 1, Iclass_xt_iclass_xsr_epc4_args, 4559 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, 4560 { 1, Iclass_xt_iclass_rsr_excsave4_args, 4561 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, 4562 { 1, Iclass_xt_iclass_wsr_excsave4_args, 4563 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, 4564 { 1, Iclass_xt_iclass_xsr_excsave4_args, 4565 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, 4566 { 1, Iclass_xt_iclass_rsr_eps2_args, 4567 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, 4568 { 1, Iclass_xt_iclass_wsr_eps2_args, 4569 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, 4570 { 1, Iclass_xt_iclass_xsr_eps2_args, 4571 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, 4572 { 1, Iclass_xt_iclass_rsr_eps3_args, 4573 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, 4574 { 1, Iclass_xt_iclass_wsr_eps3_args, 4575 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, 4576 { 1, Iclass_xt_iclass_xsr_eps3_args, 4577 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, 4578 { 1, Iclass_xt_iclass_rsr_eps4_args, 4579 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, 4580 { 1, Iclass_xt_iclass_wsr_eps4_args, 4581 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, 4582 { 1, Iclass_xt_iclass_xsr_eps4_args, 4583 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, 4584 { 1, Iclass_xt_iclass_rsr_excvaddr_args, 4585 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, 4586 { 1, Iclass_xt_iclass_wsr_excvaddr_args, 4587 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, 4588 { 1, Iclass_xt_iclass_xsr_excvaddr_args, 4589 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, 4590 { 1, Iclass_xt_iclass_rsr_depc_args, 4591 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, 4592 { 1, Iclass_xt_iclass_wsr_depc_args, 4593 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, 4594 { 1, Iclass_xt_iclass_xsr_depc_args, 4595 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, 4596 { 1, Iclass_xt_iclass_rsr_exccause_args, 4597 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, 4598 { 1, Iclass_xt_iclass_wsr_exccause_args, 4599 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, 4600 { 1, Iclass_xt_iclass_xsr_exccause_args, 4601 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, 4602 { 1, Iclass_xt_iclass_rsr_misc0_args, 4603 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, 4604 { 1, Iclass_xt_iclass_wsr_misc0_args, 4605 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, 4606 { 1, Iclass_xt_iclass_xsr_misc0_args, 4607 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, 4608 { 1, Iclass_xt_iclass_rsr_misc1_args, 4609 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, 4610 { 1, Iclass_xt_iclass_wsr_misc1_args, 4611 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, 4612 { 1, Iclass_xt_iclass_xsr_misc1_args, 4613 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, 4614 { 1, Iclass_xt_iclass_rsr_prid_args, 4615 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, 4616 { 1, Iclass_xt_iclass_rfi_args, 4617 15, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, 4618 { 1, Iclass_xt_iclass_wait_args, 4619 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, 4620 { 1, Iclass_xt_iclass_rsr_interrupt_args, 4621 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, 4622 { 1, Iclass_xt_iclass_wsr_intset_args, 4623 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, 4624 { 1, Iclass_xt_iclass_wsr_intclear_args, 4625 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, 4626 { 1, Iclass_xt_iclass_rsr_intenable_args, 4627 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, 4628 { 1, Iclass_xt_iclass_wsr_intenable_args, 4629 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, 4630 { 1, Iclass_xt_iclass_xsr_intenable_args, 4631 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, 4632 { 2, Iclass_xt_iclass_break_args, 4633 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, 4634 { 1, Iclass_xt_iclass_break_n_args, 4635 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, 4636 { 1, Iclass_xt_iclass_rsr_dbreaka0_args, 4637 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, 4638 { 1, Iclass_xt_iclass_wsr_dbreaka0_args, 4639 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, 4640 { 1, Iclass_xt_iclass_xsr_dbreaka0_args, 4641 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, 4642 { 1, Iclass_xt_iclass_rsr_dbreakc0_args, 4643 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, 4644 { 1, Iclass_xt_iclass_wsr_dbreakc0_args, 4645 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, 4646 { 1, Iclass_xt_iclass_xsr_dbreakc0_args, 4647 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, 4648 { 1, Iclass_xt_iclass_rsr_dbreaka1_args, 4649 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, 4650 { 1, Iclass_xt_iclass_wsr_dbreaka1_args, 4651 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, 4652 { 1, Iclass_xt_iclass_xsr_dbreaka1_args, 4653 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, 4654 { 1, Iclass_xt_iclass_rsr_dbreakc1_args, 4655 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, 4656 { 1, Iclass_xt_iclass_wsr_dbreakc1_args, 4657 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, 4658 { 1, Iclass_xt_iclass_xsr_dbreakc1_args, 4659 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, 4660 { 1, Iclass_xt_iclass_rsr_ibreaka0_args, 4661 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, 4662 { 1, Iclass_xt_iclass_wsr_ibreaka0_args, 4663 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, 4664 { 1, Iclass_xt_iclass_xsr_ibreaka0_args, 4665 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, 4666 { 1, Iclass_xt_iclass_rsr_ibreaka1_args, 4667 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, 4668 { 1, Iclass_xt_iclass_wsr_ibreaka1_args, 4669 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, 4670 { 1, Iclass_xt_iclass_xsr_ibreaka1_args, 4671 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, 4672 { 1, Iclass_xt_iclass_rsr_ibreakenable_args, 4673 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, 4674 { 1, Iclass_xt_iclass_wsr_ibreakenable_args, 4675 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, 4676 { 1, Iclass_xt_iclass_xsr_ibreakenable_args, 4677 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, 4678 { 1, Iclass_xt_iclass_rsr_debugcause_args, 4679 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, 4680 { 1, Iclass_xt_iclass_wsr_debugcause_args, 4681 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, 4682 { 1, Iclass_xt_iclass_xsr_debugcause_args, 4683 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, 4684 { 1, Iclass_xt_iclass_rsr_icount_args, 4685 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, 4686 { 1, Iclass_xt_iclass_wsr_icount_args, 4687 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, 4688 { 1, Iclass_xt_iclass_xsr_icount_args, 4689 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, 4690 { 1, Iclass_xt_iclass_rsr_icountlevel_args, 4691 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, 4692 { 1, Iclass_xt_iclass_wsr_icountlevel_args, 4693 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, 4694 { 1, Iclass_xt_iclass_xsr_icountlevel_args, 4695 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, 4696 { 1, Iclass_xt_iclass_rsr_ddr_args, 4697 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, 4698 { 1, Iclass_xt_iclass_wsr_ddr_args, 4699 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, 4700 { 1, Iclass_xt_iclass_xsr_ddr_args, 4701 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, 4702 { 0, 0 /* xt_iclass_rfdo */, 4703 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, 4704 { 0, 0 /* xt_iclass_rfdd */, 4705 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, 4706 { 1, Iclass_xt_iclass_rsr_ccount_args, 4707 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, 4708 { 1, Iclass_xt_iclass_wsr_ccount_args, 4709 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, 4710 { 1, Iclass_xt_iclass_xsr_ccount_args, 4711 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, 4712 { 1, Iclass_xt_iclass_rsr_ccompare0_args, 4713 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, 4714 { 1, Iclass_xt_iclass_wsr_ccompare0_args, 4715 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, 4716 { 1, Iclass_xt_iclass_xsr_ccompare0_args, 4717 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, 4718 { 1, Iclass_xt_iclass_rsr_ccompare1_args, 4719 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, 4720 { 1, Iclass_xt_iclass_wsr_ccompare1_args, 4721 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, 4722 { 1, Iclass_xt_iclass_xsr_ccompare1_args, 4723 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, 4724 { 1, Iclass_xt_iclass_rsr_ccompare2_args, 4725 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, 4726 { 1, Iclass_xt_iclass_wsr_ccompare2_args, 4727 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, 4728 { 1, Iclass_xt_iclass_xsr_ccompare2_args, 4729 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, 4730 { 2, Iclass_xt_iclass_icache_args, 4731 0, 0, 0, 0 }, 4732 { 2, Iclass_xt_iclass_icache_inv_args, 4733 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, 4734 { 2, Iclass_xt_iclass_licx_args, 4735 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, 4736 { 2, Iclass_xt_iclass_sicx_args, 4737 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, 4738 { 2, Iclass_xt_iclass_dcache_args, 4739 0, 0, 0, 0 }, 4740 { 2, Iclass_xt_iclass_dcache_ind_args, 4741 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, 4742 { 2, Iclass_xt_iclass_dcache_inv_args, 4743 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, 4744 { 2, Iclass_xt_iclass_dpf_args, 4745 0, 0, 0, 0 }, 4746 { 2, Iclass_xt_iclass_sdct_args, 4747 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, 4748 { 2, Iclass_xt_iclass_ldct_args, 4749 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, 4750 { 1, Iclass_xt_iclass_wsr_ptevaddr_args, 4751 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 }, 4752 { 1, Iclass_xt_iclass_rsr_ptevaddr_args, 4753 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 }, 4754 { 1, Iclass_xt_iclass_xsr_ptevaddr_args, 4755 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 }, 4756 { 1, Iclass_xt_iclass_rsr_rasid_args, 4757 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 }, 4758 { 1, Iclass_xt_iclass_wsr_rasid_args, 4759 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 }, 4760 { 1, Iclass_xt_iclass_xsr_rasid_args, 4761 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 }, 4762 { 1, Iclass_xt_iclass_rsr_itlbcfg_args, 4763 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 }, 4764 { 1, Iclass_xt_iclass_wsr_itlbcfg_args, 4765 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 }, 4766 { 1, Iclass_xt_iclass_xsr_itlbcfg_args, 4767 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 }, 4768 { 1, Iclass_xt_iclass_rsr_dtlbcfg_args, 4769 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 }, 4770 { 1, Iclass_xt_iclass_wsr_dtlbcfg_args, 4771 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 }, 4772 { 1, Iclass_xt_iclass_xsr_dtlbcfg_args, 4773 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 }, 4774 { 1, Iclass_xt_iclass_idtlb_args, 4775 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, 4776 { 2, Iclass_xt_iclass_rdtlb_args, 4777 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 }, 4778 { 2, Iclass_xt_iclass_wdtlb_args, 4779 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, 4780 { 1, Iclass_xt_iclass_iitlb_args, 4781 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 }, 4782 { 2, Iclass_xt_iclass_ritlb_args, 4783 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 }, 4784 { 2, Iclass_xt_iclass_witlb_args, 4785 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 }, 4786 { 0, 0 /* xt_iclass_ldpte */, 4787 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 }, 4788 { 0, 0 /* xt_iclass_hwwitlba */, 4789 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 }, 4790 { 0, 0 /* xt_iclass_hwwdtlba */, 4791 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 }, 4792 { 2, Iclass_xt_iclass_nsa_args, 4793 0, 0, 0, 0 } 4794}; 4795 4796 4797/* Opcode encodings. */ 4798 4799static void 4800Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) 4801{ 4802 slotbuf[0] = 0x80200; 4803} 4804 4805static void 4806Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) 4807{ 4808 slotbuf[0] = 0x300; 4809} 4810 4811static void 4812Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) 4813{ 4814 slotbuf[0] = 0x2300; 4815} 4816 4817static void 4818Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) 4819{ 4820 slotbuf[0] = 0x500; 4821} 4822 4823static void 4824Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) 4825{ 4826 slotbuf[0] = 0x1500; 4827} 4828 4829static void 4830Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) 4831{ 4832 slotbuf[0] = 0x5c0000; 4833} 4834 4835static void 4836Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) 4837{ 4838 slotbuf[0] = 0x580000; 4839} 4840 4841static void 4842Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) 4843{ 4844 slotbuf[0] = 0x540000; 4845} 4846 4847static void 4848Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) 4849{ 4850 slotbuf[0] = 0xf0000; 4851} 4852 4853static void 4854Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) 4855{ 4856 slotbuf[0] = 0xb0000; 4857} 4858 4859static void 4860Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) 4861{ 4862 slotbuf[0] = 0x70000; 4863} 4864 4865static void 4866Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) 4867{ 4868 slotbuf[0] = 0x6c0000; 4869} 4870 4871static void 4872Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) 4873{ 4874 slotbuf[0] = 0x100; 4875} 4876 4877static void 4878Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) 4879{ 4880 slotbuf[0] = 0x804; 4881} 4882 4883static void 4884Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) 4885{ 4886 slotbuf[0] = 0x60000; 4887} 4888 4889static void 4890Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 4891{ 4892 slotbuf[0] = 0xd10f; 4893} 4894 4895static void 4896Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) 4897{ 4898 slotbuf[0] = 0x4300; 4899} 4900 4901static void 4902Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) 4903{ 4904 slotbuf[0] = 0x5300; 4905} 4906 4907static void 4908Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) 4909{ 4910 slotbuf[0] = 0x90; 4911} 4912 4913static void 4914Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) 4915{ 4916 slotbuf[0] = 0x94; 4917} 4918 4919static void 4920Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 4921{ 4922 slotbuf[0] = 0x4830; 4923} 4924 4925static void 4926Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 4927{ 4928 slotbuf[0] = 0x4831; 4929} 4930 4931static void 4932Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 4933{ 4934 slotbuf[0] = 0x4816; 4935} 4936 4937static void 4938Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) 4939{ 4940 slotbuf[0] = 0x4930; 4941} 4942 4943static void 4944Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) 4945{ 4946 slotbuf[0] = 0x4931; 4947} 4948 4949static void 4950Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) 4951{ 4952 slotbuf[0] = 0x4916; 4953} 4954 4955static void 4956Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) 4957{ 4958 slotbuf[0] = 0xa000; 4959} 4960 4961static void 4962Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) 4963{ 4964 slotbuf[0] = 0xb000; 4965} 4966 4967static void 4968Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 4969{ 4970 slotbuf[0] = 0xc800; 4971} 4972 4973static void 4974Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 4975{ 4976 slotbuf[0] = 0xcc00; 4977} 4978 4979static void 4980Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 4981{ 4982 slotbuf[0] = 0xd60f; 4983} 4984 4985static void 4986Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) 4987{ 4988 slotbuf[0] = 0x8000; 4989} 4990 4991static void 4992Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 4993{ 4994 slotbuf[0] = 0xd000; 4995} 4996 4997static void 4998Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 4999{ 5000 slotbuf[0] = 0xc000; 5001} 5002 5003static void 5004Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 5005{ 5006 slotbuf[0] = 0xd30f; 5007} 5008 5009static void 5010Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 5011{ 5012 slotbuf[0] = 0xd00f; 5013} 5014 5015static void 5016Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) 5017{ 5018 slotbuf[0] = 0x9000; 5019} 5020 5021static void 5022Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) 5023{ 5024 slotbuf[0] = 0x200c00; 5025} 5026 5027static void 5028Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) 5029{ 5030 slotbuf[0] = 0x200d00; 5031} 5032 5033static void 5034Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) 5035{ 5036 slotbuf[0] = 0x8; 5037} 5038 5039static void 5040Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) 5041{ 5042 slotbuf[0] = 0xc; 5043} 5044 5045static void 5046Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) 5047{ 5048 slotbuf[0] = 0x9; 5049} 5050 5051static void 5052Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) 5053{ 5054 slotbuf[0] = 0xa; 5055} 5056 5057static void 5058Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) 5059{ 5060 slotbuf[0] = 0xb; 5061} 5062 5063static void 5064Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) 5065{ 5066 slotbuf[0] = 0xd; 5067} 5068 5069static void 5070Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) 5071{ 5072 slotbuf[0] = 0xe; 5073} 5074 5075static void 5076Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) 5077{ 5078 slotbuf[0] = 0xf; 5079} 5080 5081static void 5082Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) 5083{ 5084 slotbuf[0] = 0x1; 5085} 5086 5087static void 5088Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) 5089{ 5090 slotbuf[0] = 0x2; 5091} 5092 5093static void 5094Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) 5095{ 5096 slotbuf[0] = 0x3; 5097} 5098 5099static void 5100Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) 5101{ 5102 slotbuf[0] = 0x680000; 5103} 5104 5105static void 5106Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) 5107{ 5108 slotbuf[0] = 0x690000; 5109} 5110 5111static void 5112Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) 5113{ 5114 slotbuf[0] = 0x6b0000; 5115} 5116 5117static void 5118Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) 5119{ 5120 slotbuf[0] = 0x6a0000; 5121} 5122 5123static void 5124Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) 5125{ 5126 slotbuf[0] = 0x700600; 5127} 5128 5129static void 5130Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) 5131{ 5132 slotbuf[0] = 0x700e00; 5133} 5134 5135static void 5136Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) 5137{ 5138 slotbuf[0] = 0x6f0000; 5139} 5140 5141static void 5142Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) 5143{ 5144 slotbuf[0] = 0x6e0000; 5145} 5146 5147static void 5148Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) 5149{ 5150 slotbuf[0] = 0x700100; 5151} 5152 5153static void 5154Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) 5155{ 5156 slotbuf[0] = 0x700900; 5157} 5158 5159static void 5160Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) 5161{ 5162 slotbuf[0] = 0x700a00; 5163} 5164 5165static void 5166Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) 5167{ 5168 slotbuf[0] = 0x700200; 5169} 5170 5171static void 5172Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) 5173{ 5174 slotbuf[0] = 0x700b00; 5175} 5176 5177static void 5178Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) 5179{ 5180 slotbuf[0] = 0x700300; 5181} 5182 5183static void 5184Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) 5185{ 5186 slotbuf[0] = 0x700800; 5187} 5188 5189static void 5190Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) 5191{ 5192 slotbuf[0] = 0x700000; 5193} 5194 5195static void 5196Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) 5197{ 5198 slotbuf[0] = 0x700400; 5199} 5200 5201static void 5202Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) 5203{ 5204 slotbuf[0] = 0x700c00; 5205} 5206 5207static void 5208Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) 5209{ 5210 slotbuf[0] = 0x700500; 5211} 5212 5213static void 5214Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) 5215{ 5216 slotbuf[0] = 0x700d00; 5217} 5218 5219static void 5220Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) 5221{ 5222 slotbuf[0] = 0x640000; 5223} 5224 5225static void 5226Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) 5227{ 5228 slotbuf[0] = 0x650000; 5229} 5230 5231static void 5232Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) 5233{ 5234 slotbuf[0] = 0x670000; 5235} 5236 5237static void 5238Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) 5239{ 5240 slotbuf[0] = 0x660000; 5241} 5242 5243static void 5244Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) 5245{ 5246 slotbuf[0] = 0x500000; 5247} 5248 5249static void 5250Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) 5251{ 5252 slotbuf[0] = 0x30000; 5253} 5254 5255static void 5256Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) 5257{ 5258 slotbuf[0] = 0x40; 5259} 5260 5261static void 5262Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) 5263{ 5264 slotbuf[0] = 0; 5265} 5266 5267static void 5268Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) 5269{ 5270 slotbuf[0] = 0x600000; 5271} 5272 5273static void 5274Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) 5275{ 5276 slotbuf[0] = 0xa0000; 5277} 5278 5279static void 5280Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) 5281{ 5282 slotbuf[0] = 0x200100; 5283} 5284 5285static void 5286Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) 5287{ 5288 slotbuf[0] = 0x200900; 5289} 5290 5291static void 5292Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) 5293{ 5294 slotbuf[0] = 0x200200; 5295} 5296 5297static void 5298Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) 5299{ 5300 slotbuf[0] = 0x100000; 5301} 5302 5303static void 5304Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) 5305{ 5306 slotbuf[0] = 0x200000; 5307} 5308 5309static void 5310Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) 5311{ 5312 slotbuf[0] = 0x6d0800; 5313} 5314 5315static void 5316Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) 5317{ 5318 slotbuf[0] = 0x6d0900; 5319} 5320 5321static void 5322Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) 5323{ 5324 slotbuf[0] = 0x6d0a00; 5325} 5326 5327static void 5328Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) 5329{ 5330 slotbuf[0] = 0x200a00; 5331} 5332 5333static void 5334Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) 5335{ 5336 slotbuf[0] = 0x38; 5337} 5338 5339static void 5340Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) 5341{ 5342 slotbuf[0] = 0x39; 5343} 5344 5345static void 5346Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) 5347{ 5348 slotbuf[0] = 0x3a; 5349} 5350 5351static void 5352Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) 5353{ 5354 slotbuf[0] = 0x3b; 5355} 5356 5357static void 5358Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) 5359{ 5360 slotbuf[0] = 0x6; 5361} 5362 5363static void 5364Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) 5365{ 5366 slotbuf[0] = 0x1006; 5367} 5368 5369static void 5370Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) 5371{ 5372 slotbuf[0] = 0xf0200; 5373} 5374 5375static void 5376Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) 5377{ 5378 slotbuf[0] = 0x20000; 5379} 5380 5381static void 5382Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) 5383{ 5384 slotbuf[0] = 0x200500; 5385} 5386 5387static void 5388Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) 5389{ 5390 slotbuf[0] = 0x200600; 5391} 5392 5393static void 5394Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) 5395{ 5396 slotbuf[0] = 0x200400; 5397} 5398 5399static void 5400Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) 5401{ 5402 slotbuf[0] = 0x4; 5403} 5404 5405static void 5406Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) 5407{ 5408 slotbuf[0] = 0x104; 5409} 5410 5411static void 5412Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) 5413{ 5414 slotbuf[0] = 0x204; 5415} 5416 5417static void 5418Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) 5419{ 5420 slotbuf[0] = 0x304; 5421} 5422 5423static void 5424Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) 5425{ 5426 slotbuf[0] = 0x404; 5427} 5428 5429static void 5430Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) 5431{ 5432 slotbuf[0] = 0x1a; 5433} 5434 5435static void 5436Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) 5437{ 5438 slotbuf[0] = 0x18; 5439} 5440 5441static void 5442Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) 5443{ 5444 slotbuf[0] = 0x19; 5445} 5446 5447static void 5448Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) 5449{ 5450 slotbuf[0] = 0x1b; 5451} 5452 5453static void 5454Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) 5455{ 5456 slotbuf[0] = 0x10; 5457} 5458 5459static void 5460Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) 5461{ 5462 slotbuf[0] = 0x12; 5463} 5464 5465static void 5466Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) 5467{ 5468 slotbuf[0] = 0x14; 5469} 5470 5471static void 5472Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) 5473{ 5474 slotbuf[0] = 0xc0200; 5475} 5476 5477static void 5478Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) 5479{ 5480 slotbuf[0] = 0xd0200; 5481} 5482 5483static void 5484Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) 5485{ 5486 slotbuf[0] = 0x200; 5487} 5488 5489static void 5490Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) 5491{ 5492 slotbuf[0] = 0x10200; 5493} 5494 5495static void 5496Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) 5497{ 5498 slotbuf[0] = 0x20200; 5499} 5500 5501static void 5502Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) 5503{ 5504 slotbuf[0] = 0x30200; 5505} 5506 5507static void 5508Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) 5509{ 5510 slotbuf[0] = 0x600; 5511} 5512 5513static void 5514Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) 5515{ 5516 slotbuf[0] = 0x130; 5517} 5518 5519static void 5520Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) 5521{ 5522 slotbuf[0] = 0x131; 5523} 5524 5525static void 5526Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) 5527{ 5528 slotbuf[0] = 0x116; 5529} 5530 5531static void 5532Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) 5533{ 5534 slotbuf[0] = 0x230; 5535} 5536 5537static void 5538Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) 5539{ 5540 slotbuf[0] = 0x231; 5541} 5542 5543static void 5544Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) 5545{ 5546 slotbuf[0] = 0x216; 5547} 5548 5549static void 5550Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) 5551{ 5552 slotbuf[0] = 0x30; 5553} 5554 5555static void 5556Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) 5557{ 5558 slotbuf[0] = 0x31; 5559} 5560 5561static void 5562Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) 5563{ 5564 slotbuf[0] = 0x16; 5565} 5566 5567static void 5568Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) 5569{ 5570 slotbuf[0] = 0x330; 5571} 5572 5573static void 5574Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) 5575{ 5576 slotbuf[0] = 0x331; 5577} 5578 5579static void 5580Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) 5581{ 5582 slotbuf[0] = 0x316; 5583} 5584 5585static void 5586Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 5587{ 5588 slotbuf[0] = 0x530; 5589} 5590 5591static void 5592Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 5593{ 5594 slotbuf[0] = 0x531; 5595} 5596 5597static void 5598Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 5599{ 5600 slotbuf[0] = 0x516; 5601} 5602 5603static void 5604Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) 5605{ 5606 slotbuf[0] = 0xb030; 5607} 5608 5609static void 5610Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf) 5611{ 5612 slotbuf[0] = 0xd030; 5613} 5614 5615static void 5616Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) 5617{ 5618 slotbuf[0] = 0xe630; 5619} 5620 5621static void 5622Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) 5623{ 5624 slotbuf[0] = 0xe631; 5625} 5626 5627static void 5628Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) 5629{ 5630 slotbuf[0] = 0xe616; 5631} 5632 5633static void 5634Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 5635{ 5636 slotbuf[0] = 0xb130; 5637} 5638 5639static void 5640Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 5641{ 5642 slotbuf[0] = 0xb131; 5643} 5644 5645static void 5646Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 5647{ 5648 slotbuf[0] = 0xb116; 5649} 5650 5651static void 5652Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) 5653{ 5654 slotbuf[0] = 0xd130; 5655} 5656 5657static void 5658Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) 5659{ 5660 slotbuf[0] = 0xd131; 5661} 5662 5663static void 5664Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) 5665{ 5666 slotbuf[0] = 0xd116; 5667} 5668 5669static void 5670Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) 5671{ 5672 slotbuf[0] = 0xb230; 5673} 5674 5675static void 5676Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) 5677{ 5678 slotbuf[0] = 0xb231; 5679} 5680 5681static void 5682Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) 5683{ 5684 slotbuf[0] = 0xb216; 5685} 5686 5687static void 5688Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) 5689{ 5690 slotbuf[0] = 0xd230; 5691} 5692 5693static void 5694Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) 5695{ 5696 slotbuf[0] = 0xd231; 5697} 5698 5699static void 5700Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) 5701{ 5702 slotbuf[0] = 0xd216; 5703} 5704 5705static void 5706Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) 5707{ 5708 slotbuf[0] = 0xb330; 5709} 5710 5711static void 5712Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) 5713{ 5714 slotbuf[0] = 0xb331; 5715} 5716 5717static void 5718Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) 5719{ 5720 slotbuf[0] = 0xb316; 5721} 5722 5723static void 5724Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) 5725{ 5726 slotbuf[0] = 0xd330; 5727} 5728 5729static void 5730Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) 5731{ 5732 slotbuf[0] = 0xd331; 5733} 5734 5735static void 5736Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) 5737{ 5738 slotbuf[0] = 0xd316; 5739} 5740 5741static void 5742Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) 5743{ 5744 slotbuf[0] = 0xb430; 5745} 5746 5747static void 5748Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) 5749{ 5750 slotbuf[0] = 0xb431; 5751} 5752 5753static void 5754Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) 5755{ 5756 slotbuf[0] = 0xb416; 5757} 5758 5759static void 5760Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) 5761{ 5762 slotbuf[0] = 0xd430; 5763} 5764 5765static void 5766Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) 5767{ 5768 slotbuf[0] = 0xd431; 5769} 5770 5771static void 5772Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) 5773{ 5774 slotbuf[0] = 0xd416; 5775} 5776 5777static void 5778Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) 5779{ 5780 slotbuf[0] = 0xc230; 5781} 5782 5783static void 5784Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) 5785{ 5786 slotbuf[0] = 0xc231; 5787} 5788 5789static void 5790Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) 5791{ 5792 slotbuf[0] = 0xc216; 5793} 5794 5795static void 5796Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) 5797{ 5798 slotbuf[0] = 0xc330; 5799} 5800 5801static void 5802Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) 5803{ 5804 slotbuf[0] = 0xc331; 5805} 5806 5807static void 5808Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) 5809{ 5810 slotbuf[0] = 0xc316; 5811} 5812 5813static void 5814Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) 5815{ 5816 slotbuf[0] = 0xc430; 5817} 5818 5819static void 5820Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) 5821{ 5822 slotbuf[0] = 0xc431; 5823} 5824 5825static void 5826Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) 5827{ 5828 slotbuf[0] = 0xc416; 5829} 5830 5831static void 5832Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 5833{ 5834 slotbuf[0] = 0xee30; 5835} 5836 5837static void 5838Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 5839{ 5840 slotbuf[0] = 0xee31; 5841} 5842 5843static void 5844Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 5845{ 5846 slotbuf[0] = 0xee16; 5847} 5848 5849static void 5850Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) 5851{ 5852 slotbuf[0] = 0xc030; 5853} 5854 5855static void 5856Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) 5857{ 5858 slotbuf[0] = 0xc031; 5859} 5860 5861static void 5862Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) 5863{ 5864 slotbuf[0] = 0xc016; 5865} 5866 5867static void 5868Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) 5869{ 5870 slotbuf[0] = 0xe830; 5871} 5872 5873static void 5874Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) 5875{ 5876 slotbuf[0] = 0xe831; 5877} 5878 5879static void 5880Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) 5881{ 5882 slotbuf[0] = 0xe816; 5883} 5884 5885static void 5886Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 5887{ 5888 slotbuf[0] = 0xf430; 5889} 5890 5891static void 5892Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 5893{ 5894 slotbuf[0] = 0xf431; 5895} 5896 5897static void 5898Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 5899{ 5900 slotbuf[0] = 0xf416; 5901} 5902 5903static void 5904Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 5905{ 5906 slotbuf[0] = 0xf530; 5907} 5908 5909static void 5910Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 5911{ 5912 slotbuf[0] = 0xf531; 5913} 5914 5915static void 5916Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 5917{ 5918 slotbuf[0] = 0xf516; 5919} 5920 5921static void 5922Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) 5923{ 5924 slotbuf[0] = 0xeb30; 5925} 5926 5927static void 5928Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) 5929{ 5930 slotbuf[0] = 0x10300; 5931} 5932 5933static void 5934Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) 5935{ 5936 slotbuf[0] = 0x700; 5937} 5938 5939static void 5940Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) 5941{ 5942 slotbuf[0] = 0xe230; 5943} 5944 5945static void 5946Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) 5947{ 5948 slotbuf[0] = 0xe231; 5949} 5950 5951static void 5952Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) 5953{ 5954 slotbuf[0] = 0xe331; 5955} 5956 5957static void 5958Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 5959{ 5960 slotbuf[0] = 0xe430; 5961} 5962 5963static void 5964Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 5965{ 5966 slotbuf[0] = 0xe431; 5967} 5968 5969static void 5970Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 5971{ 5972 slotbuf[0] = 0xe416; 5973} 5974 5975static void 5976Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) 5977{ 5978 slotbuf[0] = 0x400; 5979} 5980 5981static void 5982Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 5983{ 5984 slotbuf[0] = 0xd20f; 5985} 5986 5987static void 5988Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 5989{ 5990 slotbuf[0] = 0x9030; 5991} 5992 5993static void 5994Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 5995{ 5996 slotbuf[0] = 0x9031; 5997} 5998 5999static void 6000Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6001{ 6002 slotbuf[0] = 0x9016; 6003} 6004 6005static void 6006Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6007{ 6008 slotbuf[0] = 0xa030; 6009} 6010 6011static void 6012Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6013{ 6014 slotbuf[0] = 0xa031; 6015} 6016 6017static void 6018Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6019{ 6020 slotbuf[0] = 0xa016; 6021} 6022 6023static void 6024Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 6025{ 6026 slotbuf[0] = 0x9130; 6027} 6028 6029static void 6030Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 6031{ 6032 slotbuf[0] = 0x9131; 6033} 6034 6035static void 6036Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 6037{ 6038 slotbuf[0] = 0x9116; 6039} 6040 6041static void 6042Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 6043{ 6044 slotbuf[0] = 0xa130; 6045} 6046 6047static void 6048Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 6049{ 6050 slotbuf[0] = 0xa131; 6051} 6052 6053static void 6054Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 6055{ 6056 slotbuf[0] = 0xa116; 6057} 6058 6059static void 6060Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6061{ 6062 slotbuf[0] = 0x8030; 6063} 6064 6065static void 6066Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6067{ 6068 slotbuf[0] = 0x8031; 6069} 6070 6071static void 6072Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6073{ 6074 slotbuf[0] = 0x8016; 6075} 6076 6077static void 6078Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 6079{ 6080 slotbuf[0] = 0x8130; 6081} 6082 6083static void 6084Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 6085{ 6086 slotbuf[0] = 0x8131; 6087} 6088 6089static void 6090Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 6091{ 6092 slotbuf[0] = 0x8116; 6093} 6094 6095static void 6096Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 6097{ 6098 slotbuf[0] = 0x6030; 6099} 6100 6101static void 6102Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 6103{ 6104 slotbuf[0] = 0x6031; 6105} 6106 6107static void 6108Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 6109{ 6110 slotbuf[0] = 0x6016; 6111} 6112 6113static void 6114Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) 6115{ 6116 slotbuf[0] = 0xe930; 6117} 6118 6119static void 6120Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) 6121{ 6122 slotbuf[0] = 0xe931; 6123} 6124 6125static void 6126Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) 6127{ 6128 slotbuf[0] = 0xe916; 6129} 6130 6131static void 6132Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) 6133{ 6134 slotbuf[0] = 0xec30; 6135} 6136 6137static void 6138Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) 6139{ 6140 slotbuf[0] = 0xec31; 6141} 6142 6143static void 6144Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) 6145{ 6146 slotbuf[0] = 0xec16; 6147} 6148 6149static void 6150Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) 6151{ 6152 slotbuf[0] = 0xed30; 6153} 6154 6155static void 6156Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) 6157{ 6158 slotbuf[0] = 0xed31; 6159} 6160 6161static void 6162Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) 6163{ 6164 slotbuf[0] = 0xed16; 6165} 6166 6167static void 6168Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 6169{ 6170 slotbuf[0] = 0x6830; 6171} 6172 6173static void 6174Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 6175{ 6176 slotbuf[0] = 0x6831; 6177} 6178 6179static void 6180Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 6181{ 6182 slotbuf[0] = 0x6816; 6183} 6184 6185static void 6186Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) 6187{ 6188 slotbuf[0] = 0xe1f; 6189} 6190 6191static void 6192Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) 6193{ 6194 slotbuf[0] = 0x10e1f; 6195} 6196 6197static void 6198Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) 6199{ 6200 slotbuf[0] = 0xea30; 6201} 6202 6203static void 6204Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) 6205{ 6206 slotbuf[0] = 0xea31; 6207} 6208 6209static void 6210Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) 6211{ 6212 slotbuf[0] = 0xea16; 6213} 6214 6215static void 6216Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6217{ 6218 slotbuf[0] = 0xf030; 6219} 6220 6221static void 6222Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6223{ 6224 slotbuf[0] = 0xf031; 6225} 6226 6227static void 6228Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6229{ 6230 slotbuf[0] = 0xf016; 6231} 6232 6233static void 6234Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 6235{ 6236 slotbuf[0] = 0xf130; 6237} 6238 6239static void 6240Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 6241{ 6242 slotbuf[0] = 0xf131; 6243} 6244 6245static void 6246Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 6247{ 6248 slotbuf[0] = 0xf116; 6249} 6250 6251static void 6252Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) 6253{ 6254 slotbuf[0] = 0xf230; 6255} 6256 6257static void 6258Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) 6259{ 6260 slotbuf[0] = 0xf231; 6261} 6262 6263static void 6264Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) 6265{ 6266 slotbuf[0] = 0xf216; 6267} 6268 6269static void 6270Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) 6271{ 6272 slotbuf[0] = 0x2c0700; 6273} 6274 6275static void 6276Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) 6277{ 6278 slotbuf[0] = 0x2e0700; 6279} 6280 6281static void 6282Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) 6283{ 6284 slotbuf[0] = 0x2f0700; 6285} 6286 6287static void 6288Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) 6289{ 6290 slotbuf[0] = 0x1f; 6291} 6292 6293static void 6294Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) 6295{ 6296 slotbuf[0] = 0x21f; 6297} 6298 6299static void 6300Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) 6301{ 6302 slotbuf[0] = 0x11f; 6303} 6304 6305static void 6306Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) 6307{ 6308 slotbuf[0] = 0x31f; 6309} 6310 6311static void 6312Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) 6313{ 6314 slotbuf[0] = 0x240700; 6315} 6316 6317static void 6318Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) 6319{ 6320 slotbuf[0] = 0x250700; 6321} 6322 6323static void 6324Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) 6325{ 6326 slotbuf[0] = 0x280740; 6327} 6328 6329static void 6330Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) 6331{ 6332 slotbuf[0] = 0x280750; 6333} 6334 6335static void 6336Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) 6337{ 6338 slotbuf[0] = 0x260700; 6339} 6340 6341static void 6342Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) 6343{ 6344 slotbuf[0] = 0x270700; 6345} 6346 6347static void 6348Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) 6349{ 6350 slotbuf[0] = 0x200700; 6351} 6352 6353static void 6354Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) 6355{ 6356 slotbuf[0] = 0x210700; 6357} 6358 6359static void 6360Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) 6361{ 6362 slotbuf[0] = 0x220700; 6363} 6364 6365static void 6366Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) 6367{ 6368 slotbuf[0] = 0x230700; 6369} 6370 6371static void 6372Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) 6373{ 6374 slotbuf[0] = 0x91f; 6375} 6376 6377static void 6378Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) 6379{ 6380 slotbuf[0] = 0x81f; 6381} 6382 6383static void 6384Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 6385{ 6386 slotbuf[0] = 0x5331; 6387} 6388 6389static void 6390Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 6391{ 6392 slotbuf[0] = 0x5330; 6393} 6394 6395static void 6396Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 6397{ 6398 slotbuf[0] = 0x5316; 6399} 6400 6401static void 6402Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) 6403{ 6404 slotbuf[0] = 0x5a30; 6405} 6406 6407static void 6408Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) 6409{ 6410 slotbuf[0] = 0x5a31; 6411} 6412 6413static void 6414Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) 6415{ 6416 slotbuf[0] = 0x5a16; 6417} 6418 6419static void 6420Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 6421{ 6422 slotbuf[0] = 0x5b30; 6423} 6424 6425static void 6426Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 6427{ 6428 slotbuf[0] = 0x5b31; 6429} 6430 6431static void 6432Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 6433{ 6434 slotbuf[0] = 0x5b16; 6435} 6436 6437static void 6438Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 6439{ 6440 slotbuf[0] = 0x5c30; 6441} 6442 6443static void 6444Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 6445{ 6446 slotbuf[0] = 0x5c31; 6447} 6448 6449static void 6450Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 6451{ 6452 slotbuf[0] = 0x5c16; 6453} 6454 6455static void 6456Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 6457{ 6458 slotbuf[0] = 0xc05; 6459} 6460 6461static void 6462Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 6463{ 6464 slotbuf[0] = 0xd05; 6465} 6466 6467static void 6468Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6469{ 6470 slotbuf[0] = 0xb05; 6471} 6472 6473static void 6474Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) 6475{ 6476 slotbuf[0] = 0xf05; 6477} 6478 6479static void 6480Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 6481{ 6482 slotbuf[0] = 0xe05; 6483} 6484 6485static void 6486Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 6487{ 6488 slotbuf[0] = 0x405; 6489} 6490 6491static void 6492Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 6493{ 6494 slotbuf[0] = 0x505; 6495} 6496 6497static void 6498Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6499{ 6500 slotbuf[0] = 0x305; 6501} 6502 6503static void 6504Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) 6505{ 6506 slotbuf[0] = 0x705; 6507} 6508 6509static void 6510Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 6511{ 6512 slotbuf[0] = 0x605; 6513} 6514 6515static void 6516Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf) 6517{ 6518 slotbuf[0] = 0xf1f; 6519} 6520 6521static void 6522Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf) 6523{ 6524 slotbuf[0] = 0x105; 6525} 6526 6527static void 6528Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf) 6529{ 6530 slotbuf[0] = 0x905; 6531} 6532 6533static void 6534Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) 6535{ 6536 slotbuf[0] = 0xe04; 6537} 6538 6539static void 6540Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) 6541{ 6542 slotbuf[0] = 0xf04; 6543} 6544 6545static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { 6546 Opcode_excw_Slot_inst_encode, 0, 0 6547}; 6548 6549static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { 6550 Opcode_rfe_Slot_inst_encode, 0, 0 6551}; 6552 6553static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { 6554 Opcode_rfde_Slot_inst_encode, 0, 0 6555}; 6556 6557static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { 6558 Opcode_syscall_Slot_inst_encode, 0, 0 6559}; 6560 6561static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { 6562 Opcode_simcall_Slot_inst_encode, 0, 0 6563}; 6564 6565static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { 6566 Opcode_call12_Slot_inst_encode, 0, 0 6567}; 6568 6569static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { 6570 Opcode_call8_Slot_inst_encode, 0, 0 6571}; 6572 6573static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { 6574 Opcode_call4_Slot_inst_encode, 0, 0 6575}; 6576 6577static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { 6578 Opcode_callx12_Slot_inst_encode, 0, 0 6579}; 6580 6581static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { 6582 Opcode_callx8_Slot_inst_encode, 0, 0 6583}; 6584 6585static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { 6586 Opcode_callx4_Slot_inst_encode, 0, 0 6587}; 6588 6589static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { 6590 Opcode_entry_Slot_inst_encode, 0, 0 6591}; 6592 6593static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { 6594 Opcode_movsp_Slot_inst_encode, 0, 0 6595}; 6596 6597static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { 6598 Opcode_rotw_Slot_inst_encode, 0, 0 6599}; 6600 6601static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { 6602 Opcode_retw_Slot_inst_encode, 0, 0 6603}; 6604 6605static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { 6606 0, 0, Opcode_retw_n_Slot_inst16b_encode 6607}; 6608 6609static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { 6610 Opcode_rfwo_Slot_inst_encode, 0, 0 6611}; 6612 6613static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { 6614 Opcode_rfwu_Slot_inst_encode, 0, 0 6615}; 6616 6617static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { 6618 Opcode_l32e_Slot_inst_encode, 0, 0 6619}; 6620 6621static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { 6622 Opcode_s32e_Slot_inst_encode, 0, 0 6623}; 6624 6625static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { 6626 Opcode_rsr_windowbase_Slot_inst_encode, 0, 0 6627}; 6628 6629static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { 6630 Opcode_wsr_windowbase_Slot_inst_encode, 0, 0 6631}; 6632 6633static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { 6634 Opcode_xsr_windowbase_Slot_inst_encode, 0, 0 6635}; 6636 6637static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { 6638 Opcode_rsr_windowstart_Slot_inst_encode, 0, 0 6639}; 6640 6641static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { 6642 Opcode_wsr_windowstart_Slot_inst_encode, 0, 0 6643}; 6644 6645static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { 6646 Opcode_xsr_windowstart_Slot_inst_encode, 0, 0 6647}; 6648 6649static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { 6650 0, Opcode_add_n_Slot_inst16a_encode, 0 6651}; 6652 6653static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { 6654 0, Opcode_addi_n_Slot_inst16a_encode, 0 6655}; 6656 6657static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { 6658 0, 0, Opcode_beqz_n_Slot_inst16b_encode 6659}; 6660 6661static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { 6662 0, 0, Opcode_bnez_n_Slot_inst16b_encode 6663}; 6664 6665static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { 6666 0, 0, Opcode_ill_n_Slot_inst16b_encode 6667}; 6668 6669static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { 6670 0, Opcode_l32i_n_Slot_inst16a_encode, 0 6671}; 6672 6673static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { 6674 0, 0, Opcode_mov_n_Slot_inst16b_encode 6675}; 6676 6677static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { 6678 0, 0, Opcode_movi_n_Slot_inst16b_encode 6679}; 6680 6681static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { 6682 0, 0, Opcode_nop_n_Slot_inst16b_encode 6683}; 6684 6685static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { 6686 0, 0, Opcode_ret_n_Slot_inst16b_encode 6687}; 6688 6689static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { 6690 0, Opcode_s32i_n_Slot_inst16a_encode, 0 6691}; 6692 6693static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { 6694 Opcode_addi_Slot_inst_encode, 0, 0 6695}; 6696 6697static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { 6698 Opcode_addmi_Slot_inst_encode, 0, 0 6699}; 6700 6701static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { 6702 Opcode_add_Slot_inst_encode, 0, 0 6703}; 6704 6705static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { 6706 Opcode_sub_Slot_inst_encode, 0, 0 6707}; 6708 6709static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { 6710 Opcode_addx2_Slot_inst_encode, 0, 0 6711}; 6712 6713static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { 6714 Opcode_addx4_Slot_inst_encode, 0, 0 6715}; 6716 6717static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { 6718 Opcode_addx8_Slot_inst_encode, 0, 0 6719}; 6720 6721static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { 6722 Opcode_subx2_Slot_inst_encode, 0, 0 6723}; 6724 6725static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { 6726 Opcode_subx4_Slot_inst_encode, 0, 0 6727}; 6728 6729static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { 6730 Opcode_subx8_Slot_inst_encode, 0, 0 6731}; 6732 6733static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { 6734 Opcode_and_Slot_inst_encode, 0, 0 6735}; 6736 6737static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { 6738 Opcode_or_Slot_inst_encode, 0, 0 6739}; 6740 6741static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { 6742 Opcode_xor_Slot_inst_encode, 0, 0 6743}; 6744 6745static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { 6746 Opcode_beqi_Slot_inst_encode, 0, 0 6747}; 6748 6749static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { 6750 Opcode_bnei_Slot_inst_encode, 0, 0 6751}; 6752 6753static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { 6754 Opcode_bgei_Slot_inst_encode, 0, 0 6755}; 6756 6757static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { 6758 Opcode_blti_Slot_inst_encode, 0, 0 6759}; 6760 6761static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { 6762 Opcode_bbci_Slot_inst_encode, 0, 0 6763}; 6764 6765static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { 6766 Opcode_bbsi_Slot_inst_encode, 0, 0 6767}; 6768 6769static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { 6770 Opcode_bgeui_Slot_inst_encode, 0, 0 6771}; 6772 6773static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { 6774 Opcode_bltui_Slot_inst_encode, 0, 0 6775}; 6776 6777static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { 6778 Opcode_beq_Slot_inst_encode, 0, 0 6779}; 6780 6781static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { 6782 Opcode_bne_Slot_inst_encode, 0, 0 6783}; 6784 6785static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { 6786 Opcode_bge_Slot_inst_encode, 0, 0 6787}; 6788 6789static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { 6790 Opcode_blt_Slot_inst_encode, 0, 0 6791}; 6792 6793static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { 6794 Opcode_bgeu_Slot_inst_encode, 0, 0 6795}; 6796 6797static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { 6798 Opcode_bltu_Slot_inst_encode, 0, 0 6799}; 6800 6801static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { 6802 Opcode_bany_Slot_inst_encode, 0, 0 6803}; 6804 6805static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { 6806 Opcode_bnone_Slot_inst_encode, 0, 0 6807}; 6808 6809static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { 6810 Opcode_ball_Slot_inst_encode, 0, 0 6811}; 6812 6813static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { 6814 Opcode_bnall_Slot_inst_encode, 0, 0 6815}; 6816 6817static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { 6818 Opcode_bbc_Slot_inst_encode, 0, 0 6819}; 6820 6821static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { 6822 Opcode_bbs_Slot_inst_encode, 0, 0 6823}; 6824 6825static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { 6826 Opcode_beqz_Slot_inst_encode, 0, 0 6827}; 6828 6829static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { 6830 Opcode_bnez_Slot_inst_encode, 0, 0 6831}; 6832 6833static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { 6834 Opcode_bgez_Slot_inst_encode, 0, 0 6835}; 6836 6837static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { 6838 Opcode_bltz_Slot_inst_encode, 0, 0 6839}; 6840 6841static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { 6842 Opcode_call0_Slot_inst_encode, 0, 0 6843}; 6844 6845static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { 6846 Opcode_callx0_Slot_inst_encode, 0, 0 6847}; 6848 6849static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { 6850 Opcode_extui_Slot_inst_encode, 0, 0 6851}; 6852 6853static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { 6854 Opcode_ill_Slot_inst_encode, 0, 0 6855}; 6856 6857static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { 6858 Opcode_j_Slot_inst_encode, 0, 0 6859}; 6860 6861static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { 6862 Opcode_jx_Slot_inst_encode, 0, 0 6863}; 6864 6865static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { 6866 Opcode_l16ui_Slot_inst_encode, 0, 0 6867}; 6868 6869static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { 6870 Opcode_l16si_Slot_inst_encode, 0, 0 6871}; 6872 6873static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { 6874 Opcode_l32i_Slot_inst_encode, 0, 0 6875}; 6876 6877static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { 6878 Opcode_l32r_Slot_inst_encode, 0, 0 6879}; 6880 6881static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { 6882 Opcode_l8ui_Slot_inst_encode, 0, 0 6883}; 6884 6885static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { 6886 Opcode_loop_Slot_inst_encode, 0, 0 6887}; 6888 6889static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { 6890 Opcode_loopnez_Slot_inst_encode, 0, 0 6891}; 6892 6893static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { 6894 Opcode_loopgtz_Slot_inst_encode, 0, 0 6895}; 6896 6897static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { 6898 Opcode_movi_Slot_inst_encode, 0, 0 6899}; 6900 6901static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { 6902 Opcode_moveqz_Slot_inst_encode, 0, 0 6903}; 6904 6905static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { 6906 Opcode_movnez_Slot_inst_encode, 0, 0 6907}; 6908 6909static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { 6910 Opcode_movltz_Slot_inst_encode, 0, 0 6911}; 6912 6913static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { 6914 Opcode_movgez_Slot_inst_encode, 0, 0 6915}; 6916 6917static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { 6918 Opcode_neg_Slot_inst_encode, 0, 0 6919}; 6920 6921static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { 6922 Opcode_abs_Slot_inst_encode, 0, 0 6923}; 6924 6925static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { 6926 Opcode_nop_Slot_inst_encode, 0, 0 6927}; 6928 6929static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { 6930 Opcode_ret_Slot_inst_encode, 0, 0 6931}; 6932 6933static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { 6934 Opcode_s16i_Slot_inst_encode, 0, 0 6935}; 6936 6937static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { 6938 Opcode_s32i_Slot_inst_encode, 0, 0 6939}; 6940 6941static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { 6942 Opcode_s8i_Slot_inst_encode, 0, 0 6943}; 6944 6945static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { 6946 Opcode_ssr_Slot_inst_encode, 0, 0 6947}; 6948 6949static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { 6950 Opcode_ssl_Slot_inst_encode, 0, 0 6951}; 6952 6953static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { 6954 Opcode_ssa8l_Slot_inst_encode, 0, 0 6955}; 6956 6957static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { 6958 Opcode_ssa8b_Slot_inst_encode, 0, 0 6959}; 6960 6961static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { 6962 Opcode_ssai_Slot_inst_encode, 0, 0 6963}; 6964 6965static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { 6966 Opcode_sll_Slot_inst_encode, 0, 0 6967}; 6968 6969static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { 6970 Opcode_src_Slot_inst_encode, 0, 0 6971}; 6972 6973static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { 6974 Opcode_srl_Slot_inst_encode, 0, 0 6975}; 6976 6977static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { 6978 Opcode_sra_Slot_inst_encode, 0, 0 6979}; 6980 6981static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { 6982 Opcode_slli_Slot_inst_encode, 0, 0 6983}; 6984 6985static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { 6986 Opcode_srai_Slot_inst_encode, 0, 0 6987}; 6988 6989static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { 6990 Opcode_srli_Slot_inst_encode, 0, 0 6991}; 6992 6993static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { 6994 Opcode_memw_Slot_inst_encode, 0, 0 6995}; 6996 6997static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { 6998 Opcode_extw_Slot_inst_encode, 0, 0 6999}; 7000 7001static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { 7002 Opcode_isync_Slot_inst_encode, 0, 0 7003}; 7004 7005static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { 7006 Opcode_rsync_Slot_inst_encode, 0, 0 7007}; 7008 7009static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { 7010 Opcode_esync_Slot_inst_encode, 0, 0 7011}; 7012 7013static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { 7014 Opcode_dsync_Slot_inst_encode, 0, 0 7015}; 7016 7017static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { 7018 Opcode_rsil_Slot_inst_encode, 0, 0 7019}; 7020 7021static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { 7022 Opcode_rsr_lend_Slot_inst_encode, 0, 0 7023}; 7024 7025static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { 7026 Opcode_wsr_lend_Slot_inst_encode, 0, 0 7027}; 7028 7029static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { 7030 Opcode_xsr_lend_Slot_inst_encode, 0, 0 7031}; 7032 7033static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { 7034 Opcode_rsr_lcount_Slot_inst_encode, 0, 0 7035}; 7036 7037static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { 7038 Opcode_wsr_lcount_Slot_inst_encode, 0, 0 7039}; 7040 7041static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { 7042 Opcode_xsr_lcount_Slot_inst_encode, 0, 0 7043}; 7044 7045static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { 7046 Opcode_rsr_lbeg_Slot_inst_encode, 0, 0 7047}; 7048 7049static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { 7050 Opcode_wsr_lbeg_Slot_inst_encode, 0, 0 7051}; 7052 7053static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { 7054 Opcode_xsr_lbeg_Slot_inst_encode, 0, 0 7055}; 7056 7057static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { 7058 Opcode_rsr_sar_Slot_inst_encode, 0, 0 7059}; 7060 7061static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { 7062 Opcode_wsr_sar_Slot_inst_encode, 0, 0 7063}; 7064 7065static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { 7066 Opcode_xsr_sar_Slot_inst_encode, 0, 0 7067}; 7068 7069static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { 7070 Opcode_rsr_litbase_Slot_inst_encode, 0, 0 7071}; 7072 7073static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { 7074 Opcode_wsr_litbase_Slot_inst_encode, 0, 0 7075}; 7076 7077static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { 7078 Opcode_xsr_litbase_Slot_inst_encode, 0, 0 7079}; 7080 7081static xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = { 7082 Opcode_rsr_176_Slot_inst_encode, 0, 0 7083}; 7084 7085static xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = { 7086 Opcode_rsr_208_Slot_inst_encode, 0, 0 7087}; 7088 7089static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { 7090 Opcode_rsr_ps_Slot_inst_encode, 0, 0 7091}; 7092 7093static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { 7094 Opcode_wsr_ps_Slot_inst_encode, 0, 0 7095}; 7096 7097static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { 7098 Opcode_xsr_ps_Slot_inst_encode, 0, 0 7099}; 7100 7101static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { 7102 Opcode_rsr_epc1_Slot_inst_encode, 0, 0 7103}; 7104 7105static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { 7106 Opcode_wsr_epc1_Slot_inst_encode, 0, 0 7107}; 7108 7109static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { 7110 Opcode_xsr_epc1_Slot_inst_encode, 0, 0 7111}; 7112 7113static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { 7114 Opcode_rsr_excsave1_Slot_inst_encode, 0, 0 7115}; 7116 7117static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { 7118 Opcode_wsr_excsave1_Slot_inst_encode, 0, 0 7119}; 7120 7121static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { 7122 Opcode_xsr_excsave1_Slot_inst_encode, 0, 0 7123}; 7124 7125static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { 7126 Opcode_rsr_epc2_Slot_inst_encode, 0, 0 7127}; 7128 7129static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { 7130 Opcode_wsr_epc2_Slot_inst_encode, 0, 0 7131}; 7132 7133static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { 7134 Opcode_xsr_epc2_Slot_inst_encode, 0, 0 7135}; 7136 7137static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { 7138 Opcode_rsr_excsave2_Slot_inst_encode, 0, 0 7139}; 7140 7141static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { 7142 Opcode_wsr_excsave2_Slot_inst_encode, 0, 0 7143}; 7144 7145static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { 7146 Opcode_xsr_excsave2_Slot_inst_encode, 0, 0 7147}; 7148 7149static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { 7150 Opcode_rsr_epc3_Slot_inst_encode, 0, 0 7151}; 7152 7153static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { 7154 Opcode_wsr_epc3_Slot_inst_encode, 0, 0 7155}; 7156 7157static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { 7158 Opcode_xsr_epc3_Slot_inst_encode, 0, 0 7159}; 7160 7161static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { 7162 Opcode_rsr_excsave3_Slot_inst_encode, 0, 0 7163}; 7164 7165static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { 7166 Opcode_wsr_excsave3_Slot_inst_encode, 0, 0 7167}; 7168 7169static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { 7170 Opcode_xsr_excsave3_Slot_inst_encode, 0, 0 7171}; 7172 7173static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { 7174 Opcode_rsr_epc4_Slot_inst_encode, 0, 0 7175}; 7176 7177static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { 7178 Opcode_wsr_epc4_Slot_inst_encode, 0, 0 7179}; 7180 7181static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { 7182 Opcode_xsr_epc4_Slot_inst_encode, 0, 0 7183}; 7184 7185static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { 7186 Opcode_rsr_excsave4_Slot_inst_encode, 0, 0 7187}; 7188 7189static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { 7190 Opcode_wsr_excsave4_Slot_inst_encode, 0, 0 7191}; 7192 7193static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { 7194 Opcode_xsr_excsave4_Slot_inst_encode, 0, 0 7195}; 7196 7197static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { 7198 Opcode_rsr_eps2_Slot_inst_encode, 0, 0 7199}; 7200 7201static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { 7202 Opcode_wsr_eps2_Slot_inst_encode, 0, 0 7203}; 7204 7205static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { 7206 Opcode_xsr_eps2_Slot_inst_encode, 0, 0 7207}; 7208 7209static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { 7210 Opcode_rsr_eps3_Slot_inst_encode, 0, 0 7211}; 7212 7213static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { 7214 Opcode_wsr_eps3_Slot_inst_encode, 0, 0 7215}; 7216 7217static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { 7218 Opcode_xsr_eps3_Slot_inst_encode, 0, 0 7219}; 7220 7221static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { 7222 Opcode_rsr_eps4_Slot_inst_encode, 0, 0 7223}; 7224 7225static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { 7226 Opcode_wsr_eps4_Slot_inst_encode, 0, 0 7227}; 7228 7229static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { 7230 Opcode_xsr_eps4_Slot_inst_encode, 0, 0 7231}; 7232 7233static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { 7234 Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0 7235}; 7236 7237static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { 7238 Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0 7239}; 7240 7241static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { 7242 Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0 7243}; 7244 7245static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { 7246 Opcode_rsr_depc_Slot_inst_encode, 0, 0 7247}; 7248 7249static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { 7250 Opcode_wsr_depc_Slot_inst_encode, 0, 0 7251}; 7252 7253static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { 7254 Opcode_xsr_depc_Slot_inst_encode, 0, 0 7255}; 7256 7257static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { 7258 Opcode_rsr_exccause_Slot_inst_encode, 0, 0 7259}; 7260 7261static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { 7262 Opcode_wsr_exccause_Slot_inst_encode, 0, 0 7263}; 7264 7265static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { 7266 Opcode_xsr_exccause_Slot_inst_encode, 0, 0 7267}; 7268 7269static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { 7270 Opcode_rsr_misc0_Slot_inst_encode, 0, 0 7271}; 7272 7273static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { 7274 Opcode_wsr_misc0_Slot_inst_encode, 0, 0 7275}; 7276 7277static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { 7278 Opcode_xsr_misc0_Slot_inst_encode, 0, 0 7279}; 7280 7281static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { 7282 Opcode_rsr_misc1_Slot_inst_encode, 0, 0 7283}; 7284 7285static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { 7286 Opcode_wsr_misc1_Slot_inst_encode, 0, 0 7287}; 7288 7289static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { 7290 Opcode_xsr_misc1_Slot_inst_encode, 0, 0 7291}; 7292 7293static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { 7294 Opcode_rsr_prid_Slot_inst_encode, 0, 0 7295}; 7296 7297static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { 7298 Opcode_rfi_Slot_inst_encode, 0, 0 7299}; 7300 7301static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { 7302 Opcode_waiti_Slot_inst_encode, 0, 0 7303}; 7304 7305static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { 7306 Opcode_rsr_interrupt_Slot_inst_encode, 0, 0 7307}; 7308 7309static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { 7310 Opcode_wsr_intset_Slot_inst_encode, 0, 0 7311}; 7312 7313static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { 7314 Opcode_wsr_intclear_Slot_inst_encode, 0, 0 7315}; 7316 7317static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { 7318 Opcode_rsr_intenable_Slot_inst_encode, 0, 0 7319}; 7320 7321static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { 7322 Opcode_wsr_intenable_Slot_inst_encode, 0, 0 7323}; 7324 7325static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { 7326 Opcode_xsr_intenable_Slot_inst_encode, 0, 0 7327}; 7328 7329static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { 7330 Opcode_break_Slot_inst_encode, 0, 0 7331}; 7332 7333static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { 7334 0, 0, Opcode_break_n_Slot_inst16b_encode 7335}; 7336 7337static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { 7338 Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0 7339}; 7340 7341static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { 7342 Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0 7343}; 7344 7345static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { 7346 Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0 7347}; 7348 7349static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { 7350 Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0 7351}; 7352 7353static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { 7354 Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0 7355}; 7356 7357static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { 7358 Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0 7359}; 7360 7361static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { 7362 Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0 7363}; 7364 7365static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { 7366 Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0 7367}; 7368 7369static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { 7370 Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0 7371}; 7372 7373static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { 7374 Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0 7375}; 7376 7377static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { 7378 Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0 7379}; 7380 7381static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { 7382 Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0 7383}; 7384 7385static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { 7386 Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0 7387}; 7388 7389static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { 7390 Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0 7391}; 7392 7393static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { 7394 Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0 7395}; 7396 7397static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { 7398 Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0 7399}; 7400 7401static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { 7402 Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0 7403}; 7404 7405static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { 7406 Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0 7407}; 7408 7409static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { 7410 Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0 7411}; 7412 7413static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { 7414 Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0 7415}; 7416 7417static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { 7418 Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0 7419}; 7420 7421static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { 7422 Opcode_rsr_debugcause_Slot_inst_encode, 0, 0 7423}; 7424 7425static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { 7426 Opcode_wsr_debugcause_Slot_inst_encode, 0, 0 7427}; 7428 7429static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { 7430 Opcode_xsr_debugcause_Slot_inst_encode, 0, 0 7431}; 7432 7433static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { 7434 Opcode_rsr_icount_Slot_inst_encode, 0, 0 7435}; 7436 7437static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { 7438 Opcode_wsr_icount_Slot_inst_encode, 0, 0 7439}; 7440 7441static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { 7442 Opcode_xsr_icount_Slot_inst_encode, 0, 0 7443}; 7444 7445static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { 7446 Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0 7447}; 7448 7449static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { 7450 Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0 7451}; 7452 7453static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { 7454 Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0 7455}; 7456 7457static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { 7458 Opcode_rsr_ddr_Slot_inst_encode, 0, 0 7459}; 7460 7461static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { 7462 Opcode_wsr_ddr_Slot_inst_encode, 0, 0 7463}; 7464 7465static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { 7466 Opcode_xsr_ddr_Slot_inst_encode, 0, 0 7467}; 7468 7469static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { 7470 Opcode_rfdo_Slot_inst_encode, 0, 0 7471}; 7472 7473static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { 7474 Opcode_rfdd_Slot_inst_encode, 0, 0 7475}; 7476 7477static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { 7478 Opcode_rsr_ccount_Slot_inst_encode, 0, 0 7479}; 7480 7481static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { 7482 Opcode_wsr_ccount_Slot_inst_encode, 0, 0 7483}; 7484 7485static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { 7486 Opcode_xsr_ccount_Slot_inst_encode, 0, 0 7487}; 7488 7489static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { 7490 Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0 7491}; 7492 7493static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { 7494 Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0 7495}; 7496 7497static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { 7498 Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0 7499}; 7500 7501static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { 7502 Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0 7503}; 7504 7505static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { 7506 Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0 7507}; 7508 7509static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { 7510 Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0 7511}; 7512 7513static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { 7514 Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0 7515}; 7516 7517static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { 7518 Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0 7519}; 7520 7521static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { 7522 Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0 7523}; 7524 7525static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { 7526 Opcode_ipf_Slot_inst_encode, 0, 0 7527}; 7528 7529static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { 7530 Opcode_ihi_Slot_inst_encode, 0, 0 7531}; 7532 7533static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { 7534 Opcode_iii_Slot_inst_encode, 0, 0 7535}; 7536 7537static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { 7538 Opcode_lict_Slot_inst_encode, 0, 0 7539}; 7540 7541static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { 7542 Opcode_licw_Slot_inst_encode, 0, 0 7543}; 7544 7545static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { 7546 Opcode_sict_Slot_inst_encode, 0, 0 7547}; 7548 7549static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { 7550 Opcode_sicw_Slot_inst_encode, 0, 0 7551}; 7552 7553static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { 7554 Opcode_dhwb_Slot_inst_encode, 0, 0 7555}; 7556 7557static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { 7558 Opcode_dhwbi_Slot_inst_encode, 0, 0 7559}; 7560 7561static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { 7562 Opcode_diwb_Slot_inst_encode, 0, 0 7563}; 7564 7565static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { 7566 Opcode_diwbi_Slot_inst_encode, 0, 0 7567}; 7568 7569static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { 7570 Opcode_dhi_Slot_inst_encode, 0, 0 7571}; 7572 7573static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { 7574 Opcode_dii_Slot_inst_encode, 0, 0 7575}; 7576 7577static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { 7578 Opcode_dpfr_Slot_inst_encode, 0, 0 7579}; 7580 7581static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { 7582 Opcode_dpfw_Slot_inst_encode, 0, 0 7583}; 7584 7585static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { 7586 Opcode_dpfro_Slot_inst_encode, 0, 0 7587}; 7588 7589static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { 7590 Opcode_dpfwo_Slot_inst_encode, 0, 0 7591}; 7592 7593static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { 7594 Opcode_sdct_Slot_inst_encode, 0, 0 7595}; 7596 7597static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { 7598 Opcode_ldct_Slot_inst_encode, 0, 0 7599}; 7600 7601static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { 7602 Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0 7603}; 7604 7605static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { 7606 Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0 7607}; 7608 7609static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { 7610 Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0 7611}; 7612 7613static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { 7614 Opcode_rsr_rasid_Slot_inst_encode, 0, 0 7615}; 7616 7617static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { 7618 Opcode_wsr_rasid_Slot_inst_encode, 0, 0 7619}; 7620 7621static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { 7622 Opcode_xsr_rasid_Slot_inst_encode, 0, 0 7623}; 7624 7625static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { 7626 Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0 7627}; 7628 7629static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { 7630 Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0 7631}; 7632 7633static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { 7634 Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0 7635}; 7636 7637static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { 7638 Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0 7639}; 7640 7641static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { 7642 Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0 7643}; 7644 7645static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { 7646 Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0 7647}; 7648 7649static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { 7650 Opcode_idtlb_Slot_inst_encode, 0, 0 7651}; 7652 7653static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { 7654 Opcode_pdtlb_Slot_inst_encode, 0, 0 7655}; 7656 7657static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { 7658 Opcode_rdtlb0_Slot_inst_encode, 0, 0 7659}; 7660 7661static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { 7662 Opcode_rdtlb1_Slot_inst_encode, 0, 0 7663}; 7664 7665static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { 7666 Opcode_wdtlb_Slot_inst_encode, 0, 0 7667}; 7668 7669static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { 7670 Opcode_iitlb_Slot_inst_encode, 0, 0 7671}; 7672 7673static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { 7674 Opcode_pitlb_Slot_inst_encode, 0, 0 7675}; 7676 7677static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { 7678 Opcode_ritlb0_Slot_inst_encode, 0, 0 7679}; 7680 7681static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { 7682 Opcode_ritlb1_Slot_inst_encode, 0, 0 7683}; 7684 7685static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { 7686 Opcode_witlb_Slot_inst_encode, 0, 0 7687}; 7688 7689static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { 7690 Opcode_ldpte_Slot_inst_encode, 0, 0 7691}; 7692 7693static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { 7694 Opcode_hwwitlba_Slot_inst_encode, 0, 0 7695}; 7696 7697static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { 7698 Opcode_hwwdtlba_Slot_inst_encode, 0, 0 7699}; 7700 7701static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { 7702 Opcode_nsa_Slot_inst_encode, 0, 0 7703}; 7704 7705static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { 7706 Opcode_nsau_Slot_inst_encode, 0, 0 7707}; 7708 7709 7710/* Opcode table. */ 7711 7712static xtensa_opcode_internal opcodes[] = { 7713 { "excw", 0 /* xt_iclass_excw */, 7714 0, 7715 Opcode_excw_encode_fns, 0, 0 }, 7716 { "rfe", 1 /* xt_iclass_rfe */, 7717 XTENSA_OPCODE_IS_JUMP, 7718 Opcode_rfe_encode_fns, 0, 0 }, 7719 { "rfde", 2 /* xt_iclass_rfde */, 7720 XTENSA_OPCODE_IS_JUMP, 7721 Opcode_rfde_encode_fns, 0, 0 }, 7722 { "syscall", 3 /* xt_iclass_syscall */, 7723 0, 7724 Opcode_syscall_encode_fns, 0, 0 }, 7725 { "simcall", 4 /* xt_iclass_simcall */, 7726 0, 7727 Opcode_simcall_encode_fns, 0, 0 }, 7728 { "call12", 5 /* xt_iclass_call12 */, 7729 XTENSA_OPCODE_IS_CALL, 7730 Opcode_call12_encode_fns, 0, 0 }, 7731 { "call8", 6 /* xt_iclass_call8 */, 7732 XTENSA_OPCODE_IS_CALL, 7733 Opcode_call8_encode_fns, 0, 0 }, 7734 { "call4", 7 /* xt_iclass_call4 */, 7735 XTENSA_OPCODE_IS_CALL, 7736 Opcode_call4_encode_fns, 0, 0 }, 7737 { "callx12", 8 /* xt_iclass_callx12 */, 7738 XTENSA_OPCODE_IS_CALL, 7739 Opcode_callx12_encode_fns, 0, 0 }, 7740 { "callx8", 9 /* xt_iclass_callx8 */, 7741 XTENSA_OPCODE_IS_CALL, 7742 Opcode_callx8_encode_fns, 0, 0 }, 7743 { "callx4", 10 /* xt_iclass_callx4 */, 7744 XTENSA_OPCODE_IS_CALL, 7745 Opcode_callx4_encode_fns, 0, 0 }, 7746 { "entry", 11 /* xt_iclass_entry */, 7747 0, 7748 Opcode_entry_encode_fns, 0, 0 }, 7749 { "movsp", 12 /* xt_iclass_movsp */, 7750 0, 7751 Opcode_movsp_encode_fns, 0, 0 }, 7752 { "rotw", 13 /* xt_iclass_rotw */, 7753 0, 7754 Opcode_rotw_encode_fns, 0, 0 }, 7755 { "retw", 14 /* xt_iclass_retw */, 7756 XTENSA_OPCODE_IS_JUMP, 7757 Opcode_retw_encode_fns, 0, 0 }, 7758 { "retw.n", 14 /* xt_iclass_retw */, 7759 XTENSA_OPCODE_IS_JUMP, 7760 Opcode_retw_n_encode_fns, 0, 0 }, 7761 { "rfwo", 15 /* xt_iclass_rfwou */, 7762 XTENSA_OPCODE_IS_JUMP, 7763 Opcode_rfwo_encode_fns, 0, 0 }, 7764 { "rfwu", 15 /* xt_iclass_rfwou */, 7765 XTENSA_OPCODE_IS_JUMP, 7766 Opcode_rfwu_encode_fns, 0, 0 }, 7767 { "l32e", 16 /* xt_iclass_l32e */, 7768 0, 7769 Opcode_l32e_encode_fns, 0, 0 }, 7770 { "s32e", 17 /* xt_iclass_s32e */, 7771 0, 7772 Opcode_s32e_encode_fns, 0, 0 }, 7773 { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */, 7774 0, 7775 Opcode_rsr_windowbase_encode_fns, 0, 0 }, 7776 { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */, 7777 0, 7778 Opcode_wsr_windowbase_encode_fns, 0, 0 }, 7779 { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */, 7780 0, 7781 Opcode_xsr_windowbase_encode_fns, 0, 0 }, 7782 { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */, 7783 0, 7784 Opcode_rsr_windowstart_encode_fns, 0, 0 }, 7785 { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */, 7786 0, 7787 Opcode_wsr_windowstart_encode_fns, 0, 0 }, 7788 { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */, 7789 0, 7790 Opcode_xsr_windowstart_encode_fns, 0, 0 }, 7791 { "add.n", 24 /* xt_iclass_add.n */, 7792 0, 7793 Opcode_add_n_encode_fns, 0, 0 }, 7794 { "addi.n", 25 /* xt_iclass_addi.n */, 7795 0, 7796 Opcode_addi_n_encode_fns, 0, 0 }, 7797 { "beqz.n", 26 /* xt_iclass_bz6 */, 7798 XTENSA_OPCODE_IS_BRANCH, 7799 Opcode_beqz_n_encode_fns, 0, 0 }, 7800 { "bnez.n", 26 /* xt_iclass_bz6 */, 7801 XTENSA_OPCODE_IS_BRANCH, 7802 Opcode_bnez_n_encode_fns, 0, 0 }, 7803 { "ill.n", 27 /* xt_iclass_ill.n */, 7804 0, 7805 Opcode_ill_n_encode_fns, 0, 0 }, 7806 { "l32i.n", 28 /* xt_iclass_loadi4 */, 7807 0, 7808 Opcode_l32i_n_encode_fns, 0, 0 }, 7809 { "mov.n", 29 /* xt_iclass_mov.n */, 7810 0, 7811 Opcode_mov_n_encode_fns, 0, 0 }, 7812 { "movi.n", 30 /* xt_iclass_movi.n */, 7813 0, 7814 Opcode_movi_n_encode_fns, 0, 0 }, 7815 { "nop.n", 31 /* xt_iclass_nopn */, 7816 0, 7817 Opcode_nop_n_encode_fns, 0, 0 }, 7818 { "ret.n", 32 /* xt_iclass_retn */, 7819 XTENSA_OPCODE_IS_JUMP, 7820 Opcode_ret_n_encode_fns, 0, 0 }, 7821 { "s32i.n", 33 /* xt_iclass_storei4 */, 7822 0, 7823 Opcode_s32i_n_encode_fns, 0, 0 }, 7824 { "addi", 34 /* xt_iclass_addi */, 7825 0, 7826 Opcode_addi_encode_fns, 0, 0 }, 7827 { "addmi", 35 /* xt_iclass_addmi */, 7828 0, 7829 Opcode_addmi_encode_fns, 0, 0 }, 7830 { "add", 36 /* xt_iclass_addsub */, 7831 0, 7832 Opcode_add_encode_fns, 0, 0 }, 7833 { "sub", 36 /* xt_iclass_addsub */, 7834 0, 7835 Opcode_sub_encode_fns, 0, 0 }, 7836 { "addx2", 36 /* xt_iclass_addsub */, 7837 0, 7838 Opcode_addx2_encode_fns, 0, 0 }, 7839 { "addx4", 36 /* xt_iclass_addsub */, 7840 0, 7841 Opcode_addx4_encode_fns, 0, 0 }, 7842 { "addx8", 36 /* xt_iclass_addsub */, 7843 0, 7844 Opcode_addx8_encode_fns, 0, 0 }, 7845 { "subx2", 36 /* xt_iclass_addsub */, 7846 0, 7847 Opcode_subx2_encode_fns, 0, 0 }, 7848 { "subx4", 36 /* xt_iclass_addsub */, 7849 0, 7850 Opcode_subx4_encode_fns, 0, 0 }, 7851 { "subx8", 36 /* xt_iclass_addsub */, 7852 0, 7853 Opcode_subx8_encode_fns, 0, 0 }, 7854 { "and", 37 /* xt_iclass_bit */, 7855 0, 7856 Opcode_and_encode_fns, 0, 0 }, 7857 { "or", 37 /* xt_iclass_bit */, 7858 0, 7859 Opcode_or_encode_fns, 0, 0 }, 7860 { "xor", 37 /* xt_iclass_bit */, 7861 0, 7862 Opcode_xor_encode_fns, 0, 0 }, 7863 { "beqi", 38 /* xt_iclass_bsi8 */, 7864 XTENSA_OPCODE_IS_BRANCH, 7865 Opcode_beqi_encode_fns, 0, 0 }, 7866 { "bnei", 38 /* xt_iclass_bsi8 */, 7867 XTENSA_OPCODE_IS_BRANCH, 7868 Opcode_bnei_encode_fns, 0, 0 }, 7869 { "bgei", 38 /* xt_iclass_bsi8 */, 7870 XTENSA_OPCODE_IS_BRANCH, 7871 Opcode_bgei_encode_fns, 0, 0 }, 7872 { "blti", 38 /* xt_iclass_bsi8 */, 7873 XTENSA_OPCODE_IS_BRANCH, 7874 Opcode_blti_encode_fns, 0, 0 }, 7875 { "bbci", 39 /* xt_iclass_bsi8b */, 7876 XTENSA_OPCODE_IS_BRANCH, 7877 Opcode_bbci_encode_fns, 0, 0 }, 7878 { "bbsi", 39 /* xt_iclass_bsi8b */, 7879 XTENSA_OPCODE_IS_BRANCH, 7880 Opcode_bbsi_encode_fns, 0, 0 }, 7881 { "bgeui", 40 /* xt_iclass_bsi8u */, 7882 XTENSA_OPCODE_IS_BRANCH, 7883 Opcode_bgeui_encode_fns, 0, 0 }, 7884 { "bltui", 40 /* xt_iclass_bsi8u */, 7885 XTENSA_OPCODE_IS_BRANCH, 7886 Opcode_bltui_encode_fns, 0, 0 }, 7887 { "beq", 41 /* xt_iclass_bst8 */, 7888 XTENSA_OPCODE_IS_BRANCH, 7889 Opcode_beq_encode_fns, 0, 0 }, 7890 { "bne", 41 /* xt_iclass_bst8 */, 7891 XTENSA_OPCODE_IS_BRANCH, 7892 Opcode_bne_encode_fns, 0, 0 }, 7893 { "bge", 41 /* xt_iclass_bst8 */, 7894 XTENSA_OPCODE_IS_BRANCH, 7895 Opcode_bge_encode_fns, 0, 0 }, 7896 { "blt", 41 /* xt_iclass_bst8 */, 7897 XTENSA_OPCODE_IS_BRANCH, 7898 Opcode_blt_encode_fns, 0, 0 }, 7899 { "bgeu", 41 /* xt_iclass_bst8 */, 7900 XTENSA_OPCODE_IS_BRANCH, 7901 Opcode_bgeu_encode_fns, 0, 0 }, 7902 { "bltu", 41 /* xt_iclass_bst8 */, 7903 XTENSA_OPCODE_IS_BRANCH, 7904 Opcode_bltu_encode_fns, 0, 0 }, 7905 { "bany", 41 /* xt_iclass_bst8 */, 7906 XTENSA_OPCODE_IS_BRANCH, 7907 Opcode_bany_encode_fns, 0, 0 }, 7908 { "bnone", 41 /* xt_iclass_bst8 */, 7909 XTENSA_OPCODE_IS_BRANCH, 7910 Opcode_bnone_encode_fns, 0, 0 }, 7911 { "ball", 41 /* xt_iclass_bst8 */, 7912 XTENSA_OPCODE_IS_BRANCH, 7913 Opcode_ball_encode_fns, 0, 0 }, 7914 { "bnall", 41 /* xt_iclass_bst8 */, 7915 XTENSA_OPCODE_IS_BRANCH, 7916 Opcode_bnall_encode_fns, 0, 0 }, 7917 { "bbc", 41 /* xt_iclass_bst8 */, 7918 XTENSA_OPCODE_IS_BRANCH, 7919 Opcode_bbc_encode_fns, 0, 0 }, 7920 { "bbs", 41 /* xt_iclass_bst8 */, 7921 XTENSA_OPCODE_IS_BRANCH, 7922 Opcode_bbs_encode_fns, 0, 0 }, 7923 { "beqz", 42 /* xt_iclass_bsz12 */, 7924 XTENSA_OPCODE_IS_BRANCH, 7925 Opcode_beqz_encode_fns, 0, 0 }, 7926 { "bnez", 42 /* xt_iclass_bsz12 */, 7927 XTENSA_OPCODE_IS_BRANCH, 7928 Opcode_bnez_encode_fns, 0, 0 }, 7929 { "bgez", 42 /* xt_iclass_bsz12 */, 7930 XTENSA_OPCODE_IS_BRANCH, 7931 Opcode_bgez_encode_fns, 0, 0 }, 7932 { "bltz", 42 /* xt_iclass_bsz12 */, 7933 XTENSA_OPCODE_IS_BRANCH, 7934 Opcode_bltz_encode_fns, 0, 0 }, 7935 { "call0", 43 /* xt_iclass_call0 */, 7936 XTENSA_OPCODE_IS_CALL, 7937 Opcode_call0_encode_fns, 0, 0 }, 7938 { "callx0", 44 /* xt_iclass_callx0 */, 7939 XTENSA_OPCODE_IS_CALL, 7940 Opcode_callx0_encode_fns, 0, 0 }, 7941 { "extui", 45 /* xt_iclass_exti */, 7942 0, 7943 Opcode_extui_encode_fns, 0, 0 }, 7944 { "ill", 46 /* xt_iclass_ill */, 7945 0, 7946 Opcode_ill_encode_fns, 0, 0 }, 7947 { "j", 47 /* xt_iclass_jump */, 7948 XTENSA_OPCODE_IS_JUMP, 7949 Opcode_j_encode_fns, 0, 0 }, 7950 { "jx", 48 /* xt_iclass_jumpx */, 7951 XTENSA_OPCODE_IS_JUMP, 7952 Opcode_jx_encode_fns, 0, 0 }, 7953 { "l16ui", 49 /* xt_iclass_l16ui */, 7954 0, 7955 Opcode_l16ui_encode_fns, 0, 0 }, 7956 { "l16si", 50 /* xt_iclass_l16si */, 7957 0, 7958 Opcode_l16si_encode_fns, 0, 0 }, 7959 { "l32i", 51 /* xt_iclass_l32i */, 7960 0, 7961 Opcode_l32i_encode_fns, 0, 0 }, 7962 { "l32r", 52 /* xt_iclass_l32r */, 7963 0, 7964 Opcode_l32r_encode_fns, 0, 0 }, 7965 { "l8ui", 53 /* xt_iclass_l8i */, 7966 0, 7967 Opcode_l8ui_encode_fns, 0, 0 }, 7968 { "loop", 54 /* xt_iclass_loop */, 7969 XTENSA_OPCODE_IS_LOOP, 7970 Opcode_loop_encode_fns, 0, 0 }, 7971 { "loopnez", 55 /* xt_iclass_loopz */, 7972 XTENSA_OPCODE_IS_LOOP, 7973 Opcode_loopnez_encode_fns, 0, 0 }, 7974 { "loopgtz", 55 /* xt_iclass_loopz */, 7975 XTENSA_OPCODE_IS_LOOP, 7976 Opcode_loopgtz_encode_fns, 0, 0 }, 7977 { "movi", 56 /* xt_iclass_movi */, 7978 0, 7979 Opcode_movi_encode_fns, 0, 0 }, 7980 { "moveqz", 57 /* xt_iclass_movz */, 7981 0, 7982 Opcode_moveqz_encode_fns, 0, 0 }, 7983 { "movnez", 57 /* xt_iclass_movz */, 7984 0, 7985 Opcode_movnez_encode_fns, 0, 0 }, 7986 { "movltz", 57 /* xt_iclass_movz */, 7987 0, 7988 Opcode_movltz_encode_fns, 0, 0 }, 7989 { "movgez", 57 /* xt_iclass_movz */, 7990 0, 7991 Opcode_movgez_encode_fns, 0, 0 }, 7992 { "neg", 58 /* xt_iclass_neg */, 7993 0, 7994 Opcode_neg_encode_fns, 0, 0 }, 7995 { "abs", 58 /* xt_iclass_neg */, 7996 0, 7997 Opcode_abs_encode_fns, 0, 0 }, 7998 { "nop", 59 /* xt_iclass_nop */, 7999 0, 8000 Opcode_nop_encode_fns, 0, 0 }, 8001 { "ret", 60 /* xt_iclass_return */, 8002 XTENSA_OPCODE_IS_JUMP, 8003 Opcode_ret_encode_fns, 0, 0 }, 8004 { "s16i", 61 /* xt_iclass_s16i */, 8005 0, 8006 Opcode_s16i_encode_fns, 0, 0 }, 8007 { "s32i", 62 /* xt_iclass_s32i */, 8008 0, 8009 Opcode_s32i_encode_fns, 0, 0 }, 8010 { "s8i", 63 /* xt_iclass_s8i */, 8011 0, 8012 Opcode_s8i_encode_fns, 0, 0 }, 8013 { "ssr", 64 /* xt_iclass_sar */, 8014 0, 8015 Opcode_ssr_encode_fns, 0, 0 }, 8016 { "ssl", 64 /* xt_iclass_sar */, 8017 0, 8018 Opcode_ssl_encode_fns, 0, 0 }, 8019 { "ssa8l", 64 /* xt_iclass_sar */, 8020 0, 8021 Opcode_ssa8l_encode_fns, 0, 0 }, 8022 { "ssa8b", 64 /* xt_iclass_sar */, 8023 0, 8024 Opcode_ssa8b_encode_fns, 0, 0 }, 8025 { "ssai", 65 /* xt_iclass_sari */, 8026 0, 8027 Opcode_ssai_encode_fns, 0, 0 }, 8028 { "sll", 66 /* xt_iclass_shifts */, 8029 0, 8030 Opcode_sll_encode_fns, 0, 0 }, 8031 { "src", 67 /* xt_iclass_shiftst */, 8032 0, 8033 Opcode_src_encode_fns, 0, 0 }, 8034 { "srl", 68 /* xt_iclass_shiftt */, 8035 0, 8036 Opcode_srl_encode_fns, 0, 0 }, 8037 { "sra", 68 /* xt_iclass_shiftt */, 8038 0, 8039 Opcode_sra_encode_fns, 0, 0 }, 8040 { "slli", 69 /* xt_iclass_slli */, 8041 0, 8042 Opcode_slli_encode_fns, 0, 0 }, 8043 { "srai", 70 /* xt_iclass_srai */, 8044 0, 8045 Opcode_srai_encode_fns, 0, 0 }, 8046 { "srli", 71 /* xt_iclass_srli */, 8047 0, 8048 Opcode_srli_encode_fns, 0, 0 }, 8049 { "memw", 72 /* xt_iclass_memw */, 8050 0, 8051 Opcode_memw_encode_fns, 0, 0 }, 8052 { "extw", 73 /* xt_iclass_extw */, 8053 0, 8054 Opcode_extw_encode_fns, 0, 0 }, 8055 { "isync", 74 /* xt_iclass_isync */, 8056 0, 8057 Opcode_isync_encode_fns, 0, 0 }, 8058 { "rsync", 75 /* xt_iclass_sync */, 8059 0, 8060 Opcode_rsync_encode_fns, 0, 0 }, 8061 { "esync", 75 /* xt_iclass_sync */, 8062 0, 8063 Opcode_esync_encode_fns, 0, 0 }, 8064 { "dsync", 75 /* xt_iclass_sync */, 8065 0, 8066 Opcode_dsync_encode_fns, 0, 0 }, 8067 { "rsil", 76 /* xt_iclass_rsil */, 8068 0, 8069 Opcode_rsil_encode_fns, 0, 0 }, 8070 { "rsr.lend", 77 /* xt_iclass_rsr.lend */, 8071 0, 8072 Opcode_rsr_lend_encode_fns, 0, 0 }, 8073 { "wsr.lend", 78 /* xt_iclass_wsr.lend */, 8074 0, 8075 Opcode_wsr_lend_encode_fns, 0, 0 }, 8076 { "xsr.lend", 79 /* xt_iclass_xsr.lend */, 8077 0, 8078 Opcode_xsr_lend_encode_fns, 0, 0 }, 8079 { "rsr.lcount", 80 /* xt_iclass_rsr.lcount */, 8080 0, 8081 Opcode_rsr_lcount_encode_fns, 0, 0 }, 8082 { "wsr.lcount", 81 /* xt_iclass_wsr.lcount */, 8083 0, 8084 Opcode_wsr_lcount_encode_fns, 0, 0 }, 8085 { "xsr.lcount", 82 /* xt_iclass_xsr.lcount */, 8086 0, 8087 Opcode_xsr_lcount_encode_fns, 0, 0 }, 8088 { "rsr.lbeg", 83 /* xt_iclass_rsr.lbeg */, 8089 0, 8090 Opcode_rsr_lbeg_encode_fns, 0, 0 }, 8091 { "wsr.lbeg", 84 /* xt_iclass_wsr.lbeg */, 8092 0, 8093 Opcode_wsr_lbeg_encode_fns, 0, 0 }, 8094 { "xsr.lbeg", 85 /* xt_iclass_xsr.lbeg */, 8095 0, 8096 Opcode_xsr_lbeg_encode_fns, 0, 0 }, 8097 { "rsr.sar", 86 /* xt_iclass_rsr.sar */, 8098 0, 8099 Opcode_rsr_sar_encode_fns, 0, 0 }, 8100 { "wsr.sar", 87 /* xt_iclass_wsr.sar */, 8101 0, 8102 Opcode_wsr_sar_encode_fns, 0, 0 }, 8103 { "xsr.sar", 88 /* xt_iclass_xsr.sar */, 8104 0, 8105 Opcode_xsr_sar_encode_fns, 0, 0 }, 8106 { "rsr.litbase", 89 /* xt_iclass_rsr.litbase */, 8107 0, 8108 Opcode_rsr_litbase_encode_fns, 0, 0 }, 8109 { "wsr.litbase", 90 /* xt_iclass_wsr.litbase */, 8110 0, 8111 Opcode_wsr_litbase_encode_fns, 0, 0 }, 8112 { "xsr.litbase", 91 /* xt_iclass_xsr.litbase */, 8113 0, 8114 Opcode_xsr_litbase_encode_fns, 0, 0 }, 8115 { "rsr.176", 92 /* xt_iclass_rsr.176 */, 8116 0, 8117 Opcode_rsr_176_encode_fns, 0, 0 }, 8118 { "rsr.208", 93 /* xt_iclass_rsr.208 */, 8119 0, 8120 Opcode_rsr_208_encode_fns, 0, 0 }, 8121 { "rsr.ps", 94 /* xt_iclass_rsr.ps */, 8122 0, 8123 Opcode_rsr_ps_encode_fns, 0, 0 }, 8124 { "wsr.ps", 95 /* xt_iclass_wsr.ps */, 8125 0, 8126 Opcode_wsr_ps_encode_fns, 0, 0 }, 8127 { "xsr.ps", 96 /* xt_iclass_xsr.ps */, 8128 0, 8129 Opcode_xsr_ps_encode_fns, 0, 0 }, 8130 { "rsr.epc1", 97 /* xt_iclass_rsr.epc1 */, 8131 0, 8132 Opcode_rsr_epc1_encode_fns, 0, 0 }, 8133 { "wsr.epc1", 98 /* xt_iclass_wsr.epc1 */, 8134 0, 8135 Opcode_wsr_epc1_encode_fns, 0, 0 }, 8136 { "xsr.epc1", 99 /* xt_iclass_xsr.epc1 */, 8137 0, 8138 Opcode_xsr_epc1_encode_fns, 0, 0 }, 8139 { "rsr.excsave1", 100 /* xt_iclass_rsr.excsave1 */, 8140 0, 8141 Opcode_rsr_excsave1_encode_fns, 0, 0 }, 8142 { "wsr.excsave1", 101 /* xt_iclass_wsr.excsave1 */, 8143 0, 8144 Opcode_wsr_excsave1_encode_fns, 0, 0 }, 8145 { "xsr.excsave1", 102 /* xt_iclass_xsr.excsave1 */, 8146 0, 8147 Opcode_xsr_excsave1_encode_fns, 0, 0 }, 8148 { "rsr.epc2", 103 /* xt_iclass_rsr.epc2 */, 8149 0, 8150 Opcode_rsr_epc2_encode_fns, 0, 0 }, 8151 { "wsr.epc2", 104 /* xt_iclass_wsr.epc2 */, 8152 0, 8153 Opcode_wsr_epc2_encode_fns, 0, 0 }, 8154 { "xsr.epc2", 105 /* xt_iclass_xsr.epc2 */, 8155 0, 8156 Opcode_xsr_epc2_encode_fns, 0, 0 }, 8157 { "rsr.excsave2", 106 /* xt_iclass_rsr.excsave2 */, 8158 0, 8159 Opcode_rsr_excsave2_encode_fns, 0, 0 }, 8160 { "wsr.excsave2", 107 /* xt_iclass_wsr.excsave2 */, 8161 0, 8162 Opcode_wsr_excsave2_encode_fns, 0, 0 }, 8163 { "xsr.excsave2", 108 /* xt_iclass_xsr.excsave2 */, 8164 0, 8165 Opcode_xsr_excsave2_encode_fns, 0, 0 }, 8166 { "rsr.epc3", 109 /* xt_iclass_rsr.epc3 */, 8167 0, 8168 Opcode_rsr_epc3_encode_fns, 0, 0 }, 8169 { "wsr.epc3", 110 /* xt_iclass_wsr.epc3 */, 8170 0, 8171 Opcode_wsr_epc3_encode_fns, 0, 0 }, 8172 { "xsr.epc3", 111 /* xt_iclass_xsr.epc3 */, 8173 0, 8174 Opcode_xsr_epc3_encode_fns, 0, 0 }, 8175 { "rsr.excsave3", 112 /* xt_iclass_rsr.excsave3 */, 8176 0, 8177 Opcode_rsr_excsave3_encode_fns, 0, 0 }, 8178 { "wsr.excsave3", 113 /* xt_iclass_wsr.excsave3 */, 8179 0, 8180 Opcode_wsr_excsave3_encode_fns, 0, 0 }, 8181 { "xsr.excsave3", 114 /* xt_iclass_xsr.excsave3 */, 8182 0, 8183 Opcode_xsr_excsave3_encode_fns, 0, 0 }, 8184 { "rsr.epc4", 115 /* xt_iclass_rsr.epc4 */, 8185 0, 8186 Opcode_rsr_epc4_encode_fns, 0, 0 }, 8187 { "wsr.epc4", 116 /* xt_iclass_wsr.epc4 */, 8188 0, 8189 Opcode_wsr_epc4_encode_fns, 0, 0 }, 8190 { "xsr.epc4", 117 /* xt_iclass_xsr.epc4 */, 8191 0, 8192 Opcode_xsr_epc4_encode_fns, 0, 0 }, 8193 { "rsr.excsave4", 118 /* xt_iclass_rsr.excsave4 */, 8194 0, 8195 Opcode_rsr_excsave4_encode_fns, 0, 0 }, 8196 { "wsr.excsave4", 119 /* xt_iclass_wsr.excsave4 */, 8197 0, 8198 Opcode_wsr_excsave4_encode_fns, 0, 0 }, 8199 { "xsr.excsave4", 120 /* xt_iclass_xsr.excsave4 */, 8200 0, 8201 Opcode_xsr_excsave4_encode_fns, 0, 0 }, 8202 { "rsr.eps2", 121 /* xt_iclass_rsr.eps2 */, 8203 0, 8204 Opcode_rsr_eps2_encode_fns, 0, 0 }, 8205 { "wsr.eps2", 122 /* xt_iclass_wsr.eps2 */, 8206 0, 8207 Opcode_wsr_eps2_encode_fns, 0, 0 }, 8208 { "xsr.eps2", 123 /* xt_iclass_xsr.eps2 */, 8209 0, 8210 Opcode_xsr_eps2_encode_fns, 0, 0 }, 8211 { "rsr.eps3", 124 /* xt_iclass_rsr.eps3 */, 8212 0, 8213 Opcode_rsr_eps3_encode_fns, 0, 0 }, 8214 { "wsr.eps3", 125 /* xt_iclass_wsr.eps3 */, 8215 0, 8216 Opcode_wsr_eps3_encode_fns, 0, 0 }, 8217 { "xsr.eps3", 126 /* xt_iclass_xsr.eps3 */, 8218 0, 8219 Opcode_xsr_eps3_encode_fns, 0, 0 }, 8220 { "rsr.eps4", 127 /* xt_iclass_rsr.eps4 */, 8221 0, 8222 Opcode_rsr_eps4_encode_fns, 0, 0 }, 8223 { "wsr.eps4", 128 /* xt_iclass_wsr.eps4 */, 8224 0, 8225 Opcode_wsr_eps4_encode_fns, 0, 0 }, 8226 { "xsr.eps4", 129 /* xt_iclass_xsr.eps4 */, 8227 0, 8228 Opcode_xsr_eps4_encode_fns, 0, 0 }, 8229 { "rsr.excvaddr", 130 /* xt_iclass_rsr.excvaddr */, 8230 0, 8231 Opcode_rsr_excvaddr_encode_fns, 0, 0 }, 8232 { "wsr.excvaddr", 131 /* xt_iclass_wsr.excvaddr */, 8233 0, 8234 Opcode_wsr_excvaddr_encode_fns, 0, 0 }, 8235 { "xsr.excvaddr", 132 /* xt_iclass_xsr.excvaddr */, 8236 0, 8237 Opcode_xsr_excvaddr_encode_fns, 0, 0 }, 8238 { "rsr.depc", 133 /* xt_iclass_rsr.depc */, 8239 0, 8240 Opcode_rsr_depc_encode_fns, 0, 0 }, 8241 { "wsr.depc", 134 /* xt_iclass_wsr.depc */, 8242 0, 8243 Opcode_wsr_depc_encode_fns, 0, 0 }, 8244 { "xsr.depc", 135 /* xt_iclass_xsr.depc */, 8245 0, 8246 Opcode_xsr_depc_encode_fns, 0, 0 }, 8247 { "rsr.exccause", 136 /* xt_iclass_rsr.exccause */, 8248 0, 8249 Opcode_rsr_exccause_encode_fns, 0, 0 }, 8250 { "wsr.exccause", 137 /* xt_iclass_wsr.exccause */, 8251 0, 8252 Opcode_wsr_exccause_encode_fns, 0, 0 }, 8253 { "xsr.exccause", 138 /* xt_iclass_xsr.exccause */, 8254 0, 8255 Opcode_xsr_exccause_encode_fns, 0, 0 }, 8256 { "rsr.misc0", 139 /* xt_iclass_rsr.misc0 */, 8257 0, 8258 Opcode_rsr_misc0_encode_fns, 0, 0 }, 8259 { "wsr.misc0", 140 /* xt_iclass_wsr.misc0 */, 8260 0, 8261 Opcode_wsr_misc0_encode_fns, 0, 0 }, 8262 { "xsr.misc0", 141 /* xt_iclass_xsr.misc0 */, 8263 0, 8264 Opcode_xsr_misc0_encode_fns, 0, 0 }, 8265 { "rsr.misc1", 142 /* xt_iclass_rsr.misc1 */, 8266 0, 8267 Opcode_rsr_misc1_encode_fns, 0, 0 }, 8268 { "wsr.misc1", 143 /* xt_iclass_wsr.misc1 */, 8269 0, 8270 Opcode_wsr_misc1_encode_fns, 0, 0 }, 8271 { "xsr.misc1", 144 /* xt_iclass_xsr.misc1 */, 8272 0, 8273 Opcode_xsr_misc1_encode_fns, 0, 0 }, 8274 { "rsr.prid", 145 /* xt_iclass_rsr.prid */, 8275 0, 8276 Opcode_rsr_prid_encode_fns, 0, 0 }, 8277 { "rfi", 146 /* xt_iclass_rfi */, 8278 XTENSA_OPCODE_IS_JUMP, 8279 Opcode_rfi_encode_fns, 0, 0 }, 8280 { "waiti", 147 /* xt_iclass_wait */, 8281 0, 8282 Opcode_waiti_encode_fns, 0, 0 }, 8283 { "rsr.interrupt", 148 /* xt_iclass_rsr.interrupt */, 8284 0, 8285 Opcode_rsr_interrupt_encode_fns, 0, 0 }, 8286 { "wsr.intset", 149 /* xt_iclass_wsr.intset */, 8287 0, 8288 Opcode_wsr_intset_encode_fns, 0, 0 }, 8289 { "wsr.intclear", 150 /* xt_iclass_wsr.intclear */, 8290 0, 8291 Opcode_wsr_intclear_encode_fns, 0, 0 }, 8292 { "rsr.intenable", 151 /* xt_iclass_rsr.intenable */, 8293 0, 8294 Opcode_rsr_intenable_encode_fns, 0, 0 }, 8295 { "wsr.intenable", 152 /* xt_iclass_wsr.intenable */, 8296 0, 8297 Opcode_wsr_intenable_encode_fns, 0, 0 }, 8298 { "xsr.intenable", 153 /* xt_iclass_xsr.intenable */, 8299 0, 8300 Opcode_xsr_intenable_encode_fns, 0, 0 }, 8301 { "break", 154 /* xt_iclass_break */, 8302 0, 8303 Opcode_break_encode_fns, 0, 0 }, 8304 { "break.n", 155 /* xt_iclass_break.n */, 8305 0, 8306 Opcode_break_n_encode_fns, 0, 0 }, 8307 { "rsr.dbreaka0", 156 /* xt_iclass_rsr.dbreaka0 */, 8308 0, 8309 Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, 8310 { "wsr.dbreaka0", 157 /* xt_iclass_wsr.dbreaka0 */, 8311 0, 8312 Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, 8313 { "xsr.dbreaka0", 158 /* xt_iclass_xsr.dbreaka0 */, 8314 0, 8315 Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, 8316 { "rsr.dbreakc0", 159 /* xt_iclass_rsr.dbreakc0 */, 8317 0, 8318 Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, 8319 { "wsr.dbreakc0", 160 /* xt_iclass_wsr.dbreakc0 */, 8320 0, 8321 Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, 8322 { "xsr.dbreakc0", 161 /* xt_iclass_xsr.dbreakc0 */, 8323 0, 8324 Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, 8325 { "rsr.dbreaka1", 162 /* xt_iclass_rsr.dbreaka1 */, 8326 0, 8327 Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, 8328 { "wsr.dbreaka1", 163 /* xt_iclass_wsr.dbreaka1 */, 8329 0, 8330 Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, 8331 { "xsr.dbreaka1", 164 /* xt_iclass_xsr.dbreaka1 */, 8332 0, 8333 Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, 8334 { "rsr.dbreakc1", 165 /* xt_iclass_rsr.dbreakc1 */, 8335 0, 8336 Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, 8337 { "wsr.dbreakc1", 166 /* xt_iclass_wsr.dbreakc1 */, 8338 0, 8339 Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, 8340 { "xsr.dbreakc1", 167 /* xt_iclass_xsr.dbreakc1 */, 8341 0, 8342 Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, 8343 { "rsr.ibreaka0", 168 /* xt_iclass_rsr.ibreaka0 */, 8344 0, 8345 Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, 8346 { "wsr.ibreaka0", 169 /* xt_iclass_wsr.ibreaka0 */, 8347 0, 8348 Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, 8349 { "xsr.ibreaka0", 170 /* xt_iclass_xsr.ibreaka0 */, 8350 0, 8351 Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, 8352 { "rsr.ibreaka1", 171 /* xt_iclass_rsr.ibreaka1 */, 8353 0, 8354 Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, 8355 { "wsr.ibreaka1", 172 /* xt_iclass_wsr.ibreaka1 */, 8356 0, 8357 Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, 8358 { "xsr.ibreaka1", 173 /* xt_iclass_xsr.ibreaka1 */, 8359 0, 8360 Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, 8361 { "rsr.ibreakenable", 174 /* xt_iclass_rsr.ibreakenable */, 8362 0, 8363 Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, 8364 { "wsr.ibreakenable", 175 /* xt_iclass_wsr.ibreakenable */, 8365 0, 8366 Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, 8367 { "xsr.ibreakenable", 176 /* xt_iclass_xsr.ibreakenable */, 8368 0, 8369 Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, 8370 { "rsr.debugcause", 177 /* xt_iclass_rsr.debugcause */, 8371 0, 8372 Opcode_rsr_debugcause_encode_fns, 0, 0 }, 8373 { "wsr.debugcause", 178 /* xt_iclass_wsr.debugcause */, 8374 0, 8375 Opcode_wsr_debugcause_encode_fns, 0, 0 }, 8376 { "xsr.debugcause", 179 /* xt_iclass_xsr.debugcause */, 8377 0, 8378 Opcode_xsr_debugcause_encode_fns, 0, 0 }, 8379 { "rsr.icount", 180 /* xt_iclass_rsr.icount */, 8380 0, 8381 Opcode_rsr_icount_encode_fns, 0, 0 }, 8382 { "wsr.icount", 181 /* xt_iclass_wsr.icount */, 8383 0, 8384 Opcode_wsr_icount_encode_fns, 0, 0 }, 8385 { "xsr.icount", 182 /* xt_iclass_xsr.icount */, 8386 0, 8387 Opcode_xsr_icount_encode_fns, 0, 0 }, 8388 { "rsr.icountlevel", 183 /* xt_iclass_rsr.icountlevel */, 8389 0, 8390 Opcode_rsr_icountlevel_encode_fns, 0, 0 }, 8391 { "wsr.icountlevel", 184 /* xt_iclass_wsr.icountlevel */, 8392 0, 8393 Opcode_wsr_icountlevel_encode_fns, 0, 0 }, 8394 { "xsr.icountlevel", 185 /* xt_iclass_xsr.icountlevel */, 8395 0, 8396 Opcode_xsr_icountlevel_encode_fns, 0, 0 }, 8397 { "rsr.ddr", 186 /* xt_iclass_rsr.ddr */, 8398 0, 8399 Opcode_rsr_ddr_encode_fns, 0, 0 }, 8400 { "wsr.ddr", 187 /* xt_iclass_wsr.ddr */, 8401 0, 8402 Opcode_wsr_ddr_encode_fns, 0, 0 }, 8403 { "xsr.ddr", 188 /* xt_iclass_xsr.ddr */, 8404 0, 8405 Opcode_xsr_ddr_encode_fns, 0, 0 }, 8406 { "rfdo", 189 /* xt_iclass_rfdo */, 8407 XTENSA_OPCODE_IS_JUMP, 8408 Opcode_rfdo_encode_fns, 0, 0 }, 8409 { "rfdd", 190 /* xt_iclass_rfdd */, 8410 XTENSA_OPCODE_IS_JUMP, 8411 Opcode_rfdd_encode_fns, 0, 0 }, 8412 { "rsr.ccount", 191 /* xt_iclass_rsr.ccount */, 8413 0, 8414 Opcode_rsr_ccount_encode_fns, 0, 0 }, 8415 { "wsr.ccount", 192 /* xt_iclass_wsr.ccount */, 8416 0, 8417 Opcode_wsr_ccount_encode_fns, 0, 0 }, 8418 { "xsr.ccount", 193 /* xt_iclass_xsr.ccount */, 8419 0, 8420 Opcode_xsr_ccount_encode_fns, 0, 0 }, 8421 { "rsr.ccompare0", 194 /* xt_iclass_rsr.ccompare0 */, 8422 0, 8423 Opcode_rsr_ccompare0_encode_fns, 0, 0 }, 8424 { "wsr.ccompare0", 195 /* xt_iclass_wsr.ccompare0 */, 8425 0, 8426 Opcode_wsr_ccompare0_encode_fns, 0, 0 }, 8427 { "xsr.ccompare0", 196 /* xt_iclass_xsr.ccompare0 */, 8428 0, 8429 Opcode_xsr_ccompare0_encode_fns, 0, 0 }, 8430 { "rsr.ccompare1", 197 /* xt_iclass_rsr.ccompare1 */, 8431 0, 8432 Opcode_rsr_ccompare1_encode_fns, 0, 0 }, 8433 { "wsr.ccompare1", 198 /* xt_iclass_wsr.ccompare1 */, 8434 0, 8435 Opcode_wsr_ccompare1_encode_fns, 0, 0 }, 8436 { "xsr.ccompare1", 199 /* xt_iclass_xsr.ccompare1 */, 8437 0, 8438 Opcode_xsr_ccompare1_encode_fns, 0, 0 }, 8439 { "rsr.ccompare2", 200 /* xt_iclass_rsr.ccompare2 */, 8440 0, 8441 Opcode_rsr_ccompare2_encode_fns, 0, 0 }, 8442 { "wsr.ccompare2", 201 /* xt_iclass_wsr.ccompare2 */, 8443 0, 8444 Opcode_wsr_ccompare2_encode_fns, 0, 0 }, 8445 { "xsr.ccompare2", 202 /* xt_iclass_xsr.ccompare2 */, 8446 0, 8447 Opcode_xsr_ccompare2_encode_fns, 0, 0 }, 8448 { "ipf", 203 /* xt_iclass_icache */, 8449 0, 8450 Opcode_ipf_encode_fns, 0, 0 }, 8451 { "ihi", 203 /* xt_iclass_icache */, 8452 0, 8453 Opcode_ihi_encode_fns, 0, 0 }, 8454 { "iii", 204 /* xt_iclass_icache_inv */, 8455 0, 8456 Opcode_iii_encode_fns, 0, 0 }, 8457 { "lict", 205 /* xt_iclass_licx */, 8458 0, 8459 Opcode_lict_encode_fns, 0, 0 }, 8460 { "licw", 205 /* xt_iclass_licx */, 8461 0, 8462 Opcode_licw_encode_fns, 0, 0 }, 8463 { "sict", 206 /* xt_iclass_sicx */, 8464 0, 8465 Opcode_sict_encode_fns, 0, 0 }, 8466 { "sicw", 206 /* xt_iclass_sicx */, 8467 0, 8468 Opcode_sicw_encode_fns, 0, 0 }, 8469 { "dhwb", 207 /* xt_iclass_dcache */, 8470 0, 8471 Opcode_dhwb_encode_fns, 0, 0 }, 8472 { "dhwbi", 207 /* xt_iclass_dcache */, 8473 0, 8474 Opcode_dhwbi_encode_fns, 0, 0 }, 8475 { "diwb", 208 /* xt_iclass_dcache_ind */, 8476 0, 8477 Opcode_diwb_encode_fns, 0, 0 }, 8478 { "diwbi", 208 /* xt_iclass_dcache_ind */, 8479 0, 8480 Opcode_diwbi_encode_fns, 0, 0 }, 8481 { "dhi", 209 /* xt_iclass_dcache_inv */, 8482 0, 8483 Opcode_dhi_encode_fns, 0, 0 }, 8484 { "dii", 209 /* xt_iclass_dcache_inv */, 8485 0, 8486 Opcode_dii_encode_fns, 0, 0 }, 8487 { "dpfr", 210 /* xt_iclass_dpf */, 8488 0, 8489 Opcode_dpfr_encode_fns, 0, 0 }, 8490 { "dpfw", 210 /* xt_iclass_dpf */, 8491 0, 8492 Opcode_dpfw_encode_fns, 0, 0 }, 8493 { "dpfro", 210 /* xt_iclass_dpf */, 8494 0, 8495 Opcode_dpfro_encode_fns, 0, 0 }, 8496 { "dpfwo", 210 /* xt_iclass_dpf */, 8497 0, 8498 Opcode_dpfwo_encode_fns, 0, 0 }, 8499 { "sdct", 211 /* xt_iclass_sdct */, 8500 0, 8501 Opcode_sdct_encode_fns, 0, 0 }, 8502 { "ldct", 212 /* xt_iclass_ldct */, 8503 0, 8504 Opcode_ldct_encode_fns, 0, 0 }, 8505 { "wsr.ptevaddr", 213 /* xt_iclass_wsr.ptevaddr */, 8506 0, 8507 Opcode_wsr_ptevaddr_encode_fns, 0, 0 }, 8508 { "rsr.ptevaddr", 214 /* xt_iclass_rsr.ptevaddr */, 8509 0, 8510 Opcode_rsr_ptevaddr_encode_fns, 0, 0 }, 8511 { "xsr.ptevaddr", 215 /* xt_iclass_xsr.ptevaddr */, 8512 0, 8513 Opcode_xsr_ptevaddr_encode_fns, 0, 0 }, 8514 { "rsr.rasid", 216 /* xt_iclass_rsr.rasid */, 8515 0, 8516 Opcode_rsr_rasid_encode_fns, 0, 0 }, 8517 { "wsr.rasid", 217 /* xt_iclass_wsr.rasid */, 8518 0, 8519 Opcode_wsr_rasid_encode_fns, 0, 0 }, 8520 { "xsr.rasid", 218 /* xt_iclass_xsr.rasid */, 8521 0, 8522 Opcode_xsr_rasid_encode_fns, 0, 0 }, 8523 { "rsr.itlbcfg", 219 /* xt_iclass_rsr.itlbcfg */, 8524 0, 8525 Opcode_rsr_itlbcfg_encode_fns, 0, 0 }, 8526 { "wsr.itlbcfg", 220 /* xt_iclass_wsr.itlbcfg */, 8527 0, 8528 Opcode_wsr_itlbcfg_encode_fns, 0, 0 }, 8529 { "xsr.itlbcfg", 221 /* xt_iclass_xsr.itlbcfg */, 8530 0, 8531 Opcode_xsr_itlbcfg_encode_fns, 0, 0 }, 8532 { "rsr.dtlbcfg", 222 /* xt_iclass_rsr.dtlbcfg */, 8533 0, 8534 Opcode_rsr_dtlbcfg_encode_fns, 0, 0 }, 8535 { "wsr.dtlbcfg", 223 /* xt_iclass_wsr.dtlbcfg */, 8536 0, 8537 Opcode_wsr_dtlbcfg_encode_fns, 0, 0 }, 8538 { "xsr.dtlbcfg", 224 /* xt_iclass_xsr.dtlbcfg */, 8539 0, 8540 Opcode_xsr_dtlbcfg_encode_fns, 0, 0 }, 8541 { "idtlb", 225 /* xt_iclass_idtlb */, 8542 0, 8543 Opcode_idtlb_encode_fns, 0, 0 }, 8544 { "pdtlb", 226 /* xt_iclass_rdtlb */, 8545 0, 8546 Opcode_pdtlb_encode_fns, 0, 0 }, 8547 { "rdtlb0", 226 /* xt_iclass_rdtlb */, 8548 0, 8549 Opcode_rdtlb0_encode_fns, 0, 0 }, 8550 { "rdtlb1", 226 /* xt_iclass_rdtlb */, 8551 0, 8552 Opcode_rdtlb1_encode_fns, 0, 0 }, 8553 { "wdtlb", 227 /* xt_iclass_wdtlb */, 8554 0, 8555 Opcode_wdtlb_encode_fns, 0, 0 }, 8556 { "iitlb", 228 /* xt_iclass_iitlb */, 8557 0, 8558 Opcode_iitlb_encode_fns, 0, 0 }, 8559 { "pitlb", 229 /* xt_iclass_ritlb */, 8560 0, 8561 Opcode_pitlb_encode_fns, 0, 0 }, 8562 { "ritlb0", 229 /* xt_iclass_ritlb */, 8563 0, 8564 Opcode_ritlb0_encode_fns, 0, 0 }, 8565 { "ritlb1", 229 /* xt_iclass_ritlb */, 8566 0, 8567 Opcode_ritlb1_encode_fns, 0, 0 }, 8568 { "witlb", 230 /* xt_iclass_witlb */, 8569 0, 8570 Opcode_witlb_encode_fns, 0, 0 }, 8571 { "ldpte", 231 /* xt_iclass_ldpte */, 8572 0, 8573 Opcode_ldpte_encode_fns, 0, 0 }, 8574 { "hwwitlba", 232 /* xt_iclass_hwwitlba */, 8575 XTENSA_OPCODE_IS_BRANCH, 8576 Opcode_hwwitlba_encode_fns, 0, 0 }, 8577 { "hwwdtlba", 233 /* xt_iclass_hwwdtlba */, 8578 0, 8579 Opcode_hwwdtlba_encode_fns, 0, 0 }, 8580 { "nsa", 234 /* xt_iclass_nsa */, 8581 0, 8582 Opcode_nsa_encode_fns, 0, 0 }, 8583 { "nsau", 234 /* xt_iclass_nsa */, 8584 0, 8585 Opcode_nsau_encode_fns, 0, 0 } 8586}; 8587 8588 8589/* Slot-specific opcode decode functions. */ 8590 8591static int 8592Slot_inst_decode (const xtensa_insnbuf insn) 8593{ 8594 switch (Field_op0_Slot_inst_get (insn)) 8595 { 8596 case 0: 8597 switch (Field_op1_Slot_inst_get (insn)) 8598 { 8599 case 0: 8600 switch (Field_op2_Slot_inst_get (insn)) 8601 { 8602 case 0: 8603 switch (Field_r_Slot_inst_get (insn)) 8604 { 8605 case 0: 8606 switch (Field_m_Slot_inst_get (insn)) 8607 { 8608 case 0: 8609 if (Field_s_Slot_inst_get (insn) == 0 && 8610 Field_n_Slot_inst_get (insn) == 0) 8611 return 77; /* ill */ 8612 break; 8613 case 2: 8614 switch (Field_n_Slot_inst_get (insn)) 8615 { 8616 case 0: 8617 return 96; /* ret */ 8618 case 1: 8619 return 14; /* retw */ 8620 case 2: 8621 return 79; /* jx */ 8622 } 8623 break; 8624 case 3: 8625 switch (Field_n_Slot_inst_get (insn)) 8626 { 8627 case 0: 8628 return 75; /* callx0 */ 8629 case 1: 8630 return 10; /* callx4 */ 8631 case 2: 8632 return 9; /* callx8 */ 8633 case 3: 8634 return 8; /* callx12 */ 8635 } 8636 break; 8637 } 8638 break; 8639 case 1: 8640 return 12; /* movsp */ 8641 case 2: 8642 if (Field_s_Slot_inst_get (insn) == 0) 8643 { 8644 switch (Field_t_Slot_inst_get (insn)) 8645 { 8646 case 0: 8647 return 114; /* isync */ 8648 case 1: 8649 return 115; /* rsync */ 8650 case 2: 8651 return 116; /* esync */ 8652 case 3: 8653 return 117; /* dsync */ 8654 case 8: 8655 return 0; /* excw */ 8656 case 12: 8657 return 112; /* memw */ 8658 case 13: 8659 return 113; /* extw */ 8660 case 15: 8661 return 95; /* nop */ 8662 } 8663 } 8664 break; 8665 case 3: 8666 switch (Field_t_Slot_inst_get (insn)) 8667 { 8668 case 0: 8669 switch (Field_s_Slot_inst_get (insn)) 8670 { 8671 case 0: 8672 return 1; /* rfe */ 8673 case 2: 8674 return 2; /* rfde */ 8675 case 4: 8676 return 16; /* rfwo */ 8677 case 5: 8678 return 17; /* rfwu */ 8679 } 8680 break; 8681 case 1: 8682 return 188; /* rfi */ 8683 } 8684 break; 8685 case 4: 8686 return 196; /* break */ 8687 case 5: 8688 switch (Field_s_Slot_inst_get (insn)) 8689 { 8690 case 0: 8691 if (Field_t_Slot_inst_get (insn) == 0) 8692 return 3; /* syscall */ 8693 break; 8694 case 1: 8695 if (Field_t_Slot_inst_get (insn) == 0) 8696 return 4; /* simcall */ 8697 break; 8698 } 8699 break; 8700 case 6: 8701 return 118; /* rsil */ 8702 case 7: 8703 if (Field_t_Slot_inst_get (insn) == 0) 8704 return 189; /* waiti */ 8705 break; 8706 } 8707 break; 8708 case 1: 8709 return 47; /* and */ 8710 case 2: 8711 return 48; /* or */ 8712 case 3: 8713 return 49; /* xor */ 8714 case 4: 8715 switch (Field_r_Slot_inst_get (insn)) 8716 { 8717 case 0: 8718 if (Field_t_Slot_inst_get (insn) == 0) 8719 return 100; /* ssr */ 8720 break; 8721 case 1: 8722 if (Field_t_Slot_inst_get (insn) == 0) 8723 return 101; /* ssl */ 8724 break; 8725 case 2: 8726 if (Field_t_Slot_inst_get (insn) == 0) 8727 return 102; /* ssa8l */ 8728 break; 8729 case 3: 8730 if (Field_t_Slot_inst_get (insn) == 0) 8731 return 103; /* ssa8b */ 8732 break; 8733 case 4: 8734 if (Field_thi3_Slot_inst_get (insn) == 0) 8735 return 104; /* ssai */ 8736 break; 8737 case 8: 8738 if (Field_s_Slot_inst_get (insn) == 0) 8739 return 13; /* rotw */ 8740 break; 8741 case 14: 8742 return 289; /* nsa */ 8743 case 15: 8744 return 290; /* nsau */ 8745 } 8746 break; 8747 case 5: 8748 switch (Field_r_Slot_inst_get (insn)) 8749 { 8750 case 1: 8751 return 287; /* hwwitlba */ 8752 case 3: 8753 return 283; /* ritlb0 */ 8754 case 4: 8755 if (Field_t_Slot_inst_get (insn) == 0) 8756 return 281; /* iitlb */ 8757 break; 8758 case 5: 8759 return 282; /* pitlb */ 8760 case 6: 8761 return 285; /* witlb */ 8762 case 7: 8763 return 284; /* ritlb1 */ 8764 case 9: 8765 return 288; /* hwwdtlba */ 8766 case 11: 8767 return 278; /* rdtlb0 */ 8768 case 12: 8769 if (Field_t_Slot_inst_get (insn) == 0) 8770 return 276; /* idtlb */ 8771 break; 8772 case 13: 8773 return 277; /* pdtlb */ 8774 case 14: 8775 return 280; /* wdtlb */ 8776 case 15: 8777 return 279; /* rdtlb1 */ 8778 } 8779 break; 8780 case 6: 8781 switch (Field_s_Slot_inst_get (insn)) 8782 { 8783 case 0: 8784 return 93; /* neg */ 8785 case 1: 8786 return 94; /* abs */ 8787 } 8788 break; 8789 case 8: 8790 return 39; /* add */ 8791 case 9: 8792 return 41; /* addx2 */ 8793 case 10: 8794 return 42; /* addx4 */ 8795 case 11: 8796 return 43; /* addx8 */ 8797 case 12: 8798 return 40; /* sub */ 8799 case 13: 8800 return 44; /* subx2 */ 8801 case 14: 8802 return 45; /* subx4 */ 8803 case 15: 8804 return 46; /* subx8 */ 8805 } 8806 break; 8807 case 1: 8808 switch (Field_op2_Slot_inst_get (insn)) 8809 { 8810 case 0: 8811 case 1: 8812 return 109; /* slli */ 8813 case 2: 8814 case 3: 8815 return 110; /* srai */ 8816 case 4: 8817 return 111; /* srli */ 8818 case 6: 8819 switch (Field_sr_Slot_inst_get (insn)) 8820 { 8821 case 0: 8822 return 127; /* xsr.lbeg */ 8823 case 1: 8824 return 121; /* xsr.lend */ 8825 case 2: 8826 return 124; /* xsr.lcount */ 8827 case 3: 8828 return 130; /* xsr.sar */ 8829 case 5: 8830 return 133; /* xsr.litbase */ 8831 case 72: 8832 return 22; /* xsr.windowbase */ 8833 case 73: 8834 return 25; /* xsr.windowstart */ 8835 case 83: 8836 return 266; /* xsr.ptevaddr */ 8837 case 90: 8838 return 269; /* xsr.rasid */ 8839 case 91: 8840 return 272; /* xsr.itlbcfg */ 8841 case 92: 8842 return 275; /* xsr.dtlbcfg */ 8843 case 96: 8844 return 218; /* xsr.ibreakenable */ 8845 case 104: 8846 return 230; /* xsr.ddr */ 8847 case 128: 8848 return 212; /* xsr.ibreaka0 */ 8849 case 129: 8850 return 215; /* xsr.ibreaka1 */ 8851 case 144: 8852 return 200; /* xsr.dbreaka0 */ 8853 case 145: 8854 return 206; /* xsr.dbreaka1 */ 8855 case 160: 8856 return 203; /* xsr.dbreakc0 */ 8857 case 161: 8858 return 209; /* xsr.dbreakc1 */ 8859 case 177: 8860 return 141; /* xsr.epc1 */ 8861 case 178: 8862 return 147; /* xsr.epc2 */ 8863 case 179: 8864 return 153; /* xsr.epc3 */ 8865 case 180: 8866 return 159; /* xsr.epc4 */ 8867 case 192: 8868 return 177; /* xsr.depc */ 8869 case 194: 8870 return 165; /* xsr.eps2 */ 8871 case 195: 8872 return 168; /* xsr.eps3 */ 8873 case 196: 8874 return 171; /* xsr.eps4 */ 8875 case 209: 8876 return 144; /* xsr.excsave1 */ 8877 case 210: 8878 return 150; /* xsr.excsave2 */ 8879 case 211: 8880 return 156; /* xsr.excsave3 */ 8881 case 212: 8882 return 162; /* xsr.excsave4 */ 8883 case 228: 8884 return 195; /* xsr.intenable */ 8885 case 230: 8886 return 138; /* xsr.ps */ 8887 case 232: 8888 return 180; /* xsr.exccause */ 8889 case 233: 8890 return 221; /* xsr.debugcause */ 8891 case 234: 8892 return 235; /* xsr.ccount */ 8893 case 236: 8894 return 224; /* xsr.icount */ 8895 case 237: 8896 return 227; /* xsr.icountlevel */ 8897 case 238: 8898 return 174; /* xsr.excvaddr */ 8899 case 240: 8900 return 238; /* xsr.ccompare0 */ 8901 case 241: 8902 return 241; /* xsr.ccompare1 */ 8903 case 242: 8904 return 244; /* xsr.ccompare2 */ 8905 case 244: 8906 return 183; /* xsr.misc0 */ 8907 case 245: 8908 return 186; /* xsr.misc1 */ 8909 } 8910 break; 8911 case 8: 8912 return 106; /* src */ 8913 case 9: 8914 if (Field_s_Slot_inst_get (insn) == 0) 8915 return 107; /* srl */ 8916 break; 8917 case 10: 8918 if (Field_t_Slot_inst_get (insn) == 0) 8919 return 105; /* sll */ 8920 break; 8921 case 11: 8922 if (Field_s_Slot_inst_get (insn) == 0) 8923 return 108; /* sra */ 8924 break; 8925 case 15: 8926 switch (Field_r_Slot_inst_get (insn)) 8927 { 8928 case 0: 8929 return 248; /* lict */ 8930 case 1: 8931 return 250; /* sict */ 8932 case 2: 8933 return 249; /* licw */ 8934 case 3: 8935 return 251; /* sicw */ 8936 case 8: 8937 return 263; /* ldct */ 8938 case 9: 8939 return 262; /* sdct */ 8940 case 14: 8941 if (Field_t_Slot_inst_get (insn) == 0 && 8942 Field_s_Slot_inst_get (insn) == 0) 8943 return 231; /* rfdo */ 8944 if (Field_t_Slot_inst_get (insn) == 1 && 8945 Field_s_Slot_inst_get (insn) == 0) 8946 return 232; /* rfdd */ 8947 break; 8948 case 15: 8949 return 286; /* ldpte */ 8950 } 8951 break; 8952 } 8953 break; 8954 case 3: 8955 switch (Field_op2_Slot_inst_get (insn)) 8956 { 8957 case 0: 8958 switch (Field_sr_Slot_inst_get (insn)) 8959 { 8960 case 0: 8961 return 125; /* rsr.lbeg */ 8962 case 1: 8963 return 119; /* rsr.lend */ 8964 case 2: 8965 return 122; /* rsr.lcount */ 8966 case 3: 8967 return 128; /* rsr.sar */ 8968 case 5: 8969 return 131; /* rsr.litbase */ 8970 case 72: 8971 return 20; /* rsr.windowbase */ 8972 case 73: 8973 return 23; /* rsr.windowstart */ 8974 case 83: 8975 return 265; /* rsr.ptevaddr */ 8976 case 90: 8977 return 267; /* rsr.rasid */ 8978 case 91: 8979 return 270; /* rsr.itlbcfg */ 8980 case 92: 8981 return 273; /* rsr.dtlbcfg */ 8982 case 96: 8983 return 216; /* rsr.ibreakenable */ 8984 case 104: 8985 return 228; /* rsr.ddr */ 8986 case 128: 8987 return 210; /* rsr.ibreaka0 */ 8988 case 129: 8989 return 213; /* rsr.ibreaka1 */ 8990 case 144: 8991 return 198; /* rsr.dbreaka0 */ 8992 case 145: 8993 return 204; /* rsr.dbreaka1 */ 8994 case 160: 8995 return 201; /* rsr.dbreakc0 */ 8996 case 161: 8997 return 207; /* rsr.dbreakc1 */ 8998 case 176: 8999 return 134; /* rsr.176 */ 9000 case 177: 9001 return 139; /* rsr.epc1 */ 9002 case 178: 9003 return 145; /* rsr.epc2 */ 9004 case 179: 9005 return 151; /* rsr.epc3 */ 9006 case 180: 9007 return 157; /* rsr.epc4 */ 9008 case 192: 9009 return 175; /* rsr.depc */ 9010 case 194: 9011 return 163; /* rsr.eps2 */ 9012 case 195: 9013 return 166; /* rsr.eps3 */ 9014 case 196: 9015 return 169; /* rsr.eps4 */ 9016 case 208: 9017 return 135; /* rsr.208 */ 9018 case 209: 9019 return 142; /* rsr.excsave1 */ 9020 case 210: 9021 return 148; /* rsr.excsave2 */ 9022 case 211: 9023 return 154; /* rsr.excsave3 */ 9024 case 212: 9025 return 160; /* rsr.excsave4 */ 9026 case 226: 9027 return 190; /* rsr.interrupt */ 9028 case 228: 9029 return 193; /* rsr.intenable */ 9030 case 230: 9031 return 136; /* rsr.ps */ 9032 case 232: 9033 return 178; /* rsr.exccause */ 9034 case 233: 9035 return 219; /* rsr.debugcause */ 9036 case 234: 9037 return 233; /* rsr.ccount */ 9038 case 235: 9039 return 187; /* rsr.prid */ 9040 case 236: 9041 return 222; /* rsr.icount */ 9042 case 237: 9043 return 225; /* rsr.icountlevel */ 9044 case 238: 9045 return 172; /* rsr.excvaddr */ 9046 case 240: 9047 return 236; /* rsr.ccompare0 */ 9048 case 241: 9049 return 239; /* rsr.ccompare1 */ 9050 case 242: 9051 return 242; /* rsr.ccompare2 */ 9052 case 244: 9053 return 181; /* rsr.misc0 */ 9054 case 245: 9055 return 184; /* rsr.misc1 */ 9056 } 9057 break; 9058 case 1: 9059 switch (Field_sr_Slot_inst_get (insn)) 9060 { 9061 case 0: 9062 return 126; /* wsr.lbeg */ 9063 case 1: 9064 return 120; /* wsr.lend */ 9065 case 2: 9066 return 123; /* wsr.lcount */ 9067 case 3: 9068 return 129; /* wsr.sar */ 9069 case 5: 9070 return 132; /* wsr.litbase */ 9071 case 72: 9072 return 21; /* wsr.windowbase */ 9073 case 73: 9074 return 24; /* wsr.windowstart */ 9075 case 83: 9076 return 264; /* wsr.ptevaddr */ 9077 case 90: 9078 return 268; /* wsr.rasid */ 9079 case 91: 9080 return 271; /* wsr.itlbcfg */ 9081 case 92: 9082 return 274; /* wsr.dtlbcfg */ 9083 case 96: 9084 return 217; /* wsr.ibreakenable */ 9085 case 104: 9086 return 229; /* wsr.ddr */ 9087 case 128: 9088 return 211; /* wsr.ibreaka0 */ 9089 case 129: 9090 return 214; /* wsr.ibreaka1 */ 9091 case 144: 9092 return 199; /* wsr.dbreaka0 */ 9093 case 145: 9094 return 205; /* wsr.dbreaka1 */ 9095 case 160: 9096 return 202; /* wsr.dbreakc0 */ 9097 case 161: 9098 return 208; /* wsr.dbreakc1 */ 9099 case 177: 9100 return 140; /* wsr.epc1 */ 9101 case 178: 9102 return 146; /* wsr.epc2 */ 9103 case 179: 9104 return 152; /* wsr.epc3 */ 9105 case 180: 9106 return 158; /* wsr.epc4 */ 9107 case 192: 9108 return 176; /* wsr.depc */ 9109 case 194: 9110 return 164; /* wsr.eps2 */ 9111 case 195: 9112 return 167; /* wsr.eps3 */ 9113 case 196: 9114 return 170; /* wsr.eps4 */ 9115 case 209: 9116 return 143; /* wsr.excsave1 */ 9117 case 210: 9118 return 149; /* wsr.excsave2 */ 9119 case 211: 9120 return 155; /* wsr.excsave3 */ 9121 case 212: 9122 return 161; /* wsr.excsave4 */ 9123 case 226: 9124 return 191; /* wsr.intset */ 9125 case 227: 9126 return 192; /* wsr.intclear */ 9127 case 228: 9128 return 194; /* wsr.intenable */ 9129 case 230: 9130 return 137; /* wsr.ps */ 9131 case 232: 9132 return 179; /* wsr.exccause */ 9133 case 233: 9134 return 220; /* wsr.debugcause */ 9135 case 234: 9136 return 234; /* wsr.ccount */ 9137 case 236: 9138 return 223; /* wsr.icount */ 9139 case 237: 9140 return 226; /* wsr.icountlevel */ 9141 case 238: 9142 return 173; /* wsr.excvaddr */ 9143 case 240: 9144 return 237; /* wsr.ccompare0 */ 9145 case 241: 9146 return 240; /* wsr.ccompare1 */ 9147 case 242: 9148 return 243; /* wsr.ccompare2 */ 9149 case 244: 9150 return 182; /* wsr.misc0 */ 9151 case 245: 9152 return 185; /* wsr.misc1 */ 9153 } 9154 break; 9155 case 8: 9156 return 89; /* moveqz */ 9157 case 9: 9158 return 90; /* movnez */ 9159 case 10: 9160 return 91; /* movltz */ 9161 case 11: 9162 return 92; /* movgez */ 9163 } 9164 break; 9165 case 4: 9166 case 5: 9167 return 76; /* extui */ 9168 case 9: 9169 switch (Field_op2_Slot_inst_get (insn)) 9170 { 9171 case 0: 9172 return 18; /* l32e */ 9173 case 4: 9174 return 19; /* s32e */ 9175 } 9176 break; 9177 } 9178 break; 9179 case 1: 9180 return 83; /* l32r */ 9181 case 2: 9182 switch (Field_r_Slot_inst_get (insn)) 9183 { 9184 case 0: 9185 return 84; /* l8ui */ 9186 case 1: 9187 return 80; /* l16ui */ 9188 case 2: 9189 return 82; /* l32i */ 9190 case 4: 9191 return 99; /* s8i */ 9192 case 5: 9193 return 97; /* s16i */ 9194 case 6: 9195 return 98; /* s32i */ 9196 case 7: 9197 switch (Field_t_Slot_inst_get (insn)) 9198 { 9199 case 0: 9200 return 258; /* dpfr */ 9201 case 1: 9202 return 259; /* dpfw */ 9203 case 2: 9204 return 260; /* dpfro */ 9205 case 3: 9206 return 261; /* dpfwo */ 9207 case 4: 9208 return 252; /* dhwb */ 9209 case 5: 9210 return 253; /* dhwbi */ 9211 case 6: 9212 return 256; /* dhi */ 9213 case 7: 9214 return 257; /* dii */ 9215 case 8: 9216 switch (Field_op1_Slot_inst_get (insn)) 9217 { 9218 case 4: 9219 return 254; /* diwb */ 9220 case 5: 9221 return 255; /* diwbi */ 9222 } 9223 break; 9224 case 12: 9225 return 245; /* ipf */ 9226 case 14: 9227 return 246; /* ihi */ 9228 case 15: 9229 return 247; /* iii */ 9230 } 9231 break; 9232 case 9: 9233 return 81; /* l16si */ 9234 case 10: 9235 return 88; /* movi */ 9236 case 12: 9237 return 37; /* addi */ 9238 case 13: 9239 return 38; /* addmi */ 9240 } 9241 break; 9242 case 5: 9243 switch (Field_n_Slot_inst_get (insn)) 9244 { 9245 case 0: 9246 return 74; /* call0 */ 9247 case 1: 9248 return 7; /* call4 */ 9249 case 2: 9250 return 6; /* call8 */ 9251 case 3: 9252 return 5; /* call12 */ 9253 } 9254 break; 9255 case 6: 9256 switch (Field_n_Slot_inst_get (insn)) 9257 { 9258 case 0: 9259 return 78; /* j */ 9260 case 1: 9261 switch (Field_m_Slot_inst_get (insn)) 9262 { 9263 case 0: 9264 return 70; /* beqz */ 9265 case 1: 9266 return 71; /* bnez */ 9267 case 2: 9268 return 73; /* bltz */ 9269 case 3: 9270 return 72; /* bgez */ 9271 } 9272 break; 9273 case 2: 9274 switch (Field_m_Slot_inst_get (insn)) 9275 { 9276 case 0: 9277 return 50; /* beqi */ 9278 case 1: 9279 return 51; /* bnei */ 9280 case 2: 9281 return 53; /* blti */ 9282 case 3: 9283 return 52; /* bgei */ 9284 } 9285 break; 9286 case 3: 9287 switch (Field_m_Slot_inst_get (insn)) 9288 { 9289 case 0: 9290 return 11; /* entry */ 9291 case 1: 9292 switch (Field_r_Slot_inst_get (insn)) 9293 { 9294 case 8: 9295 return 85; /* loop */ 9296 case 9: 9297 return 86; /* loopnez */ 9298 case 10: 9299 return 87; /* loopgtz */ 9300 } 9301 break; 9302 case 2: 9303 return 57; /* bltui */ 9304 case 3: 9305 return 56; /* bgeui */ 9306 } 9307 break; 9308 } 9309 break; 9310 case 7: 9311 switch (Field_r_Slot_inst_get (insn)) 9312 { 9313 case 0: 9314 return 65; /* bnone */ 9315 case 1: 9316 return 58; /* beq */ 9317 case 2: 9318 return 61; /* blt */ 9319 case 3: 9320 return 63; /* bltu */ 9321 case 4: 9322 return 66; /* ball */ 9323 case 5: 9324 return 68; /* bbc */ 9325 case 6: 9326 case 7: 9327 return 54; /* bbci */ 9328 case 8: 9329 return 64; /* bany */ 9330 case 9: 9331 return 59; /* bne */ 9332 case 10: 9333 return 60; /* bge */ 9334 case 11: 9335 return 62; /* bgeu */ 9336 case 12: 9337 return 67; /* bnall */ 9338 case 13: 9339 return 69; /* bbs */ 9340 case 14: 9341 case 15: 9342 return 55; /* bbsi */ 9343 } 9344 break; 9345 } 9346 return XTENSA_UNDEFINED; 9347} 9348 9349static int 9350Slot_inst16b_decode (const xtensa_insnbuf insn) 9351{ 9352 switch (Field_op0_Slot_inst16b_get (insn)) 9353 { 9354 case 12: 9355 switch (Field_i_Slot_inst16b_get (insn)) 9356 { 9357 case 0: 9358 return 33; /* movi.n */ 9359 case 1: 9360 switch (Field_z_Slot_inst16b_get (insn)) 9361 { 9362 case 0: 9363 return 28; /* beqz.n */ 9364 case 1: 9365 return 29; /* bnez.n */ 9366 } 9367 break; 9368 } 9369 break; 9370 case 13: 9371 switch (Field_r_Slot_inst16b_get (insn)) 9372 { 9373 case 0: 9374 return 32; /* mov.n */ 9375 case 15: 9376 switch (Field_t_Slot_inst16b_get (insn)) 9377 { 9378 case 0: 9379 return 35; /* ret.n */ 9380 case 1: 9381 return 15; /* retw.n */ 9382 case 2: 9383 return 197; /* break.n */ 9384 case 3: 9385 if (Field_s_Slot_inst16b_get (insn) == 0) 9386 return 34; /* nop.n */ 9387 break; 9388 case 6: 9389 if (Field_s_Slot_inst16b_get (insn) == 0) 9390 return 30; /* ill.n */ 9391 break; 9392 } 9393 break; 9394 } 9395 break; 9396 } 9397 return XTENSA_UNDEFINED; 9398} 9399 9400static int 9401Slot_inst16a_decode (const xtensa_insnbuf insn) 9402{ 9403 switch (Field_op0_Slot_inst16a_get (insn)) 9404 { 9405 case 8: 9406 return 31; /* l32i.n */ 9407 case 9: 9408 return 36; /* s32i.n */ 9409 case 10: 9410 return 26; /* add.n */ 9411 case 11: 9412 return 27; /* addi.n */ 9413 } 9414 return XTENSA_UNDEFINED; 9415} 9416 9417 9418/* Instruction slots. */ 9419 9420static void 9421Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, 9422 xtensa_insnbuf slotbuf) 9423{ 9424 slotbuf[0] = (insn[0] & 0xffffff); 9425} 9426 9427static void 9428Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, 9429 const xtensa_insnbuf slotbuf) 9430{ 9431 insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); 9432} 9433 9434static void 9435Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, 9436 xtensa_insnbuf slotbuf) 9437{ 9438 slotbuf[0] = ((insn[0] & 0xffff00) >> 8); 9439} 9440 9441static void 9442Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, 9443 const xtensa_insnbuf slotbuf) 9444{ 9445 insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8); 9446} 9447 9448static void 9449Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, 9450 xtensa_insnbuf slotbuf) 9451{ 9452 slotbuf[0] = ((insn[0] & 0xffff00) >> 8); 9453} 9454 9455static void 9456Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, 9457 const xtensa_insnbuf slotbuf) 9458{ 9459 insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8); 9460} 9461 9462static xtensa_get_field_fn 9463Slot_inst_get_field_fns[] = { 9464 Field_t_Slot_inst_get, 9465 Field_bbi4_Slot_inst_get, 9466 Field_bbi_Slot_inst_get, 9467 Field_imm12_Slot_inst_get, 9468 Field_imm8_Slot_inst_get, 9469 Field_s_Slot_inst_get, 9470 Field_imm12b_Slot_inst_get, 9471 Field_imm16_Slot_inst_get, 9472 Field_m_Slot_inst_get, 9473 Field_n_Slot_inst_get, 9474 Field_offset_Slot_inst_get, 9475 Field_op0_Slot_inst_get, 9476 Field_op1_Slot_inst_get, 9477 Field_op2_Slot_inst_get, 9478 Field_r_Slot_inst_get, 9479 Field_sa4_Slot_inst_get, 9480 Field_sae4_Slot_inst_get, 9481 Field_sae_Slot_inst_get, 9482 Field_sal_Slot_inst_get, 9483 Field_sargt_Slot_inst_get, 9484 Field_sas4_Slot_inst_get, 9485 Field_sas_Slot_inst_get, 9486 Field_sr_Slot_inst_get, 9487 Field_st_Slot_inst_get, 9488 Field_thi3_Slot_inst_get, 9489 Field_imm4_Slot_inst_get, 9490 Field_mn_Slot_inst_get, 9491 0, 9492 0, 9493 0, 9494 0, 9495 0, 9496 0, 9497 0, 9498 0, 9499 Implicit_Field_ar0_get, 9500 Implicit_Field_ar4_get, 9501 Implicit_Field_ar8_get, 9502 Implicit_Field_ar12_get 9503}; 9504 9505static xtensa_set_field_fn 9506Slot_inst_set_field_fns[] = { 9507 Field_t_Slot_inst_set, 9508 Field_bbi4_Slot_inst_set, 9509 Field_bbi_Slot_inst_set, 9510 Field_imm12_Slot_inst_set, 9511 Field_imm8_Slot_inst_set, 9512 Field_s_Slot_inst_set, 9513 Field_imm12b_Slot_inst_set, 9514 Field_imm16_Slot_inst_set, 9515 Field_m_Slot_inst_set, 9516 Field_n_Slot_inst_set, 9517 Field_offset_Slot_inst_set, 9518 Field_op0_Slot_inst_set, 9519 Field_op1_Slot_inst_set, 9520 Field_op2_Slot_inst_set, 9521 Field_r_Slot_inst_set, 9522 Field_sa4_Slot_inst_set, 9523 Field_sae4_Slot_inst_set, 9524 Field_sae_Slot_inst_set, 9525 Field_sal_Slot_inst_set, 9526 Field_sargt_Slot_inst_set, 9527 Field_sas4_Slot_inst_set, 9528 Field_sas_Slot_inst_set, 9529 Field_sr_Slot_inst_set, 9530 Field_st_Slot_inst_set, 9531 Field_thi3_Slot_inst_set, 9532 Field_imm4_Slot_inst_set, 9533 Field_mn_Slot_inst_set, 9534 0, 9535 0, 9536 0, 9537 0, 9538 0, 9539 0, 9540 0, 9541 0, 9542 Implicit_Field_set, 9543 Implicit_Field_set, 9544 Implicit_Field_set, 9545 Implicit_Field_set 9546}; 9547 9548static xtensa_get_field_fn 9549Slot_inst16a_get_field_fns[] = { 9550 Field_t_Slot_inst16a_get, 9551 0, 9552 0, 9553 0, 9554 0, 9555 Field_s_Slot_inst16a_get, 9556 0, 9557 0, 9558 0, 9559 0, 9560 0, 9561 Field_op0_Slot_inst16a_get, 9562 0, 9563 0, 9564 Field_r_Slot_inst16a_get, 9565 0, 9566 0, 9567 0, 9568 0, 9569 0, 9570 0, 9571 0, 9572 Field_sr_Slot_inst16a_get, 9573 Field_st_Slot_inst16a_get, 9574 0, 9575 Field_imm4_Slot_inst16a_get, 9576 0, 9577 Field_i_Slot_inst16a_get, 9578 Field_imm6lo_Slot_inst16a_get, 9579 Field_imm6hi_Slot_inst16a_get, 9580 Field_imm7lo_Slot_inst16a_get, 9581 Field_imm7hi_Slot_inst16a_get, 9582 Field_z_Slot_inst16a_get, 9583 Field_imm6_Slot_inst16a_get, 9584 Field_imm7_Slot_inst16a_get, 9585 Implicit_Field_ar0_get, 9586 Implicit_Field_ar4_get, 9587 Implicit_Field_ar8_get, 9588 Implicit_Field_ar12_get 9589}; 9590 9591static xtensa_set_field_fn 9592Slot_inst16a_set_field_fns[] = { 9593 Field_t_Slot_inst16a_set, 9594 0, 9595 0, 9596 0, 9597 0, 9598 Field_s_Slot_inst16a_set, 9599 0, 9600 0, 9601 0, 9602 0, 9603 0, 9604 Field_op0_Slot_inst16a_set, 9605 0, 9606 0, 9607 Field_r_Slot_inst16a_set, 9608 0, 9609 0, 9610 0, 9611 0, 9612 0, 9613 0, 9614 0, 9615 Field_sr_Slot_inst16a_set, 9616 Field_st_Slot_inst16a_set, 9617 0, 9618 Field_imm4_Slot_inst16a_set, 9619 0, 9620 Field_i_Slot_inst16a_set, 9621 Field_imm6lo_Slot_inst16a_set, 9622 Field_imm6hi_Slot_inst16a_set, 9623 Field_imm7lo_Slot_inst16a_set, 9624 Field_imm7hi_Slot_inst16a_set, 9625 Field_z_Slot_inst16a_set, 9626 Field_imm6_Slot_inst16a_set, 9627 Field_imm7_Slot_inst16a_set, 9628 Implicit_Field_set, 9629 Implicit_Field_set, 9630 Implicit_Field_set, 9631 Implicit_Field_set 9632}; 9633 9634static xtensa_get_field_fn 9635Slot_inst16b_get_field_fns[] = { 9636 Field_t_Slot_inst16b_get, 9637 0, 9638 0, 9639 0, 9640 0, 9641 Field_s_Slot_inst16b_get, 9642 0, 9643 0, 9644 0, 9645 0, 9646 0, 9647 Field_op0_Slot_inst16b_get, 9648 0, 9649 0, 9650 Field_r_Slot_inst16b_get, 9651 0, 9652 0, 9653 0, 9654 0, 9655 0, 9656 0, 9657 0, 9658 Field_sr_Slot_inst16b_get, 9659 Field_st_Slot_inst16b_get, 9660 0, 9661 Field_imm4_Slot_inst16b_get, 9662 0, 9663 Field_i_Slot_inst16b_get, 9664 Field_imm6lo_Slot_inst16b_get, 9665 Field_imm6hi_Slot_inst16b_get, 9666 Field_imm7lo_Slot_inst16b_get, 9667 Field_imm7hi_Slot_inst16b_get, 9668 Field_z_Slot_inst16b_get, 9669 Field_imm6_Slot_inst16b_get, 9670 Field_imm7_Slot_inst16b_get, 9671 Implicit_Field_ar0_get, 9672 Implicit_Field_ar4_get, 9673 Implicit_Field_ar8_get, 9674 Implicit_Field_ar12_get 9675}; 9676 9677static xtensa_set_field_fn 9678Slot_inst16b_set_field_fns[] = { 9679 Field_t_Slot_inst16b_set, 9680 0, 9681 0, 9682 0, 9683 0, 9684 Field_s_Slot_inst16b_set, 9685 0, 9686 0, 9687 0, 9688 0, 9689 0, 9690 Field_op0_Slot_inst16b_set, 9691 0, 9692 0, 9693 Field_r_Slot_inst16b_set, 9694 0, 9695 0, 9696 0, 9697 0, 9698 0, 9699 0, 9700 0, 9701 Field_sr_Slot_inst16b_set, 9702 Field_st_Slot_inst16b_set, 9703 0, 9704 Field_imm4_Slot_inst16b_set, 9705 0, 9706 Field_i_Slot_inst16b_set, 9707 Field_imm6lo_Slot_inst16b_set, 9708 Field_imm6hi_Slot_inst16b_set, 9709 Field_imm7lo_Slot_inst16b_set, 9710 Field_imm7hi_Slot_inst16b_set, 9711 Field_z_Slot_inst16b_set, 9712 Field_imm6_Slot_inst16b_set, 9713 Field_imm7_Slot_inst16b_set, 9714 Implicit_Field_set, 9715 Implicit_Field_set, 9716 Implicit_Field_set, 9717 Implicit_Field_set 9718}; 9719 9720static xtensa_slot_internal slots[] = { 9721 { "Inst", "x24", 0, 9722 Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, 9723 Slot_inst_get_field_fns, Slot_inst_set_field_fns, 9724 Slot_inst_decode, "nop" }, 9725 { "Inst16a", "x16a", 0, 9726 Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, 9727 Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, 9728 Slot_inst16a_decode, "" }, 9729 { "Inst16b", "x16b", 0, 9730 Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, 9731 Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, 9732 Slot_inst16b_decode, "nop.n" } 9733}; 9734 9735 9736/* Instruction formats. */ 9737 9738static void 9739Format_x24_encode (xtensa_insnbuf insn) 9740{ 9741 insn[0] = 0; 9742} 9743 9744static void 9745Format_x16a_encode (xtensa_insnbuf insn) 9746{ 9747 insn[0] = 0x800000; 9748} 9749 9750static void 9751Format_x16b_encode (xtensa_insnbuf insn) 9752{ 9753 insn[0] = 0xc00000; 9754} 9755 9756static int Format_x24_slots[] = { 0 }; 9757 9758static int Format_x16a_slots[] = { 1 }; 9759 9760static int Format_x16b_slots[] = { 2 }; 9761 9762static xtensa_format_internal formats[] = { 9763 { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, 9764 { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, 9765 { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots } 9766}; 9767 9768 9769static int 9770format_decoder (const xtensa_insnbuf insn) 9771{ 9772 if ((insn[0] & 0x800000) == 0) 9773 return 0; /* x24 */ 9774 if ((insn[0] & 0xc00000) == 0x800000) 9775 return 1; /* x16a */ 9776 if ((insn[0] & 0xe00000) == 0xc00000) 9777 return 2; /* x16b */ 9778 return -1; 9779} 9780 9781static int length_table[16] = { 9782 3, 9783 3, 9784 3, 9785 3, 9786 3, 9787 3, 9788 3, 9789 3, 9790 2, 9791 2, 9792 2, 9793 2, 9794 2, 9795 2, 9796 -1, 9797 -1 9798}; 9799 9800static int 9801length_decoder (const unsigned char *insn) 9802{ 9803 int op0 = (insn[0] >> 4) & 0xf; 9804 return length_table[op0]; 9805} 9806 9807 9808/* Top-level ISA structure. */ 9809 9810xtensa_isa_internal xtensa_modules = { 9811 1 /* big-endian */, 9812 3 /* insn_size */, 0, 9813 3, formats, format_decoder, length_decoder, 9814 3, slots, 9815 39 /* num_fields */, 9816 70, operands, 9817 235, iclasses, 9818 291, opcodes, 0, 9819 1, regfiles, 9820 NUM_STATES, states, 0, 9821 NUM_SYSREGS, sysregs, 0, 9822 { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, 9823 0, interfaces, 0, 9824 0, funcUnits, 0 9825}; 9826