1/* Xtensa configuration-specific ISA information. 2 Copyright 2003, 2004, 2005 Free Software Foundation, Inc. 3 4 This file is part of BFD, the Binary File Descriptor library. 5 6 This program is free software; you can redistribute it and/or 7 modify it under the terms of the GNU General Public License as 8 published by the Free Software Foundation; either version 2 of the 9 License, or (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, see 18 <https://www.gnu.org/licenses/>. */ 19 20#include "qemu/osdep.h" 21#include "xtensa-isa.h" 22#include "xtensa-isa-internal.h" 23 24 25/* Sysregs. */ 26 27static xtensa_sysreg_internal sysregs[] = { 28 { "LBEG", 0, 0 }, 29 { "LEND", 1, 0 }, 30 { "LCOUNT", 2, 0 }, 31 { "ACCLO", 16, 0 }, 32 { "ACCHI", 17, 0 }, 33 { "M0", 32, 0 }, 34 { "M1", 33, 0 }, 35 { "M2", 34, 0 }, 36 { "M3", 35, 0 }, 37 { "PTEVADDR", 83, 0 }, 38 { "MMID", 89, 0 }, 39 { "DDR", 104, 0 }, 40 { "176", 176, 0 }, 41 { "208", 208, 0 }, 42 { "INTERRUPT", 226, 0 }, 43 { "INTCLEAR", 227, 0 }, 44 { "CCOUNT", 234, 0 }, 45 { "PRID", 235, 0 }, 46 { "ICOUNT", 236, 0 }, 47 { "CCOMPARE0", 240, 0 }, 48 { "CCOMPARE1", 241, 0 }, 49 { "CCOMPARE2", 242, 0 }, 50 { "VECBASE", 231, 0 }, 51 { "EPC1", 177, 0 }, 52 { "EPC2", 178, 0 }, 53 { "EPC3", 179, 0 }, 54 { "EPC4", 180, 0 }, 55 { "EPC5", 181, 0 }, 56 { "EPC6", 182, 0 }, 57 { "EPC7", 183, 0 }, 58 { "EXCSAVE1", 209, 0 }, 59 { "EXCSAVE2", 210, 0 }, 60 { "EXCSAVE3", 211, 0 }, 61 { "EXCSAVE4", 212, 0 }, 62 { "EXCSAVE5", 213, 0 }, 63 { "EXCSAVE6", 214, 0 }, 64 { "EXCSAVE7", 215, 0 }, 65 { "EPS2", 194, 0 }, 66 { "EPS3", 195, 0 }, 67 { "EPS4", 196, 0 }, 68 { "EPS5", 197, 0 }, 69 { "EPS6", 198, 0 }, 70 { "EPS7", 199, 0 }, 71 { "EXCCAUSE", 232, 0 }, 72 { "DEPC", 192, 0 }, 73 { "EXCVADDR", 238, 0 }, 74 { "WINDOWBASE", 72, 0 }, 75 { "WINDOWSTART", 73, 0 }, 76 { "SAR", 3, 0 }, 77 { "LITBASE", 5, 0 }, 78 { "PS", 230, 0 }, 79 { "MISC0", 244, 0 }, 80 { "MISC1", 245, 0 }, 81 { "INTENABLE", 228, 0 }, 82 { "DBREAKA0", 144, 0 }, 83 { "DBREAKC0", 160, 0 }, 84 { "DBREAKA1", 145, 0 }, 85 { "DBREAKC1", 161, 0 }, 86 { "IBREAKA0", 128, 0 }, 87 { "IBREAKA1", 129, 0 }, 88 { "IBREAKENABLE", 96, 0 }, 89 { "ICOUNTLEVEL", 237, 0 }, 90 { "DEBUGCAUSE", 233, 0 }, 91 { "RASID", 90, 0 }, 92 { "ITLBCFG", 91, 0 }, 93 { "DTLBCFG", 92, 0 }, 94 { "CPENABLE", 224, 0 }, 95 { "SCOMPARE1", 12, 0 }, 96 { "THREADPTR", 231, 1 }, 97 { "EXPSTATE", 230, 1 } 98}; 99 100#define NUM_SYSREGS 70 101#define MAX_SPECIAL_REG 245 102#define MAX_USER_REG 231 103 104 105/* Processor states. */ 106 107static xtensa_state_internal states[] = { 108 { "LCOUNT", 32, 0 }, 109 { "PC", 32, 0 }, 110 { "ICOUNT", 32, 0 }, 111 { "DDR", 32, 0 }, 112 { "INTERRUPT", 22, 0 }, 113 { "CCOUNT", 32, 0 }, 114 { "XTSYNC", 1, 0 }, 115 { "VECBASE", 22, 0 }, 116 { "EPC1", 32, 0 }, 117 { "EPC2", 32, 0 }, 118 { "EPC3", 32, 0 }, 119 { "EPC4", 32, 0 }, 120 { "EPC5", 32, 0 }, 121 { "EPC6", 32, 0 }, 122 { "EPC7", 32, 0 }, 123 { "EXCSAVE1", 32, 0 }, 124 { "EXCSAVE2", 32, 0 }, 125 { "EXCSAVE3", 32, 0 }, 126 { "EXCSAVE4", 32, 0 }, 127 { "EXCSAVE5", 32, 0 }, 128 { "EXCSAVE6", 32, 0 }, 129 { "EXCSAVE7", 32, 0 }, 130 { "EPS2", 15, 0 }, 131 { "EPS3", 15, 0 }, 132 { "EPS4", 15, 0 }, 133 { "EPS5", 15, 0 }, 134 { "EPS6", 15, 0 }, 135 { "EPS7", 15, 0 }, 136 { "EXCCAUSE", 6, 0 }, 137 { "PSINTLEVEL", 4, 0 }, 138 { "PSUM", 1, 0 }, 139 { "PSWOE", 1, 0 }, 140 { "PSRING", 2, 0 }, 141 { "PSEXCM", 1, 0 }, 142 { "DEPC", 32, 0 }, 143 { "EXCVADDR", 32, 0 }, 144 { "WindowBase", 3, 0 }, 145 { "WindowStart", 8, 0 }, 146 { "PSCALLINC", 2, 0 }, 147 { "PSOWB", 4, 0 }, 148 { "LBEG", 32, 0 }, 149 { "LEND", 32, 0 }, 150 { "SAR", 6, 0 }, 151 { "THREADPTR", 32, 0 }, 152 { "LITBADDR", 20, 0 }, 153 { "LITBEN", 1, 0 }, 154 { "MISC0", 32, 0 }, 155 { "MISC1", 32, 0 }, 156 { "ACC", 40, 0 }, 157 { "InOCDMode", 1, 0 }, 158 { "INTENABLE", 22, 0 }, 159 { "DBREAKA0", 32, 0 }, 160 { "DBREAKC0", 8, 0 }, 161 { "DBREAKA1", 32, 0 }, 162 { "DBREAKC1", 8, 0 }, 163 { "IBREAKA0", 32, 0 }, 164 { "IBREAKA1", 32, 0 }, 165 { "IBREAKENABLE", 2, 0 }, 166 { "ICOUNTLEVEL", 4, 0 }, 167 { "DEBUGCAUSE", 6, 0 }, 168 { "DBNUM", 4, 0 }, 169 { "CCOMPARE0", 32, 0 }, 170 { "CCOMPARE1", 32, 0 }, 171 { "CCOMPARE2", 32, 0 }, 172 { "ASID3", 8, 0 }, 173 { "ASID2", 8, 0 }, 174 { "ASID1", 8, 0 }, 175 { "INSTPGSZID4", 2, 0 }, 176 { "DATAPGSZID4", 2, 0 }, 177 { "PTBASE", 10, 0 }, 178 { "CPENABLE", 8, 0 }, 179 { "SCOMPARE1", 32, 0 }, 180 { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED } 181}; 182 183#define NUM_STATES 73 184 185/* Macros for xtensa_state numbers (for use in iclasses because the 186 state numbers are not available when the iclass table is generated). */ 187 188#define STATE_LCOUNT 0 189#define STATE_PC 1 190#define STATE_ICOUNT 2 191#define STATE_DDR 3 192#define STATE_INTERRUPT 4 193#define STATE_CCOUNT 5 194#define STATE_XTSYNC 6 195#define STATE_VECBASE 7 196#define STATE_EPC1 8 197#define STATE_EPC2 9 198#define STATE_EPC3 10 199#define STATE_EPC4 11 200#define STATE_EPC5 12 201#define STATE_EPC6 13 202#define STATE_EPC7 14 203#define STATE_EXCSAVE1 15 204#define STATE_EXCSAVE2 16 205#define STATE_EXCSAVE3 17 206#define STATE_EXCSAVE4 18 207#define STATE_EXCSAVE5 19 208#define STATE_EXCSAVE6 20 209#define STATE_EXCSAVE7 21 210#define STATE_EPS2 22 211#define STATE_EPS3 23 212#define STATE_EPS4 24 213#define STATE_EPS5 25 214#define STATE_EPS6 26 215#define STATE_EPS7 27 216#define STATE_EXCCAUSE 28 217#define STATE_PSINTLEVEL 29 218#define STATE_PSUM 30 219#define STATE_PSWOE 31 220#define STATE_PSRING 32 221#define STATE_PSEXCM 33 222#define STATE_DEPC 34 223#define STATE_EXCVADDR 35 224#define STATE_WindowBase 36 225#define STATE_WindowStart 37 226#define STATE_PSCALLINC 38 227#define STATE_PSOWB 39 228#define STATE_LBEG 40 229#define STATE_LEND 41 230#define STATE_SAR 42 231#define STATE_THREADPTR 43 232#define STATE_LITBADDR 44 233#define STATE_LITBEN 45 234#define STATE_MISC0 46 235#define STATE_MISC1 47 236#define STATE_ACC 48 237#define STATE_InOCDMode 49 238#define STATE_INTENABLE 50 239#define STATE_DBREAKA0 51 240#define STATE_DBREAKC0 52 241#define STATE_DBREAKA1 53 242#define STATE_DBREAKC1 54 243#define STATE_IBREAKA0 55 244#define STATE_IBREAKA1 56 245#define STATE_IBREAKENABLE 57 246#define STATE_ICOUNTLEVEL 58 247#define STATE_DEBUGCAUSE 59 248#define STATE_DBNUM 60 249#define STATE_CCOMPARE0 61 250#define STATE_CCOMPARE1 62 251#define STATE_CCOMPARE2 63 252#define STATE_ASID3 64 253#define STATE_ASID2 65 254#define STATE_ASID1 66 255#define STATE_INSTPGSZID4 67 256#define STATE_DATAPGSZID4 68 257#define STATE_PTBASE 69 258#define STATE_CPENABLE 70 259#define STATE_SCOMPARE1 71 260#define STATE_EXPSTATE 72 261 262 263/* Field definitions. */ 264 265static unsigned 266Field_t_Slot_inst_get (const xtensa_insnbuf insn) 267{ 268 unsigned tie_t = 0; 269 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 270 return tie_t; 271} 272 273static void 274Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 275{ 276 uint32 tie_t; 277 tie_t = (val << 28) >> 28; 278 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 279} 280 281static unsigned 282Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) 283{ 284 unsigned tie_t = 0; 285 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 286 return tie_t; 287} 288 289static void 290Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 291{ 292 uint32 tie_t; 293 tie_t = (val << 28) >> 28; 294 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 295} 296 297static unsigned 298Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) 299{ 300 unsigned tie_t = 0; 301 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 302 return tie_t; 303} 304 305static void 306Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 307{ 308 uint32 tie_t; 309 tie_t = (val << 28) >> 28; 310 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 311} 312 313static unsigned 314Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) 315{ 316 unsigned tie_t = 0; 317 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); 318 return tie_t; 319} 320 321static void 322Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 323{ 324 uint32 tie_t; 325 tie_t = (val << 31) >> 31; 326 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); 327} 328 329static unsigned 330Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) 331{ 332 unsigned tie_t = 0; 333 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); 334 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 335 return tie_t; 336} 337 338static void 339Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 340{ 341 uint32 tie_t; 342 tie_t = (val << 28) >> 28; 343 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 344 tie_t = (val << 27) >> 31; 345 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); 346} 347 348static unsigned 349Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) 350{ 351 unsigned tie_t = 0; 352 tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); 353 return tie_t; 354} 355 356static void 357Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 358{ 359 uint32 tie_t; 360 tie_t = (val << 20) >> 20; 361 insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); 362} 363 364static unsigned 365Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) 366{ 367 unsigned tie_t = 0; 368 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); 369 return tie_t; 370} 371 372static void 373Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 374{ 375 uint32 tie_t; 376 tie_t = (val << 24) >> 24; 377 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); 378} 379 380static unsigned 381Field_s_Slot_inst_get (const xtensa_insnbuf insn) 382{ 383 unsigned tie_t = 0; 384 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 385 return tie_t; 386} 387 388static void 389Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 390{ 391 uint32 tie_t; 392 tie_t = (val << 28) >> 28; 393 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 394} 395 396static unsigned 397Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) 398{ 399 unsigned tie_t = 0; 400 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 401 return tie_t; 402} 403 404static void 405Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 406{ 407 uint32 tie_t; 408 tie_t = (val << 28) >> 28; 409 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 410} 411 412static unsigned 413Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) 414{ 415 unsigned tie_t = 0; 416 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 417 return tie_t; 418} 419 420static void 421Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 422{ 423 uint32 tie_t; 424 tie_t = (val << 28) >> 28; 425 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 426} 427 428static unsigned 429Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) 430{ 431 unsigned tie_t = 0; 432 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 433 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); 434 return tie_t; 435} 436 437static void 438Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 439{ 440 uint32 tie_t; 441 tie_t = (val << 24) >> 24; 442 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); 443 tie_t = (val << 20) >> 28; 444 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 445} 446 447static unsigned 448Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) 449{ 450 unsigned tie_t = 0; 451 tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); 452 return tie_t; 453} 454 455static void 456Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 457{ 458 uint32 tie_t; 459 tie_t = (val << 16) >> 16; 460 insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); 461} 462 463static unsigned 464Field_m_Slot_inst_get (const xtensa_insnbuf insn) 465{ 466 unsigned tie_t = 0; 467 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); 468 return tie_t; 469} 470 471static void 472Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 473{ 474 uint32 tie_t; 475 tie_t = (val << 30) >> 30; 476 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); 477} 478 479static unsigned 480Field_n_Slot_inst_get (const xtensa_insnbuf insn) 481{ 482 unsigned tie_t = 0; 483 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); 484 return tie_t; 485} 486 487static void 488Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 489{ 490 uint32 tie_t; 491 tie_t = (val << 30) >> 30; 492 insn[0] = (insn[0] & ~0x30) | (tie_t << 4); 493} 494 495static unsigned 496Field_offset_Slot_inst_get (const xtensa_insnbuf insn) 497{ 498 unsigned tie_t = 0; 499 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); 500 return tie_t; 501} 502 503static void 504Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 505{ 506 uint32 tie_t; 507 tie_t = (val << 14) >> 14; 508 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); 509} 510 511static unsigned 512Field_op0_Slot_inst_get (const xtensa_insnbuf insn) 513{ 514 unsigned tie_t = 0; 515 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 516 return tie_t; 517} 518 519static void 520Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 521{ 522 uint32 tie_t; 523 tie_t = (val << 28) >> 28; 524 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 525} 526 527static unsigned 528Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) 529{ 530 unsigned tie_t = 0; 531 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 532 return tie_t; 533} 534 535static void 536Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 537{ 538 uint32 tie_t; 539 tie_t = (val << 28) >> 28; 540 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 541} 542 543static unsigned 544Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) 545{ 546 unsigned tie_t = 0; 547 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 548 return tie_t; 549} 550 551static void 552Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 553{ 554 uint32 tie_t; 555 tie_t = (val << 28) >> 28; 556 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 557} 558 559static unsigned 560Field_op1_Slot_inst_get (const xtensa_insnbuf insn) 561{ 562 unsigned tie_t = 0; 563 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); 564 return tie_t; 565} 566 567static void 568Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 569{ 570 uint32 tie_t; 571 tie_t = (val << 28) >> 28; 572 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); 573} 574 575static unsigned 576Field_op2_Slot_inst_get (const xtensa_insnbuf insn) 577{ 578 unsigned tie_t = 0; 579 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); 580 return tie_t; 581} 582 583static void 584Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 585{ 586 uint32 tie_t; 587 tie_t = (val << 28) >> 28; 588 insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); 589} 590 591static unsigned 592Field_r_Slot_inst_get (const xtensa_insnbuf insn) 593{ 594 unsigned tie_t = 0; 595 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 596 return tie_t; 597} 598 599static void 600Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 601{ 602 uint32 tie_t; 603 tie_t = (val << 28) >> 28; 604 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 605} 606 607static unsigned 608Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) 609{ 610 unsigned tie_t = 0; 611 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 612 return tie_t; 613} 614 615static void 616Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 617{ 618 uint32 tie_t; 619 tie_t = (val << 28) >> 28; 620 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 621} 622 623static unsigned 624Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) 625{ 626 unsigned tie_t = 0; 627 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 628 return tie_t; 629} 630 631static void 632Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 633{ 634 uint32 tie_t; 635 tie_t = (val << 28) >> 28; 636 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 637} 638 639static unsigned 640Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) 641{ 642 unsigned tie_t = 0; 643 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); 644 return tie_t; 645} 646 647static void 648Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 649{ 650 uint32 tie_t; 651 tie_t = (val << 31) >> 31; 652 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); 653} 654 655static unsigned 656Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) 657{ 658 unsigned tie_t = 0; 659 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); 660 return tie_t; 661} 662 663static void 664Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 665{ 666 uint32 tie_t; 667 tie_t = (val << 31) >> 31; 668 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); 669} 670 671static unsigned 672Field_sae_Slot_inst_get (const xtensa_insnbuf insn) 673{ 674 unsigned tie_t = 0; 675 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); 676 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 677 return tie_t; 678} 679 680static void 681Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 682{ 683 uint32 tie_t; 684 tie_t = (val << 28) >> 28; 685 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 686 tie_t = (val << 27) >> 31; 687 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); 688} 689 690static unsigned 691Field_sal_Slot_inst_get (const xtensa_insnbuf insn) 692{ 693 unsigned tie_t = 0; 694 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); 695 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 696 return tie_t; 697} 698 699static void 700Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 701{ 702 uint32 tie_t; 703 tie_t = (val << 28) >> 28; 704 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 705 tie_t = (val << 27) >> 31; 706 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); 707} 708 709static unsigned 710Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) 711{ 712 unsigned tie_t = 0; 713 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); 714 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 715 return tie_t; 716} 717 718static void 719Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 720{ 721 uint32 tie_t; 722 tie_t = (val << 28) >> 28; 723 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 724 tie_t = (val << 27) >> 31; 725 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); 726} 727 728static unsigned 729Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) 730{ 731 unsigned tie_t = 0; 732 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); 733 return tie_t; 734} 735 736static void 737Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 738{ 739 uint32 tie_t; 740 tie_t = (val << 31) >> 31; 741 insn[0] = (insn[0] & ~0x10) | (tie_t << 4); 742} 743 744static unsigned 745Field_sas_Slot_inst_get (const xtensa_insnbuf insn) 746{ 747 unsigned tie_t = 0; 748 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); 749 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 750 return tie_t; 751} 752 753static void 754Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 755{ 756 uint32 tie_t; 757 tie_t = (val << 28) >> 28; 758 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 759 tie_t = (val << 27) >> 31; 760 insn[0] = (insn[0] & ~0x10) | (tie_t << 4); 761} 762 763static unsigned 764Field_sr_Slot_inst_get (const xtensa_insnbuf insn) 765{ 766 unsigned tie_t = 0; 767 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 768 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 769 return tie_t; 770} 771 772static void 773Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 774{ 775 uint32 tie_t; 776 tie_t = (val << 28) >> 28; 777 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 778 tie_t = (val << 24) >> 28; 779 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 780} 781 782static unsigned 783Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) 784{ 785 unsigned tie_t = 0; 786 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 787 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 788 return tie_t; 789} 790 791static void 792Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 793{ 794 uint32 tie_t; 795 tie_t = (val << 28) >> 28; 796 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 797 tie_t = (val << 24) >> 28; 798 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 799} 800 801static unsigned 802Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) 803{ 804 unsigned tie_t = 0; 805 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 806 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 807 return tie_t; 808} 809 810static void 811Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 812{ 813 uint32 tie_t; 814 tie_t = (val << 28) >> 28; 815 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 816 tie_t = (val << 24) >> 28; 817 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 818} 819 820static unsigned 821Field_st_Slot_inst_get (const xtensa_insnbuf insn) 822{ 823 unsigned tie_t = 0; 824 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 825 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 826 return tie_t; 827} 828 829static void 830Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 831{ 832 uint32 tie_t; 833 tie_t = (val << 28) >> 28; 834 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 835 tie_t = (val << 24) >> 28; 836 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 837} 838 839static unsigned 840Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) 841{ 842 unsigned tie_t = 0; 843 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 844 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 845 return tie_t; 846} 847 848static void 849Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 850{ 851 uint32 tie_t; 852 tie_t = (val << 28) >> 28; 853 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 854 tie_t = (val << 24) >> 28; 855 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 856} 857 858static unsigned 859Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) 860{ 861 unsigned tie_t = 0; 862 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 863 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 864 return tie_t; 865} 866 867static void 868Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 869{ 870 uint32 tie_t; 871 tie_t = (val << 28) >> 28; 872 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 873 tie_t = (val << 24) >> 28; 874 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 875} 876 877static unsigned 878Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) 879{ 880 unsigned tie_t = 0; 881 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); 882 return tie_t; 883} 884 885static void 886Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 887{ 888 uint32 tie_t; 889 tie_t = (val << 29) >> 29; 890 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); 891} 892 893static unsigned 894Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) 895{ 896 unsigned tie_t = 0; 897 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 898 return tie_t; 899} 900 901static void 902Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 903{ 904 uint32 tie_t; 905 tie_t = (val << 28) >> 28; 906 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 907} 908 909static unsigned 910Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) 911{ 912 unsigned tie_t = 0; 913 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 914 return tie_t; 915} 916 917static void 918Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 919{ 920 uint32 tie_t; 921 tie_t = (val << 28) >> 28; 922 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 923} 924 925static unsigned 926Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) 927{ 928 unsigned tie_t = 0; 929 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 930 return tie_t; 931} 932 933static void 934Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 935{ 936 uint32 tie_t; 937 tie_t = (val << 28) >> 28; 938 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 939} 940 941static unsigned 942Field_mn_Slot_inst_get (const xtensa_insnbuf insn) 943{ 944 unsigned tie_t = 0; 945 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); 946 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); 947 return tie_t; 948} 949 950static void 951Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 952{ 953 uint32 tie_t; 954 tie_t = (val << 30) >> 30; 955 insn[0] = (insn[0] & ~0x30) | (tie_t << 4); 956 tie_t = (val << 28) >> 30; 957 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); 958} 959 960static unsigned 961Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) 962{ 963 unsigned tie_t = 0; 964 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); 965 return tie_t; 966} 967 968static void 969Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 970{ 971 uint32 tie_t; 972 tie_t = (val << 31) >> 31; 973 insn[0] = (insn[0] & ~0x80) | (tie_t << 7); 974} 975 976static unsigned 977Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) 978{ 979 unsigned tie_t = 0; 980 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); 981 return tie_t; 982} 983 984static void 985Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 986{ 987 uint32 tie_t; 988 tie_t = (val << 31) >> 31; 989 insn[0] = (insn[0] & ~0x80) | (tie_t << 7); 990} 991 992static unsigned 993Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) 994{ 995 unsigned tie_t = 0; 996 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 997 return tie_t; 998} 999 1000static void 1001Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1002{ 1003 uint32 tie_t; 1004 tie_t = (val << 28) >> 28; 1005 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1006} 1007 1008static unsigned 1009Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) 1010{ 1011 unsigned tie_t = 0; 1012 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1013 return tie_t; 1014} 1015 1016static void 1017Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1018{ 1019 uint32 tie_t; 1020 tie_t = (val << 28) >> 28; 1021 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1022} 1023 1024static unsigned 1025Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) 1026{ 1027 unsigned tie_t = 0; 1028 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); 1029 return tie_t; 1030} 1031 1032static void 1033Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1034{ 1035 uint32 tie_t; 1036 tie_t = (val << 30) >> 30; 1037 insn[0] = (insn[0] & ~0x30) | (tie_t << 4); 1038} 1039 1040static unsigned 1041Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) 1042{ 1043 unsigned tie_t = 0; 1044 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); 1045 return tie_t; 1046} 1047 1048static void 1049Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1050{ 1051 uint32 tie_t; 1052 tie_t = (val << 30) >> 30; 1053 insn[0] = (insn[0] & ~0x30) | (tie_t << 4); 1054} 1055 1056static unsigned 1057Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) 1058{ 1059 unsigned tie_t = 0; 1060 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1061 return tie_t; 1062} 1063 1064static void 1065Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1066{ 1067 uint32 tie_t; 1068 tie_t = (val << 28) >> 28; 1069 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1070} 1071 1072static unsigned 1073Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) 1074{ 1075 unsigned tie_t = 0; 1076 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1077 return tie_t; 1078} 1079 1080static void 1081Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1082{ 1083 uint32 tie_t; 1084 tie_t = (val << 28) >> 28; 1085 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1086} 1087 1088static unsigned 1089Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) 1090{ 1091 unsigned tie_t = 0; 1092 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); 1093 return tie_t; 1094} 1095 1096static void 1097Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1098{ 1099 uint32 tie_t; 1100 tie_t = (val << 29) >> 29; 1101 insn[0] = (insn[0] & ~0x70) | (tie_t << 4); 1102} 1103 1104static unsigned 1105Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) 1106{ 1107 unsigned tie_t = 0; 1108 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); 1109 return tie_t; 1110} 1111 1112static void 1113Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1114{ 1115 uint32 tie_t; 1116 tie_t = (val << 29) >> 29; 1117 insn[0] = (insn[0] & ~0x70) | (tie_t << 4); 1118} 1119 1120static unsigned 1121Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) 1122{ 1123 unsigned tie_t = 0; 1124 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); 1125 return tie_t; 1126} 1127 1128static void 1129Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1130{ 1131 uint32 tie_t; 1132 tie_t = (val << 31) >> 31; 1133 insn[0] = (insn[0] & ~0x40) | (tie_t << 6); 1134} 1135 1136static unsigned 1137Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) 1138{ 1139 unsigned tie_t = 0; 1140 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); 1141 return tie_t; 1142} 1143 1144static void 1145Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1146{ 1147 uint32 tie_t; 1148 tie_t = (val << 31) >> 31; 1149 insn[0] = (insn[0] & ~0x40) | (tie_t << 6); 1150} 1151 1152static unsigned 1153Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) 1154{ 1155 unsigned tie_t = 0; 1156 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); 1157 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1158 return tie_t; 1159} 1160 1161static void 1162Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1163{ 1164 uint32 tie_t; 1165 tie_t = (val << 28) >> 28; 1166 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1167 tie_t = (val << 26) >> 30; 1168 insn[0] = (insn[0] & ~0x30) | (tie_t << 4); 1169} 1170 1171static unsigned 1172Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) 1173{ 1174 unsigned tie_t = 0; 1175 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); 1176 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1177 return tie_t; 1178} 1179 1180static void 1181Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1182{ 1183 uint32 tie_t; 1184 tie_t = (val << 28) >> 28; 1185 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1186 tie_t = (val << 26) >> 30; 1187 insn[0] = (insn[0] & ~0x30) | (tie_t << 4); 1188} 1189 1190static unsigned 1191Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) 1192{ 1193 unsigned tie_t = 0; 1194 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); 1195 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1196 return tie_t; 1197} 1198 1199static void 1200Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1201{ 1202 uint32 tie_t; 1203 tie_t = (val << 28) >> 28; 1204 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1205 tie_t = (val << 25) >> 29; 1206 insn[0] = (insn[0] & ~0x70) | (tie_t << 4); 1207} 1208 1209static unsigned 1210Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) 1211{ 1212 unsigned tie_t = 0; 1213 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); 1214 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1215 return tie_t; 1216} 1217 1218static void 1219Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1220{ 1221 uint32 tie_t; 1222 tie_t = (val << 28) >> 28; 1223 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1224 tie_t = (val << 25) >> 29; 1225 insn[0] = (insn[0] & ~0x70) | (tie_t << 4); 1226} 1227 1228static unsigned 1229Field_r3_Slot_inst_get (const xtensa_insnbuf insn) 1230{ 1231 unsigned tie_t = 0; 1232 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); 1233 return tie_t; 1234} 1235 1236static void 1237Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1238{ 1239 uint32 tie_t; 1240 tie_t = (val << 31) >> 31; 1241 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); 1242} 1243 1244static unsigned 1245Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn) 1246{ 1247 unsigned tie_t = 0; 1248 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); 1249 return tie_t; 1250} 1251 1252static void 1253Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1254{ 1255 uint32 tie_t; 1256 tie_t = (val << 31) >> 31; 1257 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); 1258} 1259 1260static unsigned 1261Field_rhi_Slot_inst_get (const xtensa_insnbuf insn) 1262{ 1263 unsigned tie_t = 0; 1264 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 1265 return tie_t; 1266} 1267 1268static void 1269Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1270{ 1271 uint32 tie_t; 1272 tie_t = (val << 30) >> 30; 1273 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 1274} 1275 1276static unsigned 1277Field_t3_Slot_inst_get (const xtensa_insnbuf insn) 1278{ 1279 unsigned tie_t = 0; 1280 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); 1281 return tie_t; 1282} 1283 1284static void 1285Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1286{ 1287 uint32 tie_t; 1288 tie_t = (val << 31) >> 31; 1289 insn[0] = (insn[0] & ~0x80) | (tie_t << 7); 1290} 1291 1292static unsigned 1293Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn) 1294{ 1295 unsigned tie_t = 0; 1296 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); 1297 return tie_t; 1298} 1299 1300static void 1301Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1302{ 1303 uint32 tie_t; 1304 tie_t = (val << 31) >> 31; 1305 insn[0] = (insn[0] & ~0x40) | (tie_t << 6); 1306} 1307 1308static unsigned 1309Field_tlo_Slot_inst_get (const xtensa_insnbuf insn) 1310{ 1311 unsigned tie_t = 0; 1312 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); 1313 return tie_t; 1314} 1315 1316static void 1317Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1318{ 1319 uint32 tie_t; 1320 tie_t = (val << 30) >> 30; 1321 insn[0] = (insn[0] & ~0x30) | (tie_t << 4); 1322} 1323 1324static unsigned 1325Field_w_Slot_inst_get (const xtensa_insnbuf insn) 1326{ 1327 unsigned tie_t = 0; 1328 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); 1329 return tie_t; 1330} 1331 1332static void 1333Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1334{ 1335 uint32 tie_t; 1336 tie_t = (val << 30) >> 30; 1337 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); 1338} 1339 1340static unsigned 1341Field_y_Slot_inst_get (const xtensa_insnbuf insn) 1342{ 1343 unsigned tie_t = 0; 1344 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); 1345 return tie_t; 1346} 1347 1348static void 1349Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1350{ 1351 uint32 tie_t; 1352 tie_t = (val << 31) >> 31; 1353 insn[0] = (insn[0] & ~0x40) | (tie_t << 6); 1354} 1355 1356static unsigned 1357Field_x_Slot_inst_get (const xtensa_insnbuf insn) 1358{ 1359 unsigned tie_t = 0; 1360 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); 1361 return tie_t; 1362} 1363 1364static void 1365Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1366{ 1367 uint32 tie_t; 1368 tie_t = (val << 31) >> 31; 1369 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); 1370} 1371 1372static unsigned 1373Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) 1374{ 1375 unsigned tie_t = 0; 1376 tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); 1377 return tie_t; 1378} 1379 1380static void 1381Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1382{ 1383 uint32 tie_t; 1384 tie_t = (val << 17) >> 17; 1385 insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); 1386} 1387 1388static unsigned 1389Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) 1390{ 1391 unsigned tie_t = 0; 1392 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); 1393 return tie_t; 1394} 1395 1396static void 1397Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1398{ 1399 uint32 tie_t; 1400 tie_t = (val << 14) >> 14; 1401 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); 1402} 1403 1404static unsigned 1405Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn) 1406{ 1407 unsigned tie_t = 0; 1408 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); 1409 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 1410 return tie_t; 1411} 1412 1413static void 1414Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1415{ 1416 uint32 tie_t; 1417 tie_t = (val << 28) >> 28; 1418 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 1419 tie_t = (val << 27) >> 31; 1420 insn[0] = (insn[0] & ~0x100) | (tie_t << 8); 1421} 1422 1423static unsigned 1424Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn) 1425{ 1426 unsigned tie_t = 0; 1427 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); 1428 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 1429 return tie_t; 1430} 1431 1432static void 1433Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1434{ 1435 uint32 tie_t; 1436 tie_t = (val << 28) >> 28; 1437 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 1438 tie_t = (val << 27) >> 31; 1439 insn[0] = (insn[0] & ~0x100) | (tie_t << 8); 1440} 1441 1442static unsigned 1443Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn) 1444{ 1445 unsigned tie_t = 0; 1446 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); 1447 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 1448 return tie_t; 1449} 1450 1451static void 1452Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1453{ 1454 uint32 tie_t; 1455 tie_t = (val << 28) >> 28; 1456 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 1457 tie_t = (val << 27) >> 31; 1458 insn[0] = (insn[0] & ~0x100) | (tie_t << 8); 1459} 1460 1461static unsigned 1462Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn) 1463{ 1464 unsigned tie_t = 0; 1465 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 1466 return tie_t; 1467} 1468 1469static void 1470Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1471{ 1472 uint32 tie_t; 1473 tie_t = (val << 29) >> 29; 1474 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 1475} 1476 1477static unsigned 1478Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn) 1479{ 1480 unsigned tie_t = 0; 1481 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 1482 return tie_t; 1483} 1484 1485static void 1486Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1487{ 1488 uint32 tie_t; 1489 tie_t = (val << 29) >> 29; 1490 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 1491} 1492 1493static unsigned 1494Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn) 1495{ 1496 unsigned tie_t = 0; 1497 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 1498 return tie_t; 1499} 1500 1501static void 1502Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1503{ 1504 uint32 tie_t; 1505 tie_t = (val << 29) >> 29; 1506 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 1507} 1508 1509static void 1510Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, 1511 uint32 val ATTRIBUTE_UNUSED) 1512{ 1513 /* Do nothing. */ 1514} 1515 1516static unsigned 1517Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1518{ 1519 return 0; 1520} 1521 1522static unsigned 1523Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1524{ 1525 return 4; 1526} 1527 1528static unsigned 1529Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1530{ 1531 return 8; 1532} 1533 1534static unsigned 1535Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1536{ 1537 return 12; 1538} 1539 1540static unsigned 1541Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1542{ 1543 return 0; 1544} 1545 1546static unsigned 1547Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1548{ 1549 return 1; 1550} 1551 1552static unsigned 1553Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1554{ 1555 return 2; 1556} 1557 1558static unsigned 1559Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1560{ 1561 return 3; 1562} 1563 1564 1565/* Functional units. */ 1566 1567static xtensa_funcUnit_internal funcUnits[] = { 1568 1569}; 1570 1571 1572/* Register files. */ 1573 1574static xtensa_regfile_internal regfiles[] = { 1575 { "AR", "a", 0, 32, 32 }, 1576 { "MR", "m", 1, 32, 4 } 1577}; 1578 1579 1580/* Interfaces. */ 1581 1582static xtensa_interface_internal interfaces[] = { 1583 { "IMPWIRE", 32, 0, 0, 'i' } 1584}; 1585 1586 1587/* Constant tables. */ 1588 1589/* constant table ai4c */ 1590static const unsigned CONST_TBL_ai4c_0[] = { 1591 0xffffffff, 1592 0x1, 1593 0x2, 1594 0x3, 1595 0x4, 1596 0x5, 1597 0x6, 1598 0x7, 1599 0x8, 1600 0x9, 1601 0xa, 1602 0xb, 1603 0xc, 1604 0xd, 1605 0xe, 1606 0xf, 1607 0 1608}; 1609 1610/* constant table b4c */ 1611static const unsigned CONST_TBL_b4c_0[] = { 1612 0xffffffff, 1613 0x1, 1614 0x2, 1615 0x3, 1616 0x4, 1617 0x5, 1618 0x6, 1619 0x7, 1620 0x8, 1621 0xa, 1622 0xc, 1623 0x10, 1624 0x20, 1625 0x40, 1626 0x80, 1627 0x100, 1628 0 1629}; 1630 1631/* constant table b4cu */ 1632static const unsigned CONST_TBL_b4cu_0[] = { 1633 0x8000, 1634 0x10000, 1635 0x2, 1636 0x3, 1637 0x4, 1638 0x5, 1639 0x6, 1640 0x7, 1641 0x8, 1642 0xa, 1643 0xc, 1644 0x10, 1645 0x20, 1646 0x40, 1647 0x80, 1648 0x100, 1649 0 1650}; 1651 1652 1653/* Instruction operands. */ 1654 1655static int 1656Operand_soffsetx4_decode (uint32 *valp) 1657{ 1658 unsigned soffsetx4_0, offset_0; 1659 offset_0 = *valp & 0x3ffff; 1660 soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2); 1661 *valp = soffsetx4_0; 1662 return 0; 1663} 1664 1665static int 1666Operand_soffsetx4_encode (uint32 *valp) 1667{ 1668 unsigned offset_0, soffsetx4_0; 1669 soffsetx4_0 = *valp; 1670 offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff; 1671 *valp = offset_0; 1672 return 0; 1673} 1674 1675static int 1676Operand_soffsetx4_ator (uint32 *valp, uint32 pc) 1677{ 1678 *valp -= (pc & ~0x3); 1679 return 0; 1680} 1681 1682static int 1683Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) 1684{ 1685 *valp += (pc & ~0x3); 1686 return 0; 1687} 1688 1689static int 1690Operand_uimm12x8_decode (uint32 *valp) 1691{ 1692 unsigned uimm12x8_0, imm12_0; 1693 imm12_0 = *valp & 0xfff; 1694 uimm12x8_0 = imm12_0 << 3; 1695 *valp = uimm12x8_0; 1696 return 0; 1697} 1698 1699static int 1700Operand_uimm12x8_encode (uint32 *valp) 1701{ 1702 unsigned imm12_0, uimm12x8_0; 1703 uimm12x8_0 = *valp; 1704 imm12_0 = ((uimm12x8_0 >> 3) & 0xfff); 1705 *valp = imm12_0; 1706 return 0; 1707} 1708 1709static int 1710Operand_simm4_decode (uint32 *valp) 1711{ 1712 unsigned simm4_0, mn_0; 1713 mn_0 = *valp & 0xf; 1714 simm4_0 = ((int) mn_0 << 28) >> 28; 1715 *valp = simm4_0; 1716 return 0; 1717} 1718 1719static int 1720Operand_simm4_encode (uint32 *valp) 1721{ 1722 unsigned mn_0, simm4_0; 1723 simm4_0 = *valp; 1724 mn_0 = (simm4_0 & 0xf); 1725 *valp = mn_0; 1726 return 0; 1727} 1728 1729static int 1730Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED) 1731{ 1732 return 0; 1733} 1734 1735static int 1736Operand_arr_encode (uint32 *valp) 1737{ 1738 return (*valp & ~0xf) != 0; 1739} 1740 1741static int 1742Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED) 1743{ 1744 return 0; 1745} 1746 1747static int 1748Operand_ars_encode (uint32 *valp) 1749{ 1750 return (*valp & ~0xf) != 0; 1751} 1752 1753static int 1754Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED) 1755{ 1756 return 0; 1757} 1758 1759static int 1760Operand_art_encode (uint32 *valp) 1761{ 1762 return (*valp & ~0xf) != 0; 1763} 1764 1765static int 1766Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED) 1767{ 1768 return 0; 1769} 1770 1771static int 1772Operand_ar0_encode (uint32 *valp) 1773{ 1774 return (*valp & ~0x1f) != 0; 1775} 1776 1777static int 1778Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED) 1779{ 1780 return 0; 1781} 1782 1783static int 1784Operand_ar4_encode (uint32 *valp) 1785{ 1786 return (*valp & ~0x1f) != 0; 1787} 1788 1789static int 1790Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED) 1791{ 1792 return 0; 1793} 1794 1795static int 1796Operand_ar8_encode (uint32 *valp) 1797{ 1798 return (*valp & ~0x1f) != 0; 1799} 1800 1801static int 1802Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED) 1803{ 1804 return 0; 1805} 1806 1807static int 1808Operand_ar12_encode (uint32 *valp) 1809{ 1810 return (*valp & ~0x1f) != 0; 1811} 1812 1813static int 1814Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED) 1815{ 1816 return 0; 1817} 1818 1819static int 1820Operand_ars_entry_encode (uint32 *valp) 1821{ 1822 return (*valp & ~0x1f) != 0; 1823} 1824 1825static int 1826Operand_immrx4_decode (uint32 *valp) 1827{ 1828 unsigned immrx4_0, r_0; 1829 r_0 = *valp & 0xf; 1830 immrx4_0 = (((0xfffffff) << 4) | r_0) << 2; 1831 *valp = immrx4_0; 1832 return 0; 1833} 1834 1835static int 1836Operand_immrx4_encode (uint32 *valp) 1837{ 1838 unsigned r_0, immrx4_0; 1839 immrx4_0 = *valp; 1840 r_0 = ((immrx4_0 >> 2) & 0xf); 1841 *valp = r_0; 1842 return 0; 1843} 1844 1845static int 1846Operand_lsi4x4_decode (uint32 *valp) 1847{ 1848 unsigned lsi4x4_0, r_0; 1849 r_0 = *valp & 0xf; 1850 lsi4x4_0 = r_0 << 2; 1851 *valp = lsi4x4_0; 1852 return 0; 1853} 1854 1855static int 1856Operand_lsi4x4_encode (uint32 *valp) 1857{ 1858 unsigned r_0, lsi4x4_0; 1859 lsi4x4_0 = *valp; 1860 r_0 = ((lsi4x4_0 >> 2) & 0xf); 1861 *valp = r_0; 1862 return 0; 1863} 1864 1865static int 1866Operand_simm7_decode (uint32 *valp) 1867{ 1868 unsigned simm7_0, imm7_0; 1869 imm7_0 = *valp & 0x7f; 1870 simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0; 1871 *valp = simm7_0; 1872 return 0; 1873} 1874 1875static int 1876Operand_simm7_encode (uint32 *valp) 1877{ 1878 unsigned imm7_0, simm7_0; 1879 simm7_0 = *valp; 1880 imm7_0 = (simm7_0 & 0x7f); 1881 *valp = imm7_0; 1882 return 0; 1883} 1884 1885static int 1886Operand_uimm6_decode (uint32 *valp) 1887{ 1888 unsigned uimm6_0, imm6_0; 1889 imm6_0 = *valp & 0x3f; 1890 uimm6_0 = 0x4 + (((0) << 6) | imm6_0); 1891 *valp = uimm6_0; 1892 return 0; 1893} 1894 1895static int 1896Operand_uimm6_encode (uint32 *valp) 1897{ 1898 unsigned imm6_0, uimm6_0; 1899 uimm6_0 = *valp; 1900 imm6_0 = (uimm6_0 - 0x4) & 0x3f; 1901 *valp = imm6_0; 1902 return 0; 1903} 1904 1905static int 1906Operand_uimm6_ator (uint32 *valp, uint32 pc) 1907{ 1908 *valp -= pc; 1909 return 0; 1910} 1911 1912static int 1913Operand_uimm6_rtoa (uint32 *valp, uint32 pc) 1914{ 1915 *valp += pc; 1916 return 0; 1917} 1918 1919static int 1920Operand_ai4const_decode (uint32 *valp) 1921{ 1922 unsigned ai4const_0, t_0; 1923 t_0 = *valp & 0xf; 1924 ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf]; 1925 *valp = ai4const_0; 1926 return 0; 1927} 1928 1929static int 1930Operand_ai4const_encode (uint32 *valp) 1931{ 1932 unsigned t_0, ai4const_0; 1933 ai4const_0 = *valp; 1934 switch (ai4const_0) 1935 { 1936 case 0xffffffff: t_0 = 0; break; 1937 case 0x1: t_0 = 0x1; break; 1938 case 0x2: t_0 = 0x2; break; 1939 case 0x3: t_0 = 0x3; break; 1940 case 0x4: t_0 = 0x4; break; 1941 case 0x5: t_0 = 0x5; break; 1942 case 0x6: t_0 = 0x6; break; 1943 case 0x7: t_0 = 0x7; break; 1944 case 0x8: t_0 = 0x8; break; 1945 case 0x9: t_0 = 0x9; break; 1946 case 0xa: t_0 = 0xa; break; 1947 case 0xb: t_0 = 0xb; break; 1948 case 0xc: t_0 = 0xc; break; 1949 case 0xd: t_0 = 0xd; break; 1950 case 0xe: t_0 = 0xe; break; 1951 default: t_0 = 0xf; break; 1952 } 1953 *valp = t_0; 1954 return 0; 1955} 1956 1957static int 1958Operand_b4const_decode (uint32 *valp) 1959{ 1960 unsigned b4const_0, r_0; 1961 r_0 = *valp & 0xf; 1962 b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf]; 1963 *valp = b4const_0; 1964 return 0; 1965} 1966 1967static int 1968Operand_b4const_encode (uint32 *valp) 1969{ 1970 unsigned r_0, b4const_0; 1971 b4const_0 = *valp; 1972 switch (b4const_0) 1973 { 1974 case 0xffffffff: r_0 = 0; break; 1975 case 0x1: r_0 = 0x1; break; 1976 case 0x2: r_0 = 0x2; break; 1977 case 0x3: r_0 = 0x3; break; 1978 case 0x4: r_0 = 0x4; break; 1979 case 0x5: r_0 = 0x5; break; 1980 case 0x6: r_0 = 0x6; break; 1981 case 0x7: r_0 = 0x7; break; 1982 case 0x8: r_0 = 0x8; break; 1983 case 0xa: r_0 = 0x9; break; 1984 case 0xc: r_0 = 0xa; break; 1985 case 0x10: r_0 = 0xb; break; 1986 case 0x20: r_0 = 0xc; break; 1987 case 0x40: r_0 = 0xd; break; 1988 case 0x80: r_0 = 0xe; break; 1989 default: r_0 = 0xf; break; 1990 } 1991 *valp = r_0; 1992 return 0; 1993} 1994 1995static int 1996Operand_b4constu_decode (uint32 *valp) 1997{ 1998 unsigned b4constu_0, r_0; 1999 r_0 = *valp & 0xf; 2000 b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf]; 2001 *valp = b4constu_0; 2002 return 0; 2003} 2004 2005static int 2006Operand_b4constu_encode (uint32 *valp) 2007{ 2008 unsigned r_0, b4constu_0; 2009 b4constu_0 = *valp; 2010 switch (b4constu_0) 2011 { 2012 case 0x8000: r_0 = 0; break; 2013 case 0x10000: r_0 = 0x1; break; 2014 case 0x2: r_0 = 0x2; break; 2015 case 0x3: r_0 = 0x3; break; 2016 case 0x4: r_0 = 0x4; break; 2017 case 0x5: r_0 = 0x5; break; 2018 case 0x6: r_0 = 0x6; break; 2019 case 0x7: r_0 = 0x7; break; 2020 case 0x8: r_0 = 0x8; break; 2021 case 0xa: r_0 = 0x9; break; 2022 case 0xc: r_0 = 0xa; break; 2023 case 0x10: r_0 = 0xb; break; 2024 case 0x20: r_0 = 0xc; break; 2025 case 0x40: r_0 = 0xd; break; 2026 case 0x80: r_0 = 0xe; break; 2027 default: r_0 = 0xf; break; 2028 } 2029 *valp = r_0; 2030 return 0; 2031} 2032 2033static int 2034Operand_uimm8_decode (uint32 *valp) 2035{ 2036 unsigned uimm8_0, imm8_0; 2037 imm8_0 = *valp & 0xff; 2038 uimm8_0 = imm8_0; 2039 *valp = uimm8_0; 2040 return 0; 2041} 2042 2043static int 2044Operand_uimm8_encode (uint32 *valp) 2045{ 2046 unsigned imm8_0, uimm8_0; 2047 uimm8_0 = *valp; 2048 imm8_0 = (uimm8_0 & 0xff); 2049 *valp = imm8_0; 2050 return 0; 2051} 2052 2053static int 2054Operand_uimm8x2_decode (uint32 *valp) 2055{ 2056 unsigned uimm8x2_0, imm8_0; 2057 imm8_0 = *valp & 0xff; 2058 uimm8x2_0 = imm8_0 << 1; 2059 *valp = uimm8x2_0; 2060 return 0; 2061} 2062 2063static int 2064Operand_uimm8x2_encode (uint32 *valp) 2065{ 2066 unsigned imm8_0, uimm8x2_0; 2067 uimm8x2_0 = *valp; 2068 imm8_0 = ((uimm8x2_0 >> 1) & 0xff); 2069 *valp = imm8_0; 2070 return 0; 2071} 2072 2073static int 2074Operand_uimm8x4_decode (uint32 *valp) 2075{ 2076 unsigned uimm8x4_0, imm8_0; 2077 imm8_0 = *valp & 0xff; 2078 uimm8x4_0 = imm8_0 << 2; 2079 *valp = uimm8x4_0; 2080 return 0; 2081} 2082 2083static int 2084Operand_uimm8x4_encode (uint32 *valp) 2085{ 2086 unsigned imm8_0, uimm8x4_0; 2087 uimm8x4_0 = *valp; 2088 imm8_0 = ((uimm8x4_0 >> 2) & 0xff); 2089 *valp = imm8_0; 2090 return 0; 2091} 2092 2093static int 2094Operand_uimm4x16_decode (uint32 *valp) 2095{ 2096 unsigned uimm4x16_0, op2_0; 2097 op2_0 = *valp & 0xf; 2098 uimm4x16_0 = op2_0 << 4; 2099 *valp = uimm4x16_0; 2100 return 0; 2101} 2102 2103static int 2104Operand_uimm4x16_encode (uint32 *valp) 2105{ 2106 unsigned op2_0, uimm4x16_0; 2107 uimm4x16_0 = *valp; 2108 op2_0 = ((uimm4x16_0 >> 4) & 0xf); 2109 *valp = op2_0; 2110 return 0; 2111} 2112 2113static int 2114Operand_simm8_decode (uint32 *valp) 2115{ 2116 unsigned simm8_0, imm8_0; 2117 imm8_0 = *valp & 0xff; 2118 simm8_0 = ((int) imm8_0 << 24) >> 24; 2119 *valp = simm8_0; 2120 return 0; 2121} 2122 2123static int 2124Operand_simm8_encode (uint32 *valp) 2125{ 2126 unsigned imm8_0, simm8_0; 2127 simm8_0 = *valp; 2128 imm8_0 = (simm8_0 & 0xff); 2129 *valp = imm8_0; 2130 return 0; 2131} 2132 2133static int 2134Operand_simm8x256_decode (uint32 *valp) 2135{ 2136 unsigned simm8x256_0, imm8_0; 2137 imm8_0 = *valp & 0xff; 2138 simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8; 2139 *valp = simm8x256_0; 2140 return 0; 2141} 2142 2143static int 2144Operand_simm8x256_encode (uint32 *valp) 2145{ 2146 unsigned imm8_0, simm8x256_0; 2147 simm8x256_0 = *valp; 2148 imm8_0 = ((simm8x256_0 >> 8) & 0xff); 2149 *valp = imm8_0; 2150 return 0; 2151} 2152 2153static int 2154Operand_simm12b_decode (uint32 *valp) 2155{ 2156 unsigned simm12b_0, imm12b_0; 2157 imm12b_0 = *valp & 0xfff; 2158 simm12b_0 = ((int) imm12b_0 << 20) >> 20; 2159 *valp = simm12b_0; 2160 return 0; 2161} 2162 2163static int 2164Operand_simm12b_encode (uint32 *valp) 2165{ 2166 unsigned imm12b_0, simm12b_0; 2167 simm12b_0 = *valp; 2168 imm12b_0 = (simm12b_0 & 0xfff); 2169 *valp = imm12b_0; 2170 return 0; 2171} 2172 2173static int 2174Operand_msalp32_decode (uint32 *valp) 2175{ 2176 unsigned msalp32_0, sal_0; 2177 sal_0 = *valp & 0x1f; 2178 msalp32_0 = 0x20 - sal_0; 2179 *valp = msalp32_0; 2180 return 0; 2181} 2182 2183static int 2184Operand_msalp32_encode (uint32 *valp) 2185{ 2186 unsigned sal_0, msalp32_0; 2187 msalp32_0 = *valp; 2188 sal_0 = (0x20 - msalp32_0) & 0x1f; 2189 *valp = sal_0; 2190 return 0; 2191} 2192 2193static int 2194Operand_op2p1_decode (uint32 *valp) 2195{ 2196 unsigned op2p1_0, op2_0; 2197 op2_0 = *valp & 0xf; 2198 op2p1_0 = op2_0 + 0x1; 2199 *valp = op2p1_0; 2200 return 0; 2201} 2202 2203static int 2204Operand_op2p1_encode (uint32 *valp) 2205{ 2206 unsigned op2_0, op2p1_0; 2207 op2p1_0 = *valp; 2208 op2_0 = (op2p1_0 - 0x1) & 0xf; 2209 *valp = op2_0; 2210 return 0; 2211} 2212 2213static int 2214Operand_label8_decode (uint32 *valp) 2215{ 2216 unsigned label8_0, imm8_0; 2217 imm8_0 = *valp & 0xff; 2218 label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24); 2219 *valp = label8_0; 2220 return 0; 2221} 2222 2223static int 2224Operand_label8_encode (uint32 *valp) 2225{ 2226 unsigned imm8_0, label8_0; 2227 label8_0 = *valp; 2228 imm8_0 = (label8_0 - 0x4) & 0xff; 2229 *valp = imm8_0; 2230 return 0; 2231} 2232 2233static int 2234Operand_label8_ator (uint32 *valp, uint32 pc) 2235{ 2236 *valp -= pc; 2237 return 0; 2238} 2239 2240static int 2241Operand_label8_rtoa (uint32 *valp, uint32 pc) 2242{ 2243 *valp += pc; 2244 return 0; 2245} 2246 2247static int 2248Operand_ulabel8_decode (uint32 *valp) 2249{ 2250 unsigned ulabel8_0, imm8_0; 2251 imm8_0 = *valp & 0xff; 2252 ulabel8_0 = 0x4 + (((0) << 8) | imm8_0); 2253 *valp = ulabel8_0; 2254 return 0; 2255} 2256 2257static int 2258Operand_ulabel8_encode (uint32 *valp) 2259{ 2260 unsigned imm8_0, ulabel8_0; 2261 ulabel8_0 = *valp; 2262 imm8_0 = (ulabel8_0 - 0x4) & 0xff; 2263 *valp = imm8_0; 2264 return 0; 2265} 2266 2267static int 2268Operand_ulabel8_ator (uint32 *valp, uint32 pc) 2269{ 2270 *valp -= pc; 2271 return 0; 2272} 2273 2274static int 2275Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) 2276{ 2277 *valp += pc; 2278 return 0; 2279} 2280 2281static int 2282Operand_label12_decode (uint32 *valp) 2283{ 2284 unsigned label12_0, imm12_0; 2285 imm12_0 = *valp & 0xfff; 2286 label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20); 2287 *valp = label12_0; 2288 return 0; 2289} 2290 2291static int 2292Operand_label12_encode (uint32 *valp) 2293{ 2294 unsigned imm12_0, label12_0; 2295 label12_0 = *valp; 2296 imm12_0 = (label12_0 - 0x4) & 0xfff; 2297 *valp = imm12_0; 2298 return 0; 2299} 2300 2301static int 2302Operand_label12_ator (uint32 *valp, uint32 pc) 2303{ 2304 *valp -= pc; 2305 return 0; 2306} 2307 2308static int 2309Operand_label12_rtoa (uint32 *valp, uint32 pc) 2310{ 2311 *valp += pc; 2312 return 0; 2313} 2314 2315static int 2316Operand_soffset_decode (uint32 *valp) 2317{ 2318 unsigned soffset_0, offset_0; 2319 offset_0 = *valp & 0x3ffff; 2320 soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14); 2321 *valp = soffset_0; 2322 return 0; 2323} 2324 2325static int 2326Operand_soffset_encode (uint32 *valp) 2327{ 2328 unsigned offset_0, soffset_0; 2329 soffset_0 = *valp; 2330 offset_0 = (soffset_0 - 0x4) & 0x3ffff; 2331 *valp = offset_0; 2332 return 0; 2333} 2334 2335static int 2336Operand_soffset_ator (uint32 *valp, uint32 pc) 2337{ 2338 *valp -= pc; 2339 return 0; 2340} 2341 2342static int 2343Operand_soffset_rtoa (uint32 *valp, uint32 pc) 2344{ 2345 *valp += pc; 2346 return 0; 2347} 2348 2349static int 2350Operand_uimm16x4_decode (uint32 *valp) 2351{ 2352 unsigned uimm16x4_0, imm16_0; 2353 imm16_0 = *valp & 0xffff; 2354 uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2; 2355 *valp = uimm16x4_0; 2356 return 0; 2357} 2358 2359static int 2360Operand_uimm16x4_encode (uint32 *valp) 2361{ 2362 unsigned imm16_0, uimm16x4_0; 2363 uimm16x4_0 = *valp; 2364 imm16_0 = (uimm16x4_0 >> 2) & 0xffff; 2365 *valp = imm16_0; 2366 return 0; 2367} 2368 2369static int 2370Operand_uimm16x4_ator (uint32 *valp, uint32 pc) 2371{ 2372 *valp -= ((pc + 3) & ~0x3); 2373 return 0; 2374} 2375 2376static int 2377Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) 2378{ 2379 *valp += ((pc + 3) & ~0x3); 2380 return 0; 2381} 2382 2383static int 2384Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED) 2385{ 2386 return 0; 2387} 2388 2389static int 2390Operand_mx_encode (uint32 *valp) 2391{ 2392 return (*valp & ~0x3) != 0; 2393} 2394 2395static int 2396Operand_my_decode (uint32 *valp) 2397{ 2398 *valp += 2; 2399 return 0; 2400} 2401 2402static int 2403Operand_my_encode (uint32 *valp) 2404{ 2405 int error; 2406 error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0); 2407 *valp = *valp & 1; 2408 return error; 2409} 2410 2411static int 2412Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED) 2413{ 2414 return 0; 2415} 2416 2417static int 2418Operand_mw_encode (uint32 *valp) 2419{ 2420 return (*valp & ~0x3) != 0; 2421} 2422 2423static int 2424Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED) 2425{ 2426 return 0; 2427} 2428 2429static int 2430Operand_mr0_encode (uint32 *valp) 2431{ 2432 return (*valp & ~0x3) != 0; 2433} 2434 2435static int 2436Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED) 2437{ 2438 return 0; 2439} 2440 2441static int 2442Operand_mr1_encode (uint32 *valp) 2443{ 2444 return (*valp & ~0x3) != 0; 2445} 2446 2447static int 2448Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED) 2449{ 2450 return 0; 2451} 2452 2453static int 2454Operand_mr2_encode (uint32 *valp) 2455{ 2456 return (*valp & ~0x3) != 0; 2457} 2458 2459static int 2460Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED) 2461{ 2462 return 0; 2463} 2464 2465static int 2466Operand_mr3_encode (uint32 *valp) 2467{ 2468 return (*valp & ~0x3) != 0; 2469} 2470 2471static int 2472Operand_immt_decode (uint32 *valp) 2473{ 2474 unsigned immt_0, t_0; 2475 t_0 = *valp & 0xf; 2476 immt_0 = t_0; 2477 *valp = immt_0; 2478 return 0; 2479} 2480 2481static int 2482Operand_immt_encode (uint32 *valp) 2483{ 2484 unsigned t_0, immt_0; 2485 immt_0 = *valp; 2486 t_0 = immt_0 & 0xf; 2487 *valp = t_0; 2488 return 0; 2489} 2490 2491static int 2492Operand_imms_decode (uint32 *valp) 2493{ 2494 unsigned imms_0, s_0; 2495 s_0 = *valp & 0xf; 2496 imms_0 = s_0; 2497 *valp = imms_0; 2498 return 0; 2499} 2500 2501static int 2502Operand_imms_encode (uint32 *valp) 2503{ 2504 unsigned s_0, imms_0; 2505 imms_0 = *valp; 2506 s_0 = imms_0 & 0xf; 2507 *valp = s_0; 2508 return 0; 2509} 2510 2511static int 2512Operand_tp7_decode (uint32 *valp) 2513{ 2514 unsigned tp7_0, t_0; 2515 t_0 = *valp & 0xf; 2516 tp7_0 = t_0 + 0x7; 2517 *valp = tp7_0; 2518 return 0; 2519} 2520 2521static int 2522Operand_tp7_encode (uint32 *valp) 2523{ 2524 unsigned t_0, tp7_0; 2525 tp7_0 = *valp; 2526 t_0 = (tp7_0 - 0x7) & 0xf; 2527 *valp = t_0; 2528 return 0; 2529} 2530 2531static int 2532Operand_xt_wbr15_label_decode (uint32 *valp) 2533{ 2534 unsigned xt_wbr15_label_0, xt_wbr15_imm_0; 2535 xt_wbr15_imm_0 = *valp & 0x7fff; 2536 xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17); 2537 *valp = xt_wbr15_label_0; 2538 return 0; 2539} 2540 2541static int 2542Operand_xt_wbr15_label_encode (uint32 *valp) 2543{ 2544 unsigned xt_wbr15_imm_0, xt_wbr15_label_0; 2545 xt_wbr15_label_0 = *valp; 2546 xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff; 2547 *valp = xt_wbr15_imm_0; 2548 return 0; 2549} 2550 2551static int 2552Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) 2553{ 2554 *valp -= pc; 2555 return 0; 2556} 2557 2558static int 2559Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) 2560{ 2561 *valp += pc; 2562 return 0; 2563} 2564 2565static int 2566Operand_xt_wbr18_label_decode (uint32 *valp) 2567{ 2568 unsigned xt_wbr18_label_0, xt_wbr18_imm_0; 2569 xt_wbr18_imm_0 = *valp & 0x3ffff; 2570 xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14); 2571 *valp = xt_wbr18_label_0; 2572 return 0; 2573} 2574 2575static int 2576Operand_xt_wbr18_label_encode (uint32 *valp) 2577{ 2578 unsigned xt_wbr18_imm_0, xt_wbr18_label_0; 2579 xt_wbr18_label_0 = *valp; 2580 xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff; 2581 *valp = xt_wbr18_imm_0; 2582 return 0; 2583} 2584 2585static int 2586Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) 2587{ 2588 *valp -= pc; 2589 return 0; 2590} 2591 2592static int 2593Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) 2594{ 2595 *valp += pc; 2596 return 0; 2597} 2598 2599static xtensa_operand_internal operands[] = { 2600 { "soffsetx4", 10, -1, 0, 2601 XTENSA_OPERAND_IS_PCRELATIVE, 2602 Operand_soffsetx4_encode, Operand_soffsetx4_decode, 2603 Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, 2604 { "uimm12x8", 3, -1, 0, 2605 0, 2606 Operand_uimm12x8_encode, Operand_uimm12x8_decode, 2607 0, 0 }, 2608 { "simm4", 26, -1, 0, 2609 0, 2610 Operand_simm4_encode, Operand_simm4_decode, 2611 0, 0 }, 2612 { "arr", 14, 0, 1, 2613 XTENSA_OPERAND_IS_REGISTER, 2614 Operand_arr_encode, Operand_arr_decode, 2615 0, 0 }, 2616 { "ars", 5, 0, 1, 2617 XTENSA_OPERAND_IS_REGISTER, 2618 Operand_ars_encode, Operand_ars_decode, 2619 0, 0 }, 2620 { "*ars_invisible", 5, 0, 1, 2621 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2622 Operand_ars_encode, Operand_ars_decode, 2623 0, 0 }, 2624 { "art", 0, 0, 1, 2625 XTENSA_OPERAND_IS_REGISTER, 2626 Operand_art_encode, Operand_art_decode, 2627 0, 0 }, 2628 { "ar0", 48, 0, 1, 2629 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2630 Operand_ar0_encode, Operand_ar0_decode, 2631 0, 0 }, 2632 { "ar4", 49, 0, 1, 2633 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2634 Operand_ar4_encode, Operand_ar4_decode, 2635 0, 0 }, 2636 { "ar8", 50, 0, 1, 2637 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2638 Operand_ar8_encode, Operand_ar8_decode, 2639 0, 0 }, 2640 { "ar12", 51, 0, 1, 2641 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2642 Operand_ar12_encode, Operand_ar12_decode, 2643 0, 0 }, 2644 { "ars_entry", 5, 0, 1, 2645 XTENSA_OPERAND_IS_REGISTER, 2646 Operand_ars_entry_encode, Operand_ars_entry_decode, 2647 0, 0 }, 2648 { "immrx4", 14, -1, 0, 2649 0, 2650 Operand_immrx4_encode, Operand_immrx4_decode, 2651 0, 0 }, 2652 { "lsi4x4", 14, -1, 0, 2653 0, 2654 Operand_lsi4x4_encode, Operand_lsi4x4_decode, 2655 0, 0 }, 2656 { "simm7", 34, -1, 0, 2657 0, 2658 Operand_simm7_encode, Operand_simm7_decode, 2659 0, 0 }, 2660 { "uimm6", 33, -1, 0, 2661 XTENSA_OPERAND_IS_PCRELATIVE, 2662 Operand_uimm6_encode, Operand_uimm6_decode, 2663 Operand_uimm6_ator, Operand_uimm6_rtoa }, 2664 { "ai4const", 0, -1, 0, 2665 0, 2666 Operand_ai4const_encode, Operand_ai4const_decode, 2667 0, 0 }, 2668 { "b4const", 14, -1, 0, 2669 0, 2670 Operand_b4const_encode, Operand_b4const_decode, 2671 0, 0 }, 2672 { "b4constu", 14, -1, 0, 2673 0, 2674 Operand_b4constu_encode, Operand_b4constu_decode, 2675 0, 0 }, 2676 { "uimm8", 4, -1, 0, 2677 0, 2678 Operand_uimm8_encode, Operand_uimm8_decode, 2679 0, 0 }, 2680 { "uimm8x2", 4, -1, 0, 2681 0, 2682 Operand_uimm8x2_encode, Operand_uimm8x2_decode, 2683 0, 0 }, 2684 { "uimm8x4", 4, -1, 0, 2685 0, 2686 Operand_uimm8x4_encode, Operand_uimm8x4_decode, 2687 0, 0 }, 2688 { "uimm4x16", 13, -1, 0, 2689 0, 2690 Operand_uimm4x16_encode, Operand_uimm4x16_decode, 2691 0, 0 }, 2692 { "simm8", 4, -1, 0, 2693 0, 2694 Operand_simm8_encode, Operand_simm8_decode, 2695 0, 0 }, 2696 { "simm8x256", 4, -1, 0, 2697 0, 2698 Operand_simm8x256_encode, Operand_simm8x256_decode, 2699 0, 0 }, 2700 { "simm12b", 6, -1, 0, 2701 0, 2702 Operand_simm12b_encode, Operand_simm12b_decode, 2703 0, 0 }, 2704 { "msalp32", 18, -1, 0, 2705 0, 2706 Operand_msalp32_encode, Operand_msalp32_decode, 2707 0, 0 }, 2708 { "op2p1", 13, -1, 0, 2709 0, 2710 Operand_op2p1_encode, Operand_op2p1_decode, 2711 0, 0 }, 2712 { "label8", 4, -1, 0, 2713 XTENSA_OPERAND_IS_PCRELATIVE, 2714 Operand_label8_encode, Operand_label8_decode, 2715 Operand_label8_ator, Operand_label8_rtoa }, 2716 { "ulabel8", 4, -1, 0, 2717 XTENSA_OPERAND_IS_PCRELATIVE, 2718 Operand_ulabel8_encode, Operand_ulabel8_decode, 2719 Operand_ulabel8_ator, Operand_ulabel8_rtoa }, 2720 { "label12", 3, -1, 0, 2721 XTENSA_OPERAND_IS_PCRELATIVE, 2722 Operand_label12_encode, Operand_label12_decode, 2723 Operand_label12_ator, Operand_label12_rtoa }, 2724 { "soffset", 10, -1, 0, 2725 XTENSA_OPERAND_IS_PCRELATIVE, 2726 Operand_soffset_encode, Operand_soffset_decode, 2727 Operand_soffset_ator, Operand_soffset_rtoa }, 2728 { "uimm16x4", 7, -1, 0, 2729 XTENSA_OPERAND_IS_PCRELATIVE, 2730 Operand_uimm16x4_encode, Operand_uimm16x4_decode, 2731 Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, 2732 { "mx", 43, 1, 1, 2733 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, 2734 Operand_mx_encode, Operand_mx_decode, 2735 0, 0 }, 2736 { "my", 42, 1, 1, 2737 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, 2738 Operand_my_encode, Operand_my_decode, 2739 0, 0 }, 2740 { "mw", 41, 1, 1, 2741 XTENSA_OPERAND_IS_REGISTER, 2742 Operand_mw_encode, Operand_mw_decode, 2743 0, 0 }, 2744 { "mr0", 52, 1, 1, 2745 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2746 Operand_mr0_encode, Operand_mr0_decode, 2747 0, 0 }, 2748 { "mr1", 53, 1, 1, 2749 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2750 Operand_mr1_encode, Operand_mr1_decode, 2751 0, 0 }, 2752 { "mr2", 54, 1, 1, 2753 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2754 Operand_mr2_encode, Operand_mr2_decode, 2755 0, 0 }, 2756 { "mr3", 55, 1, 1, 2757 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2758 Operand_mr3_encode, Operand_mr3_decode, 2759 0, 0 }, 2760 { "immt", 0, -1, 0, 2761 0, 2762 Operand_immt_encode, Operand_immt_decode, 2763 0, 0 }, 2764 { "imms", 5, -1, 0, 2765 0, 2766 Operand_imms_encode, Operand_imms_decode, 2767 0, 0 }, 2768 { "tp7", 0, -1, 0, 2769 0, 2770 Operand_tp7_encode, Operand_tp7_decode, 2771 0, 0 }, 2772 { "xt_wbr15_label", 44, -1, 0, 2773 XTENSA_OPERAND_IS_PCRELATIVE, 2774 Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode, 2775 Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, 2776 { "xt_wbr18_label", 45, -1, 0, 2777 XTENSA_OPERAND_IS_PCRELATIVE, 2778 Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode, 2779 Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, 2780 { "t", 0, -1, 0, 0, 0, 0, 0, 0 }, 2781 { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 }, 2782 { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 }, 2783 { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 }, 2784 { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 }, 2785 { "s", 5, -1, 0, 0, 0, 0, 0, 0 }, 2786 { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 }, 2787 { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 }, 2788 { "m", 8, -1, 0, 0, 0, 0, 0, 0 }, 2789 { "n", 9, -1, 0, 0, 0, 0, 0, 0 }, 2790 { "offset", 10, -1, 0, 0, 0, 0, 0, 0 }, 2791 { "op0", 11, -1, 0, 0, 0, 0, 0, 0 }, 2792 { "op1", 12, -1, 0, 0, 0, 0, 0, 0 }, 2793 { "op2", 13, -1, 0, 0, 0, 0, 0, 0 }, 2794 { "r", 14, -1, 0, 0, 0, 0, 0, 0 }, 2795 { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 }, 2796 { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 }, 2797 { "sae", 17, -1, 0, 0, 0, 0, 0, 0 }, 2798 { "sal", 18, -1, 0, 0, 0, 0, 0, 0 }, 2799 { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 }, 2800 { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 }, 2801 { "sas", 21, -1, 0, 0, 0, 0, 0, 0 }, 2802 { "sr", 22, -1, 0, 0, 0, 0, 0, 0 }, 2803 { "st", 23, -1, 0, 0, 0, 0, 0, 0 }, 2804 { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 }, 2805 { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 }, 2806 { "mn", 26, -1, 0, 0, 0, 0, 0, 0 }, 2807 { "i", 27, -1, 0, 0, 0, 0, 0, 0 }, 2808 { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 }, 2809 { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 }, 2810 { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 }, 2811 { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 }, 2812 { "z", 32, -1, 0, 0, 0, 0, 0, 0 }, 2813 { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 }, 2814 { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 }, 2815 { "r3", 35, -1, 0, 0, 0, 0, 0, 0 }, 2816 { "rbit2", 36, -1, 0, 0, 0, 0, 0, 0 }, 2817 { "rhi", 37, -1, 0, 0, 0, 0, 0, 0 }, 2818 { "t3", 38, -1, 0, 0, 0, 0, 0, 0 }, 2819 { "tbit2", 39, -1, 0, 0, 0, 0, 0, 0 }, 2820 { "tlo", 40, -1, 0, 0, 0, 0, 0, 0 }, 2821 { "w", 41, -1, 0, 0, 0, 0, 0, 0 }, 2822 { "y", 42, -1, 0, 0, 0, 0, 0, 0 }, 2823 { "x", 43, -1, 0, 0, 0, 0, 0, 0 }, 2824 { "xt_wbr15_imm", 44, -1, 0, 0, 0, 0, 0, 0 }, 2825 { "xt_wbr18_imm", 45, -1, 0, 0, 0, 0, 0, 0 }, 2826 { "bitindex", 46, -1, 0, 0, 0, 0, 0, 0 }, 2827 { "s3to1", 47, -1, 0, 0, 0, 0, 0, 0 } 2828}; 2829 2830 2831/* Iclass table. */ 2832 2833static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { 2834 { { STATE_PSRING }, 'i' }, 2835 { { STATE_PSEXCM }, 'm' }, 2836 { { STATE_EPC1 }, 'i' } 2837}; 2838 2839static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { 2840 { { STATE_PSEXCM }, 'i' }, 2841 { { STATE_PSRING }, 'i' }, 2842 { { STATE_DEPC }, 'i' } 2843}; 2844 2845static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { 2846 { { 0 /* soffsetx4 */ }, 'i' }, 2847 { { 10 /* ar12 */ }, 'o' } 2848}; 2849 2850static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { 2851 { { STATE_PSCALLINC }, 'o' } 2852}; 2853 2854static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { 2855 { { 0 /* soffsetx4 */ }, 'i' }, 2856 { { 9 /* ar8 */ }, 'o' } 2857}; 2858 2859static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { 2860 { { STATE_PSCALLINC }, 'o' } 2861}; 2862 2863static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { 2864 { { 0 /* soffsetx4 */ }, 'i' }, 2865 { { 8 /* ar4 */ }, 'o' } 2866}; 2867 2868static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { 2869 { { STATE_PSCALLINC }, 'o' } 2870}; 2871 2872static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { 2873 { { 4 /* ars */ }, 'i' }, 2874 { { 10 /* ar12 */ }, 'o' } 2875}; 2876 2877static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { 2878 { { STATE_PSCALLINC }, 'o' } 2879}; 2880 2881static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { 2882 { { 4 /* ars */ }, 'i' }, 2883 { { 9 /* ar8 */ }, 'o' } 2884}; 2885 2886static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { 2887 { { STATE_PSCALLINC }, 'o' } 2888}; 2889 2890static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { 2891 { { 4 /* ars */ }, 'i' }, 2892 { { 8 /* ar4 */ }, 'o' } 2893}; 2894 2895static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { 2896 { { STATE_PSCALLINC }, 'o' } 2897}; 2898 2899static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { 2900 { { 11 /* ars_entry */ }, 's' }, 2901 { { 4 /* ars */ }, 'i' }, 2902 { { 1 /* uimm12x8 */ }, 'i' } 2903}; 2904 2905static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { 2906 { { STATE_PSCALLINC }, 'i' }, 2907 { { STATE_PSEXCM }, 'i' }, 2908 { { STATE_PSWOE }, 'i' }, 2909 { { STATE_WindowBase }, 'm' }, 2910 { { STATE_WindowStart }, 'm' } 2911}; 2912 2913static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { 2914 { { 6 /* art */ }, 'o' }, 2915 { { 4 /* ars */ }, 'i' } 2916}; 2917 2918static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { 2919 { { STATE_WindowBase }, 'i' }, 2920 { { STATE_WindowStart }, 'i' } 2921}; 2922 2923static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { 2924 { { 2 /* simm4 */ }, 'i' } 2925}; 2926 2927static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { 2928 { { STATE_PSEXCM }, 'i' }, 2929 { { STATE_PSRING }, 'i' }, 2930 { { STATE_WindowBase }, 'm' } 2931}; 2932 2933static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { 2934 { { 5 /* *ars_invisible */ }, 'i' } 2935}; 2936 2937static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { 2938 { { STATE_WindowBase }, 'm' }, 2939 { { STATE_WindowStart }, 'm' }, 2940 { { STATE_PSEXCM }, 'i' }, 2941 { { STATE_PSWOE }, 'i' } 2942}; 2943 2944static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { 2945 { { STATE_EPC1 }, 'i' }, 2946 { { STATE_PSEXCM }, 'm' }, 2947 { { STATE_PSRING }, 'i' }, 2948 { { STATE_WindowBase }, 'm' }, 2949 { { STATE_WindowStart }, 'm' }, 2950 { { STATE_PSOWB }, 'i' } 2951}; 2952 2953static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { 2954 { { 6 /* art */ }, 'o' }, 2955 { { 4 /* ars */ }, 'i' }, 2956 { { 12 /* immrx4 */ }, 'i' } 2957}; 2958 2959static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { 2960 { { STATE_PSEXCM }, 'i' }, 2961 { { STATE_PSRING }, 'i' } 2962}; 2963 2964static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { 2965 { { 6 /* art */ }, 'i' }, 2966 { { 4 /* ars */ }, 'i' }, 2967 { { 12 /* immrx4 */ }, 'i' } 2968}; 2969 2970static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { 2971 { { STATE_PSEXCM }, 'i' }, 2972 { { STATE_PSRING }, 'i' } 2973}; 2974 2975static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { 2976 { { 6 /* art */ }, 'o' } 2977}; 2978 2979static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { 2980 { { STATE_PSEXCM }, 'i' }, 2981 { { STATE_PSRING }, 'i' }, 2982 { { STATE_WindowBase }, 'i' } 2983}; 2984 2985static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { 2986 { { 6 /* art */ }, 'i' } 2987}; 2988 2989static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { 2990 { { STATE_PSEXCM }, 'i' }, 2991 { { STATE_PSRING }, 'i' }, 2992 { { STATE_WindowBase }, 'o' } 2993}; 2994 2995static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { 2996 { { 6 /* art */ }, 'm' } 2997}; 2998 2999static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { 3000 { { STATE_PSEXCM }, 'i' }, 3001 { { STATE_PSRING }, 'i' }, 3002 { { STATE_WindowBase }, 'm' } 3003}; 3004 3005static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { 3006 { { 6 /* art */ }, 'o' } 3007}; 3008 3009static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { 3010 { { STATE_PSEXCM }, 'i' }, 3011 { { STATE_PSRING }, 'i' }, 3012 { { STATE_WindowStart }, 'i' } 3013}; 3014 3015static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { 3016 { { 6 /* art */ }, 'i' } 3017}; 3018 3019static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { 3020 { { STATE_PSEXCM }, 'i' }, 3021 { { STATE_PSRING }, 'i' }, 3022 { { STATE_WindowStart }, 'o' } 3023}; 3024 3025static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { 3026 { { 6 /* art */ }, 'm' } 3027}; 3028 3029static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { 3030 { { STATE_PSEXCM }, 'i' }, 3031 { { STATE_PSRING }, 'i' }, 3032 { { STATE_WindowStart }, 'm' } 3033}; 3034 3035static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { 3036 { { 3 /* arr */ }, 'o' }, 3037 { { 4 /* ars */ }, 'i' }, 3038 { { 6 /* art */ }, 'i' } 3039}; 3040 3041static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { 3042 { { 3 /* arr */ }, 'o' }, 3043 { { 4 /* ars */ }, 'i' }, 3044 { { 16 /* ai4const */ }, 'i' } 3045}; 3046 3047static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { 3048 { { 4 /* ars */ }, 'i' }, 3049 { { 15 /* uimm6 */ }, 'i' } 3050}; 3051 3052static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { 3053 { { 6 /* art */ }, 'o' }, 3054 { { 4 /* ars */ }, 'i' }, 3055 { { 13 /* lsi4x4 */ }, 'i' } 3056}; 3057 3058static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { 3059 { { 6 /* art */ }, 'o' }, 3060 { { 4 /* ars */ }, 'i' } 3061}; 3062 3063static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { 3064 { { 4 /* ars */ }, 'o' }, 3065 { { 14 /* simm7 */ }, 'i' } 3066}; 3067 3068static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { 3069 { { 5 /* *ars_invisible */ }, 'i' } 3070}; 3071 3072static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { 3073 { { 6 /* art */ }, 'i' }, 3074 { { 4 /* ars */ }, 'i' }, 3075 { { 13 /* lsi4x4 */ }, 'i' } 3076}; 3077 3078static xtensa_arg_internal Iclass_rur_threadptr_args[] = { 3079 { { 3 /* arr */ }, 'o' } 3080}; 3081 3082static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { 3083 { { STATE_THREADPTR }, 'i' } 3084}; 3085 3086static xtensa_arg_internal Iclass_wur_threadptr_args[] = { 3087 { { 6 /* art */ }, 'i' } 3088}; 3089 3090static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { 3091 { { STATE_THREADPTR }, 'o' } 3092}; 3093 3094static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { 3095 { { 6 /* art */ }, 'o' }, 3096 { { 4 /* ars */ }, 'i' }, 3097 { { 23 /* simm8 */ }, 'i' } 3098}; 3099 3100static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { 3101 { { 6 /* art */ }, 'o' }, 3102 { { 4 /* ars */ }, 'i' }, 3103 { { 24 /* simm8x256 */ }, 'i' } 3104}; 3105 3106static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { 3107 { { 3 /* arr */ }, 'o' }, 3108 { { 4 /* ars */ }, 'i' }, 3109 { { 6 /* art */ }, 'i' } 3110}; 3111 3112static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { 3113 { { 3 /* arr */ }, 'o' }, 3114 { { 4 /* ars */ }, 'i' }, 3115 { { 6 /* art */ }, 'i' } 3116}; 3117 3118static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { 3119 { { 4 /* ars */ }, 'i' }, 3120 { { 17 /* b4const */ }, 'i' }, 3121 { { 28 /* label8 */ }, 'i' } 3122}; 3123 3124static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { 3125 { { 4 /* ars */ }, 'i' }, 3126 { { 47 /* bbi */ }, 'i' }, 3127 { { 28 /* label8 */ }, 'i' } 3128}; 3129 3130static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { 3131 { { 4 /* ars */ }, 'i' }, 3132 { { 18 /* b4constu */ }, 'i' }, 3133 { { 28 /* label8 */ }, 'i' } 3134}; 3135 3136static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { 3137 { { 4 /* ars */ }, 'i' }, 3138 { { 6 /* art */ }, 'i' }, 3139 { { 28 /* label8 */ }, 'i' } 3140}; 3141 3142static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { 3143 { { 4 /* ars */ }, 'i' }, 3144 { { 30 /* label12 */ }, 'i' } 3145}; 3146 3147static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { 3148 { { 0 /* soffsetx4 */ }, 'i' }, 3149 { { 7 /* ar0 */ }, 'o' } 3150}; 3151 3152static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { 3153 { { 4 /* ars */ }, 'i' }, 3154 { { 7 /* ar0 */ }, 'o' } 3155}; 3156 3157static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { 3158 { { 3 /* arr */ }, 'o' }, 3159 { { 6 /* art */ }, 'i' }, 3160 { { 62 /* sae */ }, 'i' }, 3161 { { 27 /* op2p1 */ }, 'i' } 3162}; 3163 3164static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { 3165 { { 31 /* soffset */ }, 'i' } 3166}; 3167 3168static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { 3169 { { 4 /* ars */ }, 'i' } 3170}; 3171 3172static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { 3173 { { 6 /* art */ }, 'o' }, 3174 { { 4 /* ars */ }, 'i' }, 3175 { { 20 /* uimm8x2 */ }, 'i' } 3176}; 3177 3178static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { 3179 { { 6 /* art */ }, 'o' }, 3180 { { 4 /* ars */ }, 'i' }, 3181 { { 20 /* uimm8x2 */ }, 'i' } 3182}; 3183 3184static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { 3185 { { 6 /* art */ }, 'o' }, 3186 { { 4 /* ars */ }, 'i' }, 3187 { { 21 /* uimm8x4 */ }, 'i' } 3188}; 3189 3190static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { 3191 { { 6 /* art */ }, 'o' }, 3192 { { 32 /* uimm16x4 */ }, 'i' } 3193}; 3194 3195static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = { 3196 { { STATE_LITBADDR }, 'i' }, 3197 { { STATE_LITBEN }, 'i' } 3198}; 3199 3200static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { 3201 { { 6 /* art */ }, 'o' }, 3202 { { 4 /* ars */ }, 'i' }, 3203 { { 19 /* uimm8 */ }, 'i' } 3204}; 3205 3206static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { 3207 { { 4 /* ars */ }, 'i' }, 3208 { { 29 /* ulabel8 */ }, 'i' } 3209}; 3210 3211static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { 3212 { { STATE_LBEG }, 'o' }, 3213 { { STATE_LEND }, 'o' }, 3214 { { STATE_LCOUNT }, 'o' } 3215}; 3216 3217static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { 3218 { { 4 /* ars */ }, 'i' }, 3219 { { 29 /* ulabel8 */ }, 'i' } 3220}; 3221 3222static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { 3223 { { STATE_LBEG }, 'o' }, 3224 { { STATE_LEND }, 'o' }, 3225 { { STATE_LCOUNT }, 'o' } 3226}; 3227 3228static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { 3229 { { 6 /* art */ }, 'o' }, 3230 { { 25 /* simm12b */ }, 'i' } 3231}; 3232 3233static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { 3234 { { 3 /* arr */ }, 'm' }, 3235 { { 4 /* ars */ }, 'i' }, 3236 { { 6 /* art */ }, 'i' } 3237}; 3238 3239static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { 3240 { { 3 /* arr */ }, 'o' }, 3241 { { 6 /* art */ }, 'i' } 3242}; 3243 3244static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { 3245 { { 5 /* *ars_invisible */ }, 'i' } 3246}; 3247 3248static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { 3249 { { 6 /* art */ }, 'i' }, 3250 { { 4 /* ars */ }, 'i' }, 3251 { { 20 /* uimm8x2 */ }, 'i' } 3252}; 3253 3254static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { 3255 { { 6 /* art */ }, 'i' }, 3256 { { 4 /* ars */ }, 'i' }, 3257 { { 21 /* uimm8x4 */ }, 'i' } 3258}; 3259 3260static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { 3261 { { 6 /* art */ }, 'i' }, 3262 { { 4 /* ars */ }, 'i' }, 3263 { { 19 /* uimm8 */ }, 'i' } 3264}; 3265 3266static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { 3267 { { 4 /* ars */ }, 'i' } 3268}; 3269 3270static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { 3271 { { STATE_SAR }, 'o' } 3272}; 3273 3274static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { 3275 { { 66 /* sas */ }, 'i' } 3276}; 3277 3278static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { 3279 { { STATE_SAR }, 'o' } 3280}; 3281 3282static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { 3283 { { 3 /* arr */ }, 'o' }, 3284 { { 4 /* ars */ }, 'i' } 3285}; 3286 3287static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { 3288 { { STATE_SAR }, 'i' } 3289}; 3290 3291static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { 3292 { { 3 /* arr */ }, 'o' }, 3293 { { 4 /* ars */ }, 'i' }, 3294 { { 6 /* art */ }, 'i' } 3295}; 3296 3297static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { 3298 { { STATE_SAR }, 'i' } 3299}; 3300 3301static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { 3302 { { 3 /* arr */ }, 'o' }, 3303 { { 6 /* art */ }, 'i' } 3304}; 3305 3306static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { 3307 { { STATE_SAR }, 'i' } 3308}; 3309 3310static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { 3311 { { 3 /* arr */ }, 'o' }, 3312 { { 4 /* ars */ }, 'i' }, 3313 { { 26 /* msalp32 */ }, 'i' } 3314}; 3315 3316static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { 3317 { { 3 /* arr */ }, 'o' }, 3318 { { 6 /* art */ }, 'i' }, 3319 { { 64 /* sargt */ }, 'i' } 3320}; 3321 3322static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { 3323 { { 3 /* arr */ }, 'o' }, 3324 { { 6 /* art */ }, 'i' }, 3325 { { 50 /* s */ }, 'i' } 3326}; 3327 3328static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { 3329 { { STATE_XTSYNC }, 'i' } 3330}; 3331 3332static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { 3333 { { 6 /* art */ }, 'o' }, 3334 { { 50 /* s */ }, 'i' } 3335}; 3336 3337static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { 3338 { { STATE_PSWOE }, 'i' }, 3339 { { STATE_PSCALLINC }, 'i' }, 3340 { { STATE_PSOWB }, 'i' }, 3341 { { STATE_PSRING }, 'i' }, 3342 { { STATE_PSUM }, 'i' }, 3343 { { STATE_PSEXCM }, 'i' }, 3344 { { STATE_PSINTLEVEL }, 'm' } 3345}; 3346 3347static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { 3348 { { 6 /* art */ }, 'o' } 3349}; 3350 3351static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { 3352 { { STATE_LEND }, 'i' } 3353}; 3354 3355static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { 3356 { { 6 /* art */ }, 'i' } 3357}; 3358 3359static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { 3360 { { STATE_LEND }, 'o' } 3361}; 3362 3363static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { 3364 { { 6 /* art */ }, 'm' } 3365}; 3366 3367static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { 3368 { { STATE_LEND }, 'm' } 3369}; 3370 3371static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { 3372 { { 6 /* art */ }, 'o' } 3373}; 3374 3375static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { 3376 { { STATE_LCOUNT }, 'i' } 3377}; 3378 3379static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { 3380 { { 6 /* art */ }, 'i' } 3381}; 3382 3383static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { 3384 { { STATE_XTSYNC }, 'o' }, 3385 { { STATE_LCOUNT }, 'o' } 3386}; 3387 3388static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { 3389 { { 6 /* art */ }, 'm' } 3390}; 3391 3392static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { 3393 { { STATE_XTSYNC }, 'o' }, 3394 { { STATE_LCOUNT }, 'm' } 3395}; 3396 3397static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { 3398 { { 6 /* art */ }, 'o' } 3399}; 3400 3401static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { 3402 { { STATE_LBEG }, 'i' } 3403}; 3404 3405static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { 3406 { { 6 /* art */ }, 'i' } 3407}; 3408 3409static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { 3410 { { STATE_LBEG }, 'o' } 3411}; 3412 3413static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { 3414 { { 6 /* art */ }, 'm' } 3415}; 3416 3417static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { 3418 { { STATE_LBEG }, 'm' } 3419}; 3420 3421static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { 3422 { { 6 /* art */ }, 'o' } 3423}; 3424 3425static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { 3426 { { STATE_SAR }, 'i' } 3427}; 3428 3429static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { 3430 { { 6 /* art */ }, 'i' } 3431}; 3432 3433static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { 3434 { { STATE_SAR }, 'o' }, 3435 { { STATE_XTSYNC }, 'o' } 3436}; 3437 3438static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { 3439 { { 6 /* art */ }, 'm' } 3440}; 3441 3442static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { 3443 { { STATE_SAR }, 'm' } 3444}; 3445 3446static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { 3447 { { 6 /* art */ }, 'o' } 3448}; 3449 3450static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = { 3451 { { STATE_LITBADDR }, 'i' }, 3452 { { STATE_LITBEN }, 'i' } 3453}; 3454 3455static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { 3456 { { 6 /* art */ }, 'i' } 3457}; 3458 3459static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = { 3460 { { STATE_LITBADDR }, 'o' }, 3461 { { STATE_LITBEN }, 'o' } 3462}; 3463 3464static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { 3465 { { 6 /* art */ }, 'm' } 3466}; 3467 3468static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = { 3469 { { STATE_LITBADDR }, 'm' }, 3470 { { STATE_LITBEN }, 'm' } 3471}; 3472 3473static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = { 3474 { { 6 /* art */ }, 'o' } 3475}; 3476 3477static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = { 3478 { { STATE_PSEXCM }, 'i' }, 3479 { { STATE_PSRING }, 'i' } 3480}; 3481 3482static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = { 3483 { { 6 /* art */ }, 'o' } 3484}; 3485 3486static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = { 3487 { { STATE_PSEXCM }, 'i' }, 3488 { { STATE_PSRING }, 'i' } 3489}; 3490 3491static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { 3492 { { 6 /* art */ }, 'o' } 3493}; 3494 3495static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { 3496 { { STATE_PSWOE }, 'i' }, 3497 { { STATE_PSCALLINC }, 'i' }, 3498 { { STATE_PSOWB }, 'i' }, 3499 { { STATE_PSRING }, 'i' }, 3500 { { STATE_PSUM }, 'i' }, 3501 { { STATE_PSEXCM }, 'i' }, 3502 { { STATE_PSINTLEVEL }, 'i' } 3503}; 3504 3505static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { 3506 { { 6 /* art */ }, 'i' } 3507}; 3508 3509static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { 3510 { { STATE_PSWOE }, 'o' }, 3511 { { STATE_PSCALLINC }, 'o' }, 3512 { { STATE_PSOWB }, 'o' }, 3513 { { STATE_PSRING }, 'm' }, 3514 { { STATE_PSUM }, 'o' }, 3515 { { STATE_PSEXCM }, 'm' }, 3516 { { STATE_PSINTLEVEL }, 'o' } 3517}; 3518 3519static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { 3520 { { 6 /* art */ }, 'm' } 3521}; 3522 3523static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { 3524 { { STATE_PSWOE }, 'm' }, 3525 { { STATE_PSCALLINC }, 'm' }, 3526 { { STATE_PSOWB }, 'm' }, 3527 { { STATE_PSRING }, 'm' }, 3528 { { STATE_PSUM }, 'm' }, 3529 { { STATE_PSEXCM }, 'm' }, 3530 { { STATE_PSINTLEVEL }, 'm' } 3531}; 3532 3533static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { 3534 { { 6 /* art */ }, 'o' } 3535}; 3536 3537static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { 3538 { { STATE_PSEXCM }, 'i' }, 3539 { { STATE_PSRING }, 'i' }, 3540 { { STATE_EPC1 }, 'i' } 3541}; 3542 3543static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { 3544 { { 6 /* art */ }, 'i' } 3545}; 3546 3547static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { 3548 { { STATE_PSEXCM }, 'i' }, 3549 { { STATE_PSRING }, 'i' }, 3550 { { STATE_EPC1 }, 'o' } 3551}; 3552 3553static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { 3554 { { 6 /* art */ }, 'm' } 3555}; 3556 3557static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { 3558 { { STATE_PSEXCM }, 'i' }, 3559 { { STATE_PSRING }, 'i' }, 3560 { { STATE_EPC1 }, 'm' } 3561}; 3562 3563static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { 3564 { { 6 /* art */ }, 'o' } 3565}; 3566 3567static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { 3568 { { STATE_PSEXCM }, 'i' }, 3569 { { STATE_PSRING }, 'i' }, 3570 { { STATE_EXCSAVE1 }, 'i' } 3571}; 3572 3573static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { 3574 { { 6 /* art */ }, 'i' } 3575}; 3576 3577static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { 3578 { { STATE_PSEXCM }, 'i' }, 3579 { { STATE_PSRING }, 'i' }, 3580 { { STATE_EXCSAVE1 }, 'o' } 3581}; 3582 3583static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { 3584 { { 6 /* art */ }, 'm' } 3585}; 3586 3587static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { 3588 { { STATE_PSEXCM }, 'i' }, 3589 { { STATE_PSRING }, 'i' }, 3590 { { STATE_EXCSAVE1 }, 'm' } 3591}; 3592 3593static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { 3594 { { 6 /* art */ }, 'o' } 3595}; 3596 3597static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { 3598 { { STATE_PSEXCM }, 'i' }, 3599 { { STATE_PSRING }, 'i' }, 3600 { { STATE_EPC2 }, 'i' } 3601}; 3602 3603static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { 3604 { { 6 /* art */ }, 'i' } 3605}; 3606 3607static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { 3608 { { STATE_PSEXCM }, 'i' }, 3609 { { STATE_PSRING }, 'i' }, 3610 { { STATE_EPC2 }, 'o' } 3611}; 3612 3613static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { 3614 { { 6 /* art */ }, 'm' } 3615}; 3616 3617static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { 3618 { { STATE_PSEXCM }, 'i' }, 3619 { { STATE_PSRING }, 'i' }, 3620 { { STATE_EPC2 }, 'm' } 3621}; 3622 3623static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { 3624 { { 6 /* art */ }, 'o' } 3625}; 3626 3627static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { 3628 { { STATE_PSEXCM }, 'i' }, 3629 { { STATE_PSRING }, 'i' }, 3630 { { STATE_EXCSAVE2 }, 'i' } 3631}; 3632 3633static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { 3634 { { 6 /* art */ }, 'i' } 3635}; 3636 3637static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { 3638 { { STATE_PSEXCM }, 'i' }, 3639 { { STATE_PSRING }, 'i' }, 3640 { { STATE_EXCSAVE2 }, 'o' } 3641}; 3642 3643static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { 3644 { { 6 /* art */ }, 'm' } 3645}; 3646 3647static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { 3648 { { STATE_PSEXCM }, 'i' }, 3649 { { STATE_PSRING }, 'i' }, 3650 { { STATE_EXCSAVE2 }, 'm' } 3651}; 3652 3653static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { 3654 { { 6 /* art */ }, 'o' } 3655}; 3656 3657static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { 3658 { { STATE_PSEXCM }, 'i' }, 3659 { { STATE_PSRING }, 'i' }, 3660 { { STATE_EPC3 }, 'i' } 3661}; 3662 3663static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { 3664 { { 6 /* art */ }, 'i' } 3665}; 3666 3667static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { 3668 { { STATE_PSEXCM }, 'i' }, 3669 { { STATE_PSRING }, 'i' }, 3670 { { STATE_EPC3 }, 'o' } 3671}; 3672 3673static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { 3674 { { 6 /* art */ }, 'm' } 3675}; 3676 3677static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { 3678 { { STATE_PSEXCM }, 'i' }, 3679 { { STATE_PSRING }, 'i' }, 3680 { { STATE_EPC3 }, 'm' } 3681}; 3682 3683static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { 3684 { { 6 /* art */ }, 'o' } 3685}; 3686 3687static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { 3688 { { STATE_PSEXCM }, 'i' }, 3689 { { STATE_PSRING }, 'i' }, 3690 { { STATE_EXCSAVE3 }, 'i' } 3691}; 3692 3693static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { 3694 { { 6 /* art */ }, 'i' } 3695}; 3696 3697static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { 3698 { { STATE_PSEXCM }, 'i' }, 3699 { { STATE_PSRING }, 'i' }, 3700 { { STATE_EXCSAVE3 }, 'o' } 3701}; 3702 3703static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { 3704 { { 6 /* art */ }, 'm' } 3705}; 3706 3707static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { 3708 { { STATE_PSEXCM }, 'i' }, 3709 { { STATE_PSRING }, 'i' }, 3710 { { STATE_EXCSAVE3 }, 'm' } 3711}; 3712 3713static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { 3714 { { 6 /* art */ }, 'o' } 3715}; 3716 3717static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { 3718 { { STATE_PSEXCM }, 'i' }, 3719 { { STATE_PSRING }, 'i' }, 3720 { { STATE_EPC4 }, 'i' } 3721}; 3722 3723static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { 3724 { { 6 /* art */ }, 'i' } 3725}; 3726 3727static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { 3728 { { STATE_PSEXCM }, 'i' }, 3729 { { STATE_PSRING }, 'i' }, 3730 { { STATE_EPC4 }, 'o' } 3731}; 3732 3733static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { 3734 { { 6 /* art */ }, 'm' } 3735}; 3736 3737static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { 3738 { { STATE_PSEXCM }, 'i' }, 3739 { { STATE_PSRING }, 'i' }, 3740 { { STATE_EPC4 }, 'm' } 3741}; 3742 3743static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { 3744 { { 6 /* art */ }, 'o' } 3745}; 3746 3747static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { 3748 { { STATE_PSEXCM }, 'i' }, 3749 { { STATE_PSRING }, 'i' }, 3750 { { STATE_EXCSAVE4 }, 'i' } 3751}; 3752 3753static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { 3754 { { 6 /* art */ }, 'i' } 3755}; 3756 3757static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { 3758 { { STATE_PSEXCM }, 'i' }, 3759 { { STATE_PSRING }, 'i' }, 3760 { { STATE_EXCSAVE4 }, 'o' } 3761}; 3762 3763static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { 3764 { { 6 /* art */ }, 'm' } 3765}; 3766 3767static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { 3768 { { STATE_PSEXCM }, 'i' }, 3769 { { STATE_PSRING }, 'i' }, 3770 { { STATE_EXCSAVE4 }, 'm' } 3771}; 3772 3773static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { 3774 { { 6 /* art */ }, 'o' } 3775}; 3776 3777static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { 3778 { { STATE_PSEXCM }, 'i' }, 3779 { { STATE_PSRING }, 'i' }, 3780 { { STATE_EPC5 }, 'i' } 3781}; 3782 3783static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { 3784 { { 6 /* art */ }, 'i' } 3785}; 3786 3787static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { 3788 { { STATE_PSEXCM }, 'i' }, 3789 { { STATE_PSRING }, 'i' }, 3790 { { STATE_EPC5 }, 'o' } 3791}; 3792 3793static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { 3794 { { 6 /* art */ }, 'm' } 3795}; 3796 3797static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { 3798 { { STATE_PSEXCM }, 'i' }, 3799 { { STATE_PSRING }, 'i' }, 3800 { { STATE_EPC5 }, 'm' } 3801}; 3802 3803static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { 3804 { { 6 /* art */ }, 'o' } 3805}; 3806 3807static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { 3808 { { STATE_PSEXCM }, 'i' }, 3809 { { STATE_PSRING }, 'i' }, 3810 { { STATE_EXCSAVE5 }, 'i' } 3811}; 3812 3813static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { 3814 { { 6 /* art */ }, 'i' } 3815}; 3816 3817static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { 3818 { { STATE_PSEXCM }, 'i' }, 3819 { { STATE_PSRING }, 'i' }, 3820 { { STATE_EXCSAVE5 }, 'o' } 3821}; 3822 3823static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { 3824 { { 6 /* art */ }, 'm' } 3825}; 3826 3827static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { 3828 { { STATE_PSEXCM }, 'i' }, 3829 { { STATE_PSRING }, 'i' }, 3830 { { STATE_EXCSAVE5 }, 'm' } 3831}; 3832 3833static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { 3834 { { 6 /* art */ }, 'o' } 3835}; 3836 3837static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { 3838 { { STATE_PSEXCM }, 'i' }, 3839 { { STATE_PSRING }, 'i' }, 3840 { { STATE_EPC6 }, 'i' } 3841}; 3842 3843static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { 3844 { { 6 /* art */ }, 'i' } 3845}; 3846 3847static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { 3848 { { STATE_PSEXCM }, 'i' }, 3849 { { STATE_PSRING }, 'i' }, 3850 { { STATE_EPC6 }, 'o' } 3851}; 3852 3853static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { 3854 { { 6 /* art */ }, 'm' } 3855}; 3856 3857static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { 3858 { { STATE_PSEXCM }, 'i' }, 3859 { { STATE_PSRING }, 'i' }, 3860 { { STATE_EPC6 }, 'm' } 3861}; 3862 3863static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { 3864 { { 6 /* art */ }, 'o' } 3865}; 3866 3867static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { 3868 { { STATE_PSEXCM }, 'i' }, 3869 { { STATE_PSRING }, 'i' }, 3870 { { STATE_EXCSAVE6 }, 'i' } 3871}; 3872 3873static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { 3874 { { 6 /* art */ }, 'i' } 3875}; 3876 3877static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { 3878 { { STATE_PSEXCM }, 'i' }, 3879 { { STATE_PSRING }, 'i' }, 3880 { { STATE_EXCSAVE6 }, 'o' } 3881}; 3882 3883static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { 3884 { { 6 /* art */ }, 'm' } 3885}; 3886 3887static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { 3888 { { STATE_PSEXCM }, 'i' }, 3889 { { STATE_PSRING }, 'i' }, 3890 { { STATE_EXCSAVE6 }, 'm' } 3891}; 3892 3893static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = { 3894 { { 6 /* art */ }, 'o' } 3895}; 3896 3897static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = { 3898 { { STATE_PSEXCM }, 'i' }, 3899 { { STATE_PSRING }, 'i' }, 3900 { { STATE_EPC7 }, 'i' } 3901}; 3902 3903static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = { 3904 { { 6 /* art */ }, 'i' } 3905}; 3906 3907static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = { 3908 { { STATE_PSEXCM }, 'i' }, 3909 { { STATE_PSRING }, 'i' }, 3910 { { STATE_EPC7 }, 'o' } 3911}; 3912 3913static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = { 3914 { { 6 /* art */ }, 'm' } 3915}; 3916 3917static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = { 3918 { { STATE_PSEXCM }, 'i' }, 3919 { { STATE_PSRING }, 'i' }, 3920 { { STATE_EPC7 }, 'm' } 3921}; 3922 3923static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = { 3924 { { 6 /* art */ }, 'o' } 3925}; 3926 3927static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = { 3928 { { STATE_PSEXCM }, 'i' }, 3929 { { STATE_PSRING }, 'i' }, 3930 { { STATE_EXCSAVE7 }, 'i' } 3931}; 3932 3933static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = { 3934 { { 6 /* art */ }, 'i' } 3935}; 3936 3937static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = { 3938 { { STATE_PSEXCM }, 'i' }, 3939 { { STATE_PSRING }, 'i' }, 3940 { { STATE_EXCSAVE7 }, 'o' } 3941}; 3942 3943static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = { 3944 { { 6 /* art */ }, 'm' } 3945}; 3946 3947static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = { 3948 { { STATE_PSEXCM }, 'i' }, 3949 { { STATE_PSRING }, 'i' }, 3950 { { STATE_EXCSAVE7 }, 'm' } 3951}; 3952 3953static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { 3954 { { 6 /* art */ }, 'o' } 3955}; 3956 3957static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { 3958 { { STATE_PSEXCM }, 'i' }, 3959 { { STATE_PSRING }, 'i' }, 3960 { { STATE_EPS2 }, 'i' } 3961}; 3962 3963static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { 3964 { { 6 /* art */ }, 'i' } 3965}; 3966 3967static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { 3968 { { STATE_PSEXCM }, 'i' }, 3969 { { STATE_PSRING }, 'i' }, 3970 { { STATE_EPS2 }, 'o' } 3971}; 3972 3973static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { 3974 { { 6 /* art */ }, 'm' } 3975}; 3976 3977static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { 3978 { { STATE_PSEXCM }, 'i' }, 3979 { { STATE_PSRING }, 'i' }, 3980 { { STATE_EPS2 }, 'm' } 3981}; 3982 3983static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { 3984 { { 6 /* art */ }, 'o' } 3985}; 3986 3987static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { 3988 { { STATE_PSEXCM }, 'i' }, 3989 { { STATE_PSRING }, 'i' }, 3990 { { STATE_EPS3 }, 'i' } 3991}; 3992 3993static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { 3994 { { 6 /* art */ }, 'i' } 3995}; 3996 3997static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { 3998 { { STATE_PSEXCM }, 'i' }, 3999 { { STATE_PSRING }, 'i' }, 4000 { { STATE_EPS3 }, 'o' } 4001}; 4002 4003static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { 4004 { { 6 /* art */ }, 'm' } 4005}; 4006 4007static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { 4008 { { STATE_PSEXCM }, 'i' }, 4009 { { STATE_PSRING }, 'i' }, 4010 { { STATE_EPS3 }, 'm' } 4011}; 4012 4013static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { 4014 { { 6 /* art */ }, 'o' } 4015}; 4016 4017static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { 4018 { { STATE_PSEXCM }, 'i' }, 4019 { { STATE_PSRING }, 'i' }, 4020 { { STATE_EPS4 }, 'i' } 4021}; 4022 4023static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { 4024 { { 6 /* art */ }, 'i' } 4025}; 4026 4027static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { 4028 { { STATE_PSEXCM }, 'i' }, 4029 { { STATE_PSRING }, 'i' }, 4030 { { STATE_EPS4 }, 'o' } 4031}; 4032 4033static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { 4034 { { 6 /* art */ }, 'm' } 4035}; 4036 4037static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { 4038 { { STATE_PSEXCM }, 'i' }, 4039 { { STATE_PSRING }, 'i' }, 4040 { { STATE_EPS4 }, 'm' } 4041}; 4042 4043static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { 4044 { { 6 /* art */ }, 'o' } 4045}; 4046 4047static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { 4048 { { STATE_PSEXCM }, 'i' }, 4049 { { STATE_PSRING }, 'i' }, 4050 { { STATE_EPS5 }, 'i' } 4051}; 4052 4053static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { 4054 { { 6 /* art */ }, 'i' } 4055}; 4056 4057static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { 4058 { { STATE_PSEXCM }, 'i' }, 4059 { { STATE_PSRING }, 'i' }, 4060 { { STATE_EPS5 }, 'o' } 4061}; 4062 4063static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { 4064 { { 6 /* art */ }, 'm' } 4065}; 4066 4067static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { 4068 { { STATE_PSEXCM }, 'i' }, 4069 { { STATE_PSRING }, 'i' }, 4070 { { STATE_EPS5 }, 'm' } 4071}; 4072 4073static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { 4074 { { 6 /* art */ }, 'o' } 4075}; 4076 4077static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { 4078 { { STATE_PSEXCM }, 'i' }, 4079 { { STATE_PSRING }, 'i' }, 4080 { { STATE_EPS6 }, 'i' } 4081}; 4082 4083static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { 4084 { { 6 /* art */ }, 'i' } 4085}; 4086 4087static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { 4088 { { STATE_PSEXCM }, 'i' }, 4089 { { STATE_PSRING }, 'i' }, 4090 { { STATE_EPS6 }, 'o' } 4091}; 4092 4093static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { 4094 { { 6 /* art */ }, 'm' } 4095}; 4096 4097static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { 4098 { { STATE_PSEXCM }, 'i' }, 4099 { { STATE_PSRING }, 'i' }, 4100 { { STATE_EPS6 }, 'm' } 4101}; 4102 4103static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = { 4104 { { 6 /* art */ }, 'o' } 4105}; 4106 4107static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = { 4108 { { STATE_PSEXCM }, 'i' }, 4109 { { STATE_PSRING }, 'i' }, 4110 { { STATE_EPS7 }, 'i' } 4111}; 4112 4113static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = { 4114 { { 6 /* art */ }, 'i' } 4115}; 4116 4117static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = { 4118 { { STATE_PSEXCM }, 'i' }, 4119 { { STATE_PSRING }, 'i' }, 4120 { { STATE_EPS7 }, 'o' } 4121}; 4122 4123static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = { 4124 { { 6 /* art */ }, 'm' } 4125}; 4126 4127static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = { 4128 { { STATE_PSEXCM }, 'i' }, 4129 { { STATE_PSRING }, 'i' }, 4130 { { STATE_EPS7 }, 'm' } 4131}; 4132 4133static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { 4134 { { 6 /* art */ }, 'o' } 4135}; 4136 4137static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { 4138 { { STATE_PSEXCM }, 'i' }, 4139 { { STATE_PSRING }, 'i' }, 4140 { { STATE_EXCVADDR }, 'i' } 4141}; 4142 4143static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { 4144 { { 6 /* art */ }, 'i' } 4145}; 4146 4147static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { 4148 { { STATE_PSEXCM }, 'i' }, 4149 { { STATE_PSRING }, 'i' }, 4150 { { STATE_EXCVADDR }, 'o' } 4151}; 4152 4153static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { 4154 { { 6 /* art */ }, 'm' } 4155}; 4156 4157static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { 4158 { { STATE_PSEXCM }, 'i' }, 4159 { { STATE_PSRING }, 'i' }, 4160 { { STATE_EXCVADDR }, 'm' } 4161}; 4162 4163static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { 4164 { { 6 /* art */ }, 'o' } 4165}; 4166 4167static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { 4168 { { STATE_PSEXCM }, 'i' }, 4169 { { STATE_PSRING }, 'i' }, 4170 { { STATE_DEPC }, 'i' } 4171}; 4172 4173static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { 4174 { { 6 /* art */ }, 'i' } 4175}; 4176 4177static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { 4178 { { STATE_PSEXCM }, 'i' }, 4179 { { STATE_PSRING }, 'i' }, 4180 { { STATE_DEPC }, 'o' } 4181}; 4182 4183static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { 4184 { { 6 /* art */ }, 'm' } 4185}; 4186 4187static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { 4188 { { STATE_PSEXCM }, 'i' }, 4189 { { STATE_PSRING }, 'i' }, 4190 { { STATE_DEPC }, 'm' } 4191}; 4192 4193static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { 4194 { { 6 /* art */ }, 'o' } 4195}; 4196 4197static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { 4198 { { STATE_PSEXCM }, 'i' }, 4199 { { STATE_PSRING }, 'i' }, 4200 { { STATE_EXCCAUSE }, 'i' }, 4201 { { STATE_XTSYNC }, 'i' } 4202}; 4203 4204static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { 4205 { { 6 /* art */ }, 'i' } 4206}; 4207 4208static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { 4209 { { STATE_PSEXCM }, 'i' }, 4210 { { STATE_PSRING }, 'i' }, 4211 { { STATE_EXCCAUSE }, 'o' } 4212}; 4213 4214static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { 4215 { { 6 /* art */ }, 'm' } 4216}; 4217 4218static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { 4219 { { STATE_PSEXCM }, 'i' }, 4220 { { STATE_PSRING }, 'i' }, 4221 { { STATE_EXCCAUSE }, 'm' } 4222}; 4223 4224static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { 4225 { { 6 /* art */ }, 'o' } 4226}; 4227 4228static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { 4229 { { STATE_PSEXCM }, 'i' }, 4230 { { STATE_PSRING }, 'i' }, 4231 { { STATE_MISC0 }, 'i' } 4232}; 4233 4234static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { 4235 { { 6 /* art */ }, 'i' } 4236}; 4237 4238static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { 4239 { { STATE_PSEXCM }, 'i' }, 4240 { { STATE_PSRING }, 'i' }, 4241 { { STATE_MISC0 }, 'o' } 4242}; 4243 4244static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { 4245 { { 6 /* art */ }, 'm' } 4246}; 4247 4248static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { 4249 { { STATE_PSEXCM }, 'i' }, 4250 { { STATE_PSRING }, 'i' }, 4251 { { STATE_MISC0 }, 'm' } 4252}; 4253 4254static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { 4255 { { 6 /* art */ }, 'o' } 4256}; 4257 4258static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { 4259 { { STATE_PSEXCM }, 'i' }, 4260 { { STATE_PSRING }, 'i' }, 4261 { { STATE_MISC1 }, 'i' } 4262}; 4263 4264static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { 4265 { { 6 /* art */ }, 'i' } 4266}; 4267 4268static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { 4269 { { STATE_PSEXCM }, 'i' }, 4270 { { STATE_PSRING }, 'i' }, 4271 { { STATE_MISC1 }, 'o' } 4272}; 4273 4274static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { 4275 { { 6 /* art */ }, 'm' } 4276}; 4277 4278static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { 4279 { { STATE_PSEXCM }, 'i' }, 4280 { { STATE_PSRING }, 'i' }, 4281 { { STATE_MISC1 }, 'm' } 4282}; 4283 4284static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { 4285 { { 6 /* art */ }, 'o' } 4286}; 4287 4288static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { 4289 { { STATE_PSEXCM }, 'i' }, 4290 { { STATE_PSRING }, 'i' } 4291}; 4292 4293static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { 4294 { { 6 /* art */ }, 'o' } 4295}; 4296 4297static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { 4298 { { STATE_PSEXCM }, 'i' }, 4299 { { STATE_PSRING }, 'i' }, 4300 { { STATE_VECBASE }, 'i' } 4301}; 4302 4303static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { 4304 { { 6 /* art */ }, 'i' } 4305}; 4306 4307static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { 4308 { { STATE_PSEXCM }, 'i' }, 4309 { { STATE_PSRING }, 'i' }, 4310 { { STATE_VECBASE }, 'o' } 4311}; 4312 4313static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { 4314 { { 6 /* art */ }, 'm' } 4315}; 4316 4317static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { 4318 { { STATE_PSEXCM }, 'i' }, 4319 { { STATE_PSRING }, 'i' }, 4320 { { STATE_VECBASE }, 'm' } 4321}; 4322 4323static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = { 4324 { { 4 /* ars */ }, 'i' }, 4325 { { 6 /* art */ }, 'i' } 4326}; 4327 4328static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = { 4329 { { STATE_ACC }, 'o' } 4330}; 4331 4332static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = { 4333 { { 4 /* ars */ }, 'i' }, 4334 { { 34 /* my */ }, 'i' } 4335}; 4336 4337static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = { 4338 { { STATE_ACC }, 'o' } 4339}; 4340 4341static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = { 4342 { { 33 /* mx */ }, 'i' }, 4343 { { 6 /* art */ }, 'i' } 4344}; 4345 4346static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = { 4347 { { STATE_ACC }, 'o' } 4348}; 4349 4350static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = { 4351 { { 33 /* mx */ }, 'i' }, 4352 { { 34 /* my */ }, 'i' } 4353}; 4354 4355static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = { 4356 { { STATE_ACC }, 'o' } 4357}; 4358 4359static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = { 4360 { { 4 /* ars */ }, 'i' }, 4361 { { 6 /* art */ }, 'i' } 4362}; 4363 4364static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = { 4365 { { STATE_ACC }, 'm' } 4366}; 4367 4368static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = { 4369 { { 4 /* ars */ }, 'i' }, 4370 { { 34 /* my */ }, 'i' } 4371}; 4372 4373static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = { 4374 { { STATE_ACC }, 'm' } 4375}; 4376 4377static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = { 4378 { { 33 /* mx */ }, 'i' }, 4379 { { 6 /* art */ }, 'i' } 4380}; 4381 4382static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = { 4383 { { STATE_ACC }, 'm' } 4384}; 4385 4386static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = { 4387 { { 33 /* mx */ }, 'i' }, 4388 { { 34 /* my */ }, 'i' } 4389}; 4390 4391static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = { 4392 { { STATE_ACC }, 'm' } 4393}; 4394 4395static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = { 4396 { { 35 /* mw */ }, 'o' }, 4397 { { 4 /* ars */ }, 'm' }, 4398 { { 33 /* mx */ }, 'i' }, 4399 { { 6 /* art */ }, 'i' } 4400}; 4401 4402static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = { 4403 { { STATE_ACC }, 'm' } 4404}; 4405 4406static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = { 4407 { { 35 /* mw */ }, 'o' }, 4408 { { 4 /* ars */ }, 'm' }, 4409 { { 33 /* mx */ }, 'i' }, 4410 { { 34 /* my */ }, 'i' } 4411}; 4412 4413static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = { 4414 { { STATE_ACC }, 'm' } 4415}; 4416 4417static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = { 4418 { { 35 /* mw */ }, 'o' }, 4419 { { 4 /* ars */ }, 'm' } 4420}; 4421 4422static xtensa_arg_internal Iclass_xt_iclass_mul16_args[] = { 4423 { { 3 /* arr */ }, 'o' }, 4424 { { 4 /* ars */ }, 'i' }, 4425 { { 6 /* art */ }, 'i' } 4426}; 4427 4428static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = { 4429 { { 6 /* art */ }, 'o' }, 4430 { { 36 /* mr0 */ }, 'i' } 4431}; 4432 4433static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = { 4434 { { 6 /* art */ }, 'i' }, 4435 { { 36 /* mr0 */ }, 'o' } 4436}; 4437 4438static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = { 4439 { { 6 /* art */ }, 'm' }, 4440 { { 36 /* mr0 */ }, 'm' } 4441}; 4442 4443static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = { 4444 { { 6 /* art */ }, 'o' }, 4445 { { 37 /* mr1 */ }, 'i' } 4446}; 4447 4448static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = { 4449 { { 6 /* art */ }, 'i' }, 4450 { { 37 /* mr1 */ }, 'o' } 4451}; 4452 4453static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = { 4454 { { 6 /* art */ }, 'm' }, 4455 { { 37 /* mr1 */ }, 'm' } 4456}; 4457 4458static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = { 4459 { { 6 /* art */ }, 'o' }, 4460 { { 38 /* mr2 */ }, 'i' } 4461}; 4462 4463static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = { 4464 { { 6 /* art */ }, 'i' }, 4465 { { 38 /* mr2 */ }, 'o' } 4466}; 4467 4468static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = { 4469 { { 6 /* art */ }, 'm' }, 4470 { { 38 /* mr2 */ }, 'm' } 4471}; 4472 4473static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = { 4474 { { 6 /* art */ }, 'o' }, 4475 { { 39 /* mr3 */ }, 'i' } 4476}; 4477 4478static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = { 4479 { { 6 /* art */ }, 'i' }, 4480 { { 39 /* mr3 */ }, 'o' } 4481}; 4482 4483static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = { 4484 { { 6 /* art */ }, 'm' }, 4485 { { 39 /* mr3 */ }, 'm' } 4486}; 4487 4488static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = { 4489 { { 6 /* art */ }, 'o' } 4490}; 4491 4492static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = { 4493 { { STATE_ACC }, 'i' } 4494}; 4495 4496static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = { 4497 { { 6 /* art */ }, 'i' } 4498}; 4499 4500static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = { 4501 { { STATE_ACC }, 'm' } 4502}; 4503 4504static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = { 4505 { { 6 /* art */ }, 'm' } 4506}; 4507 4508static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = { 4509 { { STATE_ACC }, 'm' } 4510}; 4511 4512static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = { 4513 { { 6 /* art */ }, 'o' } 4514}; 4515 4516static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = { 4517 { { STATE_ACC }, 'i' } 4518}; 4519 4520static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = { 4521 { { 6 /* art */ }, 'i' } 4522}; 4523 4524static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = { 4525 { { STATE_ACC }, 'm' } 4526}; 4527 4528static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = { 4529 { { 6 /* art */ }, 'm' } 4530}; 4531 4532static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = { 4533 { { STATE_ACC }, 'm' } 4534}; 4535 4536static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { 4537 { { 50 /* s */ }, 'i' } 4538}; 4539 4540static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { 4541 { { STATE_PSWOE }, 'o' }, 4542 { { STATE_PSCALLINC }, 'o' }, 4543 { { STATE_PSOWB }, 'o' }, 4544 { { STATE_PSRING }, 'm' }, 4545 { { STATE_PSUM }, 'o' }, 4546 { { STATE_PSEXCM }, 'm' }, 4547 { { STATE_PSINTLEVEL }, 'o' }, 4548 { { STATE_EPC1 }, 'i' }, 4549 { { STATE_EPC2 }, 'i' }, 4550 { { STATE_EPC3 }, 'i' }, 4551 { { STATE_EPC4 }, 'i' }, 4552 { { STATE_EPC5 }, 'i' }, 4553 { { STATE_EPC6 }, 'i' }, 4554 { { STATE_EPC7 }, 'i' }, 4555 { { STATE_EPS2 }, 'i' }, 4556 { { STATE_EPS3 }, 'i' }, 4557 { { STATE_EPS4 }, 'i' }, 4558 { { STATE_EPS5 }, 'i' }, 4559 { { STATE_EPS6 }, 'i' }, 4560 { { STATE_EPS7 }, 'i' }, 4561 { { STATE_InOCDMode }, 'm' } 4562}; 4563 4564static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { 4565 { { 50 /* s */ }, 'i' } 4566}; 4567 4568static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { 4569 { { STATE_PSEXCM }, 'i' }, 4570 { { STATE_PSRING }, 'i' }, 4571 { { STATE_PSINTLEVEL }, 'o' } 4572}; 4573 4574static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { 4575 { { 6 /* art */ }, 'o' } 4576}; 4577 4578static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { 4579 { { STATE_PSEXCM }, 'i' }, 4580 { { STATE_PSRING }, 'i' }, 4581 { { STATE_INTERRUPT }, 'i' } 4582}; 4583 4584static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { 4585 { { 6 /* art */ }, 'i' } 4586}; 4587 4588static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { 4589 { { STATE_PSEXCM }, 'i' }, 4590 { { STATE_PSRING }, 'i' }, 4591 { { STATE_XTSYNC }, 'o' }, 4592 { { STATE_INTERRUPT }, 'm' } 4593}; 4594 4595static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { 4596 { { 6 /* art */ }, 'i' } 4597}; 4598 4599static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { 4600 { { STATE_PSEXCM }, 'i' }, 4601 { { STATE_PSRING }, 'i' }, 4602 { { STATE_XTSYNC }, 'o' }, 4603 { { STATE_INTERRUPT }, 'm' } 4604}; 4605 4606static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { 4607 { { 6 /* art */ }, 'o' } 4608}; 4609 4610static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { 4611 { { STATE_PSEXCM }, 'i' }, 4612 { { STATE_PSRING }, 'i' }, 4613 { { STATE_INTENABLE }, 'i' } 4614}; 4615 4616static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { 4617 { { 6 /* art */ }, 'i' } 4618}; 4619 4620static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { 4621 { { STATE_PSEXCM }, 'i' }, 4622 { { STATE_PSRING }, 'i' }, 4623 { { STATE_INTENABLE }, 'o' } 4624}; 4625 4626static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { 4627 { { 6 /* art */ }, 'm' } 4628}; 4629 4630static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { 4631 { { STATE_PSEXCM }, 'i' }, 4632 { { STATE_PSRING }, 'i' }, 4633 { { STATE_INTENABLE }, 'm' } 4634}; 4635 4636static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { 4637 { { 41 /* imms */ }, 'i' }, 4638 { { 40 /* immt */ }, 'i' } 4639}; 4640 4641static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { 4642 { { STATE_PSEXCM }, 'i' }, 4643 { { STATE_PSINTLEVEL }, 'i' } 4644}; 4645 4646static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { 4647 { { 41 /* imms */ }, 'i' } 4648}; 4649 4650static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { 4651 { { STATE_PSEXCM }, 'i' }, 4652 { { STATE_PSINTLEVEL }, 'i' } 4653}; 4654 4655static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { 4656 { { 6 /* art */ }, 'o' } 4657}; 4658 4659static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { 4660 { { STATE_PSEXCM }, 'i' }, 4661 { { STATE_PSRING }, 'i' }, 4662 { { STATE_DBREAKA0 }, 'i' } 4663}; 4664 4665static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { 4666 { { 6 /* art */ }, 'i' } 4667}; 4668 4669static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { 4670 { { STATE_PSEXCM }, 'i' }, 4671 { { STATE_PSRING }, 'i' }, 4672 { { STATE_DBREAKA0 }, 'o' }, 4673 { { STATE_XTSYNC }, 'o' } 4674}; 4675 4676static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { 4677 { { 6 /* art */ }, 'm' } 4678}; 4679 4680static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { 4681 { { STATE_PSEXCM }, 'i' }, 4682 { { STATE_PSRING }, 'i' }, 4683 { { STATE_DBREAKA0 }, 'm' }, 4684 { { STATE_XTSYNC }, 'o' } 4685}; 4686 4687static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { 4688 { { 6 /* art */ }, 'o' } 4689}; 4690 4691static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { 4692 { { STATE_PSEXCM }, 'i' }, 4693 { { STATE_PSRING }, 'i' }, 4694 { { STATE_DBREAKC0 }, 'i' } 4695}; 4696 4697static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { 4698 { { 6 /* art */ }, 'i' } 4699}; 4700 4701static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { 4702 { { STATE_PSEXCM }, 'i' }, 4703 { { STATE_PSRING }, 'i' }, 4704 { { STATE_DBREAKC0 }, 'o' }, 4705 { { STATE_XTSYNC }, 'o' } 4706}; 4707 4708static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { 4709 { { 6 /* art */ }, 'm' } 4710}; 4711 4712static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { 4713 { { STATE_PSEXCM }, 'i' }, 4714 { { STATE_PSRING }, 'i' }, 4715 { { STATE_DBREAKC0 }, 'm' }, 4716 { { STATE_XTSYNC }, 'o' } 4717}; 4718 4719static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { 4720 { { 6 /* art */ }, 'o' } 4721}; 4722 4723static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { 4724 { { STATE_PSEXCM }, 'i' }, 4725 { { STATE_PSRING }, 'i' }, 4726 { { STATE_DBREAKA1 }, 'i' } 4727}; 4728 4729static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { 4730 { { 6 /* art */ }, 'i' } 4731}; 4732 4733static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { 4734 { { STATE_PSEXCM }, 'i' }, 4735 { { STATE_PSRING }, 'i' }, 4736 { { STATE_DBREAKA1 }, 'o' }, 4737 { { STATE_XTSYNC }, 'o' } 4738}; 4739 4740static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { 4741 { { 6 /* art */ }, 'm' } 4742}; 4743 4744static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { 4745 { { STATE_PSEXCM }, 'i' }, 4746 { { STATE_PSRING }, 'i' }, 4747 { { STATE_DBREAKA1 }, 'm' }, 4748 { { STATE_XTSYNC }, 'o' } 4749}; 4750 4751static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { 4752 { { 6 /* art */ }, 'o' } 4753}; 4754 4755static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { 4756 { { STATE_PSEXCM }, 'i' }, 4757 { { STATE_PSRING }, 'i' }, 4758 { { STATE_DBREAKC1 }, 'i' } 4759}; 4760 4761static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { 4762 { { 6 /* art */ }, 'i' } 4763}; 4764 4765static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { 4766 { { STATE_PSEXCM }, 'i' }, 4767 { { STATE_PSRING }, 'i' }, 4768 { { STATE_DBREAKC1 }, 'o' }, 4769 { { STATE_XTSYNC }, 'o' } 4770}; 4771 4772static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { 4773 { { 6 /* art */ }, 'm' } 4774}; 4775 4776static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { 4777 { { STATE_PSEXCM }, 'i' }, 4778 { { STATE_PSRING }, 'i' }, 4779 { { STATE_DBREAKC1 }, 'm' }, 4780 { { STATE_XTSYNC }, 'o' } 4781}; 4782 4783static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { 4784 { { 6 /* art */ }, 'o' } 4785}; 4786 4787static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { 4788 { { STATE_PSEXCM }, 'i' }, 4789 { { STATE_PSRING }, 'i' }, 4790 { { STATE_IBREAKA0 }, 'i' } 4791}; 4792 4793static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { 4794 { { 6 /* art */ }, 'i' } 4795}; 4796 4797static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { 4798 { { STATE_PSEXCM }, 'i' }, 4799 { { STATE_PSRING }, 'i' }, 4800 { { STATE_IBREAKA0 }, 'o' } 4801}; 4802 4803static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { 4804 { { 6 /* art */ }, 'm' } 4805}; 4806 4807static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { 4808 { { STATE_PSEXCM }, 'i' }, 4809 { { STATE_PSRING }, 'i' }, 4810 { { STATE_IBREAKA0 }, 'm' } 4811}; 4812 4813static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { 4814 { { 6 /* art */ }, 'o' } 4815}; 4816 4817static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { 4818 { { STATE_PSEXCM }, 'i' }, 4819 { { STATE_PSRING }, 'i' }, 4820 { { STATE_IBREAKA1 }, 'i' } 4821}; 4822 4823static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { 4824 { { 6 /* art */ }, 'i' } 4825}; 4826 4827static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { 4828 { { STATE_PSEXCM }, 'i' }, 4829 { { STATE_PSRING }, 'i' }, 4830 { { STATE_IBREAKA1 }, 'o' } 4831}; 4832 4833static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { 4834 { { 6 /* art */ }, 'm' } 4835}; 4836 4837static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { 4838 { { STATE_PSEXCM }, 'i' }, 4839 { { STATE_PSRING }, 'i' }, 4840 { { STATE_IBREAKA1 }, 'm' } 4841}; 4842 4843static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { 4844 { { 6 /* art */ }, 'o' } 4845}; 4846 4847static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { 4848 { { STATE_PSEXCM }, 'i' }, 4849 { { STATE_PSRING }, 'i' }, 4850 { { STATE_IBREAKENABLE }, 'i' } 4851}; 4852 4853static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { 4854 { { 6 /* art */ }, 'i' } 4855}; 4856 4857static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { 4858 { { STATE_PSEXCM }, 'i' }, 4859 { { STATE_PSRING }, 'i' }, 4860 { { STATE_IBREAKENABLE }, 'o' } 4861}; 4862 4863static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { 4864 { { 6 /* art */ }, 'm' } 4865}; 4866 4867static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { 4868 { { STATE_PSEXCM }, 'i' }, 4869 { { STATE_PSRING }, 'i' }, 4870 { { STATE_IBREAKENABLE }, 'm' } 4871}; 4872 4873static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { 4874 { { 6 /* art */ }, 'o' } 4875}; 4876 4877static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { 4878 { { STATE_PSEXCM }, 'i' }, 4879 { { STATE_PSRING }, 'i' }, 4880 { { STATE_DEBUGCAUSE }, 'i' }, 4881 { { STATE_DBNUM }, 'i' } 4882}; 4883 4884static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { 4885 { { 6 /* art */ }, 'i' } 4886}; 4887 4888static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { 4889 { { STATE_PSEXCM }, 'i' }, 4890 { { STATE_PSRING }, 'i' }, 4891 { { STATE_DEBUGCAUSE }, 'o' }, 4892 { { STATE_DBNUM }, 'o' } 4893}; 4894 4895static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { 4896 { { 6 /* art */ }, 'm' } 4897}; 4898 4899static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { 4900 { { STATE_PSEXCM }, 'i' }, 4901 { { STATE_PSRING }, 'i' }, 4902 { { STATE_DEBUGCAUSE }, 'm' }, 4903 { { STATE_DBNUM }, 'm' } 4904}; 4905 4906static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { 4907 { { 6 /* art */ }, 'o' } 4908}; 4909 4910static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { 4911 { { STATE_PSEXCM }, 'i' }, 4912 { { STATE_PSRING }, 'i' }, 4913 { { STATE_ICOUNT }, 'i' } 4914}; 4915 4916static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { 4917 { { 6 /* art */ }, 'i' } 4918}; 4919 4920static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { 4921 { { STATE_PSEXCM }, 'i' }, 4922 { { STATE_PSRING }, 'i' }, 4923 { { STATE_XTSYNC }, 'o' }, 4924 { { STATE_ICOUNT }, 'o' } 4925}; 4926 4927static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { 4928 { { 6 /* art */ }, 'm' } 4929}; 4930 4931static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { 4932 { { STATE_PSEXCM }, 'i' }, 4933 { { STATE_PSRING }, 'i' }, 4934 { { STATE_XTSYNC }, 'o' }, 4935 { { STATE_ICOUNT }, 'm' } 4936}; 4937 4938static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { 4939 { { 6 /* art */ }, 'o' } 4940}; 4941 4942static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { 4943 { { STATE_PSEXCM }, 'i' }, 4944 { { STATE_PSRING }, 'i' }, 4945 { { STATE_ICOUNTLEVEL }, 'i' } 4946}; 4947 4948static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { 4949 { { 6 /* art */ }, 'i' } 4950}; 4951 4952static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { 4953 { { STATE_PSEXCM }, 'i' }, 4954 { { STATE_PSRING }, 'i' }, 4955 { { STATE_ICOUNTLEVEL }, 'o' } 4956}; 4957 4958static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { 4959 { { 6 /* art */ }, 'm' } 4960}; 4961 4962static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { 4963 { { STATE_PSEXCM }, 'i' }, 4964 { { STATE_PSRING }, 'i' }, 4965 { { STATE_ICOUNTLEVEL }, 'm' } 4966}; 4967 4968static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { 4969 { { 6 /* art */ }, 'o' } 4970}; 4971 4972static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { 4973 { { STATE_PSEXCM }, 'i' }, 4974 { { STATE_PSRING }, 'i' }, 4975 { { STATE_DDR }, 'i' } 4976}; 4977 4978static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { 4979 { { 6 /* art */ }, 'i' } 4980}; 4981 4982static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { 4983 { { STATE_PSEXCM }, 'i' }, 4984 { { STATE_PSRING }, 'i' }, 4985 { { STATE_XTSYNC }, 'o' }, 4986 { { STATE_DDR }, 'o' } 4987}; 4988 4989static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { 4990 { { 6 /* art */ }, 'm' } 4991}; 4992 4993static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { 4994 { { STATE_PSEXCM }, 'i' }, 4995 { { STATE_PSRING }, 'i' }, 4996 { { STATE_XTSYNC }, 'o' }, 4997 { { STATE_DDR }, 'm' } 4998}; 4999 5000static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { 5001 { { 41 /* imms */ }, 'i' } 5002}; 5003 5004static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { 5005 { { STATE_InOCDMode }, 'm' }, 5006 { { STATE_EPC6 }, 'i' }, 5007 { { STATE_PSWOE }, 'o' }, 5008 { { STATE_PSCALLINC }, 'o' }, 5009 { { STATE_PSOWB }, 'o' }, 5010 { { STATE_PSRING }, 'o' }, 5011 { { STATE_PSUM }, 'o' }, 5012 { { STATE_PSEXCM }, 'o' }, 5013 { { STATE_PSINTLEVEL }, 'o' }, 5014 { { STATE_EPS6 }, 'i' } 5015}; 5016 5017static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { 5018 { { STATE_InOCDMode }, 'm' } 5019}; 5020 5021static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { 5022 { { 6 /* art */ }, 'i' } 5023}; 5024 5025static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { 5026 { { STATE_PSEXCM }, 'i' }, 5027 { { STATE_PSRING }, 'i' }, 5028 { { STATE_XTSYNC }, 'o' } 5029}; 5030 5031static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { 5032 { { 6 /* art */ }, 'o' } 5033}; 5034 5035static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { 5036 { { STATE_PSEXCM }, 'i' }, 5037 { { STATE_PSRING }, 'i' }, 5038 { { STATE_CCOUNT }, 'i' } 5039}; 5040 5041static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { 5042 { { 6 /* art */ }, 'i' } 5043}; 5044 5045static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { 5046 { { STATE_PSEXCM }, 'i' }, 5047 { { STATE_PSRING }, 'i' }, 5048 { { STATE_XTSYNC }, 'o' }, 5049 { { STATE_CCOUNT }, 'o' } 5050}; 5051 5052static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { 5053 { { 6 /* art */ }, 'm' } 5054}; 5055 5056static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { 5057 { { STATE_PSEXCM }, 'i' }, 5058 { { STATE_PSRING }, 'i' }, 5059 { { STATE_XTSYNC }, 'o' }, 5060 { { STATE_CCOUNT }, 'm' } 5061}; 5062 5063static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { 5064 { { 6 /* art */ }, 'o' } 5065}; 5066 5067static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { 5068 { { STATE_PSEXCM }, 'i' }, 5069 { { STATE_PSRING }, 'i' }, 5070 { { STATE_CCOMPARE0 }, 'i' } 5071}; 5072 5073static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { 5074 { { 6 /* art */ }, 'i' } 5075}; 5076 5077static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { 5078 { { STATE_PSEXCM }, 'i' }, 5079 { { STATE_PSRING }, 'i' }, 5080 { { STATE_CCOMPARE0 }, 'o' }, 5081 { { STATE_INTERRUPT }, 'm' } 5082}; 5083 5084static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { 5085 { { 6 /* art */ }, 'm' } 5086}; 5087 5088static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { 5089 { { STATE_PSEXCM }, 'i' }, 5090 { { STATE_PSRING }, 'i' }, 5091 { { STATE_CCOMPARE0 }, 'm' }, 5092 { { STATE_INTERRUPT }, 'm' } 5093}; 5094 5095static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { 5096 { { 6 /* art */ }, 'o' } 5097}; 5098 5099static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { 5100 { { STATE_PSEXCM }, 'i' }, 5101 { { STATE_PSRING }, 'i' }, 5102 { { STATE_CCOMPARE1 }, 'i' } 5103}; 5104 5105static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { 5106 { { 6 /* art */ }, 'i' } 5107}; 5108 5109static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { 5110 { { STATE_PSEXCM }, 'i' }, 5111 { { STATE_PSRING }, 'i' }, 5112 { { STATE_CCOMPARE1 }, 'o' }, 5113 { { STATE_INTERRUPT }, 'm' } 5114}; 5115 5116static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { 5117 { { 6 /* art */ }, 'm' } 5118}; 5119 5120static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { 5121 { { STATE_PSEXCM }, 'i' }, 5122 { { STATE_PSRING }, 'i' }, 5123 { { STATE_CCOMPARE1 }, 'm' }, 5124 { { STATE_INTERRUPT }, 'm' } 5125}; 5126 5127static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { 5128 { { 6 /* art */ }, 'o' } 5129}; 5130 5131static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { 5132 { { STATE_PSEXCM }, 'i' }, 5133 { { STATE_PSRING }, 'i' }, 5134 { { STATE_CCOMPARE2 }, 'i' } 5135}; 5136 5137static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { 5138 { { 6 /* art */ }, 'i' } 5139}; 5140 5141static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { 5142 { { STATE_PSEXCM }, 'i' }, 5143 { { STATE_PSRING }, 'i' }, 5144 { { STATE_CCOMPARE2 }, 'o' }, 5145 { { STATE_INTERRUPT }, 'm' } 5146}; 5147 5148static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { 5149 { { 6 /* art */ }, 'm' } 5150}; 5151 5152static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { 5153 { { STATE_PSEXCM }, 'i' }, 5154 { { STATE_PSRING }, 'i' }, 5155 { { STATE_CCOMPARE2 }, 'm' }, 5156 { { STATE_INTERRUPT }, 'm' } 5157}; 5158 5159static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { 5160 { { 4 /* ars */ }, 'i' }, 5161 { { 21 /* uimm8x4 */ }, 'i' } 5162}; 5163 5164static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { 5165 { { 4 /* ars */ }, 'i' }, 5166 { { 22 /* uimm4x16 */ }, 'i' } 5167}; 5168 5169static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = { 5170 { { STATE_PSEXCM }, 'i' }, 5171 { { STATE_PSRING }, 'i' } 5172}; 5173 5174static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { 5175 { { 4 /* ars */ }, 'i' }, 5176 { { 21 /* uimm8x4 */ }, 'i' } 5177}; 5178 5179static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { 5180 { { STATE_PSEXCM }, 'i' }, 5181 { { STATE_PSRING }, 'i' } 5182}; 5183 5184static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { 5185 { { 6 /* art */ }, 'o' }, 5186 { { 4 /* ars */ }, 'i' } 5187}; 5188 5189static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { 5190 { { STATE_PSEXCM }, 'i' }, 5191 { { STATE_PSRING }, 'i' } 5192}; 5193 5194static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { 5195 { { 6 /* art */ }, 'i' }, 5196 { { 4 /* ars */ }, 'i' } 5197}; 5198 5199static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { 5200 { { STATE_PSEXCM }, 'i' }, 5201 { { STATE_PSRING }, 'i' } 5202}; 5203 5204static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { 5205 { { 4 /* ars */ }, 'i' }, 5206 { { 21 /* uimm8x4 */ }, 'i' } 5207}; 5208 5209static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { 5210 { { 4 /* ars */ }, 'i' }, 5211 { { 22 /* uimm4x16 */ }, 'i' } 5212}; 5213 5214static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { 5215 { { STATE_PSEXCM }, 'i' }, 5216 { { STATE_PSRING }, 'i' } 5217}; 5218 5219static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { 5220 { { 4 /* ars */ }, 'i' }, 5221 { { 21 /* uimm8x4 */ }, 'i' } 5222}; 5223 5224static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { 5225 { { STATE_PSEXCM }, 'i' }, 5226 { { STATE_PSRING }, 'i' } 5227}; 5228 5229static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { 5230 { { 4 /* ars */ }, 'i' }, 5231 { { 21 /* uimm8x4 */ }, 'i' } 5232}; 5233 5234static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { 5235 { { 4 /* ars */ }, 'i' }, 5236 { { 22 /* uimm4x16 */ }, 'i' } 5237}; 5238 5239static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = { 5240 { { STATE_PSEXCM }, 'i' }, 5241 { { STATE_PSRING }, 'i' } 5242}; 5243 5244static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { 5245 { { 6 /* art */ }, 'i' }, 5246 { { 4 /* ars */ }, 'i' } 5247}; 5248 5249static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { 5250 { { STATE_PSEXCM }, 'i' }, 5251 { { STATE_PSRING }, 'i' } 5252}; 5253 5254static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { 5255 { { 6 /* art */ }, 'o' }, 5256 { { 4 /* ars */ }, 'i' } 5257}; 5258 5259static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { 5260 { { STATE_PSEXCM }, 'i' }, 5261 { { STATE_PSRING }, 'i' } 5262}; 5263 5264static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = { 5265 { { 6 /* art */ }, 'i' } 5266}; 5267 5268static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = { 5269 { { STATE_PSEXCM }, 'i' }, 5270 { { STATE_PSRING }, 'i' }, 5271 { { STATE_PTBASE }, 'o' }, 5272 { { STATE_XTSYNC }, 'o' } 5273}; 5274 5275static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = { 5276 { { 6 /* art */ }, 'o' } 5277}; 5278 5279static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = { 5280 { { STATE_PSEXCM }, 'i' }, 5281 { { STATE_PSRING }, 'i' }, 5282 { { STATE_PTBASE }, 'i' }, 5283 { { STATE_EXCVADDR }, 'i' } 5284}; 5285 5286static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = { 5287 { { 6 /* art */ }, 'm' } 5288}; 5289 5290static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = { 5291 { { STATE_PSEXCM }, 'i' }, 5292 { { STATE_PSRING }, 'i' }, 5293 { { STATE_PTBASE }, 'm' }, 5294 { { STATE_EXCVADDR }, 'i' }, 5295 { { STATE_XTSYNC }, 'o' } 5296}; 5297 5298static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = { 5299 { { 6 /* art */ }, 'o' } 5300}; 5301 5302static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = { 5303 { { STATE_PSEXCM }, 'i' }, 5304 { { STATE_PSRING }, 'i' }, 5305 { { STATE_ASID3 }, 'i' }, 5306 { { STATE_ASID2 }, 'i' }, 5307 { { STATE_ASID1 }, 'i' } 5308}; 5309 5310static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = { 5311 { { 6 /* art */ }, 'i' } 5312}; 5313 5314static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = { 5315 { { STATE_XTSYNC }, 'o' }, 5316 { { STATE_PSEXCM }, 'i' }, 5317 { { STATE_PSRING }, 'i' }, 5318 { { STATE_ASID3 }, 'o' }, 5319 { { STATE_ASID2 }, 'o' }, 5320 { { STATE_ASID1 }, 'o' } 5321}; 5322 5323static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = { 5324 { { 6 /* art */ }, 'm' } 5325}; 5326 5327static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = { 5328 { { STATE_XTSYNC }, 'o' }, 5329 { { STATE_PSEXCM }, 'i' }, 5330 { { STATE_PSRING }, 'i' }, 5331 { { STATE_ASID3 }, 'm' }, 5332 { { STATE_ASID2 }, 'm' }, 5333 { { STATE_ASID1 }, 'm' } 5334}; 5335 5336static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = { 5337 { { 6 /* art */ }, 'o' } 5338}; 5339 5340static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = { 5341 { { STATE_PSEXCM }, 'i' }, 5342 { { STATE_PSRING }, 'i' }, 5343 { { STATE_INSTPGSZID4 }, 'i' } 5344}; 5345 5346static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = { 5347 { { 6 /* art */ }, 'i' } 5348}; 5349 5350static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = { 5351 { { STATE_XTSYNC }, 'o' }, 5352 { { STATE_PSEXCM }, 'i' }, 5353 { { STATE_PSRING }, 'i' }, 5354 { { STATE_INSTPGSZID4 }, 'o' } 5355}; 5356 5357static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = { 5358 { { 6 /* art */ }, 'm' } 5359}; 5360 5361static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = { 5362 { { STATE_XTSYNC }, 'o' }, 5363 { { STATE_PSEXCM }, 'i' }, 5364 { { STATE_PSRING }, 'i' }, 5365 { { STATE_INSTPGSZID4 }, 'm' } 5366}; 5367 5368static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = { 5369 { { 6 /* art */ }, 'o' } 5370}; 5371 5372static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = { 5373 { { STATE_PSEXCM }, 'i' }, 5374 { { STATE_PSRING }, 'i' }, 5375 { { STATE_DATAPGSZID4 }, 'i' } 5376}; 5377 5378static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = { 5379 { { 6 /* art */ }, 'i' } 5380}; 5381 5382static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = { 5383 { { STATE_XTSYNC }, 'o' }, 5384 { { STATE_PSEXCM }, 'i' }, 5385 { { STATE_PSRING }, 'i' }, 5386 { { STATE_DATAPGSZID4 }, 'o' } 5387}; 5388 5389static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = { 5390 { { 6 /* art */ }, 'm' } 5391}; 5392 5393static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = { 5394 { { STATE_XTSYNC }, 'o' }, 5395 { { STATE_PSEXCM }, 'i' }, 5396 { { STATE_PSRING }, 'i' }, 5397 { { STATE_DATAPGSZID4 }, 'm' } 5398}; 5399 5400static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { 5401 { { 4 /* ars */ }, 'i' } 5402}; 5403 5404static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { 5405 { { STATE_PSEXCM }, 'i' }, 5406 { { STATE_PSRING }, 'i' }, 5407 { { STATE_XTSYNC }, 'o' } 5408}; 5409 5410static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { 5411 { { 6 /* art */ }, 'o' }, 5412 { { 4 /* ars */ }, 'i' } 5413}; 5414 5415static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = { 5416 { { STATE_PSEXCM }, 'i' }, 5417 { { STATE_PSRING }, 'i' } 5418}; 5419 5420static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { 5421 { { 6 /* art */ }, 'i' }, 5422 { { 4 /* ars */ }, 'i' } 5423}; 5424 5425static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { 5426 { { STATE_PSEXCM }, 'i' }, 5427 { { STATE_PSRING }, 'i' }, 5428 { { STATE_XTSYNC }, 'o' } 5429}; 5430 5431static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { 5432 { { 4 /* ars */ }, 'i' } 5433}; 5434 5435static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = { 5436 { { STATE_PSEXCM }, 'i' }, 5437 { { STATE_PSRING }, 'i' } 5438}; 5439 5440static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { 5441 { { 6 /* art */ }, 'o' }, 5442 { { 4 /* ars */ }, 'i' } 5443}; 5444 5445static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = { 5446 { { STATE_PSEXCM }, 'i' }, 5447 { { STATE_PSRING }, 'i' } 5448}; 5449 5450static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { 5451 { { 6 /* art */ }, 'i' }, 5452 { { 4 /* ars */ }, 'i' } 5453}; 5454 5455static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = { 5456 { { STATE_PSEXCM }, 'i' }, 5457 { { STATE_PSRING }, 'i' } 5458}; 5459 5460static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = { 5461 { { STATE_PTBASE }, 'i' }, 5462 { { STATE_EXCVADDR }, 'i' } 5463}; 5464 5465static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = { 5466 { { STATE_EXCVADDR }, 'i' } 5467}; 5468 5469static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = { 5470 { { STATE_EXCVADDR }, 'i' } 5471}; 5472 5473static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { 5474 { { 6 /* art */ }, 'o' } 5475}; 5476 5477static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { 5478 { { STATE_PSEXCM }, 'i' }, 5479 { { STATE_PSRING }, 'i' }, 5480 { { STATE_CPENABLE }, 'i' } 5481}; 5482 5483static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { 5484 { { 6 /* art */ }, 'i' } 5485}; 5486 5487static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { 5488 { { STATE_PSEXCM }, 'i' }, 5489 { { STATE_PSRING }, 'i' }, 5490 { { STATE_CPENABLE }, 'o' } 5491}; 5492 5493static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { 5494 { { 6 /* art */ }, 'm' } 5495}; 5496 5497static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { 5498 { { STATE_PSEXCM }, 'i' }, 5499 { { STATE_PSRING }, 'i' }, 5500 { { STATE_CPENABLE }, 'm' } 5501}; 5502 5503static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { 5504 { { 3 /* arr */ }, 'o' }, 5505 { { 4 /* ars */ }, 'i' }, 5506 { { 42 /* tp7 */ }, 'i' } 5507}; 5508 5509static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { 5510 { { 3 /* arr */ }, 'o' }, 5511 { { 4 /* ars */ }, 'i' }, 5512 { { 6 /* art */ }, 'i' } 5513}; 5514 5515static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { 5516 { { 6 /* art */ }, 'o' }, 5517 { { 4 /* ars */ }, 'i' } 5518}; 5519 5520static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { 5521 { { 3 /* arr */ }, 'o' }, 5522 { { 4 /* ars */ }, 'i' }, 5523 { { 42 /* tp7 */ }, 'i' } 5524}; 5525 5526static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { 5527 { { 6 /* art */ }, 'o' }, 5528 { { 4 /* ars */ }, 'i' }, 5529 { { 21 /* uimm8x4 */ }, 'i' } 5530}; 5531 5532static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { 5533 { { 6 /* art */ }, 'i' }, 5534 { { 4 /* ars */ }, 'i' }, 5535 { { 21 /* uimm8x4 */ }, 'i' } 5536}; 5537 5538static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { 5539 { { 6 /* art */ }, 'm' }, 5540 { { 4 /* ars */ }, 'i' }, 5541 { { 21 /* uimm8x4 */ }, 'i' } 5542}; 5543 5544static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { 5545 { { STATE_SCOMPARE1 }, 'i' }, 5546 { { STATE_SCOMPARE1 }, 'i' } 5547}; 5548 5549static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { 5550 { { 6 /* art */ }, 'o' } 5551}; 5552 5553static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { 5554 { { STATE_SCOMPARE1 }, 'i' } 5555}; 5556 5557static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { 5558 { { 6 /* art */ }, 'i' } 5559}; 5560 5561static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { 5562 { { STATE_SCOMPARE1 }, 'o' } 5563}; 5564 5565static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { 5566 { { 6 /* art */ }, 'm' } 5567}; 5568 5569static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { 5570 { { STATE_SCOMPARE1 }, 'm' } 5571}; 5572 5573static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { 5574 { { 3 /* arr */ }, 'o' }, 5575 { { 4 /* ars */ }, 'i' }, 5576 { { 6 /* art */ }, 'i' } 5577}; 5578 5579static xtensa_arg_internal Iclass_xt_mul32_args[] = { 5580 { { 3 /* arr */ }, 'o' }, 5581 { { 4 /* ars */ }, 'i' }, 5582 { { 6 /* art */ }, 'i' } 5583}; 5584 5585static xtensa_arg_internal Iclass_rur_expstate_args[] = { 5586 { { 3 /* arr */ }, 'o' } 5587}; 5588 5589static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = { 5590 { { STATE_EXPSTATE }, 'i' }, 5591 { { STATE_CPENABLE }, 'i' } 5592}; 5593 5594static xtensa_arg_internal Iclass_wur_expstate_args[] = { 5595 { { 6 /* art */ }, 'i' } 5596}; 5597 5598static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = { 5599 { { STATE_EXPSTATE }, 'o' }, 5600 { { STATE_CPENABLE }, 'i' } 5601}; 5602 5603static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = { 5604 { { 6 /* art */ }, 'o' } 5605}; 5606 5607static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_stateArgs[] = { 5608 { { STATE_CPENABLE }, 'i' } 5609}; 5610 5611static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = { 5612 0 /* IMPWIRE */ 5613}; 5614 5615static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = { 5616 { { 91 /* bitindex */ }, 'i' } 5617}; 5618 5619static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = { 5620 { { STATE_EXPSTATE }, 'm' }, 5621 { { STATE_CPENABLE }, 'i' } 5622}; 5623 5624static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = { 5625 { { 91 /* bitindex */ }, 'i' } 5626}; 5627 5628static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = { 5629 { { STATE_EXPSTATE }, 'm' }, 5630 { { STATE_CPENABLE }, 'i' } 5631}; 5632 5633static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = { 5634 { { 6 /* art */ }, 'i' }, 5635 { { 4 /* ars */ }, 'i' } 5636}; 5637 5638static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = { 5639 { { STATE_EXPSTATE }, 'm' }, 5640 { { STATE_CPENABLE }, 'i' } 5641}; 5642 5643static xtensa_iclass_internal iclasses[] = { 5644 { 0, 0 /* xt_iclass_excw */, 5645 0, 0, 0, 0 }, 5646 { 0, 0 /* xt_iclass_rfe */, 5647 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, 5648 { 0, 0 /* xt_iclass_rfde */, 5649 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, 5650 { 0, 0 /* xt_iclass_syscall */, 5651 0, 0, 0, 0 }, 5652 { 0, 0 /* xt_iclass_simcall */, 5653 0, 0, 0, 0 }, 5654 { 2, Iclass_xt_iclass_call12_args, 5655 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, 5656 { 2, Iclass_xt_iclass_call8_args, 5657 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, 5658 { 2, Iclass_xt_iclass_call4_args, 5659 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, 5660 { 2, Iclass_xt_iclass_callx12_args, 5661 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, 5662 { 2, Iclass_xt_iclass_callx8_args, 5663 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, 5664 { 2, Iclass_xt_iclass_callx4_args, 5665 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, 5666 { 3, Iclass_xt_iclass_entry_args, 5667 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, 5668 { 2, Iclass_xt_iclass_movsp_args, 5669 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, 5670 { 1, Iclass_xt_iclass_rotw_args, 5671 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, 5672 { 1, Iclass_xt_iclass_retw_args, 5673 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, 5674 { 0, 0 /* xt_iclass_rfwou */, 5675 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, 5676 { 3, Iclass_xt_iclass_l32e_args, 5677 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, 5678 { 3, Iclass_xt_iclass_s32e_args, 5679 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, 5680 { 1, Iclass_xt_iclass_rsr_windowbase_args, 5681 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, 5682 { 1, Iclass_xt_iclass_wsr_windowbase_args, 5683 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, 5684 { 1, Iclass_xt_iclass_xsr_windowbase_args, 5685 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, 5686 { 1, Iclass_xt_iclass_rsr_windowstart_args, 5687 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, 5688 { 1, Iclass_xt_iclass_wsr_windowstart_args, 5689 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, 5690 { 1, Iclass_xt_iclass_xsr_windowstart_args, 5691 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, 5692 { 3, Iclass_xt_iclass_add_n_args, 5693 0, 0, 0, 0 }, 5694 { 3, Iclass_xt_iclass_addi_n_args, 5695 0, 0, 0, 0 }, 5696 { 2, Iclass_xt_iclass_bz6_args, 5697 0, 0, 0, 0 }, 5698 { 0, 0 /* xt_iclass_ill_n */, 5699 0, 0, 0, 0 }, 5700 { 3, Iclass_xt_iclass_loadi4_args, 5701 0, 0, 0, 0 }, 5702 { 2, Iclass_xt_iclass_mov_n_args, 5703 0, 0, 0, 0 }, 5704 { 2, Iclass_xt_iclass_movi_n_args, 5705 0, 0, 0, 0 }, 5706 { 0, 0 /* xt_iclass_nopn */, 5707 0, 0, 0, 0 }, 5708 { 1, Iclass_xt_iclass_retn_args, 5709 0, 0, 0, 0 }, 5710 { 3, Iclass_xt_iclass_storei4_args, 5711 0, 0, 0, 0 }, 5712 { 1, Iclass_rur_threadptr_args, 5713 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, 5714 { 1, Iclass_wur_threadptr_args, 5715 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, 5716 { 3, Iclass_xt_iclass_addi_args, 5717 0, 0, 0, 0 }, 5718 { 3, Iclass_xt_iclass_addmi_args, 5719 0, 0, 0, 0 }, 5720 { 3, Iclass_xt_iclass_addsub_args, 5721 0, 0, 0, 0 }, 5722 { 3, Iclass_xt_iclass_bit_args, 5723 0, 0, 0, 0 }, 5724 { 3, Iclass_xt_iclass_bsi8_args, 5725 0, 0, 0, 0 }, 5726 { 3, Iclass_xt_iclass_bsi8b_args, 5727 0, 0, 0, 0 }, 5728 { 3, Iclass_xt_iclass_bsi8u_args, 5729 0, 0, 0, 0 }, 5730 { 3, Iclass_xt_iclass_bst8_args, 5731 0, 0, 0, 0 }, 5732 { 2, Iclass_xt_iclass_bsz12_args, 5733 0, 0, 0, 0 }, 5734 { 2, Iclass_xt_iclass_call0_args, 5735 0, 0, 0, 0 }, 5736 { 2, Iclass_xt_iclass_callx0_args, 5737 0, 0, 0, 0 }, 5738 { 4, Iclass_xt_iclass_exti_args, 5739 0, 0, 0, 0 }, 5740 { 0, 0 /* xt_iclass_ill */, 5741 0, 0, 0, 0 }, 5742 { 1, Iclass_xt_iclass_jump_args, 5743 0, 0, 0, 0 }, 5744 { 1, Iclass_xt_iclass_jumpx_args, 5745 0, 0, 0, 0 }, 5746 { 3, Iclass_xt_iclass_l16ui_args, 5747 0, 0, 0, 0 }, 5748 { 3, Iclass_xt_iclass_l16si_args, 5749 0, 0, 0, 0 }, 5750 { 3, Iclass_xt_iclass_l32i_args, 5751 0, 0, 0, 0 }, 5752 { 2, Iclass_xt_iclass_l32r_args, 5753 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 }, 5754 { 3, Iclass_xt_iclass_l8i_args, 5755 0, 0, 0, 0 }, 5756 { 2, Iclass_xt_iclass_loop_args, 5757 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, 5758 { 2, Iclass_xt_iclass_loopz_args, 5759 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, 5760 { 2, Iclass_xt_iclass_movi_args, 5761 0, 0, 0, 0 }, 5762 { 3, Iclass_xt_iclass_movz_args, 5763 0, 0, 0, 0 }, 5764 { 2, Iclass_xt_iclass_neg_args, 5765 0, 0, 0, 0 }, 5766 { 0, 0 /* xt_iclass_nop */, 5767 0, 0, 0, 0 }, 5768 { 1, Iclass_xt_iclass_return_args, 5769 0, 0, 0, 0 }, 5770 { 3, Iclass_xt_iclass_s16i_args, 5771 0, 0, 0, 0 }, 5772 { 3, Iclass_xt_iclass_s32i_args, 5773 0, 0, 0, 0 }, 5774 { 3, Iclass_xt_iclass_s8i_args, 5775 0, 0, 0, 0 }, 5776 { 1, Iclass_xt_iclass_sar_args, 5777 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, 5778 { 1, Iclass_xt_iclass_sari_args, 5779 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, 5780 { 2, Iclass_xt_iclass_shifts_args, 5781 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, 5782 { 3, Iclass_xt_iclass_shiftst_args, 5783 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, 5784 { 2, Iclass_xt_iclass_shiftt_args, 5785 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, 5786 { 3, Iclass_xt_iclass_slli_args, 5787 0, 0, 0, 0 }, 5788 { 3, Iclass_xt_iclass_srai_args, 5789 0, 0, 0, 0 }, 5790 { 3, Iclass_xt_iclass_srli_args, 5791 0, 0, 0, 0 }, 5792 { 0, 0 /* xt_iclass_memw */, 5793 0, 0, 0, 0 }, 5794 { 0, 0 /* xt_iclass_extw */, 5795 0, 0, 0, 0 }, 5796 { 0, 0 /* xt_iclass_isync */, 5797 0, 0, 0, 0 }, 5798 { 0, 0 /* xt_iclass_sync */, 5799 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, 5800 { 2, Iclass_xt_iclass_rsil_args, 5801 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, 5802 { 1, Iclass_xt_iclass_rsr_lend_args, 5803 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, 5804 { 1, Iclass_xt_iclass_wsr_lend_args, 5805 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, 5806 { 1, Iclass_xt_iclass_xsr_lend_args, 5807 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, 5808 { 1, Iclass_xt_iclass_rsr_lcount_args, 5809 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, 5810 { 1, Iclass_xt_iclass_wsr_lcount_args, 5811 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, 5812 { 1, Iclass_xt_iclass_xsr_lcount_args, 5813 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, 5814 { 1, Iclass_xt_iclass_rsr_lbeg_args, 5815 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, 5816 { 1, Iclass_xt_iclass_wsr_lbeg_args, 5817 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, 5818 { 1, Iclass_xt_iclass_xsr_lbeg_args, 5819 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, 5820 { 1, Iclass_xt_iclass_rsr_sar_args, 5821 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, 5822 { 1, Iclass_xt_iclass_wsr_sar_args, 5823 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, 5824 { 1, Iclass_xt_iclass_xsr_sar_args, 5825 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, 5826 { 1, Iclass_xt_iclass_rsr_litbase_args, 5827 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 }, 5828 { 1, Iclass_xt_iclass_wsr_litbase_args, 5829 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 }, 5830 { 1, Iclass_xt_iclass_xsr_litbase_args, 5831 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 }, 5832 { 1, Iclass_xt_iclass_rsr_176_args, 5833 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 }, 5834 { 1, Iclass_xt_iclass_rsr_208_args, 5835 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 }, 5836 { 1, Iclass_xt_iclass_rsr_ps_args, 5837 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, 5838 { 1, Iclass_xt_iclass_wsr_ps_args, 5839 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, 5840 { 1, Iclass_xt_iclass_xsr_ps_args, 5841 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, 5842 { 1, Iclass_xt_iclass_rsr_epc1_args, 5843 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, 5844 { 1, Iclass_xt_iclass_wsr_epc1_args, 5845 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, 5846 { 1, Iclass_xt_iclass_xsr_epc1_args, 5847 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, 5848 { 1, Iclass_xt_iclass_rsr_excsave1_args, 5849 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, 5850 { 1, Iclass_xt_iclass_wsr_excsave1_args, 5851 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, 5852 { 1, Iclass_xt_iclass_xsr_excsave1_args, 5853 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, 5854 { 1, Iclass_xt_iclass_rsr_epc2_args, 5855 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, 5856 { 1, Iclass_xt_iclass_wsr_epc2_args, 5857 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, 5858 { 1, Iclass_xt_iclass_xsr_epc2_args, 5859 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, 5860 { 1, Iclass_xt_iclass_rsr_excsave2_args, 5861 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, 5862 { 1, Iclass_xt_iclass_wsr_excsave2_args, 5863 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, 5864 { 1, Iclass_xt_iclass_xsr_excsave2_args, 5865 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, 5866 { 1, Iclass_xt_iclass_rsr_epc3_args, 5867 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, 5868 { 1, Iclass_xt_iclass_wsr_epc3_args, 5869 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, 5870 { 1, Iclass_xt_iclass_xsr_epc3_args, 5871 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, 5872 { 1, Iclass_xt_iclass_rsr_excsave3_args, 5873 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, 5874 { 1, Iclass_xt_iclass_wsr_excsave3_args, 5875 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, 5876 { 1, Iclass_xt_iclass_xsr_excsave3_args, 5877 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, 5878 { 1, Iclass_xt_iclass_rsr_epc4_args, 5879 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, 5880 { 1, Iclass_xt_iclass_wsr_epc4_args, 5881 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, 5882 { 1, Iclass_xt_iclass_xsr_epc4_args, 5883 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, 5884 { 1, Iclass_xt_iclass_rsr_excsave4_args, 5885 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, 5886 { 1, Iclass_xt_iclass_wsr_excsave4_args, 5887 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, 5888 { 1, Iclass_xt_iclass_xsr_excsave4_args, 5889 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, 5890 { 1, Iclass_xt_iclass_rsr_epc5_args, 5891 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, 5892 { 1, Iclass_xt_iclass_wsr_epc5_args, 5893 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, 5894 { 1, Iclass_xt_iclass_xsr_epc5_args, 5895 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, 5896 { 1, Iclass_xt_iclass_rsr_excsave5_args, 5897 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, 5898 { 1, Iclass_xt_iclass_wsr_excsave5_args, 5899 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, 5900 { 1, Iclass_xt_iclass_xsr_excsave5_args, 5901 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, 5902 { 1, Iclass_xt_iclass_rsr_epc6_args, 5903 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, 5904 { 1, Iclass_xt_iclass_wsr_epc6_args, 5905 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, 5906 { 1, Iclass_xt_iclass_xsr_epc6_args, 5907 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, 5908 { 1, Iclass_xt_iclass_rsr_excsave6_args, 5909 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, 5910 { 1, Iclass_xt_iclass_wsr_excsave6_args, 5911 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, 5912 { 1, Iclass_xt_iclass_xsr_excsave6_args, 5913 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, 5914 { 1, Iclass_xt_iclass_rsr_epc7_args, 5915 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 }, 5916 { 1, Iclass_xt_iclass_wsr_epc7_args, 5917 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 }, 5918 { 1, Iclass_xt_iclass_xsr_epc7_args, 5919 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 }, 5920 { 1, Iclass_xt_iclass_rsr_excsave7_args, 5921 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 }, 5922 { 1, Iclass_xt_iclass_wsr_excsave7_args, 5923 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 }, 5924 { 1, Iclass_xt_iclass_xsr_excsave7_args, 5925 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 }, 5926 { 1, Iclass_xt_iclass_rsr_eps2_args, 5927 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, 5928 { 1, Iclass_xt_iclass_wsr_eps2_args, 5929 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, 5930 { 1, Iclass_xt_iclass_xsr_eps2_args, 5931 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, 5932 { 1, Iclass_xt_iclass_rsr_eps3_args, 5933 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, 5934 { 1, Iclass_xt_iclass_wsr_eps3_args, 5935 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, 5936 { 1, Iclass_xt_iclass_xsr_eps3_args, 5937 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, 5938 { 1, Iclass_xt_iclass_rsr_eps4_args, 5939 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, 5940 { 1, Iclass_xt_iclass_wsr_eps4_args, 5941 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, 5942 { 1, Iclass_xt_iclass_xsr_eps4_args, 5943 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, 5944 { 1, Iclass_xt_iclass_rsr_eps5_args, 5945 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, 5946 { 1, Iclass_xt_iclass_wsr_eps5_args, 5947 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, 5948 { 1, Iclass_xt_iclass_xsr_eps5_args, 5949 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, 5950 { 1, Iclass_xt_iclass_rsr_eps6_args, 5951 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, 5952 { 1, Iclass_xt_iclass_wsr_eps6_args, 5953 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, 5954 { 1, Iclass_xt_iclass_xsr_eps6_args, 5955 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, 5956 { 1, Iclass_xt_iclass_rsr_eps7_args, 5957 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 }, 5958 { 1, Iclass_xt_iclass_wsr_eps7_args, 5959 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 }, 5960 { 1, Iclass_xt_iclass_xsr_eps7_args, 5961 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 }, 5962 { 1, Iclass_xt_iclass_rsr_excvaddr_args, 5963 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, 5964 { 1, Iclass_xt_iclass_wsr_excvaddr_args, 5965 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, 5966 { 1, Iclass_xt_iclass_xsr_excvaddr_args, 5967 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, 5968 { 1, Iclass_xt_iclass_rsr_depc_args, 5969 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, 5970 { 1, Iclass_xt_iclass_wsr_depc_args, 5971 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, 5972 { 1, Iclass_xt_iclass_xsr_depc_args, 5973 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, 5974 { 1, Iclass_xt_iclass_rsr_exccause_args, 5975 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, 5976 { 1, Iclass_xt_iclass_wsr_exccause_args, 5977 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, 5978 { 1, Iclass_xt_iclass_xsr_exccause_args, 5979 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, 5980 { 1, Iclass_xt_iclass_rsr_misc0_args, 5981 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, 5982 { 1, Iclass_xt_iclass_wsr_misc0_args, 5983 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, 5984 { 1, Iclass_xt_iclass_xsr_misc0_args, 5985 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, 5986 { 1, Iclass_xt_iclass_rsr_misc1_args, 5987 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, 5988 { 1, Iclass_xt_iclass_wsr_misc1_args, 5989 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, 5990 { 1, Iclass_xt_iclass_xsr_misc1_args, 5991 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, 5992 { 1, Iclass_xt_iclass_rsr_prid_args, 5993 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, 5994 { 1, Iclass_xt_iclass_rsr_vecbase_args, 5995 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, 5996 { 1, Iclass_xt_iclass_wsr_vecbase_args, 5997 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, 5998 { 1, Iclass_xt_iclass_xsr_vecbase_args, 5999 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, 6000 { 2, Iclass_xt_iclass_mac16_aa_args, 6001 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 }, 6002 { 2, Iclass_xt_iclass_mac16_ad_args, 6003 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 }, 6004 { 2, Iclass_xt_iclass_mac16_da_args, 6005 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 }, 6006 { 2, Iclass_xt_iclass_mac16_dd_args, 6007 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 }, 6008 { 2, Iclass_xt_iclass_mac16a_aa_args, 6009 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 }, 6010 { 2, Iclass_xt_iclass_mac16a_ad_args, 6011 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 }, 6012 { 2, Iclass_xt_iclass_mac16a_da_args, 6013 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 }, 6014 { 2, Iclass_xt_iclass_mac16a_dd_args, 6015 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 }, 6016 { 4, Iclass_xt_iclass_mac16al_da_args, 6017 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 }, 6018 { 4, Iclass_xt_iclass_mac16al_dd_args, 6019 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 }, 6020 { 2, Iclass_xt_iclass_mac16_l_args, 6021 0, 0, 0, 0 }, 6022 { 3, Iclass_xt_iclass_mul16_args, 6023 0, 0, 0, 0 }, 6024 { 2, Iclass_xt_iclass_rsr_m0_args, 6025 0, 0, 0, 0 }, 6026 { 2, Iclass_xt_iclass_wsr_m0_args, 6027 0, 0, 0, 0 }, 6028 { 2, Iclass_xt_iclass_xsr_m0_args, 6029 0, 0, 0, 0 }, 6030 { 2, Iclass_xt_iclass_rsr_m1_args, 6031 0, 0, 0, 0 }, 6032 { 2, Iclass_xt_iclass_wsr_m1_args, 6033 0, 0, 0, 0 }, 6034 { 2, Iclass_xt_iclass_xsr_m1_args, 6035 0, 0, 0, 0 }, 6036 { 2, Iclass_xt_iclass_rsr_m2_args, 6037 0, 0, 0, 0 }, 6038 { 2, Iclass_xt_iclass_wsr_m2_args, 6039 0, 0, 0, 0 }, 6040 { 2, Iclass_xt_iclass_xsr_m2_args, 6041 0, 0, 0, 0 }, 6042 { 2, Iclass_xt_iclass_rsr_m3_args, 6043 0, 0, 0, 0 }, 6044 { 2, Iclass_xt_iclass_wsr_m3_args, 6045 0, 0, 0, 0 }, 6046 { 2, Iclass_xt_iclass_xsr_m3_args, 6047 0, 0, 0, 0 }, 6048 { 1, Iclass_xt_iclass_rsr_acclo_args, 6049 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 }, 6050 { 1, Iclass_xt_iclass_wsr_acclo_args, 6051 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 }, 6052 { 1, Iclass_xt_iclass_xsr_acclo_args, 6053 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 }, 6054 { 1, Iclass_xt_iclass_rsr_acchi_args, 6055 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 }, 6056 { 1, Iclass_xt_iclass_wsr_acchi_args, 6057 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 }, 6058 { 1, Iclass_xt_iclass_xsr_acchi_args, 6059 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 }, 6060 { 1, Iclass_xt_iclass_rfi_args, 6061 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, 6062 { 1, Iclass_xt_iclass_wait_args, 6063 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, 6064 { 1, Iclass_xt_iclass_rsr_interrupt_args, 6065 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, 6066 { 1, Iclass_xt_iclass_wsr_intset_args, 6067 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, 6068 { 1, Iclass_xt_iclass_wsr_intclear_args, 6069 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, 6070 { 1, Iclass_xt_iclass_rsr_intenable_args, 6071 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, 6072 { 1, Iclass_xt_iclass_wsr_intenable_args, 6073 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, 6074 { 1, Iclass_xt_iclass_xsr_intenable_args, 6075 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, 6076 { 2, Iclass_xt_iclass_break_args, 6077 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, 6078 { 1, Iclass_xt_iclass_break_n_args, 6079 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, 6080 { 1, Iclass_xt_iclass_rsr_dbreaka0_args, 6081 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, 6082 { 1, Iclass_xt_iclass_wsr_dbreaka0_args, 6083 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, 6084 { 1, Iclass_xt_iclass_xsr_dbreaka0_args, 6085 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, 6086 { 1, Iclass_xt_iclass_rsr_dbreakc0_args, 6087 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, 6088 { 1, Iclass_xt_iclass_wsr_dbreakc0_args, 6089 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, 6090 { 1, Iclass_xt_iclass_xsr_dbreakc0_args, 6091 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, 6092 { 1, Iclass_xt_iclass_rsr_dbreaka1_args, 6093 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, 6094 { 1, Iclass_xt_iclass_wsr_dbreaka1_args, 6095 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, 6096 { 1, Iclass_xt_iclass_xsr_dbreaka1_args, 6097 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, 6098 { 1, Iclass_xt_iclass_rsr_dbreakc1_args, 6099 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, 6100 { 1, Iclass_xt_iclass_wsr_dbreakc1_args, 6101 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, 6102 { 1, Iclass_xt_iclass_xsr_dbreakc1_args, 6103 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, 6104 { 1, Iclass_xt_iclass_rsr_ibreaka0_args, 6105 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, 6106 { 1, Iclass_xt_iclass_wsr_ibreaka0_args, 6107 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, 6108 { 1, Iclass_xt_iclass_xsr_ibreaka0_args, 6109 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, 6110 { 1, Iclass_xt_iclass_rsr_ibreaka1_args, 6111 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, 6112 { 1, Iclass_xt_iclass_wsr_ibreaka1_args, 6113 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, 6114 { 1, Iclass_xt_iclass_xsr_ibreaka1_args, 6115 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, 6116 { 1, Iclass_xt_iclass_rsr_ibreakenable_args, 6117 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, 6118 { 1, Iclass_xt_iclass_wsr_ibreakenable_args, 6119 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, 6120 { 1, Iclass_xt_iclass_xsr_ibreakenable_args, 6121 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, 6122 { 1, Iclass_xt_iclass_rsr_debugcause_args, 6123 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, 6124 { 1, Iclass_xt_iclass_wsr_debugcause_args, 6125 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, 6126 { 1, Iclass_xt_iclass_xsr_debugcause_args, 6127 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, 6128 { 1, Iclass_xt_iclass_rsr_icount_args, 6129 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, 6130 { 1, Iclass_xt_iclass_wsr_icount_args, 6131 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, 6132 { 1, Iclass_xt_iclass_xsr_icount_args, 6133 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, 6134 { 1, Iclass_xt_iclass_rsr_icountlevel_args, 6135 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, 6136 { 1, Iclass_xt_iclass_wsr_icountlevel_args, 6137 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, 6138 { 1, Iclass_xt_iclass_xsr_icountlevel_args, 6139 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, 6140 { 1, Iclass_xt_iclass_rsr_ddr_args, 6141 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, 6142 { 1, Iclass_xt_iclass_wsr_ddr_args, 6143 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, 6144 { 1, Iclass_xt_iclass_xsr_ddr_args, 6145 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, 6146 { 1, Iclass_xt_iclass_rfdo_args, 6147 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, 6148 { 0, 0 /* xt_iclass_rfdd */, 6149 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, 6150 { 1, Iclass_xt_iclass_wsr_mmid_args, 6151 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, 6152 { 1, Iclass_xt_iclass_rsr_ccount_args, 6153 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, 6154 { 1, Iclass_xt_iclass_wsr_ccount_args, 6155 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, 6156 { 1, Iclass_xt_iclass_xsr_ccount_args, 6157 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, 6158 { 1, Iclass_xt_iclass_rsr_ccompare0_args, 6159 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, 6160 { 1, Iclass_xt_iclass_wsr_ccompare0_args, 6161 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, 6162 { 1, Iclass_xt_iclass_xsr_ccompare0_args, 6163 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, 6164 { 1, Iclass_xt_iclass_rsr_ccompare1_args, 6165 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, 6166 { 1, Iclass_xt_iclass_wsr_ccompare1_args, 6167 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, 6168 { 1, Iclass_xt_iclass_xsr_ccompare1_args, 6169 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, 6170 { 1, Iclass_xt_iclass_rsr_ccompare2_args, 6171 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, 6172 { 1, Iclass_xt_iclass_wsr_ccompare2_args, 6173 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, 6174 { 1, Iclass_xt_iclass_xsr_ccompare2_args, 6175 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, 6176 { 2, Iclass_xt_iclass_icache_args, 6177 0, 0, 0, 0 }, 6178 { 2, Iclass_xt_iclass_icache_lock_args, 6179 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 }, 6180 { 2, Iclass_xt_iclass_icache_inv_args, 6181 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, 6182 { 2, Iclass_xt_iclass_licx_args, 6183 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, 6184 { 2, Iclass_xt_iclass_sicx_args, 6185 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, 6186 { 2, Iclass_xt_iclass_dcache_args, 6187 0, 0, 0, 0 }, 6188 { 2, Iclass_xt_iclass_dcache_ind_args, 6189 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, 6190 { 2, Iclass_xt_iclass_dcache_inv_args, 6191 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, 6192 { 2, Iclass_xt_iclass_dpf_args, 6193 0, 0, 0, 0 }, 6194 { 2, Iclass_xt_iclass_dcache_lock_args, 6195 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 }, 6196 { 2, Iclass_xt_iclass_sdct_args, 6197 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, 6198 { 2, Iclass_xt_iclass_ldct_args, 6199 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, 6200 { 1, Iclass_xt_iclass_wsr_ptevaddr_args, 6201 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 }, 6202 { 1, Iclass_xt_iclass_rsr_ptevaddr_args, 6203 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 }, 6204 { 1, Iclass_xt_iclass_xsr_ptevaddr_args, 6205 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 }, 6206 { 1, Iclass_xt_iclass_rsr_rasid_args, 6207 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 }, 6208 { 1, Iclass_xt_iclass_wsr_rasid_args, 6209 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 }, 6210 { 1, Iclass_xt_iclass_xsr_rasid_args, 6211 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 }, 6212 { 1, Iclass_xt_iclass_rsr_itlbcfg_args, 6213 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 }, 6214 { 1, Iclass_xt_iclass_wsr_itlbcfg_args, 6215 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 }, 6216 { 1, Iclass_xt_iclass_xsr_itlbcfg_args, 6217 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 }, 6218 { 1, Iclass_xt_iclass_rsr_dtlbcfg_args, 6219 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 }, 6220 { 1, Iclass_xt_iclass_wsr_dtlbcfg_args, 6221 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 }, 6222 { 1, Iclass_xt_iclass_xsr_dtlbcfg_args, 6223 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 }, 6224 { 1, Iclass_xt_iclass_idtlb_args, 6225 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, 6226 { 2, Iclass_xt_iclass_rdtlb_args, 6227 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 }, 6228 { 2, Iclass_xt_iclass_wdtlb_args, 6229 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, 6230 { 1, Iclass_xt_iclass_iitlb_args, 6231 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 }, 6232 { 2, Iclass_xt_iclass_ritlb_args, 6233 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 }, 6234 { 2, Iclass_xt_iclass_witlb_args, 6235 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 }, 6236 { 0, 0 /* xt_iclass_ldpte */, 6237 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 }, 6238 { 0, 0 /* xt_iclass_hwwitlba */, 6239 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 }, 6240 { 0, 0 /* xt_iclass_hwwdtlba */, 6241 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 }, 6242 { 1, Iclass_xt_iclass_rsr_cpenable_args, 6243 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, 6244 { 1, Iclass_xt_iclass_wsr_cpenable_args, 6245 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, 6246 { 1, Iclass_xt_iclass_xsr_cpenable_args, 6247 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, 6248 { 3, Iclass_xt_iclass_clamp_args, 6249 0, 0, 0, 0 }, 6250 { 3, Iclass_xt_iclass_minmax_args, 6251 0, 0, 0, 0 }, 6252 { 2, Iclass_xt_iclass_nsa_args, 6253 0, 0, 0, 0 }, 6254 { 3, Iclass_xt_iclass_sx_args, 6255 0, 0, 0, 0 }, 6256 { 3, Iclass_xt_iclass_l32ai_args, 6257 0, 0, 0, 0 }, 6258 { 3, Iclass_xt_iclass_s32ri_args, 6259 0, 0, 0, 0 }, 6260 { 3, Iclass_xt_iclass_s32c1i_args, 6261 2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, 6262 { 1, Iclass_xt_iclass_rsr_scompare1_args, 6263 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, 6264 { 1, Iclass_xt_iclass_wsr_scompare1_args, 6265 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, 6266 { 1, Iclass_xt_iclass_xsr_scompare1_args, 6267 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, 6268 { 3, Iclass_xt_iclass_div_args, 6269 0, 0, 0, 0 }, 6270 { 3, Iclass_xt_mul32_args, 6271 0, 0, 0, 0 }, 6272 { 1, Iclass_rur_expstate_args, 6273 2, Iclass_rur_expstate_stateArgs, 0, 0 }, 6274 { 1, Iclass_wur_expstate_args, 6275 2, Iclass_wur_expstate_stateArgs, 0, 0 }, 6276 { 1, Iclass_iclass_READ_IMPWIRE_args, 6277 1, Iclass_iclass_READ_IMPWIRE_stateArgs, 1, Iclass_iclass_READ_IMPWIRE_intfArgs }, 6278 { 1, Iclass_iclass_SETB_EXPSTATE_args, 6279 2, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 }, 6280 { 1, Iclass_iclass_CLRB_EXPSTATE_args, 6281 2, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 }, 6282 { 2, Iclass_iclass_WRMSK_EXPSTATE_args, 6283 2, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 } 6284}; 6285 6286 6287/* Opcode encodings. */ 6288 6289static void 6290Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) 6291{ 6292 slotbuf[0] = 0x2080; 6293} 6294 6295static void 6296Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) 6297{ 6298 slotbuf[0] = 0x3000; 6299} 6300 6301static void 6302Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) 6303{ 6304 slotbuf[0] = 0x3200; 6305} 6306 6307static void 6308Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) 6309{ 6310 slotbuf[0] = 0x5000; 6311} 6312 6313static void 6314Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) 6315{ 6316 slotbuf[0] = 0x5100; 6317} 6318 6319static void 6320Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) 6321{ 6322 slotbuf[0] = 0x35; 6323} 6324 6325static void 6326Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) 6327{ 6328 slotbuf[0] = 0x25; 6329} 6330 6331static void 6332Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) 6333{ 6334 slotbuf[0] = 0x15; 6335} 6336 6337static void 6338Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) 6339{ 6340 slotbuf[0] = 0xf0; 6341} 6342 6343static void 6344Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) 6345{ 6346 slotbuf[0] = 0xe0; 6347} 6348 6349static void 6350Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) 6351{ 6352 slotbuf[0] = 0xd0; 6353} 6354 6355static void 6356Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) 6357{ 6358 slotbuf[0] = 0x36; 6359} 6360 6361static void 6362Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) 6363{ 6364 slotbuf[0] = 0x1000; 6365} 6366 6367static void 6368Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) 6369{ 6370 slotbuf[0] = 0x408000; 6371} 6372 6373static void 6374Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) 6375{ 6376 slotbuf[0] = 0x90; 6377} 6378 6379static void 6380Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 6381{ 6382 slotbuf[0] = 0xf01d; 6383} 6384 6385static void 6386Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) 6387{ 6388 slotbuf[0] = 0x3400; 6389} 6390 6391static void 6392Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) 6393{ 6394 slotbuf[0] = 0x3500; 6395} 6396 6397static void 6398Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) 6399{ 6400 slotbuf[0] = 0x90000; 6401} 6402 6403static void 6404Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) 6405{ 6406 slotbuf[0] = 0x490000; 6407} 6408 6409static void 6410Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 6411{ 6412 slotbuf[0] = 0x34800; 6413} 6414 6415static void 6416Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 6417{ 6418 slotbuf[0] = 0x134800; 6419} 6420 6421static void 6422Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 6423{ 6424 slotbuf[0] = 0x614800; 6425} 6426 6427static void 6428Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) 6429{ 6430 slotbuf[0] = 0x34900; 6431} 6432 6433static void 6434Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) 6435{ 6436 slotbuf[0] = 0x134900; 6437} 6438 6439static void 6440Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) 6441{ 6442 slotbuf[0] = 0x614900; 6443} 6444 6445static void 6446Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) 6447{ 6448 slotbuf[0] = 0xa; 6449} 6450 6451static void 6452Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) 6453{ 6454 slotbuf[0] = 0xb; 6455} 6456 6457static void 6458Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 6459{ 6460 slotbuf[0] = 0x8c; 6461} 6462 6463static void 6464Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 6465{ 6466 slotbuf[0] = 0xcc; 6467} 6468 6469static void 6470Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 6471{ 6472 slotbuf[0] = 0xf06d; 6473} 6474 6475static void 6476Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) 6477{ 6478 slotbuf[0] = 0x8; 6479} 6480 6481static void 6482Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 6483{ 6484 slotbuf[0] = 0xd; 6485} 6486 6487static void 6488Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 6489{ 6490 slotbuf[0] = 0xc; 6491} 6492 6493static void 6494Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 6495{ 6496 slotbuf[0] = 0xf03d; 6497} 6498 6499static void 6500Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 6501{ 6502 slotbuf[0] = 0xf00d; 6503} 6504 6505static void 6506Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) 6507{ 6508 slotbuf[0] = 0x9; 6509} 6510 6511static void 6512Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) 6513{ 6514 slotbuf[0] = 0xe30e70; 6515} 6516 6517static void 6518Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) 6519{ 6520 slotbuf[0] = 0xf3e700; 6521} 6522 6523static void 6524Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) 6525{ 6526 slotbuf[0] = 0xc002; 6527} 6528 6529static void 6530Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) 6531{ 6532 slotbuf[0] = 0xd002; 6533} 6534 6535static void 6536Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) 6537{ 6538 slotbuf[0] = 0x800000; 6539} 6540 6541static void 6542Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) 6543{ 6544 slotbuf[0] = 0xc00000; 6545} 6546 6547static void 6548Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) 6549{ 6550 slotbuf[0] = 0x900000; 6551} 6552 6553static void 6554Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) 6555{ 6556 slotbuf[0] = 0xa00000; 6557} 6558 6559static void 6560Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) 6561{ 6562 slotbuf[0] = 0xb00000; 6563} 6564 6565static void 6566Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) 6567{ 6568 slotbuf[0] = 0xd00000; 6569} 6570 6571static void 6572Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) 6573{ 6574 slotbuf[0] = 0xe00000; 6575} 6576 6577static void 6578Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) 6579{ 6580 slotbuf[0] = 0xf00000; 6581} 6582 6583static void 6584Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) 6585{ 6586 slotbuf[0] = 0x100000; 6587} 6588 6589static void 6590Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) 6591{ 6592 slotbuf[0] = 0x200000; 6593} 6594 6595static void 6596Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) 6597{ 6598 slotbuf[0] = 0x300000; 6599} 6600 6601static void 6602Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) 6603{ 6604 slotbuf[0] = 0x26; 6605} 6606 6607static void 6608Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) 6609{ 6610 slotbuf[0] = 0x66; 6611} 6612 6613static void 6614Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) 6615{ 6616 slotbuf[0] = 0xe6; 6617} 6618 6619static void 6620Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) 6621{ 6622 slotbuf[0] = 0xa6; 6623} 6624 6625static void 6626Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) 6627{ 6628 slotbuf[0] = 0x6007; 6629} 6630 6631static void 6632Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) 6633{ 6634 slotbuf[0] = 0xe007; 6635} 6636 6637static void 6638Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) 6639{ 6640 slotbuf[0] = 0xf6; 6641} 6642 6643static void 6644Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) 6645{ 6646 slotbuf[0] = 0xb6; 6647} 6648 6649static void 6650Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) 6651{ 6652 slotbuf[0] = 0x1007; 6653} 6654 6655static void 6656Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) 6657{ 6658 slotbuf[0] = 0x9007; 6659} 6660 6661static void 6662Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) 6663{ 6664 slotbuf[0] = 0xa007; 6665} 6666 6667static void 6668Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) 6669{ 6670 slotbuf[0] = 0x2007; 6671} 6672 6673static void 6674Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) 6675{ 6676 slotbuf[0] = 0xb007; 6677} 6678 6679static void 6680Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) 6681{ 6682 slotbuf[0] = 0x3007; 6683} 6684 6685static void 6686Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) 6687{ 6688 slotbuf[0] = 0x8007; 6689} 6690 6691static void 6692Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) 6693{ 6694 slotbuf[0] = 0x7; 6695} 6696 6697static void 6698Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) 6699{ 6700 slotbuf[0] = 0x4007; 6701} 6702 6703static void 6704Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) 6705{ 6706 slotbuf[0] = 0xc007; 6707} 6708 6709static void 6710Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) 6711{ 6712 slotbuf[0] = 0x5007; 6713} 6714 6715static void 6716Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) 6717{ 6718 slotbuf[0] = 0xd007; 6719} 6720 6721static void 6722Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) 6723{ 6724 slotbuf[0] = 0x16; 6725} 6726 6727static void 6728Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) 6729{ 6730 slotbuf[0] = 0x56; 6731} 6732 6733static void 6734Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) 6735{ 6736 slotbuf[0] = 0xd6; 6737} 6738 6739static void 6740Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) 6741{ 6742 slotbuf[0] = 0x96; 6743} 6744 6745static void 6746Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6747{ 6748 slotbuf[0] = 0x5; 6749} 6750 6751static void 6752Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6753{ 6754 slotbuf[0] = 0xc0; 6755} 6756 6757static void 6758Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) 6759{ 6760 slotbuf[0] = 0x40000; 6761} 6762 6763static void 6764Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) 6765{ 6766 slotbuf[0] = 0; 6767} 6768 6769static void 6770Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) 6771{ 6772 slotbuf[0] = 0x6; 6773} 6774 6775static void 6776Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) 6777{ 6778 slotbuf[0] = 0xa0; 6779} 6780 6781static void 6782Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) 6783{ 6784 slotbuf[0] = 0x1002; 6785} 6786 6787static void 6788Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) 6789{ 6790 slotbuf[0] = 0x9002; 6791} 6792 6793static void 6794Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) 6795{ 6796 slotbuf[0] = 0x2002; 6797} 6798 6799static void 6800Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) 6801{ 6802 slotbuf[0] = 0x1; 6803} 6804 6805static void 6806Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) 6807{ 6808 slotbuf[0] = 0x2; 6809} 6810 6811static void 6812Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) 6813{ 6814 slotbuf[0] = 0x8076; 6815} 6816 6817static void 6818Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) 6819{ 6820 slotbuf[0] = 0x9076; 6821} 6822 6823static void 6824Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) 6825{ 6826 slotbuf[0] = 0xa076; 6827} 6828 6829static void 6830Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) 6831{ 6832 slotbuf[0] = 0xa002; 6833} 6834 6835static void 6836Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) 6837{ 6838 slotbuf[0] = 0x830000; 6839} 6840 6841static void 6842Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) 6843{ 6844 slotbuf[0] = 0x930000; 6845} 6846 6847static void 6848Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) 6849{ 6850 slotbuf[0] = 0xa30000; 6851} 6852 6853static void 6854Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) 6855{ 6856 slotbuf[0] = 0xb30000; 6857} 6858 6859static void 6860Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) 6861{ 6862 slotbuf[0] = 0x600000; 6863} 6864 6865static void 6866Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) 6867{ 6868 slotbuf[0] = 0x600100; 6869} 6870 6871static void 6872Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) 6873{ 6874 slotbuf[0] = 0x20f0; 6875} 6876 6877static void 6878Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) 6879{ 6880 slotbuf[0] = 0x80; 6881} 6882 6883static void 6884Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) 6885{ 6886 slotbuf[0] = 0x5002; 6887} 6888 6889static void 6890Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) 6891{ 6892 slotbuf[0] = 0x6002; 6893} 6894 6895static void 6896Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) 6897{ 6898 slotbuf[0] = 0x4002; 6899} 6900 6901static void 6902Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) 6903{ 6904 slotbuf[0] = 0x400000; 6905} 6906 6907static void 6908Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) 6909{ 6910 slotbuf[0] = 0x401000; 6911} 6912 6913static void 6914Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) 6915{ 6916 slotbuf[0] = 0x402000; 6917} 6918 6919static void 6920Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) 6921{ 6922 slotbuf[0] = 0x403000; 6923} 6924 6925static void 6926Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) 6927{ 6928 slotbuf[0] = 0x404000; 6929} 6930 6931static void 6932Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) 6933{ 6934 slotbuf[0] = 0xa10000; 6935} 6936 6937static void 6938Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) 6939{ 6940 slotbuf[0] = 0x810000; 6941} 6942 6943static void 6944Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) 6945{ 6946 slotbuf[0] = 0x910000; 6947} 6948 6949static void 6950Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) 6951{ 6952 slotbuf[0] = 0xb10000; 6953} 6954 6955static void 6956Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) 6957{ 6958 slotbuf[0] = 0x10000; 6959} 6960 6961static void 6962Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) 6963{ 6964 slotbuf[0] = 0x210000; 6965} 6966 6967static void 6968Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) 6969{ 6970 slotbuf[0] = 0x410000; 6971} 6972 6973static void 6974Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) 6975{ 6976 slotbuf[0] = 0x20c0; 6977} 6978 6979static void 6980Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) 6981{ 6982 slotbuf[0] = 0x20d0; 6983} 6984 6985static void 6986Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) 6987{ 6988 slotbuf[0] = 0x2000; 6989} 6990 6991static void 6992Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) 6993{ 6994 slotbuf[0] = 0x2010; 6995} 6996 6997static void 6998Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) 6999{ 7000 slotbuf[0] = 0x2020; 7001} 7002 7003static void 7004Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) 7005{ 7006 slotbuf[0] = 0x2030; 7007} 7008 7009static void 7010Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) 7011{ 7012 slotbuf[0] = 0x6000; 7013} 7014 7015static void 7016Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) 7017{ 7018 slotbuf[0] = 0x30100; 7019} 7020 7021static void 7022Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) 7023{ 7024 slotbuf[0] = 0x130100; 7025} 7026 7027static void 7028Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) 7029{ 7030 slotbuf[0] = 0x610100; 7031} 7032 7033static void 7034Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) 7035{ 7036 slotbuf[0] = 0x30200; 7037} 7038 7039static void 7040Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) 7041{ 7042 slotbuf[0] = 0x130200; 7043} 7044 7045static void 7046Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) 7047{ 7048 slotbuf[0] = 0x610200; 7049} 7050 7051static void 7052Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) 7053{ 7054 slotbuf[0] = 0x30000; 7055} 7056 7057static void 7058Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) 7059{ 7060 slotbuf[0] = 0x130000; 7061} 7062 7063static void 7064Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) 7065{ 7066 slotbuf[0] = 0x610000; 7067} 7068 7069static void 7070Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) 7071{ 7072 slotbuf[0] = 0x30300; 7073} 7074 7075static void 7076Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) 7077{ 7078 slotbuf[0] = 0x130300; 7079} 7080 7081static void 7082Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) 7083{ 7084 slotbuf[0] = 0x610300; 7085} 7086 7087static void 7088Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 7089{ 7090 slotbuf[0] = 0x30500; 7091} 7092 7093static void 7094Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 7095{ 7096 slotbuf[0] = 0x130500; 7097} 7098 7099static void 7100Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 7101{ 7102 slotbuf[0] = 0x610500; 7103} 7104 7105static void 7106Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf) 7107{ 7108 slotbuf[0] = 0x3b000; 7109} 7110 7111static void 7112Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf) 7113{ 7114 slotbuf[0] = 0x3d000; 7115} 7116 7117static void 7118Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) 7119{ 7120 slotbuf[0] = 0x3e600; 7121} 7122 7123static void 7124Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) 7125{ 7126 slotbuf[0] = 0x13e600; 7127} 7128 7129static void 7130Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) 7131{ 7132 slotbuf[0] = 0x61e600; 7133} 7134 7135static void 7136Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 7137{ 7138 slotbuf[0] = 0x3b100; 7139} 7140 7141static void 7142Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 7143{ 7144 slotbuf[0] = 0x13b100; 7145} 7146 7147static void 7148Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 7149{ 7150 slotbuf[0] = 0x61b100; 7151} 7152 7153static void 7154Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) 7155{ 7156 slotbuf[0] = 0x3d100; 7157} 7158 7159static void 7160Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) 7161{ 7162 slotbuf[0] = 0x13d100; 7163} 7164 7165static void 7166Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) 7167{ 7168 slotbuf[0] = 0x61d100; 7169} 7170 7171static void 7172Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) 7173{ 7174 slotbuf[0] = 0x3b200; 7175} 7176 7177static void 7178Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) 7179{ 7180 slotbuf[0] = 0x13b200; 7181} 7182 7183static void 7184Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) 7185{ 7186 slotbuf[0] = 0x61b200; 7187} 7188 7189static void 7190Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) 7191{ 7192 slotbuf[0] = 0x3d200; 7193} 7194 7195static void 7196Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) 7197{ 7198 slotbuf[0] = 0x13d200; 7199} 7200 7201static void 7202Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) 7203{ 7204 slotbuf[0] = 0x61d200; 7205} 7206 7207static void 7208Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) 7209{ 7210 slotbuf[0] = 0x3b300; 7211} 7212 7213static void 7214Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) 7215{ 7216 slotbuf[0] = 0x13b300; 7217} 7218 7219static void 7220Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) 7221{ 7222 slotbuf[0] = 0x61b300; 7223} 7224 7225static void 7226Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) 7227{ 7228 slotbuf[0] = 0x3d300; 7229} 7230 7231static void 7232Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) 7233{ 7234 slotbuf[0] = 0x13d300; 7235} 7236 7237static void 7238Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) 7239{ 7240 slotbuf[0] = 0x61d300; 7241} 7242 7243static void 7244Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) 7245{ 7246 slotbuf[0] = 0x3b400; 7247} 7248 7249static void 7250Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) 7251{ 7252 slotbuf[0] = 0x13b400; 7253} 7254 7255static void 7256Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) 7257{ 7258 slotbuf[0] = 0x61b400; 7259} 7260 7261static void 7262Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) 7263{ 7264 slotbuf[0] = 0x3d400; 7265} 7266 7267static void 7268Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) 7269{ 7270 slotbuf[0] = 0x13d400; 7271} 7272 7273static void 7274Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) 7275{ 7276 slotbuf[0] = 0x61d400; 7277} 7278 7279static void 7280Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) 7281{ 7282 slotbuf[0] = 0x3b500; 7283} 7284 7285static void 7286Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) 7287{ 7288 slotbuf[0] = 0x13b500; 7289} 7290 7291static void 7292Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) 7293{ 7294 slotbuf[0] = 0x61b500; 7295} 7296 7297static void 7298Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) 7299{ 7300 slotbuf[0] = 0x3d500; 7301} 7302 7303static void 7304Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) 7305{ 7306 slotbuf[0] = 0x13d500; 7307} 7308 7309static void 7310Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) 7311{ 7312 slotbuf[0] = 0x61d500; 7313} 7314 7315static void 7316Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) 7317{ 7318 slotbuf[0] = 0x3b600; 7319} 7320 7321static void 7322Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) 7323{ 7324 slotbuf[0] = 0x13b600; 7325} 7326 7327static void 7328Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) 7329{ 7330 slotbuf[0] = 0x61b600; 7331} 7332 7333static void 7334Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) 7335{ 7336 slotbuf[0] = 0x3d600; 7337} 7338 7339static void 7340Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) 7341{ 7342 slotbuf[0] = 0x13d600; 7343} 7344 7345static void 7346Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) 7347{ 7348 slotbuf[0] = 0x61d600; 7349} 7350 7351static void 7352Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) 7353{ 7354 slotbuf[0] = 0x3b700; 7355} 7356 7357static void 7358Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) 7359{ 7360 slotbuf[0] = 0x13b700; 7361} 7362 7363static void 7364Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) 7365{ 7366 slotbuf[0] = 0x61b700; 7367} 7368 7369static void 7370Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) 7371{ 7372 slotbuf[0] = 0x3d700; 7373} 7374 7375static void 7376Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) 7377{ 7378 slotbuf[0] = 0x13d700; 7379} 7380 7381static void 7382Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) 7383{ 7384 slotbuf[0] = 0x61d700; 7385} 7386 7387static void 7388Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) 7389{ 7390 slotbuf[0] = 0x3c200; 7391} 7392 7393static void 7394Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) 7395{ 7396 slotbuf[0] = 0x13c200; 7397} 7398 7399static void 7400Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) 7401{ 7402 slotbuf[0] = 0x61c200; 7403} 7404 7405static void 7406Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) 7407{ 7408 slotbuf[0] = 0x3c300; 7409} 7410 7411static void 7412Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) 7413{ 7414 slotbuf[0] = 0x13c300; 7415} 7416 7417static void 7418Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) 7419{ 7420 slotbuf[0] = 0x61c300; 7421} 7422 7423static void 7424Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) 7425{ 7426 slotbuf[0] = 0x3c400; 7427} 7428 7429static void 7430Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) 7431{ 7432 slotbuf[0] = 0x13c400; 7433} 7434 7435static void 7436Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) 7437{ 7438 slotbuf[0] = 0x61c400; 7439} 7440 7441static void 7442Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) 7443{ 7444 slotbuf[0] = 0x3c500; 7445} 7446 7447static void 7448Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) 7449{ 7450 slotbuf[0] = 0x13c500; 7451} 7452 7453static void 7454Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) 7455{ 7456 slotbuf[0] = 0x61c500; 7457} 7458 7459static void 7460Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) 7461{ 7462 slotbuf[0] = 0x3c600; 7463} 7464 7465static void 7466Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) 7467{ 7468 slotbuf[0] = 0x13c600; 7469} 7470 7471static void 7472Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) 7473{ 7474 slotbuf[0] = 0x61c600; 7475} 7476 7477static void 7478Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) 7479{ 7480 slotbuf[0] = 0x3c700; 7481} 7482 7483static void 7484Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) 7485{ 7486 slotbuf[0] = 0x13c700; 7487} 7488 7489static void 7490Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) 7491{ 7492 slotbuf[0] = 0x61c700; 7493} 7494 7495static void 7496Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 7497{ 7498 slotbuf[0] = 0x3ee00; 7499} 7500 7501static void 7502Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 7503{ 7504 slotbuf[0] = 0x13ee00; 7505} 7506 7507static void 7508Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 7509{ 7510 slotbuf[0] = 0x61ee00; 7511} 7512 7513static void 7514Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) 7515{ 7516 slotbuf[0] = 0x3c000; 7517} 7518 7519static void 7520Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) 7521{ 7522 slotbuf[0] = 0x13c000; 7523} 7524 7525static void 7526Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) 7527{ 7528 slotbuf[0] = 0x61c000; 7529} 7530 7531static void 7532Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) 7533{ 7534 slotbuf[0] = 0x3e800; 7535} 7536 7537static void 7538Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) 7539{ 7540 slotbuf[0] = 0x13e800; 7541} 7542 7543static void 7544Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) 7545{ 7546 slotbuf[0] = 0x61e800; 7547} 7548 7549static void 7550Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 7551{ 7552 slotbuf[0] = 0x3f400; 7553} 7554 7555static void 7556Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 7557{ 7558 slotbuf[0] = 0x13f400; 7559} 7560 7561static void 7562Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 7563{ 7564 slotbuf[0] = 0x61f400; 7565} 7566 7567static void 7568Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 7569{ 7570 slotbuf[0] = 0x3f500; 7571} 7572 7573static void 7574Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 7575{ 7576 slotbuf[0] = 0x13f500; 7577} 7578 7579static void 7580Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 7581{ 7582 slotbuf[0] = 0x61f500; 7583} 7584 7585static void 7586Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) 7587{ 7588 slotbuf[0] = 0x3eb00; 7589} 7590 7591static void 7592Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 7593{ 7594 slotbuf[0] = 0x3e700; 7595} 7596 7597static void 7598Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 7599{ 7600 slotbuf[0] = 0x13e700; 7601} 7602 7603static void 7604Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 7605{ 7606 slotbuf[0] = 0x61e700; 7607} 7608 7609static void 7610Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7611{ 7612 slotbuf[0] = 0x740004; 7613} 7614 7615static void 7616Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7617{ 7618 slotbuf[0] = 0x750004; 7619} 7620 7621static void 7622Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7623{ 7624 slotbuf[0] = 0x760004; 7625} 7626 7627static void 7628Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7629{ 7630 slotbuf[0] = 0x770004; 7631} 7632 7633static void 7634Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7635{ 7636 slotbuf[0] = 0x700004; 7637} 7638 7639static void 7640Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7641{ 7642 slotbuf[0] = 0x710004; 7643} 7644 7645static void 7646Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7647{ 7648 slotbuf[0] = 0x720004; 7649} 7650 7651static void 7652Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7653{ 7654 slotbuf[0] = 0x730004; 7655} 7656 7657static void 7658Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7659{ 7660 slotbuf[0] = 0x340004; 7661} 7662 7663static void 7664Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7665{ 7666 slotbuf[0] = 0x350004; 7667} 7668 7669static void 7670Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7671{ 7672 slotbuf[0] = 0x360004; 7673} 7674 7675static void 7676Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7677{ 7678 slotbuf[0] = 0x370004; 7679} 7680 7681static void 7682Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7683{ 7684 slotbuf[0] = 0x640004; 7685} 7686 7687static void 7688Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7689{ 7690 slotbuf[0] = 0x650004; 7691} 7692 7693static void 7694Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7695{ 7696 slotbuf[0] = 0x660004; 7697} 7698 7699static void 7700Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7701{ 7702 slotbuf[0] = 0x670004; 7703} 7704 7705static void 7706Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7707{ 7708 slotbuf[0] = 0x240004; 7709} 7710 7711static void 7712Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7713{ 7714 slotbuf[0] = 0x250004; 7715} 7716 7717static void 7718Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7719{ 7720 slotbuf[0] = 0x260004; 7721} 7722 7723static void 7724Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7725{ 7726 slotbuf[0] = 0x270004; 7727} 7728 7729static void 7730Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7731{ 7732 slotbuf[0] = 0x780004; 7733} 7734 7735static void 7736Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7737{ 7738 slotbuf[0] = 0x790004; 7739} 7740 7741static void 7742Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7743{ 7744 slotbuf[0] = 0x7a0004; 7745} 7746 7747static void 7748Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7749{ 7750 slotbuf[0] = 0x7b0004; 7751} 7752 7753static void 7754Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7755{ 7756 slotbuf[0] = 0x7c0004; 7757} 7758 7759static void 7760Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7761{ 7762 slotbuf[0] = 0x7d0004; 7763} 7764 7765static void 7766Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7767{ 7768 slotbuf[0] = 0x7e0004; 7769} 7770 7771static void 7772Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7773{ 7774 slotbuf[0] = 0x7f0004; 7775} 7776 7777static void 7778Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7779{ 7780 slotbuf[0] = 0x380004; 7781} 7782 7783static void 7784Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7785{ 7786 slotbuf[0] = 0x390004; 7787} 7788 7789static void 7790Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7791{ 7792 slotbuf[0] = 0x3a0004; 7793} 7794 7795static void 7796Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7797{ 7798 slotbuf[0] = 0x3b0004; 7799} 7800 7801static void 7802Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7803{ 7804 slotbuf[0] = 0x3c0004; 7805} 7806 7807static void 7808Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7809{ 7810 slotbuf[0] = 0x3d0004; 7811} 7812 7813static void 7814Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7815{ 7816 slotbuf[0] = 0x3e0004; 7817} 7818 7819static void 7820Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7821{ 7822 slotbuf[0] = 0x3f0004; 7823} 7824 7825static void 7826Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7827{ 7828 slotbuf[0] = 0x680004; 7829} 7830 7831static void 7832Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7833{ 7834 slotbuf[0] = 0x690004; 7835} 7836 7837static void 7838Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7839{ 7840 slotbuf[0] = 0x6a0004; 7841} 7842 7843static void 7844Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7845{ 7846 slotbuf[0] = 0x6b0004; 7847} 7848 7849static void 7850Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7851{ 7852 slotbuf[0] = 0x6c0004; 7853} 7854 7855static void 7856Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7857{ 7858 slotbuf[0] = 0x6d0004; 7859} 7860 7861static void 7862Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7863{ 7864 slotbuf[0] = 0x6e0004; 7865} 7866 7867static void 7868Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7869{ 7870 slotbuf[0] = 0x6f0004; 7871} 7872 7873static void 7874Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7875{ 7876 slotbuf[0] = 0x280004; 7877} 7878 7879static void 7880Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7881{ 7882 slotbuf[0] = 0x290004; 7883} 7884 7885static void 7886Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7887{ 7888 slotbuf[0] = 0x2a0004; 7889} 7890 7891static void 7892Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7893{ 7894 slotbuf[0] = 0x2b0004; 7895} 7896 7897static void 7898Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7899{ 7900 slotbuf[0] = 0x2c0004; 7901} 7902 7903static void 7904Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7905{ 7906 slotbuf[0] = 0x2d0004; 7907} 7908 7909static void 7910Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7911{ 7912 slotbuf[0] = 0x2e0004; 7913} 7914 7915static void 7916Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7917{ 7918 slotbuf[0] = 0x2f0004; 7919} 7920 7921static void 7922Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 7923{ 7924 slotbuf[0] = 0x580004; 7925} 7926 7927static void 7928Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 7929{ 7930 slotbuf[0] = 0x480004; 7931} 7932 7933static void 7934Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 7935{ 7936 slotbuf[0] = 0x590004; 7937} 7938 7939static void 7940Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 7941{ 7942 slotbuf[0] = 0x490004; 7943} 7944 7945static void 7946Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 7947{ 7948 slotbuf[0] = 0x5a0004; 7949} 7950 7951static void 7952Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 7953{ 7954 slotbuf[0] = 0x4a0004; 7955} 7956 7957static void 7958Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 7959{ 7960 slotbuf[0] = 0x5b0004; 7961} 7962 7963static void 7964Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 7965{ 7966 slotbuf[0] = 0x4b0004; 7967} 7968 7969static void 7970Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 7971{ 7972 slotbuf[0] = 0x180004; 7973} 7974 7975static void 7976Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 7977{ 7978 slotbuf[0] = 0x80004; 7979} 7980 7981static void 7982Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 7983{ 7984 slotbuf[0] = 0x190004; 7985} 7986 7987static void 7988Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 7989{ 7990 slotbuf[0] = 0x90004; 7991} 7992 7993static void 7994Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 7995{ 7996 slotbuf[0] = 0x1a0004; 7997} 7998 7999static void 8000Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 8001{ 8002 slotbuf[0] = 0xa0004; 8003} 8004 8005static void 8006Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 8007{ 8008 slotbuf[0] = 0x1b0004; 8009} 8010 8011static void 8012Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 8013{ 8014 slotbuf[0] = 0xb0004; 8015} 8016 8017static void 8018Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 8019{ 8020 slotbuf[0] = 0x900004; 8021} 8022 8023static void 8024Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 8025{ 8026 slotbuf[0] = 0x800004; 8027} 8028 8029static void 8030Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) 8031{ 8032 slotbuf[0] = 0xc10000; 8033} 8034 8035static void 8036Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) 8037{ 8038 slotbuf[0] = 0xd10000; 8039} 8040 8041static void 8042Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8043{ 8044 slotbuf[0] = 0x32000; 8045} 8046 8047static void 8048Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8049{ 8050 slotbuf[0] = 0x132000; 8051} 8052 8053static void 8054Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8055{ 8056 slotbuf[0] = 0x612000; 8057} 8058 8059static void 8060Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8061{ 8062 slotbuf[0] = 0x32100; 8063} 8064 8065static void 8066Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8067{ 8068 slotbuf[0] = 0x132100; 8069} 8070 8071static void 8072Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8073{ 8074 slotbuf[0] = 0x612100; 8075} 8076 8077static void 8078Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) 8079{ 8080 slotbuf[0] = 0x32200; 8081} 8082 8083static void 8084Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) 8085{ 8086 slotbuf[0] = 0x132200; 8087} 8088 8089static void 8090Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) 8091{ 8092 slotbuf[0] = 0x612200; 8093} 8094 8095static void 8096Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) 8097{ 8098 slotbuf[0] = 0x32300; 8099} 8100 8101static void 8102Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) 8103{ 8104 slotbuf[0] = 0x132300; 8105} 8106 8107static void 8108Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) 8109{ 8110 slotbuf[0] = 0x612300; 8111} 8112 8113static void 8114Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) 8115{ 8116 slotbuf[0] = 0x31000; 8117} 8118 8119static void 8120Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) 8121{ 8122 slotbuf[0] = 0x131000; 8123} 8124 8125static void 8126Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) 8127{ 8128 slotbuf[0] = 0x611000; 8129} 8130 8131static void 8132Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) 8133{ 8134 slotbuf[0] = 0x31100; 8135} 8136 8137static void 8138Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) 8139{ 8140 slotbuf[0] = 0x131100; 8141} 8142 8143static void 8144Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) 8145{ 8146 slotbuf[0] = 0x611100; 8147} 8148 8149static void 8150Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) 8151{ 8152 slotbuf[0] = 0x3010; 8153} 8154 8155static void 8156Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) 8157{ 8158 slotbuf[0] = 0x7000; 8159} 8160 8161static void 8162Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) 8163{ 8164 slotbuf[0] = 0x3e200; 8165} 8166 8167static void 8168Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) 8169{ 8170 slotbuf[0] = 0x13e200; 8171} 8172 8173static void 8174Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) 8175{ 8176 slotbuf[0] = 0x13e300; 8177} 8178 8179static void 8180Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 8181{ 8182 slotbuf[0] = 0x3e400; 8183} 8184 8185static void 8186Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 8187{ 8188 slotbuf[0] = 0x13e400; 8189} 8190 8191static void 8192Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 8193{ 8194 slotbuf[0] = 0x61e400; 8195} 8196 8197static void 8198Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) 8199{ 8200 slotbuf[0] = 0x4000; 8201} 8202 8203static void 8204Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 8205{ 8206 slotbuf[0] = 0xf02d; 8207} 8208 8209static void 8210Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8211{ 8212 slotbuf[0] = 0x39000; 8213} 8214 8215static void 8216Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8217{ 8218 slotbuf[0] = 0x139000; 8219} 8220 8221static void 8222Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8223{ 8224 slotbuf[0] = 0x619000; 8225} 8226 8227static void 8228Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8229{ 8230 slotbuf[0] = 0x3a000; 8231} 8232 8233static void 8234Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8235{ 8236 slotbuf[0] = 0x13a000; 8237} 8238 8239static void 8240Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8241{ 8242 slotbuf[0] = 0x61a000; 8243} 8244 8245static void 8246Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8247{ 8248 slotbuf[0] = 0x39100; 8249} 8250 8251static void 8252Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8253{ 8254 slotbuf[0] = 0x139100; 8255} 8256 8257static void 8258Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8259{ 8260 slotbuf[0] = 0x619100; 8261} 8262 8263static void 8264Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8265{ 8266 slotbuf[0] = 0x3a100; 8267} 8268 8269static void 8270Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8271{ 8272 slotbuf[0] = 0x13a100; 8273} 8274 8275static void 8276Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8277{ 8278 slotbuf[0] = 0x61a100; 8279} 8280 8281static void 8282Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8283{ 8284 slotbuf[0] = 0x38000; 8285} 8286 8287static void 8288Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8289{ 8290 slotbuf[0] = 0x138000; 8291} 8292 8293static void 8294Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8295{ 8296 slotbuf[0] = 0x618000; 8297} 8298 8299static void 8300Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8301{ 8302 slotbuf[0] = 0x38100; 8303} 8304 8305static void 8306Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8307{ 8308 slotbuf[0] = 0x138100; 8309} 8310 8311static void 8312Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8313{ 8314 slotbuf[0] = 0x618100; 8315} 8316 8317static void 8318Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 8319{ 8320 slotbuf[0] = 0x36000; 8321} 8322 8323static void 8324Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 8325{ 8326 slotbuf[0] = 0x136000; 8327} 8328 8329static void 8330Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 8331{ 8332 slotbuf[0] = 0x616000; 8333} 8334 8335static void 8336Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) 8337{ 8338 slotbuf[0] = 0x3e900; 8339} 8340 8341static void 8342Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) 8343{ 8344 slotbuf[0] = 0x13e900; 8345} 8346 8347static void 8348Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) 8349{ 8350 slotbuf[0] = 0x61e900; 8351} 8352 8353static void 8354Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) 8355{ 8356 slotbuf[0] = 0x3ec00; 8357} 8358 8359static void 8360Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) 8361{ 8362 slotbuf[0] = 0x13ec00; 8363} 8364 8365static void 8366Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) 8367{ 8368 slotbuf[0] = 0x61ec00; 8369} 8370 8371static void 8372Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) 8373{ 8374 slotbuf[0] = 0x3ed00; 8375} 8376 8377static void 8378Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) 8379{ 8380 slotbuf[0] = 0x13ed00; 8381} 8382 8383static void 8384Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) 8385{ 8386 slotbuf[0] = 0x61ed00; 8387} 8388 8389static void 8390Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 8391{ 8392 slotbuf[0] = 0x36800; 8393} 8394 8395static void 8396Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 8397{ 8398 slotbuf[0] = 0x136800; 8399} 8400 8401static void 8402Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 8403{ 8404 slotbuf[0] = 0x616800; 8405} 8406 8407static void 8408Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) 8409{ 8410 slotbuf[0] = 0xf1e000; 8411} 8412 8413static void 8414Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) 8415{ 8416 slotbuf[0] = 0xf1e010; 8417} 8418 8419static void 8420Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) 8421{ 8422 slotbuf[0] = 0x135900; 8423} 8424 8425static void 8426Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) 8427{ 8428 slotbuf[0] = 0x3ea00; 8429} 8430 8431static void 8432Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) 8433{ 8434 slotbuf[0] = 0x13ea00; 8435} 8436 8437static void 8438Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) 8439{ 8440 slotbuf[0] = 0x61ea00; 8441} 8442 8443static void 8444Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8445{ 8446 slotbuf[0] = 0x3f000; 8447} 8448 8449static void 8450Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8451{ 8452 slotbuf[0] = 0x13f000; 8453} 8454 8455static void 8456Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8457{ 8458 slotbuf[0] = 0x61f000; 8459} 8460 8461static void 8462Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8463{ 8464 slotbuf[0] = 0x3f100; 8465} 8466 8467static void 8468Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8469{ 8470 slotbuf[0] = 0x13f100; 8471} 8472 8473static void 8474Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8475{ 8476 slotbuf[0] = 0x61f100; 8477} 8478 8479static void 8480Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) 8481{ 8482 slotbuf[0] = 0x3f200; 8483} 8484 8485static void 8486Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) 8487{ 8488 slotbuf[0] = 0x13f200; 8489} 8490 8491static void 8492Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) 8493{ 8494 slotbuf[0] = 0x61f200; 8495} 8496 8497static void 8498Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) 8499{ 8500 slotbuf[0] = 0x70c2; 8501} 8502 8503static void 8504Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) 8505{ 8506 slotbuf[0] = 0x70e2; 8507} 8508 8509static void 8510Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) 8511{ 8512 slotbuf[0] = 0x70d2; 8513} 8514 8515static void 8516Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) 8517{ 8518 slotbuf[0] = 0x270d2; 8519} 8520 8521static void 8522Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) 8523{ 8524 slotbuf[0] = 0x370d2; 8525} 8526 8527static void 8528Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) 8529{ 8530 slotbuf[0] = 0x70f2; 8531} 8532 8533static void 8534Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) 8535{ 8536 slotbuf[0] = 0xf10000; 8537} 8538 8539static void 8540Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) 8541{ 8542 slotbuf[0] = 0xf12000; 8543} 8544 8545static void 8546Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) 8547{ 8548 slotbuf[0] = 0xf11000; 8549} 8550 8551static void 8552Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) 8553{ 8554 slotbuf[0] = 0xf13000; 8555} 8556 8557static void 8558Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) 8559{ 8560 slotbuf[0] = 0x7042; 8561} 8562 8563static void 8564Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) 8565{ 8566 slotbuf[0] = 0x7052; 8567} 8568 8569static void 8570Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) 8571{ 8572 slotbuf[0] = 0x47082; 8573} 8574 8575static void 8576Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) 8577{ 8578 slotbuf[0] = 0x57082; 8579} 8580 8581static void 8582Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) 8583{ 8584 slotbuf[0] = 0x7062; 8585} 8586 8587static void 8588Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) 8589{ 8590 slotbuf[0] = 0x7072; 8591} 8592 8593static void 8594Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) 8595{ 8596 slotbuf[0] = 0x7002; 8597} 8598 8599static void 8600Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) 8601{ 8602 slotbuf[0] = 0x7012; 8603} 8604 8605static void 8606Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) 8607{ 8608 slotbuf[0] = 0x7022; 8609} 8610 8611static void 8612Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) 8613{ 8614 slotbuf[0] = 0x7032; 8615} 8616 8617static void 8618Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) 8619{ 8620 slotbuf[0] = 0x7082; 8621} 8622 8623static void 8624Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) 8625{ 8626 slotbuf[0] = 0x27082; 8627} 8628 8629static void 8630Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) 8631{ 8632 slotbuf[0] = 0x37082; 8633} 8634 8635static void 8636Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) 8637{ 8638 slotbuf[0] = 0xf19000; 8639} 8640 8641static void 8642Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) 8643{ 8644 slotbuf[0] = 0xf18000; 8645} 8646 8647static void 8648Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 8649{ 8650 slotbuf[0] = 0x135300; 8651} 8652 8653static void 8654Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 8655{ 8656 slotbuf[0] = 0x35300; 8657} 8658 8659static void 8660Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 8661{ 8662 slotbuf[0] = 0x615300; 8663} 8664 8665static void 8666Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) 8667{ 8668 slotbuf[0] = 0x35a00; 8669} 8670 8671static void 8672Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) 8673{ 8674 slotbuf[0] = 0x135a00; 8675} 8676 8677static void 8678Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) 8679{ 8680 slotbuf[0] = 0x615a00; 8681} 8682 8683static void 8684Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 8685{ 8686 slotbuf[0] = 0x35b00; 8687} 8688 8689static void 8690Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 8691{ 8692 slotbuf[0] = 0x135b00; 8693} 8694 8695static void 8696Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 8697{ 8698 slotbuf[0] = 0x615b00; 8699} 8700 8701static void 8702Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 8703{ 8704 slotbuf[0] = 0x35c00; 8705} 8706 8707static void 8708Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 8709{ 8710 slotbuf[0] = 0x135c00; 8711} 8712 8713static void 8714Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 8715{ 8716 slotbuf[0] = 0x615c00; 8717} 8718 8719static void 8720Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 8721{ 8722 slotbuf[0] = 0x50c000; 8723} 8724 8725static void 8726Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 8727{ 8728 slotbuf[0] = 0x50d000; 8729} 8730 8731static void 8732Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8733{ 8734 slotbuf[0] = 0x50b000; 8735} 8736 8737static void 8738Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8739{ 8740 slotbuf[0] = 0x50f000; 8741} 8742 8743static void 8744Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 8745{ 8746 slotbuf[0] = 0x50e000; 8747} 8748 8749static void 8750Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 8751{ 8752 slotbuf[0] = 0x504000; 8753} 8754 8755static void 8756Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 8757{ 8758 slotbuf[0] = 0x505000; 8759} 8760 8761static void 8762Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8763{ 8764 slotbuf[0] = 0x503000; 8765} 8766 8767static void 8768Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8769{ 8770 slotbuf[0] = 0x507000; 8771} 8772 8773static void 8774Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 8775{ 8776 slotbuf[0] = 0x506000; 8777} 8778 8779static void 8780Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf) 8781{ 8782 slotbuf[0] = 0xf1f000; 8783} 8784 8785static void 8786Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf) 8787{ 8788 slotbuf[0] = 0x501000; 8789} 8790 8791static void 8792Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf) 8793{ 8794 slotbuf[0] = 0x509000; 8795} 8796 8797static void 8798Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 8799{ 8800 slotbuf[0] = 0x3e000; 8801} 8802 8803static void 8804Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 8805{ 8806 slotbuf[0] = 0x13e000; 8807} 8808 8809static void 8810Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 8811{ 8812 slotbuf[0] = 0x61e000; 8813} 8814 8815static void 8816Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) 8817{ 8818 slotbuf[0] = 0x330000; 8819} 8820 8821static void 8822Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) 8823{ 8824 slotbuf[0] = 0x430000; 8825} 8826 8827static void 8828Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) 8829{ 8830 slotbuf[0] = 0x530000; 8831} 8832 8833static void 8834Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) 8835{ 8836 slotbuf[0] = 0x630000; 8837} 8838 8839static void 8840Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) 8841{ 8842 slotbuf[0] = 0x730000; 8843} 8844 8845static void 8846Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) 8847{ 8848 slotbuf[0] = 0x40e000; 8849} 8850 8851static void 8852Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) 8853{ 8854 slotbuf[0] = 0x40f000; 8855} 8856 8857static void 8858Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) 8859{ 8860 slotbuf[0] = 0x230000; 8861} 8862 8863static void 8864Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) 8865{ 8866 slotbuf[0] = 0xb002; 8867} 8868 8869static void 8870Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) 8871{ 8872 slotbuf[0] = 0xf002; 8873} 8874 8875static void 8876Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) 8877{ 8878 slotbuf[0] = 0xe002; 8879} 8880 8881static void 8882Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8883{ 8884 slotbuf[0] = 0x30c00; 8885} 8886 8887static void 8888Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8889{ 8890 slotbuf[0] = 0x130c00; 8891} 8892 8893static void 8894Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8895{ 8896 slotbuf[0] = 0x610c00; 8897} 8898 8899static void 8900Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) 8901{ 8902 slotbuf[0] = 0xc20000; 8903} 8904 8905static void 8906Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) 8907{ 8908 slotbuf[0] = 0xd20000; 8909} 8910 8911static void 8912Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) 8913{ 8914 slotbuf[0] = 0xe20000; 8915} 8916 8917static void 8918Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) 8919{ 8920 slotbuf[0] = 0xf20000; 8921} 8922 8923static void 8924Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) 8925{ 8926 slotbuf[0] = 0x820000; 8927} 8928 8929static void 8930Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) 8931{ 8932 slotbuf[0] = 0xe30e60; 8933} 8934 8935static void 8936Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) 8937{ 8938 slotbuf[0] = 0xf3e600; 8939} 8940 8941static void 8942Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf) 8943{ 8944 slotbuf[0] = 0xe0000; 8945} 8946 8947static void 8948Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) 8949{ 8950 slotbuf[0] = 0xe1000; 8951} 8952 8953static void 8954Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) 8955{ 8956 slotbuf[0] = 0xe1200; 8957} 8958 8959static void 8960Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) 8961{ 8962 slotbuf[0] = 0xe2000; 8963} 8964 8965static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { 8966 Opcode_excw_Slot_inst_encode, 0, 0 8967}; 8968 8969static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { 8970 Opcode_rfe_Slot_inst_encode, 0, 0 8971}; 8972 8973static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { 8974 Opcode_rfde_Slot_inst_encode, 0, 0 8975}; 8976 8977static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { 8978 Opcode_syscall_Slot_inst_encode, 0, 0 8979}; 8980 8981static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { 8982 Opcode_simcall_Slot_inst_encode, 0, 0 8983}; 8984 8985static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { 8986 Opcode_call12_Slot_inst_encode, 0, 0 8987}; 8988 8989static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { 8990 Opcode_call8_Slot_inst_encode, 0, 0 8991}; 8992 8993static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { 8994 Opcode_call4_Slot_inst_encode, 0, 0 8995}; 8996 8997static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { 8998 Opcode_callx12_Slot_inst_encode, 0, 0 8999}; 9000 9001static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { 9002 Opcode_callx8_Slot_inst_encode, 0, 0 9003}; 9004 9005static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { 9006 Opcode_callx4_Slot_inst_encode, 0, 0 9007}; 9008 9009static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { 9010 Opcode_entry_Slot_inst_encode, 0, 0 9011}; 9012 9013static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { 9014 Opcode_movsp_Slot_inst_encode, 0, 0 9015}; 9016 9017static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { 9018 Opcode_rotw_Slot_inst_encode, 0, 0 9019}; 9020 9021static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { 9022 Opcode_retw_Slot_inst_encode, 0, 0 9023}; 9024 9025static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { 9026 0, 0, Opcode_retw_n_Slot_inst16b_encode 9027}; 9028 9029static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { 9030 Opcode_rfwo_Slot_inst_encode, 0, 0 9031}; 9032 9033static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { 9034 Opcode_rfwu_Slot_inst_encode, 0, 0 9035}; 9036 9037static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { 9038 Opcode_l32e_Slot_inst_encode, 0, 0 9039}; 9040 9041static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { 9042 Opcode_s32e_Slot_inst_encode, 0, 0 9043}; 9044 9045static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { 9046 Opcode_rsr_windowbase_Slot_inst_encode, 0, 0 9047}; 9048 9049static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { 9050 Opcode_wsr_windowbase_Slot_inst_encode, 0, 0 9051}; 9052 9053static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { 9054 Opcode_xsr_windowbase_Slot_inst_encode, 0, 0 9055}; 9056 9057static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { 9058 Opcode_rsr_windowstart_Slot_inst_encode, 0, 0 9059}; 9060 9061static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { 9062 Opcode_wsr_windowstart_Slot_inst_encode, 0, 0 9063}; 9064 9065static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { 9066 Opcode_xsr_windowstart_Slot_inst_encode, 0, 0 9067}; 9068 9069static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { 9070 0, Opcode_add_n_Slot_inst16a_encode, 0 9071}; 9072 9073static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { 9074 0, Opcode_addi_n_Slot_inst16a_encode, 0 9075}; 9076 9077static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { 9078 0, 0, Opcode_beqz_n_Slot_inst16b_encode 9079}; 9080 9081static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { 9082 0, 0, Opcode_bnez_n_Slot_inst16b_encode 9083}; 9084 9085static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { 9086 0, 0, Opcode_ill_n_Slot_inst16b_encode 9087}; 9088 9089static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { 9090 0, Opcode_l32i_n_Slot_inst16a_encode, 0 9091}; 9092 9093static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { 9094 0, 0, Opcode_mov_n_Slot_inst16b_encode 9095}; 9096 9097static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { 9098 0, 0, Opcode_movi_n_Slot_inst16b_encode 9099}; 9100 9101static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { 9102 0, 0, Opcode_nop_n_Slot_inst16b_encode 9103}; 9104 9105static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { 9106 0, 0, Opcode_ret_n_Slot_inst16b_encode 9107}; 9108 9109static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { 9110 0, Opcode_s32i_n_Slot_inst16a_encode, 0 9111}; 9112 9113static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { 9114 Opcode_rur_threadptr_Slot_inst_encode, 0, 0 9115}; 9116 9117static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { 9118 Opcode_wur_threadptr_Slot_inst_encode, 0, 0 9119}; 9120 9121static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { 9122 Opcode_addi_Slot_inst_encode, 0, 0 9123}; 9124 9125static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { 9126 Opcode_addmi_Slot_inst_encode, 0, 0 9127}; 9128 9129static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { 9130 Opcode_add_Slot_inst_encode, 0, 0 9131}; 9132 9133static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { 9134 Opcode_sub_Slot_inst_encode, 0, 0 9135}; 9136 9137static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { 9138 Opcode_addx2_Slot_inst_encode, 0, 0 9139}; 9140 9141static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { 9142 Opcode_addx4_Slot_inst_encode, 0, 0 9143}; 9144 9145static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { 9146 Opcode_addx8_Slot_inst_encode, 0, 0 9147}; 9148 9149static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { 9150 Opcode_subx2_Slot_inst_encode, 0, 0 9151}; 9152 9153static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { 9154 Opcode_subx4_Slot_inst_encode, 0, 0 9155}; 9156 9157static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { 9158 Opcode_subx8_Slot_inst_encode, 0, 0 9159}; 9160 9161static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { 9162 Opcode_and_Slot_inst_encode, 0, 0 9163}; 9164 9165static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { 9166 Opcode_or_Slot_inst_encode, 0, 0 9167}; 9168 9169static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { 9170 Opcode_xor_Slot_inst_encode, 0, 0 9171}; 9172 9173static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { 9174 Opcode_beqi_Slot_inst_encode, 0, 0 9175}; 9176 9177static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { 9178 Opcode_bnei_Slot_inst_encode, 0, 0 9179}; 9180 9181static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { 9182 Opcode_bgei_Slot_inst_encode, 0, 0 9183}; 9184 9185static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { 9186 Opcode_blti_Slot_inst_encode, 0, 0 9187}; 9188 9189static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { 9190 Opcode_bbci_Slot_inst_encode, 0, 0 9191}; 9192 9193static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { 9194 Opcode_bbsi_Slot_inst_encode, 0, 0 9195}; 9196 9197static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { 9198 Opcode_bgeui_Slot_inst_encode, 0, 0 9199}; 9200 9201static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { 9202 Opcode_bltui_Slot_inst_encode, 0, 0 9203}; 9204 9205static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { 9206 Opcode_beq_Slot_inst_encode, 0, 0 9207}; 9208 9209static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { 9210 Opcode_bne_Slot_inst_encode, 0, 0 9211}; 9212 9213static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { 9214 Opcode_bge_Slot_inst_encode, 0, 0 9215}; 9216 9217static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { 9218 Opcode_blt_Slot_inst_encode, 0, 0 9219}; 9220 9221static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { 9222 Opcode_bgeu_Slot_inst_encode, 0, 0 9223}; 9224 9225static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { 9226 Opcode_bltu_Slot_inst_encode, 0, 0 9227}; 9228 9229static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { 9230 Opcode_bany_Slot_inst_encode, 0, 0 9231}; 9232 9233static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { 9234 Opcode_bnone_Slot_inst_encode, 0, 0 9235}; 9236 9237static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { 9238 Opcode_ball_Slot_inst_encode, 0, 0 9239}; 9240 9241static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { 9242 Opcode_bnall_Slot_inst_encode, 0, 0 9243}; 9244 9245static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { 9246 Opcode_bbc_Slot_inst_encode, 0, 0 9247}; 9248 9249static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { 9250 Opcode_bbs_Slot_inst_encode, 0, 0 9251}; 9252 9253static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { 9254 Opcode_beqz_Slot_inst_encode, 0, 0 9255}; 9256 9257static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { 9258 Opcode_bnez_Slot_inst_encode, 0, 0 9259}; 9260 9261static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { 9262 Opcode_bgez_Slot_inst_encode, 0, 0 9263}; 9264 9265static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { 9266 Opcode_bltz_Slot_inst_encode, 0, 0 9267}; 9268 9269static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { 9270 Opcode_call0_Slot_inst_encode, 0, 0 9271}; 9272 9273static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { 9274 Opcode_callx0_Slot_inst_encode, 0, 0 9275}; 9276 9277static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { 9278 Opcode_extui_Slot_inst_encode, 0, 0 9279}; 9280 9281static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { 9282 Opcode_ill_Slot_inst_encode, 0, 0 9283}; 9284 9285static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { 9286 Opcode_j_Slot_inst_encode, 0, 0 9287}; 9288 9289static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { 9290 Opcode_jx_Slot_inst_encode, 0, 0 9291}; 9292 9293static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { 9294 Opcode_l16ui_Slot_inst_encode, 0, 0 9295}; 9296 9297static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { 9298 Opcode_l16si_Slot_inst_encode, 0, 0 9299}; 9300 9301static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { 9302 Opcode_l32i_Slot_inst_encode, 0, 0 9303}; 9304 9305static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { 9306 Opcode_l32r_Slot_inst_encode, 0, 0 9307}; 9308 9309static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { 9310 Opcode_l8ui_Slot_inst_encode, 0, 0 9311}; 9312 9313static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { 9314 Opcode_loop_Slot_inst_encode, 0, 0 9315}; 9316 9317static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { 9318 Opcode_loopnez_Slot_inst_encode, 0, 0 9319}; 9320 9321static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { 9322 Opcode_loopgtz_Slot_inst_encode, 0, 0 9323}; 9324 9325static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { 9326 Opcode_movi_Slot_inst_encode, 0, 0 9327}; 9328 9329static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { 9330 Opcode_moveqz_Slot_inst_encode, 0, 0 9331}; 9332 9333static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { 9334 Opcode_movnez_Slot_inst_encode, 0, 0 9335}; 9336 9337static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { 9338 Opcode_movltz_Slot_inst_encode, 0, 0 9339}; 9340 9341static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { 9342 Opcode_movgez_Slot_inst_encode, 0, 0 9343}; 9344 9345static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { 9346 Opcode_neg_Slot_inst_encode, 0, 0 9347}; 9348 9349static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { 9350 Opcode_abs_Slot_inst_encode, 0, 0 9351}; 9352 9353static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { 9354 Opcode_nop_Slot_inst_encode, 0, 0 9355}; 9356 9357static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { 9358 Opcode_ret_Slot_inst_encode, 0, 0 9359}; 9360 9361static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { 9362 Opcode_s16i_Slot_inst_encode, 0, 0 9363}; 9364 9365static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { 9366 Opcode_s32i_Slot_inst_encode, 0, 0 9367}; 9368 9369static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { 9370 Opcode_s8i_Slot_inst_encode, 0, 0 9371}; 9372 9373static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { 9374 Opcode_ssr_Slot_inst_encode, 0, 0 9375}; 9376 9377static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { 9378 Opcode_ssl_Slot_inst_encode, 0, 0 9379}; 9380 9381static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { 9382 Opcode_ssa8l_Slot_inst_encode, 0, 0 9383}; 9384 9385static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { 9386 Opcode_ssa8b_Slot_inst_encode, 0, 0 9387}; 9388 9389static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { 9390 Opcode_ssai_Slot_inst_encode, 0, 0 9391}; 9392 9393static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { 9394 Opcode_sll_Slot_inst_encode, 0, 0 9395}; 9396 9397static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { 9398 Opcode_src_Slot_inst_encode, 0, 0 9399}; 9400 9401static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { 9402 Opcode_srl_Slot_inst_encode, 0, 0 9403}; 9404 9405static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { 9406 Opcode_sra_Slot_inst_encode, 0, 0 9407}; 9408 9409static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { 9410 Opcode_slli_Slot_inst_encode, 0, 0 9411}; 9412 9413static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { 9414 Opcode_srai_Slot_inst_encode, 0, 0 9415}; 9416 9417static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { 9418 Opcode_srli_Slot_inst_encode, 0, 0 9419}; 9420 9421static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { 9422 Opcode_memw_Slot_inst_encode, 0, 0 9423}; 9424 9425static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { 9426 Opcode_extw_Slot_inst_encode, 0, 0 9427}; 9428 9429static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { 9430 Opcode_isync_Slot_inst_encode, 0, 0 9431}; 9432 9433static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { 9434 Opcode_rsync_Slot_inst_encode, 0, 0 9435}; 9436 9437static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { 9438 Opcode_esync_Slot_inst_encode, 0, 0 9439}; 9440 9441static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { 9442 Opcode_dsync_Slot_inst_encode, 0, 0 9443}; 9444 9445static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { 9446 Opcode_rsil_Slot_inst_encode, 0, 0 9447}; 9448 9449static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { 9450 Opcode_rsr_lend_Slot_inst_encode, 0, 0 9451}; 9452 9453static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { 9454 Opcode_wsr_lend_Slot_inst_encode, 0, 0 9455}; 9456 9457static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { 9458 Opcode_xsr_lend_Slot_inst_encode, 0, 0 9459}; 9460 9461static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { 9462 Opcode_rsr_lcount_Slot_inst_encode, 0, 0 9463}; 9464 9465static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { 9466 Opcode_wsr_lcount_Slot_inst_encode, 0, 0 9467}; 9468 9469static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { 9470 Opcode_xsr_lcount_Slot_inst_encode, 0, 0 9471}; 9472 9473static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { 9474 Opcode_rsr_lbeg_Slot_inst_encode, 0, 0 9475}; 9476 9477static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { 9478 Opcode_wsr_lbeg_Slot_inst_encode, 0, 0 9479}; 9480 9481static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { 9482 Opcode_xsr_lbeg_Slot_inst_encode, 0, 0 9483}; 9484 9485static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { 9486 Opcode_rsr_sar_Slot_inst_encode, 0, 0 9487}; 9488 9489static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { 9490 Opcode_wsr_sar_Slot_inst_encode, 0, 0 9491}; 9492 9493static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { 9494 Opcode_xsr_sar_Slot_inst_encode, 0, 0 9495}; 9496 9497static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { 9498 Opcode_rsr_litbase_Slot_inst_encode, 0, 0 9499}; 9500 9501static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { 9502 Opcode_wsr_litbase_Slot_inst_encode, 0, 0 9503}; 9504 9505static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { 9506 Opcode_xsr_litbase_Slot_inst_encode, 0, 0 9507}; 9508 9509static xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = { 9510 Opcode_rsr_176_Slot_inst_encode, 0, 0 9511}; 9512 9513static xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = { 9514 Opcode_rsr_208_Slot_inst_encode, 0, 0 9515}; 9516 9517static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { 9518 Opcode_rsr_ps_Slot_inst_encode, 0, 0 9519}; 9520 9521static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { 9522 Opcode_wsr_ps_Slot_inst_encode, 0, 0 9523}; 9524 9525static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { 9526 Opcode_xsr_ps_Slot_inst_encode, 0, 0 9527}; 9528 9529static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { 9530 Opcode_rsr_epc1_Slot_inst_encode, 0, 0 9531}; 9532 9533static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { 9534 Opcode_wsr_epc1_Slot_inst_encode, 0, 0 9535}; 9536 9537static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { 9538 Opcode_xsr_epc1_Slot_inst_encode, 0, 0 9539}; 9540 9541static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { 9542 Opcode_rsr_excsave1_Slot_inst_encode, 0, 0 9543}; 9544 9545static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { 9546 Opcode_wsr_excsave1_Slot_inst_encode, 0, 0 9547}; 9548 9549static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { 9550 Opcode_xsr_excsave1_Slot_inst_encode, 0, 0 9551}; 9552 9553static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { 9554 Opcode_rsr_epc2_Slot_inst_encode, 0, 0 9555}; 9556 9557static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { 9558 Opcode_wsr_epc2_Slot_inst_encode, 0, 0 9559}; 9560 9561static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { 9562 Opcode_xsr_epc2_Slot_inst_encode, 0, 0 9563}; 9564 9565static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { 9566 Opcode_rsr_excsave2_Slot_inst_encode, 0, 0 9567}; 9568 9569static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { 9570 Opcode_wsr_excsave2_Slot_inst_encode, 0, 0 9571}; 9572 9573static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { 9574 Opcode_xsr_excsave2_Slot_inst_encode, 0, 0 9575}; 9576 9577static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { 9578 Opcode_rsr_epc3_Slot_inst_encode, 0, 0 9579}; 9580 9581static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { 9582 Opcode_wsr_epc3_Slot_inst_encode, 0, 0 9583}; 9584 9585static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { 9586 Opcode_xsr_epc3_Slot_inst_encode, 0, 0 9587}; 9588 9589static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { 9590 Opcode_rsr_excsave3_Slot_inst_encode, 0, 0 9591}; 9592 9593static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { 9594 Opcode_wsr_excsave3_Slot_inst_encode, 0, 0 9595}; 9596 9597static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { 9598 Opcode_xsr_excsave3_Slot_inst_encode, 0, 0 9599}; 9600 9601static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { 9602 Opcode_rsr_epc4_Slot_inst_encode, 0, 0 9603}; 9604 9605static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { 9606 Opcode_wsr_epc4_Slot_inst_encode, 0, 0 9607}; 9608 9609static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { 9610 Opcode_xsr_epc4_Slot_inst_encode, 0, 0 9611}; 9612 9613static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { 9614 Opcode_rsr_excsave4_Slot_inst_encode, 0, 0 9615}; 9616 9617static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { 9618 Opcode_wsr_excsave4_Slot_inst_encode, 0, 0 9619}; 9620 9621static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { 9622 Opcode_xsr_excsave4_Slot_inst_encode, 0, 0 9623}; 9624 9625static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { 9626 Opcode_rsr_epc5_Slot_inst_encode, 0, 0 9627}; 9628 9629static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { 9630 Opcode_wsr_epc5_Slot_inst_encode, 0, 0 9631}; 9632 9633static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { 9634 Opcode_xsr_epc5_Slot_inst_encode, 0, 0 9635}; 9636 9637static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { 9638 Opcode_rsr_excsave5_Slot_inst_encode, 0, 0 9639}; 9640 9641static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { 9642 Opcode_wsr_excsave5_Slot_inst_encode, 0, 0 9643}; 9644 9645static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { 9646 Opcode_xsr_excsave5_Slot_inst_encode, 0, 0 9647}; 9648 9649static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { 9650 Opcode_rsr_epc6_Slot_inst_encode, 0, 0 9651}; 9652 9653static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { 9654 Opcode_wsr_epc6_Slot_inst_encode, 0, 0 9655}; 9656 9657static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { 9658 Opcode_xsr_epc6_Slot_inst_encode, 0, 0 9659}; 9660 9661static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { 9662 Opcode_rsr_excsave6_Slot_inst_encode, 0, 0 9663}; 9664 9665static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { 9666 Opcode_wsr_excsave6_Slot_inst_encode, 0, 0 9667}; 9668 9669static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { 9670 Opcode_xsr_excsave6_Slot_inst_encode, 0, 0 9671}; 9672 9673static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = { 9674 Opcode_rsr_epc7_Slot_inst_encode, 0, 0 9675}; 9676 9677static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = { 9678 Opcode_wsr_epc7_Slot_inst_encode, 0, 0 9679}; 9680 9681static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = { 9682 Opcode_xsr_epc7_Slot_inst_encode, 0, 0 9683}; 9684 9685static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = { 9686 Opcode_rsr_excsave7_Slot_inst_encode, 0, 0 9687}; 9688 9689static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = { 9690 Opcode_wsr_excsave7_Slot_inst_encode, 0, 0 9691}; 9692 9693static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = { 9694 Opcode_xsr_excsave7_Slot_inst_encode, 0, 0 9695}; 9696 9697static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { 9698 Opcode_rsr_eps2_Slot_inst_encode, 0, 0 9699}; 9700 9701static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { 9702 Opcode_wsr_eps2_Slot_inst_encode, 0, 0 9703}; 9704 9705static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { 9706 Opcode_xsr_eps2_Slot_inst_encode, 0, 0 9707}; 9708 9709static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { 9710 Opcode_rsr_eps3_Slot_inst_encode, 0, 0 9711}; 9712 9713static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { 9714 Opcode_wsr_eps3_Slot_inst_encode, 0, 0 9715}; 9716 9717static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { 9718 Opcode_xsr_eps3_Slot_inst_encode, 0, 0 9719}; 9720 9721static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { 9722 Opcode_rsr_eps4_Slot_inst_encode, 0, 0 9723}; 9724 9725static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { 9726 Opcode_wsr_eps4_Slot_inst_encode, 0, 0 9727}; 9728 9729static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { 9730 Opcode_xsr_eps4_Slot_inst_encode, 0, 0 9731}; 9732 9733static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { 9734 Opcode_rsr_eps5_Slot_inst_encode, 0, 0 9735}; 9736 9737static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { 9738 Opcode_wsr_eps5_Slot_inst_encode, 0, 0 9739}; 9740 9741static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { 9742 Opcode_xsr_eps5_Slot_inst_encode, 0, 0 9743}; 9744 9745static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { 9746 Opcode_rsr_eps6_Slot_inst_encode, 0, 0 9747}; 9748 9749static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { 9750 Opcode_wsr_eps6_Slot_inst_encode, 0, 0 9751}; 9752 9753static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { 9754 Opcode_xsr_eps6_Slot_inst_encode, 0, 0 9755}; 9756 9757static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = { 9758 Opcode_rsr_eps7_Slot_inst_encode, 0, 0 9759}; 9760 9761static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = { 9762 Opcode_wsr_eps7_Slot_inst_encode, 0, 0 9763}; 9764 9765static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = { 9766 Opcode_xsr_eps7_Slot_inst_encode, 0, 0 9767}; 9768 9769static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { 9770 Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0 9771}; 9772 9773static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { 9774 Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0 9775}; 9776 9777static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { 9778 Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0 9779}; 9780 9781static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { 9782 Opcode_rsr_depc_Slot_inst_encode, 0, 0 9783}; 9784 9785static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { 9786 Opcode_wsr_depc_Slot_inst_encode, 0, 0 9787}; 9788 9789static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { 9790 Opcode_xsr_depc_Slot_inst_encode, 0, 0 9791}; 9792 9793static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { 9794 Opcode_rsr_exccause_Slot_inst_encode, 0, 0 9795}; 9796 9797static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { 9798 Opcode_wsr_exccause_Slot_inst_encode, 0, 0 9799}; 9800 9801static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { 9802 Opcode_xsr_exccause_Slot_inst_encode, 0, 0 9803}; 9804 9805static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { 9806 Opcode_rsr_misc0_Slot_inst_encode, 0, 0 9807}; 9808 9809static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { 9810 Opcode_wsr_misc0_Slot_inst_encode, 0, 0 9811}; 9812 9813static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { 9814 Opcode_xsr_misc0_Slot_inst_encode, 0, 0 9815}; 9816 9817static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { 9818 Opcode_rsr_misc1_Slot_inst_encode, 0, 0 9819}; 9820 9821static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { 9822 Opcode_wsr_misc1_Slot_inst_encode, 0, 0 9823}; 9824 9825static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { 9826 Opcode_xsr_misc1_Slot_inst_encode, 0, 0 9827}; 9828 9829static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { 9830 Opcode_rsr_prid_Slot_inst_encode, 0, 0 9831}; 9832 9833static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { 9834 Opcode_rsr_vecbase_Slot_inst_encode, 0, 0 9835}; 9836 9837static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { 9838 Opcode_wsr_vecbase_Slot_inst_encode, 0, 0 9839}; 9840 9841static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { 9842 Opcode_xsr_vecbase_Slot_inst_encode, 0, 0 9843}; 9844 9845static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = { 9846 Opcode_mul_aa_ll_Slot_inst_encode, 0, 0 9847}; 9848 9849static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = { 9850 Opcode_mul_aa_hl_Slot_inst_encode, 0, 0 9851}; 9852 9853static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = { 9854 Opcode_mul_aa_lh_Slot_inst_encode, 0, 0 9855}; 9856 9857static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = { 9858 Opcode_mul_aa_hh_Slot_inst_encode, 0, 0 9859}; 9860 9861static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = { 9862 Opcode_umul_aa_ll_Slot_inst_encode, 0, 0 9863}; 9864 9865static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = { 9866 Opcode_umul_aa_hl_Slot_inst_encode, 0, 0 9867}; 9868 9869static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = { 9870 Opcode_umul_aa_lh_Slot_inst_encode, 0, 0 9871}; 9872 9873static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = { 9874 Opcode_umul_aa_hh_Slot_inst_encode, 0, 0 9875}; 9876 9877static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = { 9878 Opcode_mul_ad_ll_Slot_inst_encode, 0, 0 9879}; 9880 9881static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = { 9882 Opcode_mul_ad_hl_Slot_inst_encode, 0, 0 9883}; 9884 9885static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = { 9886 Opcode_mul_ad_lh_Slot_inst_encode, 0, 0 9887}; 9888 9889static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = { 9890 Opcode_mul_ad_hh_Slot_inst_encode, 0, 0 9891}; 9892 9893static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = { 9894 Opcode_mul_da_ll_Slot_inst_encode, 0, 0 9895}; 9896 9897static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = { 9898 Opcode_mul_da_hl_Slot_inst_encode, 0, 0 9899}; 9900 9901static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = { 9902 Opcode_mul_da_lh_Slot_inst_encode, 0, 0 9903}; 9904 9905static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = { 9906 Opcode_mul_da_hh_Slot_inst_encode, 0, 0 9907}; 9908 9909static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = { 9910 Opcode_mul_dd_ll_Slot_inst_encode, 0, 0 9911}; 9912 9913static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = { 9914 Opcode_mul_dd_hl_Slot_inst_encode, 0, 0 9915}; 9916 9917static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = { 9918 Opcode_mul_dd_lh_Slot_inst_encode, 0, 0 9919}; 9920 9921static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = { 9922 Opcode_mul_dd_hh_Slot_inst_encode, 0, 0 9923}; 9924 9925static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = { 9926 Opcode_mula_aa_ll_Slot_inst_encode, 0, 0 9927}; 9928 9929static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = { 9930 Opcode_mula_aa_hl_Slot_inst_encode, 0, 0 9931}; 9932 9933static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = { 9934 Opcode_mula_aa_lh_Slot_inst_encode, 0, 0 9935}; 9936 9937static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = { 9938 Opcode_mula_aa_hh_Slot_inst_encode, 0, 0 9939}; 9940 9941static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = { 9942 Opcode_muls_aa_ll_Slot_inst_encode, 0, 0 9943}; 9944 9945static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = { 9946 Opcode_muls_aa_hl_Slot_inst_encode, 0, 0 9947}; 9948 9949static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = { 9950 Opcode_muls_aa_lh_Slot_inst_encode, 0, 0 9951}; 9952 9953static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = { 9954 Opcode_muls_aa_hh_Slot_inst_encode, 0, 0 9955}; 9956 9957static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = { 9958 Opcode_mula_ad_ll_Slot_inst_encode, 0, 0 9959}; 9960 9961static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = { 9962 Opcode_mula_ad_hl_Slot_inst_encode, 0, 0 9963}; 9964 9965static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = { 9966 Opcode_mula_ad_lh_Slot_inst_encode, 0, 0 9967}; 9968 9969static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = { 9970 Opcode_mula_ad_hh_Slot_inst_encode, 0, 0 9971}; 9972 9973static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = { 9974 Opcode_muls_ad_ll_Slot_inst_encode, 0, 0 9975}; 9976 9977static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = { 9978 Opcode_muls_ad_hl_Slot_inst_encode, 0, 0 9979}; 9980 9981static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = { 9982 Opcode_muls_ad_lh_Slot_inst_encode, 0, 0 9983}; 9984 9985static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = { 9986 Opcode_muls_ad_hh_Slot_inst_encode, 0, 0 9987}; 9988 9989static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = { 9990 Opcode_mula_da_ll_Slot_inst_encode, 0, 0 9991}; 9992 9993static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = { 9994 Opcode_mula_da_hl_Slot_inst_encode, 0, 0 9995}; 9996 9997static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = { 9998 Opcode_mula_da_lh_Slot_inst_encode, 0, 0 9999}; 10000 10001static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = { 10002 Opcode_mula_da_hh_Slot_inst_encode, 0, 0 10003}; 10004 10005static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = { 10006 Opcode_muls_da_ll_Slot_inst_encode, 0, 0 10007}; 10008 10009static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = { 10010 Opcode_muls_da_hl_Slot_inst_encode, 0, 0 10011}; 10012 10013static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = { 10014 Opcode_muls_da_lh_Slot_inst_encode, 0, 0 10015}; 10016 10017static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = { 10018 Opcode_muls_da_hh_Slot_inst_encode, 0, 0 10019}; 10020 10021static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = { 10022 Opcode_mula_dd_ll_Slot_inst_encode, 0, 0 10023}; 10024 10025static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = { 10026 Opcode_mula_dd_hl_Slot_inst_encode, 0, 0 10027}; 10028 10029static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = { 10030 Opcode_mula_dd_lh_Slot_inst_encode, 0, 0 10031}; 10032 10033static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = { 10034 Opcode_mula_dd_hh_Slot_inst_encode, 0, 0 10035}; 10036 10037static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = { 10038 Opcode_muls_dd_ll_Slot_inst_encode, 0, 0 10039}; 10040 10041static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = { 10042 Opcode_muls_dd_hl_Slot_inst_encode, 0, 0 10043}; 10044 10045static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = { 10046 Opcode_muls_dd_lh_Slot_inst_encode, 0, 0 10047}; 10048 10049static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = { 10050 Opcode_muls_dd_hh_Slot_inst_encode, 0, 0 10051}; 10052 10053static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = { 10054 Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0 10055}; 10056 10057static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = { 10058 Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0 10059}; 10060 10061static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = { 10062 Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0 10063}; 10064 10065static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = { 10066 Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0 10067}; 10068 10069static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = { 10070 Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0 10071}; 10072 10073static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = { 10074 Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0 10075}; 10076 10077static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = { 10078 Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0 10079}; 10080 10081static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = { 10082 Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0 10083}; 10084 10085static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = { 10086 Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0 10087}; 10088 10089static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = { 10090 Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0 10091}; 10092 10093static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = { 10094 Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0 10095}; 10096 10097static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = { 10098 Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0 10099}; 10100 10101static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = { 10102 Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0 10103}; 10104 10105static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = { 10106 Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0 10107}; 10108 10109static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = { 10110 Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0 10111}; 10112 10113static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = { 10114 Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0 10115}; 10116 10117static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = { 10118 Opcode_lddec_Slot_inst_encode, 0, 0 10119}; 10120 10121static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = { 10122 Opcode_ldinc_Slot_inst_encode, 0, 0 10123}; 10124 10125static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { 10126 Opcode_mul16u_Slot_inst_encode, 0, 0 10127}; 10128 10129static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { 10130 Opcode_mul16s_Slot_inst_encode, 0, 0 10131}; 10132 10133static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = { 10134 Opcode_rsr_m0_Slot_inst_encode, 0, 0 10135}; 10136 10137static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = { 10138 Opcode_wsr_m0_Slot_inst_encode, 0, 0 10139}; 10140 10141static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = { 10142 Opcode_xsr_m0_Slot_inst_encode, 0, 0 10143}; 10144 10145static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = { 10146 Opcode_rsr_m1_Slot_inst_encode, 0, 0 10147}; 10148 10149static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = { 10150 Opcode_wsr_m1_Slot_inst_encode, 0, 0 10151}; 10152 10153static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = { 10154 Opcode_xsr_m1_Slot_inst_encode, 0, 0 10155}; 10156 10157static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = { 10158 Opcode_rsr_m2_Slot_inst_encode, 0, 0 10159}; 10160 10161static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = { 10162 Opcode_wsr_m2_Slot_inst_encode, 0, 0 10163}; 10164 10165static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = { 10166 Opcode_xsr_m2_Slot_inst_encode, 0, 0 10167}; 10168 10169static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = { 10170 Opcode_rsr_m3_Slot_inst_encode, 0, 0 10171}; 10172 10173static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = { 10174 Opcode_wsr_m3_Slot_inst_encode, 0, 0 10175}; 10176 10177static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = { 10178 Opcode_xsr_m3_Slot_inst_encode, 0, 0 10179}; 10180 10181static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = { 10182 Opcode_rsr_acclo_Slot_inst_encode, 0, 0 10183}; 10184 10185static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = { 10186 Opcode_wsr_acclo_Slot_inst_encode, 0, 0 10187}; 10188 10189static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = { 10190 Opcode_xsr_acclo_Slot_inst_encode, 0, 0 10191}; 10192 10193static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = { 10194 Opcode_rsr_acchi_Slot_inst_encode, 0, 0 10195}; 10196 10197static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = { 10198 Opcode_wsr_acchi_Slot_inst_encode, 0, 0 10199}; 10200 10201static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = { 10202 Opcode_xsr_acchi_Slot_inst_encode, 0, 0 10203}; 10204 10205static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { 10206 Opcode_rfi_Slot_inst_encode, 0, 0 10207}; 10208 10209static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { 10210 Opcode_waiti_Slot_inst_encode, 0, 0 10211}; 10212 10213static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { 10214 Opcode_rsr_interrupt_Slot_inst_encode, 0, 0 10215}; 10216 10217static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { 10218 Opcode_wsr_intset_Slot_inst_encode, 0, 0 10219}; 10220 10221static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { 10222 Opcode_wsr_intclear_Slot_inst_encode, 0, 0 10223}; 10224 10225static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { 10226 Opcode_rsr_intenable_Slot_inst_encode, 0, 0 10227}; 10228 10229static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { 10230 Opcode_wsr_intenable_Slot_inst_encode, 0, 0 10231}; 10232 10233static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { 10234 Opcode_xsr_intenable_Slot_inst_encode, 0, 0 10235}; 10236 10237static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { 10238 Opcode_break_Slot_inst_encode, 0, 0 10239}; 10240 10241static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { 10242 0, 0, Opcode_break_n_Slot_inst16b_encode 10243}; 10244 10245static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { 10246 Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0 10247}; 10248 10249static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { 10250 Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0 10251}; 10252 10253static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { 10254 Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0 10255}; 10256 10257static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { 10258 Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0 10259}; 10260 10261static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { 10262 Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0 10263}; 10264 10265static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { 10266 Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0 10267}; 10268 10269static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { 10270 Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0 10271}; 10272 10273static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { 10274 Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0 10275}; 10276 10277static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { 10278 Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0 10279}; 10280 10281static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { 10282 Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0 10283}; 10284 10285static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { 10286 Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0 10287}; 10288 10289static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { 10290 Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0 10291}; 10292 10293static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { 10294 Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0 10295}; 10296 10297static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { 10298 Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0 10299}; 10300 10301static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { 10302 Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0 10303}; 10304 10305static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { 10306 Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0 10307}; 10308 10309static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { 10310 Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0 10311}; 10312 10313static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { 10314 Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0 10315}; 10316 10317static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { 10318 Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0 10319}; 10320 10321static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { 10322 Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0 10323}; 10324 10325static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { 10326 Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0 10327}; 10328 10329static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { 10330 Opcode_rsr_debugcause_Slot_inst_encode, 0, 0 10331}; 10332 10333static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { 10334 Opcode_wsr_debugcause_Slot_inst_encode, 0, 0 10335}; 10336 10337static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { 10338 Opcode_xsr_debugcause_Slot_inst_encode, 0, 0 10339}; 10340 10341static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { 10342 Opcode_rsr_icount_Slot_inst_encode, 0, 0 10343}; 10344 10345static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { 10346 Opcode_wsr_icount_Slot_inst_encode, 0, 0 10347}; 10348 10349static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { 10350 Opcode_xsr_icount_Slot_inst_encode, 0, 0 10351}; 10352 10353static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { 10354 Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0 10355}; 10356 10357static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { 10358 Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0 10359}; 10360 10361static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { 10362 Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0 10363}; 10364 10365static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { 10366 Opcode_rsr_ddr_Slot_inst_encode, 0, 0 10367}; 10368 10369static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { 10370 Opcode_wsr_ddr_Slot_inst_encode, 0, 0 10371}; 10372 10373static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { 10374 Opcode_xsr_ddr_Slot_inst_encode, 0, 0 10375}; 10376 10377static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { 10378 Opcode_rfdo_Slot_inst_encode, 0, 0 10379}; 10380 10381static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { 10382 Opcode_rfdd_Slot_inst_encode, 0, 0 10383}; 10384 10385static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { 10386 Opcode_wsr_mmid_Slot_inst_encode, 0, 0 10387}; 10388 10389static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { 10390 Opcode_rsr_ccount_Slot_inst_encode, 0, 0 10391}; 10392 10393static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { 10394 Opcode_wsr_ccount_Slot_inst_encode, 0, 0 10395}; 10396 10397static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { 10398 Opcode_xsr_ccount_Slot_inst_encode, 0, 0 10399}; 10400 10401static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { 10402 Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0 10403}; 10404 10405static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { 10406 Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0 10407}; 10408 10409static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { 10410 Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0 10411}; 10412 10413static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { 10414 Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0 10415}; 10416 10417static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { 10418 Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0 10419}; 10420 10421static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { 10422 Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0 10423}; 10424 10425static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { 10426 Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0 10427}; 10428 10429static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { 10430 Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0 10431}; 10432 10433static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { 10434 Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0 10435}; 10436 10437static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { 10438 Opcode_ipf_Slot_inst_encode, 0, 0 10439}; 10440 10441static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { 10442 Opcode_ihi_Slot_inst_encode, 0, 0 10443}; 10444 10445static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { 10446 Opcode_ipfl_Slot_inst_encode, 0, 0 10447}; 10448 10449static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { 10450 Opcode_ihu_Slot_inst_encode, 0, 0 10451}; 10452 10453static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { 10454 Opcode_iiu_Slot_inst_encode, 0, 0 10455}; 10456 10457static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { 10458 Opcode_iii_Slot_inst_encode, 0, 0 10459}; 10460 10461static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { 10462 Opcode_lict_Slot_inst_encode, 0, 0 10463}; 10464 10465static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { 10466 Opcode_licw_Slot_inst_encode, 0, 0 10467}; 10468 10469static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { 10470 Opcode_sict_Slot_inst_encode, 0, 0 10471}; 10472 10473static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { 10474 Opcode_sicw_Slot_inst_encode, 0, 0 10475}; 10476 10477static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { 10478 Opcode_dhwb_Slot_inst_encode, 0, 0 10479}; 10480 10481static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { 10482 Opcode_dhwbi_Slot_inst_encode, 0, 0 10483}; 10484 10485static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { 10486 Opcode_diwb_Slot_inst_encode, 0, 0 10487}; 10488 10489static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { 10490 Opcode_diwbi_Slot_inst_encode, 0, 0 10491}; 10492 10493static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { 10494 Opcode_dhi_Slot_inst_encode, 0, 0 10495}; 10496 10497static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { 10498 Opcode_dii_Slot_inst_encode, 0, 0 10499}; 10500 10501static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { 10502 Opcode_dpfr_Slot_inst_encode, 0, 0 10503}; 10504 10505static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { 10506 Opcode_dpfw_Slot_inst_encode, 0, 0 10507}; 10508 10509static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { 10510 Opcode_dpfro_Slot_inst_encode, 0, 0 10511}; 10512 10513static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { 10514 Opcode_dpfwo_Slot_inst_encode, 0, 0 10515}; 10516 10517static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { 10518 Opcode_dpfl_Slot_inst_encode, 0, 0 10519}; 10520 10521static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { 10522 Opcode_dhu_Slot_inst_encode, 0, 0 10523}; 10524 10525static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { 10526 Opcode_diu_Slot_inst_encode, 0, 0 10527}; 10528 10529static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { 10530 Opcode_sdct_Slot_inst_encode, 0, 0 10531}; 10532 10533static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { 10534 Opcode_ldct_Slot_inst_encode, 0, 0 10535}; 10536 10537static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { 10538 Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0 10539}; 10540 10541static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { 10542 Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0 10543}; 10544 10545static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { 10546 Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0 10547}; 10548 10549static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { 10550 Opcode_rsr_rasid_Slot_inst_encode, 0, 0 10551}; 10552 10553static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { 10554 Opcode_wsr_rasid_Slot_inst_encode, 0, 0 10555}; 10556 10557static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { 10558 Opcode_xsr_rasid_Slot_inst_encode, 0, 0 10559}; 10560 10561static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { 10562 Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0 10563}; 10564 10565static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { 10566 Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0 10567}; 10568 10569static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { 10570 Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0 10571}; 10572 10573static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { 10574 Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0 10575}; 10576 10577static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { 10578 Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0 10579}; 10580 10581static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { 10582 Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0 10583}; 10584 10585static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { 10586 Opcode_idtlb_Slot_inst_encode, 0, 0 10587}; 10588 10589static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { 10590 Opcode_pdtlb_Slot_inst_encode, 0, 0 10591}; 10592 10593static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { 10594 Opcode_rdtlb0_Slot_inst_encode, 0, 0 10595}; 10596 10597static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { 10598 Opcode_rdtlb1_Slot_inst_encode, 0, 0 10599}; 10600 10601static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { 10602 Opcode_wdtlb_Slot_inst_encode, 0, 0 10603}; 10604 10605static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { 10606 Opcode_iitlb_Slot_inst_encode, 0, 0 10607}; 10608 10609static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { 10610 Opcode_pitlb_Slot_inst_encode, 0, 0 10611}; 10612 10613static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { 10614 Opcode_ritlb0_Slot_inst_encode, 0, 0 10615}; 10616 10617static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { 10618 Opcode_ritlb1_Slot_inst_encode, 0, 0 10619}; 10620 10621static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { 10622 Opcode_witlb_Slot_inst_encode, 0, 0 10623}; 10624 10625static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { 10626 Opcode_ldpte_Slot_inst_encode, 0, 0 10627}; 10628 10629static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { 10630 Opcode_hwwitlba_Slot_inst_encode, 0, 0 10631}; 10632 10633static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { 10634 Opcode_hwwdtlba_Slot_inst_encode, 0, 0 10635}; 10636 10637static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { 10638 Opcode_rsr_cpenable_Slot_inst_encode, 0, 0 10639}; 10640 10641static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { 10642 Opcode_wsr_cpenable_Slot_inst_encode, 0, 0 10643}; 10644 10645static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { 10646 Opcode_xsr_cpenable_Slot_inst_encode, 0, 0 10647}; 10648 10649static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { 10650 Opcode_clamps_Slot_inst_encode, 0, 0 10651}; 10652 10653static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { 10654 Opcode_min_Slot_inst_encode, 0, 0 10655}; 10656 10657static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { 10658 Opcode_max_Slot_inst_encode, 0, 0 10659}; 10660 10661static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { 10662 Opcode_minu_Slot_inst_encode, 0, 0 10663}; 10664 10665static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { 10666 Opcode_maxu_Slot_inst_encode, 0, 0 10667}; 10668 10669static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { 10670 Opcode_nsa_Slot_inst_encode, 0, 0 10671}; 10672 10673static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { 10674 Opcode_nsau_Slot_inst_encode, 0, 0 10675}; 10676 10677static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { 10678 Opcode_sext_Slot_inst_encode, 0, 0 10679}; 10680 10681static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { 10682 Opcode_l32ai_Slot_inst_encode, 0, 0 10683}; 10684 10685static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { 10686 Opcode_s32ri_Slot_inst_encode, 0, 0 10687}; 10688 10689static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { 10690 Opcode_s32c1i_Slot_inst_encode, 0, 0 10691}; 10692 10693static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { 10694 Opcode_rsr_scompare1_Slot_inst_encode, 0, 0 10695}; 10696 10697static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { 10698 Opcode_wsr_scompare1_Slot_inst_encode, 0, 0 10699}; 10700 10701static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { 10702 Opcode_xsr_scompare1_Slot_inst_encode, 0, 0 10703}; 10704 10705static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { 10706 Opcode_quou_Slot_inst_encode, 0, 0 10707}; 10708 10709static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { 10710 Opcode_quos_Slot_inst_encode, 0, 0 10711}; 10712 10713static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { 10714 Opcode_remu_Slot_inst_encode, 0, 0 10715}; 10716 10717static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { 10718 Opcode_rems_Slot_inst_encode, 0, 0 10719}; 10720 10721static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { 10722 Opcode_mull_Slot_inst_encode, 0, 0 10723}; 10724 10725static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = { 10726 Opcode_rur_expstate_Slot_inst_encode, 0, 0 10727}; 10728 10729static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = { 10730 Opcode_wur_expstate_Slot_inst_encode, 0, 0 10731}; 10732 10733static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = { 10734 Opcode_read_impwire_Slot_inst_encode, 0, 0 10735}; 10736 10737static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = { 10738 Opcode_setb_expstate_Slot_inst_encode, 0, 0 10739}; 10740 10741static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = { 10742 Opcode_clrb_expstate_Slot_inst_encode, 0, 0 10743}; 10744 10745static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = { 10746 Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0 10747}; 10748 10749 10750/* Opcode table. */ 10751 10752static xtensa_opcode_internal opcodes[] = { 10753 { "excw", 0 /* xt_iclass_excw */, 10754 0, 10755 Opcode_excw_encode_fns, 0, 0 }, 10756 { "rfe", 1 /* xt_iclass_rfe */, 10757 XTENSA_OPCODE_IS_JUMP, 10758 Opcode_rfe_encode_fns, 0, 0 }, 10759 { "rfde", 2 /* xt_iclass_rfde */, 10760 XTENSA_OPCODE_IS_JUMP, 10761 Opcode_rfde_encode_fns, 0, 0 }, 10762 { "syscall", 3 /* xt_iclass_syscall */, 10763 0, 10764 Opcode_syscall_encode_fns, 0, 0 }, 10765 { "simcall", 4 /* xt_iclass_simcall */, 10766 0, 10767 Opcode_simcall_encode_fns, 0, 0 }, 10768 { "call12", 5 /* xt_iclass_call12 */, 10769 XTENSA_OPCODE_IS_CALL, 10770 Opcode_call12_encode_fns, 0, 0 }, 10771 { "call8", 6 /* xt_iclass_call8 */, 10772 XTENSA_OPCODE_IS_CALL, 10773 Opcode_call8_encode_fns, 0, 0 }, 10774 { "call4", 7 /* xt_iclass_call4 */, 10775 XTENSA_OPCODE_IS_CALL, 10776 Opcode_call4_encode_fns, 0, 0 }, 10777 { "callx12", 8 /* xt_iclass_callx12 */, 10778 XTENSA_OPCODE_IS_CALL, 10779 Opcode_callx12_encode_fns, 0, 0 }, 10780 { "callx8", 9 /* xt_iclass_callx8 */, 10781 XTENSA_OPCODE_IS_CALL, 10782 Opcode_callx8_encode_fns, 0, 0 }, 10783 { "callx4", 10 /* xt_iclass_callx4 */, 10784 XTENSA_OPCODE_IS_CALL, 10785 Opcode_callx4_encode_fns, 0, 0 }, 10786 { "entry", 11 /* xt_iclass_entry */, 10787 0, 10788 Opcode_entry_encode_fns, 0, 0 }, 10789 { "movsp", 12 /* xt_iclass_movsp */, 10790 0, 10791 Opcode_movsp_encode_fns, 0, 0 }, 10792 { "rotw", 13 /* xt_iclass_rotw */, 10793 0, 10794 Opcode_rotw_encode_fns, 0, 0 }, 10795 { "retw", 14 /* xt_iclass_retw */, 10796 XTENSA_OPCODE_IS_JUMP, 10797 Opcode_retw_encode_fns, 0, 0 }, 10798 { "retw.n", 14 /* xt_iclass_retw */, 10799 XTENSA_OPCODE_IS_JUMP, 10800 Opcode_retw_n_encode_fns, 0, 0 }, 10801 { "rfwo", 15 /* xt_iclass_rfwou */, 10802 XTENSA_OPCODE_IS_JUMP, 10803 Opcode_rfwo_encode_fns, 0, 0 }, 10804 { "rfwu", 15 /* xt_iclass_rfwou */, 10805 XTENSA_OPCODE_IS_JUMP, 10806 Opcode_rfwu_encode_fns, 0, 0 }, 10807 { "l32e", 16 /* xt_iclass_l32e */, 10808 0, 10809 Opcode_l32e_encode_fns, 0, 0 }, 10810 { "s32e", 17 /* xt_iclass_s32e */, 10811 0, 10812 Opcode_s32e_encode_fns, 0, 0 }, 10813 { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */, 10814 0, 10815 Opcode_rsr_windowbase_encode_fns, 0, 0 }, 10816 { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */, 10817 0, 10818 Opcode_wsr_windowbase_encode_fns, 0, 0 }, 10819 { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */, 10820 0, 10821 Opcode_xsr_windowbase_encode_fns, 0, 0 }, 10822 { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */, 10823 0, 10824 Opcode_rsr_windowstart_encode_fns, 0, 0 }, 10825 { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */, 10826 0, 10827 Opcode_wsr_windowstart_encode_fns, 0, 0 }, 10828 { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */, 10829 0, 10830 Opcode_xsr_windowstart_encode_fns, 0, 0 }, 10831 { "add.n", 24 /* xt_iclass_add.n */, 10832 0, 10833 Opcode_add_n_encode_fns, 0, 0 }, 10834 { "addi.n", 25 /* xt_iclass_addi.n */, 10835 0, 10836 Opcode_addi_n_encode_fns, 0, 0 }, 10837 { "beqz.n", 26 /* xt_iclass_bz6 */, 10838 XTENSA_OPCODE_IS_BRANCH, 10839 Opcode_beqz_n_encode_fns, 0, 0 }, 10840 { "bnez.n", 26 /* xt_iclass_bz6 */, 10841 XTENSA_OPCODE_IS_BRANCH, 10842 Opcode_bnez_n_encode_fns, 0, 0 }, 10843 { "ill.n", 27 /* xt_iclass_ill.n */, 10844 0, 10845 Opcode_ill_n_encode_fns, 0, 0 }, 10846 { "l32i.n", 28 /* xt_iclass_loadi4 */, 10847 0, 10848 Opcode_l32i_n_encode_fns, 0, 0 }, 10849 { "mov.n", 29 /* xt_iclass_mov.n */, 10850 0, 10851 Opcode_mov_n_encode_fns, 0, 0 }, 10852 { "movi.n", 30 /* xt_iclass_movi.n */, 10853 0, 10854 Opcode_movi_n_encode_fns, 0, 0 }, 10855 { "nop.n", 31 /* xt_iclass_nopn */, 10856 0, 10857 Opcode_nop_n_encode_fns, 0, 0 }, 10858 { "ret.n", 32 /* xt_iclass_retn */, 10859 XTENSA_OPCODE_IS_JUMP, 10860 Opcode_ret_n_encode_fns, 0, 0 }, 10861 { "s32i.n", 33 /* xt_iclass_storei4 */, 10862 0, 10863 Opcode_s32i_n_encode_fns, 0, 0 }, 10864 { "rur.threadptr", 34 /* rur_threadptr */, 10865 0, 10866 Opcode_rur_threadptr_encode_fns, 0, 0 }, 10867 { "wur.threadptr", 35 /* wur_threadptr */, 10868 0, 10869 Opcode_wur_threadptr_encode_fns, 0, 0 }, 10870 { "addi", 36 /* xt_iclass_addi */, 10871 0, 10872 Opcode_addi_encode_fns, 0, 0 }, 10873 { "addmi", 37 /* xt_iclass_addmi */, 10874 0, 10875 Opcode_addmi_encode_fns, 0, 0 }, 10876 { "add", 38 /* xt_iclass_addsub */, 10877 0, 10878 Opcode_add_encode_fns, 0, 0 }, 10879 { "sub", 38 /* xt_iclass_addsub */, 10880 0, 10881 Opcode_sub_encode_fns, 0, 0 }, 10882 { "addx2", 38 /* xt_iclass_addsub */, 10883 0, 10884 Opcode_addx2_encode_fns, 0, 0 }, 10885 { "addx4", 38 /* xt_iclass_addsub */, 10886 0, 10887 Opcode_addx4_encode_fns, 0, 0 }, 10888 { "addx8", 38 /* xt_iclass_addsub */, 10889 0, 10890 Opcode_addx8_encode_fns, 0, 0 }, 10891 { "subx2", 38 /* xt_iclass_addsub */, 10892 0, 10893 Opcode_subx2_encode_fns, 0, 0 }, 10894 { "subx4", 38 /* xt_iclass_addsub */, 10895 0, 10896 Opcode_subx4_encode_fns, 0, 0 }, 10897 { "subx8", 38 /* xt_iclass_addsub */, 10898 0, 10899 Opcode_subx8_encode_fns, 0, 0 }, 10900 { "and", 39 /* xt_iclass_bit */, 10901 0, 10902 Opcode_and_encode_fns, 0, 0 }, 10903 { "or", 39 /* xt_iclass_bit */, 10904 0, 10905 Opcode_or_encode_fns, 0, 0 }, 10906 { "xor", 39 /* xt_iclass_bit */, 10907 0, 10908 Opcode_xor_encode_fns, 0, 0 }, 10909 { "beqi", 40 /* xt_iclass_bsi8 */, 10910 XTENSA_OPCODE_IS_BRANCH, 10911 Opcode_beqi_encode_fns, 0, 0 }, 10912 { "bnei", 40 /* xt_iclass_bsi8 */, 10913 XTENSA_OPCODE_IS_BRANCH, 10914 Opcode_bnei_encode_fns, 0, 0 }, 10915 { "bgei", 40 /* xt_iclass_bsi8 */, 10916 XTENSA_OPCODE_IS_BRANCH, 10917 Opcode_bgei_encode_fns, 0, 0 }, 10918 { "blti", 40 /* xt_iclass_bsi8 */, 10919 XTENSA_OPCODE_IS_BRANCH, 10920 Opcode_blti_encode_fns, 0, 0 }, 10921 { "bbci", 41 /* xt_iclass_bsi8b */, 10922 XTENSA_OPCODE_IS_BRANCH, 10923 Opcode_bbci_encode_fns, 0, 0 }, 10924 { "bbsi", 41 /* xt_iclass_bsi8b */, 10925 XTENSA_OPCODE_IS_BRANCH, 10926 Opcode_bbsi_encode_fns, 0, 0 }, 10927 { "bgeui", 42 /* xt_iclass_bsi8u */, 10928 XTENSA_OPCODE_IS_BRANCH, 10929 Opcode_bgeui_encode_fns, 0, 0 }, 10930 { "bltui", 42 /* xt_iclass_bsi8u */, 10931 XTENSA_OPCODE_IS_BRANCH, 10932 Opcode_bltui_encode_fns, 0, 0 }, 10933 { "beq", 43 /* xt_iclass_bst8 */, 10934 XTENSA_OPCODE_IS_BRANCH, 10935 Opcode_beq_encode_fns, 0, 0 }, 10936 { "bne", 43 /* xt_iclass_bst8 */, 10937 XTENSA_OPCODE_IS_BRANCH, 10938 Opcode_bne_encode_fns, 0, 0 }, 10939 { "bge", 43 /* xt_iclass_bst8 */, 10940 XTENSA_OPCODE_IS_BRANCH, 10941 Opcode_bge_encode_fns, 0, 0 }, 10942 { "blt", 43 /* xt_iclass_bst8 */, 10943 XTENSA_OPCODE_IS_BRANCH, 10944 Opcode_blt_encode_fns, 0, 0 }, 10945 { "bgeu", 43 /* xt_iclass_bst8 */, 10946 XTENSA_OPCODE_IS_BRANCH, 10947 Opcode_bgeu_encode_fns, 0, 0 }, 10948 { "bltu", 43 /* xt_iclass_bst8 */, 10949 XTENSA_OPCODE_IS_BRANCH, 10950 Opcode_bltu_encode_fns, 0, 0 }, 10951 { "bany", 43 /* xt_iclass_bst8 */, 10952 XTENSA_OPCODE_IS_BRANCH, 10953 Opcode_bany_encode_fns, 0, 0 }, 10954 { "bnone", 43 /* xt_iclass_bst8 */, 10955 XTENSA_OPCODE_IS_BRANCH, 10956 Opcode_bnone_encode_fns, 0, 0 }, 10957 { "ball", 43 /* xt_iclass_bst8 */, 10958 XTENSA_OPCODE_IS_BRANCH, 10959 Opcode_ball_encode_fns, 0, 0 }, 10960 { "bnall", 43 /* xt_iclass_bst8 */, 10961 XTENSA_OPCODE_IS_BRANCH, 10962 Opcode_bnall_encode_fns, 0, 0 }, 10963 { "bbc", 43 /* xt_iclass_bst8 */, 10964 XTENSA_OPCODE_IS_BRANCH, 10965 Opcode_bbc_encode_fns, 0, 0 }, 10966 { "bbs", 43 /* xt_iclass_bst8 */, 10967 XTENSA_OPCODE_IS_BRANCH, 10968 Opcode_bbs_encode_fns, 0, 0 }, 10969 { "beqz", 44 /* xt_iclass_bsz12 */, 10970 XTENSA_OPCODE_IS_BRANCH, 10971 Opcode_beqz_encode_fns, 0, 0 }, 10972 { "bnez", 44 /* xt_iclass_bsz12 */, 10973 XTENSA_OPCODE_IS_BRANCH, 10974 Opcode_bnez_encode_fns, 0, 0 }, 10975 { "bgez", 44 /* xt_iclass_bsz12 */, 10976 XTENSA_OPCODE_IS_BRANCH, 10977 Opcode_bgez_encode_fns, 0, 0 }, 10978 { "bltz", 44 /* xt_iclass_bsz12 */, 10979 XTENSA_OPCODE_IS_BRANCH, 10980 Opcode_bltz_encode_fns, 0, 0 }, 10981 { "call0", 45 /* xt_iclass_call0 */, 10982 XTENSA_OPCODE_IS_CALL, 10983 Opcode_call0_encode_fns, 0, 0 }, 10984 { "callx0", 46 /* xt_iclass_callx0 */, 10985 XTENSA_OPCODE_IS_CALL, 10986 Opcode_callx0_encode_fns, 0, 0 }, 10987 { "extui", 47 /* xt_iclass_exti */, 10988 0, 10989 Opcode_extui_encode_fns, 0, 0 }, 10990 { "ill", 48 /* xt_iclass_ill */, 10991 0, 10992 Opcode_ill_encode_fns, 0, 0 }, 10993 { "j", 49 /* xt_iclass_jump */, 10994 XTENSA_OPCODE_IS_JUMP, 10995 Opcode_j_encode_fns, 0, 0 }, 10996 { "jx", 50 /* xt_iclass_jumpx */, 10997 XTENSA_OPCODE_IS_JUMP, 10998 Opcode_jx_encode_fns, 0, 0 }, 10999 { "l16ui", 51 /* xt_iclass_l16ui */, 11000 0, 11001 Opcode_l16ui_encode_fns, 0, 0 }, 11002 { "l16si", 52 /* xt_iclass_l16si */, 11003 0, 11004 Opcode_l16si_encode_fns, 0, 0 }, 11005 { "l32i", 53 /* xt_iclass_l32i */, 11006 0, 11007 Opcode_l32i_encode_fns, 0, 0 }, 11008 { "l32r", 54 /* xt_iclass_l32r */, 11009 0, 11010 Opcode_l32r_encode_fns, 0, 0 }, 11011 { "l8ui", 55 /* xt_iclass_l8i */, 11012 0, 11013 Opcode_l8ui_encode_fns, 0, 0 }, 11014 { "loop", 56 /* xt_iclass_loop */, 11015 XTENSA_OPCODE_IS_LOOP, 11016 Opcode_loop_encode_fns, 0, 0 }, 11017 { "loopnez", 57 /* xt_iclass_loopz */, 11018 XTENSA_OPCODE_IS_LOOP, 11019 Opcode_loopnez_encode_fns, 0, 0 }, 11020 { "loopgtz", 57 /* xt_iclass_loopz */, 11021 XTENSA_OPCODE_IS_LOOP, 11022 Opcode_loopgtz_encode_fns, 0, 0 }, 11023 { "movi", 58 /* xt_iclass_movi */, 11024 0, 11025 Opcode_movi_encode_fns, 0, 0 }, 11026 { "moveqz", 59 /* xt_iclass_movz */, 11027 0, 11028 Opcode_moveqz_encode_fns, 0, 0 }, 11029 { "movnez", 59 /* xt_iclass_movz */, 11030 0, 11031 Opcode_movnez_encode_fns, 0, 0 }, 11032 { "movltz", 59 /* xt_iclass_movz */, 11033 0, 11034 Opcode_movltz_encode_fns, 0, 0 }, 11035 { "movgez", 59 /* xt_iclass_movz */, 11036 0, 11037 Opcode_movgez_encode_fns, 0, 0 }, 11038 { "neg", 60 /* xt_iclass_neg */, 11039 0, 11040 Opcode_neg_encode_fns, 0, 0 }, 11041 { "abs", 60 /* xt_iclass_neg */, 11042 0, 11043 Opcode_abs_encode_fns, 0, 0 }, 11044 { "nop", 61 /* xt_iclass_nop */, 11045 0, 11046 Opcode_nop_encode_fns, 0, 0 }, 11047 { "ret", 62 /* xt_iclass_return */, 11048 XTENSA_OPCODE_IS_JUMP, 11049 Opcode_ret_encode_fns, 0, 0 }, 11050 { "s16i", 63 /* xt_iclass_s16i */, 11051 0, 11052 Opcode_s16i_encode_fns, 0, 0 }, 11053 { "s32i", 64 /* xt_iclass_s32i */, 11054 0, 11055 Opcode_s32i_encode_fns, 0, 0 }, 11056 { "s8i", 65 /* xt_iclass_s8i */, 11057 0, 11058 Opcode_s8i_encode_fns, 0, 0 }, 11059 { "ssr", 66 /* xt_iclass_sar */, 11060 0, 11061 Opcode_ssr_encode_fns, 0, 0 }, 11062 { "ssl", 66 /* xt_iclass_sar */, 11063 0, 11064 Opcode_ssl_encode_fns, 0, 0 }, 11065 { "ssa8l", 66 /* xt_iclass_sar */, 11066 0, 11067 Opcode_ssa8l_encode_fns, 0, 0 }, 11068 { "ssa8b", 66 /* xt_iclass_sar */, 11069 0, 11070 Opcode_ssa8b_encode_fns, 0, 0 }, 11071 { "ssai", 67 /* xt_iclass_sari */, 11072 0, 11073 Opcode_ssai_encode_fns, 0, 0 }, 11074 { "sll", 68 /* xt_iclass_shifts */, 11075 0, 11076 Opcode_sll_encode_fns, 0, 0 }, 11077 { "src", 69 /* xt_iclass_shiftst */, 11078 0, 11079 Opcode_src_encode_fns, 0, 0 }, 11080 { "srl", 70 /* xt_iclass_shiftt */, 11081 0, 11082 Opcode_srl_encode_fns, 0, 0 }, 11083 { "sra", 70 /* xt_iclass_shiftt */, 11084 0, 11085 Opcode_sra_encode_fns, 0, 0 }, 11086 { "slli", 71 /* xt_iclass_slli */, 11087 0, 11088 Opcode_slli_encode_fns, 0, 0 }, 11089 { "srai", 72 /* xt_iclass_srai */, 11090 0, 11091 Opcode_srai_encode_fns, 0, 0 }, 11092 { "srli", 73 /* xt_iclass_srli */, 11093 0, 11094 Opcode_srli_encode_fns, 0, 0 }, 11095 { "memw", 74 /* xt_iclass_memw */, 11096 0, 11097 Opcode_memw_encode_fns, 0, 0 }, 11098 { "extw", 75 /* xt_iclass_extw */, 11099 0, 11100 Opcode_extw_encode_fns, 0, 0 }, 11101 { "isync", 76 /* xt_iclass_isync */, 11102 0, 11103 Opcode_isync_encode_fns, 0, 0 }, 11104 { "rsync", 77 /* xt_iclass_sync */, 11105 0, 11106 Opcode_rsync_encode_fns, 0, 0 }, 11107 { "esync", 77 /* xt_iclass_sync */, 11108 0, 11109 Opcode_esync_encode_fns, 0, 0 }, 11110 { "dsync", 77 /* xt_iclass_sync */, 11111 0, 11112 Opcode_dsync_encode_fns, 0, 0 }, 11113 { "rsil", 78 /* xt_iclass_rsil */, 11114 0, 11115 Opcode_rsil_encode_fns, 0, 0 }, 11116 { "rsr.lend", 79 /* xt_iclass_rsr.lend */, 11117 0, 11118 Opcode_rsr_lend_encode_fns, 0, 0 }, 11119 { "wsr.lend", 80 /* xt_iclass_wsr.lend */, 11120 0, 11121 Opcode_wsr_lend_encode_fns, 0, 0 }, 11122 { "xsr.lend", 81 /* xt_iclass_xsr.lend */, 11123 0, 11124 Opcode_xsr_lend_encode_fns, 0, 0 }, 11125 { "rsr.lcount", 82 /* xt_iclass_rsr.lcount */, 11126 0, 11127 Opcode_rsr_lcount_encode_fns, 0, 0 }, 11128 { "wsr.lcount", 83 /* xt_iclass_wsr.lcount */, 11129 0, 11130 Opcode_wsr_lcount_encode_fns, 0, 0 }, 11131 { "xsr.lcount", 84 /* xt_iclass_xsr.lcount */, 11132 0, 11133 Opcode_xsr_lcount_encode_fns, 0, 0 }, 11134 { "rsr.lbeg", 85 /* xt_iclass_rsr.lbeg */, 11135 0, 11136 Opcode_rsr_lbeg_encode_fns, 0, 0 }, 11137 { "wsr.lbeg", 86 /* xt_iclass_wsr.lbeg */, 11138 0, 11139 Opcode_wsr_lbeg_encode_fns, 0, 0 }, 11140 { "xsr.lbeg", 87 /* xt_iclass_xsr.lbeg */, 11141 0, 11142 Opcode_xsr_lbeg_encode_fns, 0, 0 }, 11143 { "rsr.sar", 88 /* xt_iclass_rsr.sar */, 11144 0, 11145 Opcode_rsr_sar_encode_fns, 0, 0 }, 11146 { "wsr.sar", 89 /* xt_iclass_wsr.sar */, 11147 0, 11148 Opcode_wsr_sar_encode_fns, 0, 0 }, 11149 { "xsr.sar", 90 /* xt_iclass_xsr.sar */, 11150 0, 11151 Opcode_xsr_sar_encode_fns, 0, 0 }, 11152 { "rsr.litbase", 91 /* xt_iclass_rsr.litbase */, 11153 0, 11154 Opcode_rsr_litbase_encode_fns, 0, 0 }, 11155 { "wsr.litbase", 92 /* xt_iclass_wsr.litbase */, 11156 0, 11157 Opcode_wsr_litbase_encode_fns, 0, 0 }, 11158 { "xsr.litbase", 93 /* xt_iclass_xsr.litbase */, 11159 0, 11160 Opcode_xsr_litbase_encode_fns, 0, 0 }, 11161 { "rsr.176", 94 /* xt_iclass_rsr.176 */, 11162 0, 11163 Opcode_rsr_176_encode_fns, 0, 0 }, 11164 { "rsr.208", 95 /* xt_iclass_rsr.208 */, 11165 0, 11166 Opcode_rsr_208_encode_fns, 0, 0 }, 11167 { "rsr.ps", 96 /* xt_iclass_rsr.ps */, 11168 0, 11169 Opcode_rsr_ps_encode_fns, 0, 0 }, 11170 { "wsr.ps", 97 /* xt_iclass_wsr.ps */, 11171 0, 11172 Opcode_wsr_ps_encode_fns, 0, 0 }, 11173 { "xsr.ps", 98 /* xt_iclass_xsr.ps */, 11174 0, 11175 Opcode_xsr_ps_encode_fns, 0, 0 }, 11176 { "rsr.epc1", 99 /* xt_iclass_rsr.epc1 */, 11177 0, 11178 Opcode_rsr_epc1_encode_fns, 0, 0 }, 11179 { "wsr.epc1", 100 /* xt_iclass_wsr.epc1 */, 11180 0, 11181 Opcode_wsr_epc1_encode_fns, 0, 0 }, 11182 { "xsr.epc1", 101 /* xt_iclass_xsr.epc1 */, 11183 0, 11184 Opcode_xsr_epc1_encode_fns, 0, 0 }, 11185 { "rsr.excsave1", 102 /* xt_iclass_rsr.excsave1 */, 11186 0, 11187 Opcode_rsr_excsave1_encode_fns, 0, 0 }, 11188 { "wsr.excsave1", 103 /* xt_iclass_wsr.excsave1 */, 11189 0, 11190 Opcode_wsr_excsave1_encode_fns, 0, 0 }, 11191 { "xsr.excsave1", 104 /* xt_iclass_xsr.excsave1 */, 11192 0, 11193 Opcode_xsr_excsave1_encode_fns, 0, 0 }, 11194 { "rsr.epc2", 105 /* xt_iclass_rsr.epc2 */, 11195 0, 11196 Opcode_rsr_epc2_encode_fns, 0, 0 }, 11197 { "wsr.epc2", 106 /* xt_iclass_wsr.epc2 */, 11198 0, 11199 Opcode_wsr_epc2_encode_fns, 0, 0 }, 11200 { "xsr.epc2", 107 /* xt_iclass_xsr.epc2 */, 11201 0, 11202 Opcode_xsr_epc2_encode_fns, 0, 0 }, 11203 { "rsr.excsave2", 108 /* xt_iclass_rsr.excsave2 */, 11204 0, 11205 Opcode_rsr_excsave2_encode_fns, 0, 0 }, 11206 { "wsr.excsave2", 109 /* xt_iclass_wsr.excsave2 */, 11207 0, 11208 Opcode_wsr_excsave2_encode_fns, 0, 0 }, 11209 { "xsr.excsave2", 110 /* xt_iclass_xsr.excsave2 */, 11210 0, 11211 Opcode_xsr_excsave2_encode_fns, 0, 0 }, 11212 { "rsr.epc3", 111 /* xt_iclass_rsr.epc3 */, 11213 0, 11214 Opcode_rsr_epc3_encode_fns, 0, 0 }, 11215 { "wsr.epc3", 112 /* xt_iclass_wsr.epc3 */, 11216 0, 11217 Opcode_wsr_epc3_encode_fns, 0, 0 }, 11218 { "xsr.epc3", 113 /* xt_iclass_xsr.epc3 */, 11219 0, 11220 Opcode_xsr_epc3_encode_fns, 0, 0 }, 11221 { "rsr.excsave3", 114 /* xt_iclass_rsr.excsave3 */, 11222 0, 11223 Opcode_rsr_excsave3_encode_fns, 0, 0 }, 11224 { "wsr.excsave3", 115 /* xt_iclass_wsr.excsave3 */, 11225 0, 11226 Opcode_wsr_excsave3_encode_fns, 0, 0 }, 11227 { "xsr.excsave3", 116 /* xt_iclass_xsr.excsave3 */, 11228 0, 11229 Opcode_xsr_excsave3_encode_fns, 0, 0 }, 11230 { "rsr.epc4", 117 /* xt_iclass_rsr.epc4 */, 11231 0, 11232 Opcode_rsr_epc4_encode_fns, 0, 0 }, 11233 { "wsr.epc4", 118 /* xt_iclass_wsr.epc4 */, 11234 0, 11235 Opcode_wsr_epc4_encode_fns, 0, 0 }, 11236 { "xsr.epc4", 119 /* xt_iclass_xsr.epc4 */, 11237 0, 11238 Opcode_xsr_epc4_encode_fns, 0, 0 }, 11239 { "rsr.excsave4", 120 /* xt_iclass_rsr.excsave4 */, 11240 0, 11241 Opcode_rsr_excsave4_encode_fns, 0, 0 }, 11242 { "wsr.excsave4", 121 /* xt_iclass_wsr.excsave4 */, 11243 0, 11244 Opcode_wsr_excsave4_encode_fns, 0, 0 }, 11245 { "xsr.excsave4", 122 /* xt_iclass_xsr.excsave4 */, 11246 0, 11247 Opcode_xsr_excsave4_encode_fns, 0, 0 }, 11248 { "rsr.epc5", 123 /* xt_iclass_rsr.epc5 */, 11249 0, 11250 Opcode_rsr_epc5_encode_fns, 0, 0 }, 11251 { "wsr.epc5", 124 /* xt_iclass_wsr.epc5 */, 11252 0, 11253 Opcode_wsr_epc5_encode_fns, 0, 0 }, 11254 { "xsr.epc5", 125 /* xt_iclass_xsr.epc5 */, 11255 0, 11256 Opcode_xsr_epc5_encode_fns, 0, 0 }, 11257 { "rsr.excsave5", 126 /* xt_iclass_rsr.excsave5 */, 11258 0, 11259 Opcode_rsr_excsave5_encode_fns, 0, 0 }, 11260 { "wsr.excsave5", 127 /* xt_iclass_wsr.excsave5 */, 11261 0, 11262 Opcode_wsr_excsave5_encode_fns, 0, 0 }, 11263 { "xsr.excsave5", 128 /* xt_iclass_xsr.excsave5 */, 11264 0, 11265 Opcode_xsr_excsave5_encode_fns, 0, 0 }, 11266 { "rsr.epc6", 129 /* xt_iclass_rsr.epc6 */, 11267 0, 11268 Opcode_rsr_epc6_encode_fns, 0, 0 }, 11269 { "wsr.epc6", 130 /* xt_iclass_wsr.epc6 */, 11270 0, 11271 Opcode_wsr_epc6_encode_fns, 0, 0 }, 11272 { "xsr.epc6", 131 /* xt_iclass_xsr.epc6 */, 11273 0, 11274 Opcode_xsr_epc6_encode_fns, 0, 0 }, 11275 { "rsr.excsave6", 132 /* xt_iclass_rsr.excsave6 */, 11276 0, 11277 Opcode_rsr_excsave6_encode_fns, 0, 0 }, 11278 { "wsr.excsave6", 133 /* xt_iclass_wsr.excsave6 */, 11279 0, 11280 Opcode_wsr_excsave6_encode_fns, 0, 0 }, 11281 { "xsr.excsave6", 134 /* xt_iclass_xsr.excsave6 */, 11282 0, 11283 Opcode_xsr_excsave6_encode_fns, 0, 0 }, 11284 { "rsr.epc7", 135 /* xt_iclass_rsr.epc7 */, 11285 0, 11286 Opcode_rsr_epc7_encode_fns, 0, 0 }, 11287 { "wsr.epc7", 136 /* xt_iclass_wsr.epc7 */, 11288 0, 11289 Opcode_wsr_epc7_encode_fns, 0, 0 }, 11290 { "xsr.epc7", 137 /* xt_iclass_xsr.epc7 */, 11291 0, 11292 Opcode_xsr_epc7_encode_fns, 0, 0 }, 11293 { "rsr.excsave7", 138 /* xt_iclass_rsr.excsave7 */, 11294 0, 11295 Opcode_rsr_excsave7_encode_fns, 0, 0 }, 11296 { "wsr.excsave7", 139 /* xt_iclass_wsr.excsave7 */, 11297 0, 11298 Opcode_wsr_excsave7_encode_fns, 0, 0 }, 11299 { "xsr.excsave7", 140 /* xt_iclass_xsr.excsave7 */, 11300 0, 11301 Opcode_xsr_excsave7_encode_fns, 0, 0 }, 11302 { "rsr.eps2", 141 /* xt_iclass_rsr.eps2 */, 11303 0, 11304 Opcode_rsr_eps2_encode_fns, 0, 0 }, 11305 { "wsr.eps2", 142 /* xt_iclass_wsr.eps2 */, 11306 0, 11307 Opcode_wsr_eps2_encode_fns, 0, 0 }, 11308 { "xsr.eps2", 143 /* xt_iclass_xsr.eps2 */, 11309 0, 11310 Opcode_xsr_eps2_encode_fns, 0, 0 }, 11311 { "rsr.eps3", 144 /* xt_iclass_rsr.eps3 */, 11312 0, 11313 Opcode_rsr_eps3_encode_fns, 0, 0 }, 11314 { "wsr.eps3", 145 /* xt_iclass_wsr.eps3 */, 11315 0, 11316 Opcode_wsr_eps3_encode_fns, 0, 0 }, 11317 { "xsr.eps3", 146 /* xt_iclass_xsr.eps3 */, 11318 0, 11319 Opcode_xsr_eps3_encode_fns, 0, 0 }, 11320 { "rsr.eps4", 147 /* xt_iclass_rsr.eps4 */, 11321 0, 11322 Opcode_rsr_eps4_encode_fns, 0, 0 }, 11323 { "wsr.eps4", 148 /* xt_iclass_wsr.eps4 */, 11324 0, 11325 Opcode_wsr_eps4_encode_fns, 0, 0 }, 11326 { "xsr.eps4", 149 /* xt_iclass_xsr.eps4 */, 11327 0, 11328 Opcode_xsr_eps4_encode_fns, 0, 0 }, 11329 { "rsr.eps5", 150 /* xt_iclass_rsr.eps5 */, 11330 0, 11331 Opcode_rsr_eps5_encode_fns, 0, 0 }, 11332 { "wsr.eps5", 151 /* xt_iclass_wsr.eps5 */, 11333 0, 11334 Opcode_wsr_eps5_encode_fns, 0, 0 }, 11335 { "xsr.eps5", 152 /* xt_iclass_xsr.eps5 */, 11336 0, 11337 Opcode_xsr_eps5_encode_fns, 0, 0 }, 11338 { "rsr.eps6", 153 /* xt_iclass_rsr.eps6 */, 11339 0, 11340 Opcode_rsr_eps6_encode_fns, 0, 0 }, 11341 { "wsr.eps6", 154 /* xt_iclass_wsr.eps6 */, 11342 0, 11343 Opcode_wsr_eps6_encode_fns, 0, 0 }, 11344 { "xsr.eps6", 155 /* xt_iclass_xsr.eps6 */, 11345 0, 11346 Opcode_xsr_eps6_encode_fns, 0, 0 }, 11347 { "rsr.eps7", 156 /* xt_iclass_rsr.eps7 */, 11348 0, 11349 Opcode_rsr_eps7_encode_fns, 0, 0 }, 11350 { "wsr.eps7", 157 /* xt_iclass_wsr.eps7 */, 11351 0, 11352 Opcode_wsr_eps7_encode_fns, 0, 0 }, 11353 { "xsr.eps7", 158 /* xt_iclass_xsr.eps7 */, 11354 0, 11355 Opcode_xsr_eps7_encode_fns, 0, 0 }, 11356 { "rsr.excvaddr", 159 /* xt_iclass_rsr.excvaddr */, 11357 0, 11358 Opcode_rsr_excvaddr_encode_fns, 0, 0 }, 11359 { "wsr.excvaddr", 160 /* xt_iclass_wsr.excvaddr */, 11360 0, 11361 Opcode_wsr_excvaddr_encode_fns, 0, 0 }, 11362 { "xsr.excvaddr", 161 /* xt_iclass_xsr.excvaddr */, 11363 0, 11364 Opcode_xsr_excvaddr_encode_fns, 0, 0 }, 11365 { "rsr.depc", 162 /* xt_iclass_rsr.depc */, 11366 0, 11367 Opcode_rsr_depc_encode_fns, 0, 0 }, 11368 { "wsr.depc", 163 /* xt_iclass_wsr.depc */, 11369 0, 11370 Opcode_wsr_depc_encode_fns, 0, 0 }, 11371 { "xsr.depc", 164 /* xt_iclass_xsr.depc */, 11372 0, 11373 Opcode_xsr_depc_encode_fns, 0, 0 }, 11374 { "rsr.exccause", 165 /* xt_iclass_rsr.exccause */, 11375 0, 11376 Opcode_rsr_exccause_encode_fns, 0, 0 }, 11377 { "wsr.exccause", 166 /* xt_iclass_wsr.exccause */, 11378 0, 11379 Opcode_wsr_exccause_encode_fns, 0, 0 }, 11380 { "xsr.exccause", 167 /* xt_iclass_xsr.exccause */, 11381 0, 11382 Opcode_xsr_exccause_encode_fns, 0, 0 }, 11383 { "rsr.misc0", 168 /* xt_iclass_rsr.misc0 */, 11384 0, 11385 Opcode_rsr_misc0_encode_fns, 0, 0 }, 11386 { "wsr.misc0", 169 /* xt_iclass_wsr.misc0 */, 11387 0, 11388 Opcode_wsr_misc0_encode_fns, 0, 0 }, 11389 { "xsr.misc0", 170 /* xt_iclass_xsr.misc0 */, 11390 0, 11391 Opcode_xsr_misc0_encode_fns, 0, 0 }, 11392 { "rsr.misc1", 171 /* xt_iclass_rsr.misc1 */, 11393 0, 11394 Opcode_rsr_misc1_encode_fns, 0, 0 }, 11395 { "wsr.misc1", 172 /* xt_iclass_wsr.misc1 */, 11396 0, 11397 Opcode_wsr_misc1_encode_fns, 0, 0 }, 11398 { "xsr.misc1", 173 /* xt_iclass_xsr.misc1 */, 11399 0, 11400 Opcode_xsr_misc1_encode_fns, 0, 0 }, 11401 { "rsr.prid", 174 /* xt_iclass_rsr.prid */, 11402 0, 11403 Opcode_rsr_prid_encode_fns, 0, 0 }, 11404 { "rsr.vecbase", 175 /* xt_iclass_rsr.vecbase */, 11405 0, 11406 Opcode_rsr_vecbase_encode_fns, 0, 0 }, 11407 { "wsr.vecbase", 176 /* xt_iclass_wsr.vecbase */, 11408 0, 11409 Opcode_wsr_vecbase_encode_fns, 0, 0 }, 11410 { "xsr.vecbase", 177 /* xt_iclass_xsr.vecbase */, 11411 0, 11412 Opcode_xsr_vecbase_encode_fns, 0, 0 }, 11413 { "mul.aa.ll", 178 /* xt_iclass_mac16_aa */, 11414 0, 11415 Opcode_mul_aa_ll_encode_fns, 0, 0 }, 11416 { "mul.aa.hl", 178 /* xt_iclass_mac16_aa */, 11417 0, 11418 Opcode_mul_aa_hl_encode_fns, 0, 0 }, 11419 { "mul.aa.lh", 178 /* xt_iclass_mac16_aa */, 11420 0, 11421 Opcode_mul_aa_lh_encode_fns, 0, 0 }, 11422 { "mul.aa.hh", 178 /* xt_iclass_mac16_aa */, 11423 0, 11424 Opcode_mul_aa_hh_encode_fns, 0, 0 }, 11425 { "umul.aa.ll", 178 /* xt_iclass_mac16_aa */, 11426 0, 11427 Opcode_umul_aa_ll_encode_fns, 0, 0 }, 11428 { "umul.aa.hl", 178 /* xt_iclass_mac16_aa */, 11429 0, 11430 Opcode_umul_aa_hl_encode_fns, 0, 0 }, 11431 { "umul.aa.lh", 178 /* xt_iclass_mac16_aa */, 11432 0, 11433 Opcode_umul_aa_lh_encode_fns, 0, 0 }, 11434 { "umul.aa.hh", 178 /* xt_iclass_mac16_aa */, 11435 0, 11436 Opcode_umul_aa_hh_encode_fns, 0, 0 }, 11437 { "mul.ad.ll", 179 /* xt_iclass_mac16_ad */, 11438 0, 11439 Opcode_mul_ad_ll_encode_fns, 0, 0 }, 11440 { "mul.ad.hl", 179 /* xt_iclass_mac16_ad */, 11441 0, 11442 Opcode_mul_ad_hl_encode_fns, 0, 0 }, 11443 { "mul.ad.lh", 179 /* xt_iclass_mac16_ad */, 11444 0, 11445 Opcode_mul_ad_lh_encode_fns, 0, 0 }, 11446 { "mul.ad.hh", 179 /* xt_iclass_mac16_ad */, 11447 0, 11448 Opcode_mul_ad_hh_encode_fns, 0, 0 }, 11449 { "mul.da.ll", 180 /* xt_iclass_mac16_da */, 11450 0, 11451 Opcode_mul_da_ll_encode_fns, 0, 0 }, 11452 { "mul.da.hl", 180 /* xt_iclass_mac16_da */, 11453 0, 11454 Opcode_mul_da_hl_encode_fns, 0, 0 }, 11455 { "mul.da.lh", 180 /* xt_iclass_mac16_da */, 11456 0, 11457 Opcode_mul_da_lh_encode_fns, 0, 0 }, 11458 { "mul.da.hh", 180 /* xt_iclass_mac16_da */, 11459 0, 11460 Opcode_mul_da_hh_encode_fns, 0, 0 }, 11461 { "mul.dd.ll", 181 /* xt_iclass_mac16_dd */, 11462 0, 11463 Opcode_mul_dd_ll_encode_fns, 0, 0 }, 11464 { "mul.dd.hl", 181 /* xt_iclass_mac16_dd */, 11465 0, 11466 Opcode_mul_dd_hl_encode_fns, 0, 0 }, 11467 { "mul.dd.lh", 181 /* xt_iclass_mac16_dd */, 11468 0, 11469 Opcode_mul_dd_lh_encode_fns, 0, 0 }, 11470 { "mul.dd.hh", 181 /* xt_iclass_mac16_dd */, 11471 0, 11472 Opcode_mul_dd_hh_encode_fns, 0, 0 }, 11473 { "mula.aa.ll", 182 /* xt_iclass_mac16a_aa */, 11474 0, 11475 Opcode_mula_aa_ll_encode_fns, 0, 0 }, 11476 { "mula.aa.hl", 182 /* xt_iclass_mac16a_aa */, 11477 0, 11478 Opcode_mula_aa_hl_encode_fns, 0, 0 }, 11479 { "mula.aa.lh", 182 /* xt_iclass_mac16a_aa */, 11480 0, 11481 Opcode_mula_aa_lh_encode_fns, 0, 0 }, 11482 { "mula.aa.hh", 182 /* xt_iclass_mac16a_aa */, 11483 0, 11484 Opcode_mula_aa_hh_encode_fns, 0, 0 }, 11485 { "muls.aa.ll", 182 /* xt_iclass_mac16a_aa */, 11486 0, 11487 Opcode_muls_aa_ll_encode_fns, 0, 0 }, 11488 { "muls.aa.hl", 182 /* xt_iclass_mac16a_aa */, 11489 0, 11490 Opcode_muls_aa_hl_encode_fns, 0, 0 }, 11491 { "muls.aa.lh", 182 /* xt_iclass_mac16a_aa */, 11492 0, 11493 Opcode_muls_aa_lh_encode_fns, 0, 0 }, 11494 { "muls.aa.hh", 182 /* xt_iclass_mac16a_aa */, 11495 0, 11496 Opcode_muls_aa_hh_encode_fns, 0, 0 }, 11497 { "mula.ad.ll", 183 /* xt_iclass_mac16a_ad */, 11498 0, 11499 Opcode_mula_ad_ll_encode_fns, 0, 0 }, 11500 { "mula.ad.hl", 183 /* xt_iclass_mac16a_ad */, 11501 0, 11502 Opcode_mula_ad_hl_encode_fns, 0, 0 }, 11503 { "mula.ad.lh", 183 /* xt_iclass_mac16a_ad */, 11504 0, 11505 Opcode_mula_ad_lh_encode_fns, 0, 0 }, 11506 { "mula.ad.hh", 183 /* xt_iclass_mac16a_ad */, 11507 0, 11508 Opcode_mula_ad_hh_encode_fns, 0, 0 }, 11509 { "muls.ad.ll", 183 /* xt_iclass_mac16a_ad */, 11510 0, 11511 Opcode_muls_ad_ll_encode_fns, 0, 0 }, 11512 { "muls.ad.hl", 183 /* xt_iclass_mac16a_ad */, 11513 0, 11514 Opcode_muls_ad_hl_encode_fns, 0, 0 }, 11515 { "muls.ad.lh", 183 /* xt_iclass_mac16a_ad */, 11516 0, 11517 Opcode_muls_ad_lh_encode_fns, 0, 0 }, 11518 { "muls.ad.hh", 183 /* xt_iclass_mac16a_ad */, 11519 0, 11520 Opcode_muls_ad_hh_encode_fns, 0, 0 }, 11521 { "mula.da.ll", 184 /* xt_iclass_mac16a_da */, 11522 0, 11523 Opcode_mula_da_ll_encode_fns, 0, 0 }, 11524 { "mula.da.hl", 184 /* xt_iclass_mac16a_da */, 11525 0, 11526 Opcode_mula_da_hl_encode_fns, 0, 0 }, 11527 { "mula.da.lh", 184 /* xt_iclass_mac16a_da */, 11528 0, 11529 Opcode_mula_da_lh_encode_fns, 0, 0 }, 11530 { "mula.da.hh", 184 /* xt_iclass_mac16a_da */, 11531 0, 11532 Opcode_mula_da_hh_encode_fns, 0, 0 }, 11533 { "muls.da.ll", 184 /* xt_iclass_mac16a_da */, 11534 0, 11535 Opcode_muls_da_ll_encode_fns, 0, 0 }, 11536 { "muls.da.hl", 184 /* xt_iclass_mac16a_da */, 11537 0, 11538 Opcode_muls_da_hl_encode_fns, 0, 0 }, 11539 { "muls.da.lh", 184 /* xt_iclass_mac16a_da */, 11540 0, 11541 Opcode_muls_da_lh_encode_fns, 0, 0 }, 11542 { "muls.da.hh", 184 /* xt_iclass_mac16a_da */, 11543 0, 11544 Opcode_muls_da_hh_encode_fns, 0, 0 }, 11545 { "mula.dd.ll", 185 /* xt_iclass_mac16a_dd */, 11546 0, 11547 Opcode_mula_dd_ll_encode_fns, 0, 0 }, 11548 { "mula.dd.hl", 185 /* xt_iclass_mac16a_dd */, 11549 0, 11550 Opcode_mula_dd_hl_encode_fns, 0, 0 }, 11551 { "mula.dd.lh", 185 /* xt_iclass_mac16a_dd */, 11552 0, 11553 Opcode_mula_dd_lh_encode_fns, 0, 0 }, 11554 { "mula.dd.hh", 185 /* xt_iclass_mac16a_dd */, 11555 0, 11556 Opcode_mula_dd_hh_encode_fns, 0, 0 }, 11557 { "muls.dd.ll", 185 /* xt_iclass_mac16a_dd */, 11558 0, 11559 Opcode_muls_dd_ll_encode_fns, 0, 0 }, 11560 { "muls.dd.hl", 185 /* xt_iclass_mac16a_dd */, 11561 0, 11562 Opcode_muls_dd_hl_encode_fns, 0, 0 }, 11563 { "muls.dd.lh", 185 /* xt_iclass_mac16a_dd */, 11564 0, 11565 Opcode_muls_dd_lh_encode_fns, 0, 0 }, 11566 { "muls.dd.hh", 185 /* xt_iclass_mac16a_dd */, 11567 0, 11568 Opcode_muls_dd_hh_encode_fns, 0, 0 }, 11569 { "mula.da.ll.lddec", 186 /* xt_iclass_mac16al_da */, 11570 0, 11571 Opcode_mula_da_ll_lddec_encode_fns, 0, 0 }, 11572 { "mula.da.ll.ldinc", 186 /* xt_iclass_mac16al_da */, 11573 0, 11574 Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 }, 11575 { "mula.da.hl.lddec", 186 /* xt_iclass_mac16al_da */, 11576 0, 11577 Opcode_mula_da_hl_lddec_encode_fns, 0, 0 }, 11578 { "mula.da.hl.ldinc", 186 /* xt_iclass_mac16al_da */, 11579 0, 11580 Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 }, 11581 { "mula.da.lh.lddec", 186 /* xt_iclass_mac16al_da */, 11582 0, 11583 Opcode_mula_da_lh_lddec_encode_fns, 0, 0 }, 11584 { "mula.da.lh.ldinc", 186 /* xt_iclass_mac16al_da */, 11585 0, 11586 Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 }, 11587 { "mula.da.hh.lddec", 186 /* xt_iclass_mac16al_da */, 11588 0, 11589 Opcode_mula_da_hh_lddec_encode_fns, 0, 0 }, 11590 { "mula.da.hh.ldinc", 186 /* xt_iclass_mac16al_da */, 11591 0, 11592 Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 }, 11593 { "mula.dd.ll.lddec", 187 /* xt_iclass_mac16al_dd */, 11594 0, 11595 Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 }, 11596 { "mula.dd.ll.ldinc", 187 /* xt_iclass_mac16al_dd */, 11597 0, 11598 Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 }, 11599 { "mula.dd.hl.lddec", 187 /* xt_iclass_mac16al_dd */, 11600 0, 11601 Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 }, 11602 { "mula.dd.hl.ldinc", 187 /* xt_iclass_mac16al_dd */, 11603 0, 11604 Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 }, 11605 { "mula.dd.lh.lddec", 187 /* xt_iclass_mac16al_dd */, 11606 0, 11607 Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 }, 11608 { "mula.dd.lh.ldinc", 187 /* xt_iclass_mac16al_dd */, 11609 0, 11610 Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 }, 11611 { "mula.dd.hh.lddec", 187 /* xt_iclass_mac16al_dd */, 11612 0, 11613 Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 }, 11614 { "mula.dd.hh.ldinc", 187 /* xt_iclass_mac16al_dd */, 11615 0, 11616 Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 }, 11617 { "lddec", 188 /* xt_iclass_mac16_l */, 11618 0, 11619 Opcode_lddec_encode_fns, 0, 0 }, 11620 { "ldinc", 188 /* xt_iclass_mac16_l */, 11621 0, 11622 Opcode_ldinc_encode_fns, 0, 0 }, 11623 { "mul16u", 189 /* xt_iclass_mul16 */, 11624 0, 11625 Opcode_mul16u_encode_fns, 0, 0 }, 11626 { "mul16s", 189 /* xt_iclass_mul16 */, 11627 0, 11628 Opcode_mul16s_encode_fns, 0, 0 }, 11629 { "rsr.m0", 190 /* xt_iclass_rsr.m0 */, 11630 0, 11631 Opcode_rsr_m0_encode_fns, 0, 0 }, 11632 { "wsr.m0", 191 /* xt_iclass_wsr.m0 */, 11633 0, 11634 Opcode_wsr_m0_encode_fns, 0, 0 }, 11635 { "xsr.m0", 192 /* xt_iclass_xsr.m0 */, 11636 0, 11637 Opcode_xsr_m0_encode_fns, 0, 0 }, 11638 { "rsr.m1", 193 /* xt_iclass_rsr.m1 */, 11639 0, 11640 Opcode_rsr_m1_encode_fns, 0, 0 }, 11641 { "wsr.m1", 194 /* xt_iclass_wsr.m1 */, 11642 0, 11643 Opcode_wsr_m1_encode_fns, 0, 0 }, 11644 { "xsr.m1", 195 /* xt_iclass_xsr.m1 */, 11645 0, 11646 Opcode_xsr_m1_encode_fns, 0, 0 }, 11647 { "rsr.m2", 196 /* xt_iclass_rsr.m2 */, 11648 0, 11649 Opcode_rsr_m2_encode_fns, 0, 0 }, 11650 { "wsr.m2", 197 /* xt_iclass_wsr.m2 */, 11651 0, 11652 Opcode_wsr_m2_encode_fns, 0, 0 }, 11653 { "xsr.m2", 198 /* xt_iclass_xsr.m2 */, 11654 0, 11655 Opcode_xsr_m2_encode_fns, 0, 0 }, 11656 { "rsr.m3", 199 /* xt_iclass_rsr.m3 */, 11657 0, 11658 Opcode_rsr_m3_encode_fns, 0, 0 }, 11659 { "wsr.m3", 200 /* xt_iclass_wsr.m3 */, 11660 0, 11661 Opcode_wsr_m3_encode_fns, 0, 0 }, 11662 { "xsr.m3", 201 /* xt_iclass_xsr.m3 */, 11663 0, 11664 Opcode_xsr_m3_encode_fns, 0, 0 }, 11665 { "rsr.acclo", 202 /* xt_iclass_rsr.acclo */, 11666 0, 11667 Opcode_rsr_acclo_encode_fns, 0, 0 }, 11668 { "wsr.acclo", 203 /* xt_iclass_wsr.acclo */, 11669 0, 11670 Opcode_wsr_acclo_encode_fns, 0, 0 }, 11671 { "xsr.acclo", 204 /* xt_iclass_xsr.acclo */, 11672 0, 11673 Opcode_xsr_acclo_encode_fns, 0, 0 }, 11674 { "rsr.acchi", 205 /* xt_iclass_rsr.acchi */, 11675 0, 11676 Opcode_rsr_acchi_encode_fns, 0, 0 }, 11677 { "wsr.acchi", 206 /* xt_iclass_wsr.acchi */, 11678 0, 11679 Opcode_wsr_acchi_encode_fns, 0, 0 }, 11680 { "xsr.acchi", 207 /* xt_iclass_xsr.acchi */, 11681 0, 11682 Opcode_xsr_acchi_encode_fns, 0, 0 }, 11683 { "rfi", 208 /* xt_iclass_rfi */, 11684 XTENSA_OPCODE_IS_JUMP, 11685 Opcode_rfi_encode_fns, 0, 0 }, 11686 { "waiti", 209 /* xt_iclass_wait */, 11687 0, 11688 Opcode_waiti_encode_fns, 0, 0 }, 11689 { "rsr.interrupt", 210 /* xt_iclass_rsr.interrupt */, 11690 0, 11691 Opcode_rsr_interrupt_encode_fns, 0, 0 }, 11692 { "wsr.intset", 211 /* xt_iclass_wsr.intset */, 11693 0, 11694 Opcode_wsr_intset_encode_fns, 0, 0 }, 11695 { "wsr.intclear", 212 /* xt_iclass_wsr.intclear */, 11696 0, 11697 Opcode_wsr_intclear_encode_fns, 0, 0 }, 11698 { "rsr.intenable", 213 /* xt_iclass_rsr.intenable */, 11699 0, 11700 Opcode_rsr_intenable_encode_fns, 0, 0 }, 11701 { "wsr.intenable", 214 /* xt_iclass_wsr.intenable */, 11702 0, 11703 Opcode_wsr_intenable_encode_fns, 0, 0 }, 11704 { "xsr.intenable", 215 /* xt_iclass_xsr.intenable */, 11705 0, 11706 Opcode_xsr_intenable_encode_fns, 0, 0 }, 11707 { "break", 216 /* xt_iclass_break */, 11708 0, 11709 Opcode_break_encode_fns, 0, 0 }, 11710 { "break.n", 217 /* xt_iclass_break.n */, 11711 0, 11712 Opcode_break_n_encode_fns, 0, 0 }, 11713 { "rsr.dbreaka0", 218 /* xt_iclass_rsr.dbreaka0 */, 11714 0, 11715 Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, 11716 { "wsr.dbreaka0", 219 /* xt_iclass_wsr.dbreaka0 */, 11717 0, 11718 Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, 11719 { "xsr.dbreaka0", 220 /* xt_iclass_xsr.dbreaka0 */, 11720 0, 11721 Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, 11722 { "rsr.dbreakc0", 221 /* xt_iclass_rsr.dbreakc0 */, 11723 0, 11724 Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, 11725 { "wsr.dbreakc0", 222 /* xt_iclass_wsr.dbreakc0 */, 11726 0, 11727 Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, 11728 { "xsr.dbreakc0", 223 /* xt_iclass_xsr.dbreakc0 */, 11729 0, 11730 Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, 11731 { "rsr.dbreaka1", 224 /* xt_iclass_rsr.dbreaka1 */, 11732 0, 11733 Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, 11734 { "wsr.dbreaka1", 225 /* xt_iclass_wsr.dbreaka1 */, 11735 0, 11736 Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, 11737 { "xsr.dbreaka1", 226 /* xt_iclass_xsr.dbreaka1 */, 11738 0, 11739 Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, 11740 { "rsr.dbreakc1", 227 /* xt_iclass_rsr.dbreakc1 */, 11741 0, 11742 Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, 11743 { "wsr.dbreakc1", 228 /* xt_iclass_wsr.dbreakc1 */, 11744 0, 11745 Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, 11746 { "xsr.dbreakc1", 229 /* xt_iclass_xsr.dbreakc1 */, 11747 0, 11748 Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, 11749 { "rsr.ibreaka0", 230 /* xt_iclass_rsr.ibreaka0 */, 11750 0, 11751 Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, 11752 { "wsr.ibreaka0", 231 /* xt_iclass_wsr.ibreaka0 */, 11753 0, 11754 Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, 11755 { "xsr.ibreaka0", 232 /* xt_iclass_xsr.ibreaka0 */, 11756 0, 11757 Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, 11758 { "rsr.ibreaka1", 233 /* xt_iclass_rsr.ibreaka1 */, 11759 0, 11760 Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, 11761 { "wsr.ibreaka1", 234 /* xt_iclass_wsr.ibreaka1 */, 11762 0, 11763 Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, 11764 { "xsr.ibreaka1", 235 /* xt_iclass_xsr.ibreaka1 */, 11765 0, 11766 Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, 11767 { "rsr.ibreakenable", 236 /* xt_iclass_rsr.ibreakenable */, 11768 0, 11769 Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, 11770 { "wsr.ibreakenable", 237 /* xt_iclass_wsr.ibreakenable */, 11771 0, 11772 Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, 11773 { "xsr.ibreakenable", 238 /* xt_iclass_xsr.ibreakenable */, 11774 0, 11775 Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, 11776 { "rsr.debugcause", 239 /* xt_iclass_rsr.debugcause */, 11777 0, 11778 Opcode_rsr_debugcause_encode_fns, 0, 0 }, 11779 { "wsr.debugcause", 240 /* xt_iclass_wsr.debugcause */, 11780 0, 11781 Opcode_wsr_debugcause_encode_fns, 0, 0 }, 11782 { "xsr.debugcause", 241 /* xt_iclass_xsr.debugcause */, 11783 0, 11784 Opcode_xsr_debugcause_encode_fns, 0, 0 }, 11785 { "rsr.icount", 242 /* xt_iclass_rsr.icount */, 11786 0, 11787 Opcode_rsr_icount_encode_fns, 0, 0 }, 11788 { "wsr.icount", 243 /* xt_iclass_wsr.icount */, 11789 0, 11790 Opcode_wsr_icount_encode_fns, 0, 0 }, 11791 { "xsr.icount", 244 /* xt_iclass_xsr.icount */, 11792 0, 11793 Opcode_xsr_icount_encode_fns, 0, 0 }, 11794 { "rsr.icountlevel", 245 /* xt_iclass_rsr.icountlevel */, 11795 0, 11796 Opcode_rsr_icountlevel_encode_fns, 0, 0 }, 11797 { "wsr.icountlevel", 246 /* xt_iclass_wsr.icountlevel */, 11798 0, 11799 Opcode_wsr_icountlevel_encode_fns, 0, 0 }, 11800 { "xsr.icountlevel", 247 /* xt_iclass_xsr.icountlevel */, 11801 0, 11802 Opcode_xsr_icountlevel_encode_fns, 0, 0 }, 11803 { "rsr.ddr", 248 /* xt_iclass_rsr.ddr */, 11804 0, 11805 Opcode_rsr_ddr_encode_fns, 0, 0 }, 11806 { "wsr.ddr", 249 /* xt_iclass_wsr.ddr */, 11807 0, 11808 Opcode_wsr_ddr_encode_fns, 0, 0 }, 11809 { "xsr.ddr", 250 /* xt_iclass_xsr.ddr */, 11810 0, 11811 Opcode_xsr_ddr_encode_fns, 0, 0 }, 11812 { "rfdo", 251 /* xt_iclass_rfdo */, 11813 XTENSA_OPCODE_IS_JUMP, 11814 Opcode_rfdo_encode_fns, 0, 0 }, 11815 { "rfdd", 252 /* xt_iclass_rfdd */, 11816 XTENSA_OPCODE_IS_JUMP, 11817 Opcode_rfdd_encode_fns, 0, 0 }, 11818 { "wsr.mmid", 253 /* xt_iclass_wsr.mmid */, 11819 0, 11820 Opcode_wsr_mmid_encode_fns, 0, 0 }, 11821 { "rsr.ccount", 254 /* xt_iclass_rsr.ccount */, 11822 0, 11823 Opcode_rsr_ccount_encode_fns, 0, 0 }, 11824 { "wsr.ccount", 255 /* xt_iclass_wsr.ccount */, 11825 0, 11826 Opcode_wsr_ccount_encode_fns, 0, 0 }, 11827 { "xsr.ccount", 256 /* xt_iclass_xsr.ccount */, 11828 0, 11829 Opcode_xsr_ccount_encode_fns, 0, 0 }, 11830 { "rsr.ccompare0", 257 /* xt_iclass_rsr.ccompare0 */, 11831 0, 11832 Opcode_rsr_ccompare0_encode_fns, 0, 0 }, 11833 { "wsr.ccompare0", 258 /* xt_iclass_wsr.ccompare0 */, 11834 0, 11835 Opcode_wsr_ccompare0_encode_fns, 0, 0 }, 11836 { "xsr.ccompare0", 259 /* xt_iclass_xsr.ccompare0 */, 11837 0, 11838 Opcode_xsr_ccompare0_encode_fns, 0, 0 }, 11839 { "rsr.ccompare1", 260 /* xt_iclass_rsr.ccompare1 */, 11840 0, 11841 Opcode_rsr_ccompare1_encode_fns, 0, 0 }, 11842 { "wsr.ccompare1", 261 /* xt_iclass_wsr.ccompare1 */, 11843 0, 11844 Opcode_wsr_ccompare1_encode_fns, 0, 0 }, 11845 { "xsr.ccompare1", 262 /* xt_iclass_xsr.ccompare1 */, 11846 0, 11847 Opcode_xsr_ccompare1_encode_fns, 0, 0 }, 11848 { "rsr.ccompare2", 263 /* xt_iclass_rsr.ccompare2 */, 11849 0, 11850 Opcode_rsr_ccompare2_encode_fns, 0, 0 }, 11851 { "wsr.ccompare2", 264 /* xt_iclass_wsr.ccompare2 */, 11852 0, 11853 Opcode_wsr_ccompare2_encode_fns, 0, 0 }, 11854 { "xsr.ccompare2", 265 /* xt_iclass_xsr.ccompare2 */, 11855 0, 11856 Opcode_xsr_ccompare2_encode_fns, 0, 0 }, 11857 { "ipf", 266 /* xt_iclass_icache */, 11858 0, 11859 Opcode_ipf_encode_fns, 0, 0 }, 11860 { "ihi", 266 /* xt_iclass_icache */, 11861 0, 11862 Opcode_ihi_encode_fns, 0, 0 }, 11863 { "ipfl", 267 /* xt_iclass_icache_lock */, 11864 0, 11865 Opcode_ipfl_encode_fns, 0, 0 }, 11866 { "ihu", 267 /* xt_iclass_icache_lock */, 11867 0, 11868 Opcode_ihu_encode_fns, 0, 0 }, 11869 { "iiu", 267 /* xt_iclass_icache_lock */, 11870 0, 11871 Opcode_iiu_encode_fns, 0, 0 }, 11872 { "iii", 268 /* xt_iclass_icache_inv */, 11873 0, 11874 Opcode_iii_encode_fns, 0, 0 }, 11875 { "lict", 269 /* xt_iclass_licx */, 11876 0, 11877 Opcode_lict_encode_fns, 0, 0 }, 11878 { "licw", 269 /* xt_iclass_licx */, 11879 0, 11880 Opcode_licw_encode_fns, 0, 0 }, 11881 { "sict", 270 /* xt_iclass_sicx */, 11882 0, 11883 Opcode_sict_encode_fns, 0, 0 }, 11884 { "sicw", 270 /* xt_iclass_sicx */, 11885 0, 11886 Opcode_sicw_encode_fns, 0, 0 }, 11887 { "dhwb", 271 /* xt_iclass_dcache */, 11888 0, 11889 Opcode_dhwb_encode_fns, 0, 0 }, 11890 { "dhwbi", 271 /* xt_iclass_dcache */, 11891 0, 11892 Opcode_dhwbi_encode_fns, 0, 0 }, 11893 { "diwb", 272 /* xt_iclass_dcache_ind */, 11894 0, 11895 Opcode_diwb_encode_fns, 0, 0 }, 11896 { "diwbi", 272 /* xt_iclass_dcache_ind */, 11897 0, 11898 Opcode_diwbi_encode_fns, 0, 0 }, 11899 { "dhi", 273 /* xt_iclass_dcache_inv */, 11900 0, 11901 Opcode_dhi_encode_fns, 0, 0 }, 11902 { "dii", 273 /* xt_iclass_dcache_inv */, 11903 0, 11904 Opcode_dii_encode_fns, 0, 0 }, 11905 { "dpfr", 274 /* xt_iclass_dpf */, 11906 0, 11907 Opcode_dpfr_encode_fns, 0, 0 }, 11908 { "dpfw", 274 /* xt_iclass_dpf */, 11909 0, 11910 Opcode_dpfw_encode_fns, 0, 0 }, 11911 { "dpfro", 274 /* xt_iclass_dpf */, 11912 0, 11913 Opcode_dpfro_encode_fns, 0, 0 }, 11914 { "dpfwo", 274 /* xt_iclass_dpf */, 11915 0, 11916 Opcode_dpfwo_encode_fns, 0, 0 }, 11917 { "dpfl", 275 /* xt_iclass_dcache_lock */, 11918 0, 11919 Opcode_dpfl_encode_fns, 0, 0 }, 11920 { "dhu", 275 /* xt_iclass_dcache_lock */, 11921 0, 11922 Opcode_dhu_encode_fns, 0, 0 }, 11923 { "diu", 275 /* xt_iclass_dcache_lock */, 11924 0, 11925 Opcode_diu_encode_fns, 0, 0 }, 11926 { "sdct", 276 /* xt_iclass_sdct */, 11927 0, 11928 Opcode_sdct_encode_fns, 0, 0 }, 11929 { "ldct", 277 /* xt_iclass_ldct */, 11930 0, 11931 Opcode_ldct_encode_fns, 0, 0 }, 11932 { "wsr.ptevaddr", 278 /* xt_iclass_wsr.ptevaddr */, 11933 0, 11934 Opcode_wsr_ptevaddr_encode_fns, 0, 0 }, 11935 { "rsr.ptevaddr", 279 /* xt_iclass_rsr.ptevaddr */, 11936 0, 11937 Opcode_rsr_ptevaddr_encode_fns, 0, 0 }, 11938 { "xsr.ptevaddr", 280 /* xt_iclass_xsr.ptevaddr */, 11939 0, 11940 Opcode_xsr_ptevaddr_encode_fns, 0, 0 }, 11941 { "rsr.rasid", 281 /* xt_iclass_rsr.rasid */, 11942 0, 11943 Opcode_rsr_rasid_encode_fns, 0, 0 }, 11944 { "wsr.rasid", 282 /* xt_iclass_wsr.rasid */, 11945 0, 11946 Opcode_wsr_rasid_encode_fns, 0, 0 }, 11947 { "xsr.rasid", 283 /* xt_iclass_xsr.rasid */, 11948 0, 11949 Opcode_xsr_rasid_encode_fns, 0, 0 }, 11950 { "rsr.itlbcfg", 284 /* xt_iclass_rsr.itlbcfg */, 11951 0, 11952 Opcode_rsr_itlbcfg_encode_fns, 0, 0 }, 11953 { "wsr.itlbcfg", 285 /* xt_iclass_wsr.itlbcfg */, 11954 0, 11955 Opcode_wsr_itlbcfg_encode_fns, 0, 0 }, 11956 { "xsr.itlbcfg", 286 /* xt_iclass_xsr.itlbcfg */, 11957 0, 11958 Opcode_xsr_itlbcfg_encode_fns, 0, 0 }, 11959 { "rsr.dtlbcfg", 287 /* xt_iclass_rsr.dtlbcfg */, 11960 0, 11961 Opcode_rsr_dtlbcfg_encode_fns, 0, 0 }, 11962 { "wsr.dtlbcfg", 288 /* xt_iclass_wsr.dtlbcfg */, 11963 0, 11964 Opcode_wsr_dtlbcfg_encode_fns, 0, 0 }, 11965 { "xsr.dtlbcfg", 289 /* xt_iclass_xsr.dtlbcfg */, 11966 0, 11967 Opcode_xsr_dtlbcfg_encode_fns, 0, 0 }, 11968 { "idtlb", 290 /* xt_iclass_idtlb */, 11969 0, 11970 Opcode_idtlb_encode_fns, 0, 0 }, 11971 { "pdtlb", 291 /* xt_iclass_rdtlb */, 11972 0, 11973 Opcode_pdtlb_encode_fns, 0, 0 }, 11974 { "rdtlb0", 291 /* xt_iclass_rdtlb */, 11975 0, 11976 Opcode_rdtlb0_encode_fns, 0, 0 }, 11977 { "rdtlb1", 291 /* xt_iclass_rdtlb */, 11978 0, 11979 Opcode_rdtlb1_encode_fns, 0, 0 }, 11980 { "wdtlb", 292 /* xt_iclass_wdtlb */, 11981 0, 11982 Opcode_wdtlb_encode_fns, 0, 0 }, 11983 { "iitlb", 293 /* xt_iclass_iitlb */, 11984 0, 11985 Opcode_iitlb_encode_fns, 0, 0 }, 11986 { "pitlb", 294 /* xt_iclass_ritlb */, 11987 0, 11988 Opcode_pitlb_encode_fns, 0, 0 }, 11989 { "ritlb0", 294 /* xt_iclass_ritlb */, 11990 0, 11991 Opcode_ritlb0_encode_fns, 0, 0 }, 11992 { "ritlb1", 294 /* xt_iclass_ritlb */, 11993 0, 11994 Opcode_ritlb1_encode_fns, 0, 0 }, 11995 { "witlb", 295 /* xt_iclass_witlb */, 11996 0, 11997 Opcode_witlb_encode_fns, 0, 0 }, 11998 { "ldpte", 296 /* xt_iclass_ldpte */, 11999 0, 12000 Opcode_ldpte_encode_fns, 0, 0 }, 12001 { "hwwitlba", 297 /* xt_iclass_hwwitlba */, 12002 XTENSA_OPCODE_IS_BRANCH, 12003 Opcode_hwwitlba_encode_fns, 0, 0 }, 12004 { "hwwdtlba", 298 /* xt_iclass_hwwdtlba */, 12005 0, 12006 Opcode_hwwdtlba_encode_fns, 0, 0 }, 12007 { "rsr.cpenable", 299 /* xt_iclass_rsr.cpenable */, 12008 0, 12009 Opcode_rsr_cpenable_encode_fns, 0, 0 }, 12010 { "wsr.cpenable", 300 /* xt_iclass_wsr.cpenable */, 12011 0, 12012 Opcode_wsr_cpenable_encode_fns, 0, 0 }, 12013 { "xsr.cpenable", 301 /* xt_iclass_xsr.cpenable */, 12014 0, 12015 Opcode_xsr_cpenable_encode_fns, 0, 0 }, 12016 { "clamps", 302 /* xt_iclass_clamp */, 12017 0, 12018 Opcode_clamps_encode_fns, 0, 0 }, 12019 { "min", 303 /* xt_iclass_minmax */, 12020 0, 12021 Opcode_min_encode_fns, 0, 0 }, 12022 { "max", 303 /* xt_iclass_minmax */, 12023 0, 12024 Opcode_max_encode_fns, 0, 0 }, 12025 { "minu", 303 /* xt_iclass_minmax */, 12026 0, 12027 Opcode_minu_encode_fns, 0, 0 }, 12028 { "maxu", 303 /* xt_iclass_minmax */, 12029 0, 12030 Opcode_maxu_encode_fns, 0, 0 }, 12031 { "nsa", 304 /* xt_iclass_nsa */, 12032 0, 12033 Opcode_nsa_encode_fns, 0, 0 }, 12034 { "nsau", 304 /* xt_iclass_nsa */, 12035 0, 12036 Opcode_nsau_encode_fns, 0, 0 }, 12037 { "sext", 305 /* xt_iclass_sx */, 12038 0, 12039 Opcode_sext_encode_fns, 0, 0 }, 12040 { "l32ai", 306 /* xt_iclass_l32ai */, 12041 0, 12042 Opcode_l32ai_encode_fns, 0, 0 }, 12043 { "s32ri", 307 /* xt_iclass_s32ri */, 12044 0, 12045 Opcode_s32ri_encode_fns, 0, 0 }, 12046 { "s32c1i", 308 /* xt_iclass_s32c1i */, 12047 0, 12048 Opcode_s32c1i_encode_fns, 0, 0 }, 12049 { "rsr.scompare1", 309 /* xt_iclass_rsr.scompare1 */, 12050 0, 12051 Opcode_rsr_scompare1_encode_fns, 0, 0 }, 12052 { "wsr.scompare1", 310 /* xt_iclass_wsr.scompare1 */, 12053 0, 12054 Opcode_wsr_scompare1_encode_fns, 0, 0 }, 12055 { "xsr.scompare1", 311 /* xt_iclass_xsr.scompare1 */, 12056 0, 12057 Opcode_xsr_scompare1_encode_fns, 0, 0 }, 12058 { "quou", 312 /* xt_iclass_div */, 12059 0, 12060 Opcode_quou_encode_fns, 0, 0 }, 12061 { "quos", 312 /* xt_iclass_div */, 12062 0, 12063 Opcode_quos_encode_fns, 0, 0 }, 12064 { "remu", 312 /* xt_iclass_div */, 12065 0, 12066 Opcode_remu_encode_fns, 0, 0 }, 12067 { "rems", 312 /* xt_iclass_div */, 12068 0, 12069 Opcode_rems_encode_fns, 0, 0 }, 12070 { "mull", 313 /* xt_mul32 */, 12071 0, 12072 Opcode_mull_encode_fns, 0, 0 }, 12073 { "rur.expstate", 314 /* rur_expstate */, 12074 0, 12075 Opcode_rur_expstate_encode_fns, 0, 0 }, 12076 { "wur.expstate", 315 /* wur_expstate */, 12077 0, 12078 Opcode_wur_expstate_encode_fns, 0, 0 }, 12079 { "read_impwire", 316 /* iclass_READ_IMPWIRE */, 12080 0, 12081 Opcode_read_impwire_encode_fns, 0, 0 }, 12082 { "setb_expstate", 317 /* iclass_SETB_EXPSTATE */, 12083 0, 12084 Opcode_setb_expstate_encode_fns, 0, 0 }, 12085 { "clrb_expstate", 318 /* iclass_CLRB_EXPSTATE */, 12086 0, 12087 Opcode_clrb_expstate_encode_fns, 0, 0 }, 12088 { "wrmsk_expstate", 319 /* iclass_WRMSK_EXPSTATE */, 12089 0, 12090 Opcode_wrmsk_expstate_encode_fns, 0, 0 } 12091}; 12092 12093 12094/* Slot-specific opcode decode functions. */ 12095 12096static int 12097Slot_inst_decode (const xtensa_insnbuf insn) 12098{ 12099 switch (Field_op0_Slot_inst_get (insn)) 12100 { 12101 case 0: 12102 switch (Field_op1_Slot_inst_get (insn)) 12103 { 12104 case 0: 12105 switch (Field_op2_Slot_inst_get (insn)) 12106 { 12107 case 0: 12108 switch (Field_r_Slot_inst_get (insn)) 12109 { 12110 case 0: 12111 switch (Field_m_Slot_inst_get (insn)) 12112 { 12113 case 0: 12114 if (Field_s_Slot_inst_get (insn) == 0 && 12115 Field_n_Slot_inst_get (insn) == 0) 12116 return 79; /* ill */ 12117 break; 12118 case 2: 12119 switch (Field_n_Slot_inst_get (insn)) 12120 { 12121 case 0: 12122 return 98; /* ret */ 12123 case 1: 12124 return 14; /* retw */ 12125 case 2: 12126 return 81; /* jx */ 12127 } 12128 break; 12129 case 3: 12130 switch (Field_n_Slot_inst_get (insn)) 12131 { 12132 case 0: 12133 return 77; /* callx0 */ 12134 case 1: 12135 return 10; /* callx4 */ 12136 case 2: 12137 return 9; /* callx8 */ 12138 case 3: 12139 return 8; /* callx12 */ 12140 } 12141 break; 12142 } 12143 break; 12144 case 1: 12145 return 12; /* movsp */ 12146 case 2: 12147 if (Field_s_Slot_inst_get (insn) == 0) 12148 { 12149 switch (Field_t_Slot_inst_get (insn)) 12150 { 12151 case 0: 12152 return 116; /* isync */ 12153 case 1: 12154 return 117; /* rsync */ 12155 case 2: 12156 return 118; /* esync */ 12157 case 3: 12158 return 119; /* dsync */ 12159 case 8: 12160 return 0; /* excw */ 12161 case 12: 12162 return 114; /* memw */ 12163 case 13: 12164 return 115; /* extw */ 12165 case 15: 12166 return 97; /* nop */ 12167 } 12168 } 12169 break; 12170 case 3: 12171 switch (Field_t_Slot_inst_get (insn)) 12172 { 12173 case 0: 12174 switch (Field_s_Slot_inst_get (insn)) 12175 { 12176 case 0: 12177 return 1; /* rfe */ 12178 case 2: 12179 return 2; /* rfde */ 12180 case 4: 12181 return 16; /* rfwo */ 12182 case 5: 12183 return 17; /* rfwu */ 12184 } 12185 break; 12186 case 1: 12187 return 310; /* rfi */ 12188 } 12189 break; 12190 case 4: 12191 return 318; /* break */ 12192 case 5: 12193 switch (Field_s_Slot_inst_get (insn)) 12194 { 12195 case 0: 12196 if (Field_t_Slot_inst_get (insn) == 0) 12197 return 3; /* syscall */ 12198 break; 12199 case 1: 12200 if (Field_t_Slot_inst_get (insn) == 0) 12201 return 4; /* simcall */ 12202 break; 12203 } 12204 break; 12205 case 6: 12206 return 120; /* rsil */ 12207 case 7: 12208 if (Field_t_Slot_inst_get (insn) == 0) 12209 return 311; /* waiti */ 12210 break; 12211 } 12212 break; 12213 case 1: 12214 return 49; /* and */ 12215 case 2: 12216 return 50; /* or */ 12217 case 3: 12218 return 51; /* xor */ 12219 case 4: 12220 switch (Field_r_Slot_inst_get (insn)) 12221 { 12222 case 0: 12223 if (Field_t_Slot_inst_get (insn) == 0) 12224 return 102; /* ssr */ 12225 break; 12226 case 1: 12227 if (Field_t_Slot_inst_get (insn) == 0) 12228 return 103; /* ssl */ 12229 break; 12230 case 2: 12231 if (Field_t_Slot_inst_get (insn) == 0) 12232 return 104; /* ssa8l */ 12233 break; 12234 case 3: 12235 if (Field_t_Slot_inst_get (insn) == 0) 12236 return 105; /* ssa8b */ 12237 break; 12238 case 4: 12239 if (Field_thi3_Slot_inst_get (insn) == 0) 12240 return 106; /* ssai */ 12241 break; 12242 case 8: 12243 if (Field_s_Slot_inst_get (insn) == 0) 12244 return 13; /* rotw */ 12245 break; 12246 case 14: 12247 return 426; /* nsa */ 12248 case 15: 12249 return 427; /* nsau */ 12250 } 12251 break; 12252 case 5: 12253 switch (Field_r_Slot_inst_get (insn)) 12254 { 12255 case 1: 12256 return 416; /* hwwitlba */ 12257 case 3: 12258 return 412; /* ritlb0 */ 12259 case 4: 12260 if (Field_t_Slot_inst_get (insn) == 0) 12261 return 410; /* iitlb */ 12262 break; 12263 case 5: 12264 return 411; /* pitlb */ 12265 case 6: 12266 return 414; /* witlb */ 12267 case 7: 12268 return 413; /* ritlb1 */ 12269 case 9: 12270 return 417; /* hwwdtlba */ 12271 case 11: 12272 return 407; /* rdtlb0 */ 12273 case 12: 12274 if (Field_t_Slot_inst_get (insn) == 0) 12275 return 405; /* idtlb */ 12276 break; 12277 case 13: 12278 return 406; /* pdtlb */ 12279 case 14: 12280 return 409; /* wdtlb */ 12281 case 15: 12282 return 408; /* rdtlb1 */ 12283 } 12284 break; 12285 case 6: 12286 switch (Field_s_Slot_inst_get (insn)) 12287 { 12288 case 0: 12289 return 95; /* neg */ 12290 case 1: 12291 return 96; /* abs */ 12292 } 12293 break; 12294 case 8: 12295 return 41; /* add */ 12296 case 9: 12297 return 43; /* addx2 */ 12298 case 10: 12299 return 44; /* addx4 */ 12300 case 11: 12301 return 45; /* addx8 */ 12302 case 12: 12303 return 42; /* sub */ 12304 case 13: 12305 return 46; /* subx2 */ 12306 case 14: 12307 return 47; /* subx4 */ 12308 case 15: 12309 return 48; /* subx8 */ 12310 } 12311 break; 12312 case 1: 12313 switch (Field_op2_Slot_inst_get (insn)) 12314 { 12315 case 0: 12316 case 1: 12317 return 111; /* slli */ 12318 case 2: 12319 case 3: 12320 return 112; /* srai */ 12321 case 4: 12322 return 113; /* srli */ 12323 case 6: 12324 switch (Field_sr_Slot_inst_get (insn)) 12325 { 12326 case 0: 12327 return 129; /* xsr.lbeg */ 12328 case 1: 12329 return 123; /* xsr.lend */ 12330 case 2: 12331 return 126; /* xsr.lcount */ 12332 case 3: 12333 return 132; /* xsr.sar */ 12334 case 5: 12335 return 135; /* xsr.litbase */ 12336 case 12: 12337 return 434; /* xsr.scompare1 */ 12338 case 16: 12339 return 306; /* xsr.acclo */ 12340 case 17: 12341 return 309; /* xsr.acchi */ 12342 case 32: 12343 return 294; /* xsr.m0 */ 12344 case 33: 12345 return 297; /* xsr.m1 */ 12346 case 34: 12347 return 300; /* xsr.m2 */ 12348 case 35: 12349 return 303; /* xsr.m3 */ 12350 case 72: 12351 return 22; /* xsr.windowbase */ 12352 case 73: 12353 return 25; /* xsr.windowstart */ 12354 case 83: 12355 return 395; /* xsr.ptevaddr */ 12356 case 90: 12357 return 398; /* xsr.rasid */ 12358 case 91: 12359 return 401; /* xsr.itlbcfg */ 12360 case 92: 12361 return 404; /* xsr.dtlbcfg */ 12362 case 96: 12363 return 340; /* xsr.ibreakenable */ 12364 case 104: 12365 return 352; /* xsr.ddr */ 12366 case 128: 12367 return 334; /* xsr.ibreaka0 */ 12368 case 129: 12369 return 337; /* xsr.ibreaka1 */ 12370 case 144: 12371 return 322; /* xsr.dbreaka0 */ 12372 case 145: 12373 return 328; /* xsr.dbreaka1 */ 12374 case 160: 12375 return 325; /* xsr.dbreakc0 */ 12376 case 161: 12377 return 331; /* xsr.dbreakc1 */ 12378 case 177: 12379 return 143; /* xsr.epc1 */ 12380 case 178: 12381 return 149; /* xsr.epc2 */ 12382 case 179: 12383 return 155; /* xsr.epc3 */ 12384 case 180: 12385 return 161; /* xsr.epc4 */ 12386 case 181: 12387 return 167; /* xsr.epc5 */ 12388 case 182: 12389 return 173; /* xsr.epc6 */ 12390 case 183: 12391 return 179; /* xsr.epc7 */ 12392 case 192: 12393 return 206; /* xsr.depc */ 12394 case 194: 12395 return 185; /* xsr.eps2 */ 12396 case 195: 12397 return 188; /* xsr.eps3 */ 12398 case 196: 12399 return 191; /* xsr.eps4 */ 12400 case 197: 12401 return 194; /* xsr.eps5 */ 12402 case 198: 12403 return 197; /* xsr.eps6 */ 12404 case 199: 12405 return 200; /* xsr.eps7 */ 12406 case 209: 12407 return 146; /* xsr.excsave1 */ 12408 case 210: 12409 return 152; /* xsr.excsave2 */ 12410 case 211: 12411 return 158; /* xsr.excsave3 */ 12412 case 212: 12413 return 164; /* xsr.excsave4 */ 12414 case 213: 12415 return 170; /* xsr.excsave5 */ 12416 case 214: 12417 return 176; /* xsr.excsave6 */ 12418 case 215: 12419 return 182; /* xsr.excsave7 */ 12420 case 224: 12421 return 420; /* xsr.cpenable */ 12422 case 228: 12423 return 317; /* xsr.intenable */ 12424 case 230: 12425 return 140; /* xsr.ps */ 12426 case 231: 12427 return 219; /* xsr.vecbase */ 12428 case 232: 12429 return 209; /* xsr.exccause */ 12430 case 233: 12431 return 343; /* xsr.debugcause */ 12432 case 234: 12433 return 358; /* xsr.ccount */ 12434 case 236: 12435 return 346; /* xsr.icount */ 12436 case 237: 12437 return 349; /* xsr.icountlevel */ 12438 case 238: 12439 return 203; /* xsr.excvaddr */ 12440 case 240: 12441 return 361; /* xsr.ccompare0 */ 12442 case 241: 12443 return 364; /* xsr.ccompare1 */ 12444 case 242: 12445 return 367; /* xsr.ccompare2 */ 12446 case 244: 12447 return 212; /* xsr.misc0 */ 12448 case 245: 12449 return 215; /* xsr.misc1 */ 12450 } 12451 break; 12452 case 8: 12453 return 108; /* src */ 12454 case 9: 12455 if (Field_s_Slot_inst_get (insn) == 0) 12456 return 109; /* srl */ 12457 break; 12458 case 10: 12459 if (Field_t_Slot_inst_get (insn) == 0) 12460 return 107; /* sll */ 12461 break; 12462 case 11: 12463 if (Field_s_Slot_inst_get (insn) == 0) 12464 return 110; /* sra */ 12465 break; 12466 case 12: 12467 return 290; /* mul16u */ 12468 case 13: 12469 return 291; /* mul16s */ 12470 case 15: 12471 switch (Field_r_Slot_inst_get (insn)) 12472 { 12473 case 0: 12474 return 374; /* lict */ 12475 case 1: 12476 return 376; /* sict */ 12477 case 2: 12478 return 375; /* licw */ 12479 case 3: 12480 return 377; /* sicw */ 12481 case 8: 12482 return 392; /* ldct */ 12483 case 9: 12484 return 391; /* sdct */ 12485 case 14: 12486 if (Field_t_Slot_inst_get (insn) == 0) 12487 return 353; /* rfdo */ 12488 if (Field_t_Slot_inst_get (insn) == 1) 12489 return 354; /* rfdd */ 12490 break; 12491 case 15: 12492 return 415; /* ldpte */ 12493 } 12494 break; 12495 } 12496 break; 12497 case 2: 12498 switch (Field_op2_Slot_inst_get (insn)) 12499 { 12500 case 8: 12501 return 439; /* mull */ 12502 case 12: 12503 return 435; /* quou */ 12504 case 13: 12505 return 436; /* quos */ 12506 case 14: 12507 return 437; /* remu */ 12508 case 15: 12509 return 438; /* rems */ 12510 } 12511 break; 12512 case 3: 12513 switch (Field_op2_Slot_inst_get (insn)) 12514 { 12515 case 0: 12516 switch (Field_sr_Slot_inst_get (insn)) 12517 { 12518 case 0: 12519 return 127; /* rsr.lbeg */ 12520 case 1: 12521 return 121; /* rsr.lend */ 12522 case 2: 12523 return 124; /* rsr.lcount */ 12524 case 3: 12525 return 130; /* rsr.sar */ 12526 case 5: 12527 return 133; /* rsr.litbase */ 12528 case 12: 12529 return 432; /* rsr.scompare1 */ 12530 case 16: 12531 return 304; /* rsr.acclo */ 12532 case 17: 12533 return 307; /* rsr.acchi */ 12534 case 32: 12535 return 292; /* rsr.m0 */ 12536 case 33: 12537 return 295; /* rsr.m1 */ 12538 case 34: 12539 return 298; /* rsr.m2 */ 12540 case 35: 12541 return 301; /* rsr.m3 */ 12542 case 72: 12543 return 20; /* rsr.windowbase */ 12544 case 73: 12545 return 23; /* rsr.windowstart */ 12546 case 83: 12547 return 394; /* rsr.ptevaddr */ 12548 case 90: 12549 return 396; /* rsr.rasid */ 12550 case 91: 12551 return 399; /* rsr.itlbcfg */ 12552 case 92: 12553 return 402; /* rsr.dtlbcfg */ 12554 case 96: 12555 return 338; /* rsr.ibreakenable */ 12556 case 104: 12557 return 350; /* rsr.ddr */ 12558 case 128: 12559 return 332; /* rsr.ibreaka0 */ 12560 case 129: 12561 return 335; /* rsr.ibreaka1 */ 12562 case 144: 12563 return 320; /* rsr.dbreaka0 */ 12564 case 145: 12565 return 326; /* rsr.dbreaka1 */ 12566 case 160: 12567 return 323; /* rsr.dbreakc0 */ 12568 case 161: 12569 return 329; /* rsr.dbreakc1 */ 12570 case 176: 12571 return 136; /* rsr.176 */ 12572 case 177: 12573 return 141; /* rsr.epc1 */ 12574 case 178: 12575 return 147; /* rsr.epc2 */ 12576 case 179: 12577 return 153; /* rsr.epc3 */ 12578 case 180: 12579 return 159; /* rsr.epc4 */ 12580 case 181: 12581 return 165; /* rsr.epc5 */ 12582 case 182: 12583 return 171; /* rsr.epc6 */ 12584 case 183: 12585 return 177; /* rsr.epc7 */ 12586 case 192: 12587 return 204; /* rsr.depc */ 12588 case 194: 12589 return 183; /* rsr.eps2 */ 12590 case 195: 12591 return 186; /* rsr.eps3 */ 12592 case 196: 12593 return 189; /* rsr.eps4 */ 12594 case 197: 12595 return 192; /* rsr.eps5 */ 12596 case 198: 12597 return 195; /* rsr.eps6 */ 12598 case 199: 12599 return 198; /* rsr.eps7 */ 12600 case 208: 12601 return 137; /* rsr.208 */ 12602 case 209: 12603 return 144; /* rsr.excsave1 */ 12604 case 210: 12605 return 150; /* rsr.excsave2 */ 12606 case 211: 12607 return 156; /* rsr.excsave3 */ 12608 case 212: 12609 return 162; /* rsr.excsave4 */ 12610 case 213: 12611 return 168; /* rsr.excsave5 */ 12612 case 214: 12613 return 174; /* rsr.excsave6 */ 12614 case 215: 12615 return 180; /* rsr.excsave7 */ 12616 case 224: 12617 return 418; /* rsr.cpenable */ 12618 case 226: 12619 return 312; /* rsr.interrupt */ 12620 case 228: 12621 return 315; /* rsr.intenable */ 12622 case 230: 12623 return 138; /* rsr.ps */ 12624 case 231: 12625 return 217; /* rsr.vecbase */ 12626 case 232: 12627 return 207; /* rsr.exccause */ 12628 case 233: 12629 return 341; /* rsr.debugcause */ 12630 case 234: 12631 return 356; /* rsr.ccount */ 12632 case 235: 12633 return 216; /* rsr.prid */ 12634 case 236: 12635 return 344; /* rsr.icount */ 12636 case 237: 12637 return 347; /* rsr.icountlevel */ 12638 case 238: 12639 return 201; /* rsr.excvaddr */ 12640 case 240: 12641 return 359; /* rsr.ccompare0 */ 12642 case 241: 12643 return 362; /* rsr.ccompare1 */ 12644 case 242: 12645 return 365; /* rsr.ccompare2 */ 12646 case 244: 12647 return 210; /* rsr.misc0 */ 12648 case 245: 12649 return 213; /* rsr.misc1 */ 12650 } 12651 break; 12652 case 1: 12653 switch (Field_sr_Slot_inst_get (insn)) 12654 { 12655 case 0: 12656 return 128; /* wsr.lbeg */ 12657 case 1: 12658 return 122; /* wsr.lend */ 12659 case 2: 12660 return 125; /* wsr.lcount */ 12661 case 3: 12662 return 131; /* wsr.sar */ 12663 case 5: 12664 return 134; /* wsr.litbase */ 12665 case 12: 12666 return 433; /* wsr.scompare1 */ 12667 case 16: 12668 return 305; /* wsr.acclo */ 12669 case 17: 12670 return 308; /* wsr.acchi */ 12671 case 32: 12672 return 293; /* wsr.m0 */ 12673 case 33: 12674 return 296; /* wsr.m1 */ 12675 case 34: 12676 return 299; /* wsr.m2 */ 12677 case 35: 12678 return 302; /* wsr.m3 */ 12679 case 72: 12680 return 21; /* wsr.windowbase */ 12681 case 73: 12682 return 24; /* wsr.windowstart */ 12683 case 83: 12684 return 393; /* wsr.ptevaddr */ 12685 case 89: 12686 return 355; /* wsr.mmid */ 12687 case 90: 12688 return 397; /* wsr.rasid */ 12689 case 91: 12690 return 400; /* wsr.itlbcfg */ 12691 case 92: 12692 return 403; /* wsr.dtlbcfg */ 12693 case 96: 12694 return 339; /* wsr.ibreakenable */ 12695 case 104: 12696 return 351; /* wsr.ddr */ 12697 case 128: 12698 return 333; /* wsr.ibreaka0 */ 12699 case 129: 12700 return 336; /* wsr.ibreaka1 */ 12701 case 144: 12702 return 321; /* wsr.dbreaka0 */ 12703 case 145: 12704 return 327; /* wsr.dbreaka1 */ 12705 case 160: 12706 return 324; /* wsr.dbreakc0 */ 12707 case 161: 12708 return 330; /* wsr.dbreakc1 */ 12709 case 177: 12710 return 142; /* wsr.epc1 */ 12711 case 178: 12712 return 148; /* wsr.epc2 */ 12713 case 179: 12714 return 154; /* wsr.epc3 */ 12715 case 180: 12716 return 160; /* wsr.epc4 */ 12717 case 181: 12718 return 166; /* wsr.epc5 */ 12719 case 182: 12720 return 172; /* wsr.epc6 */ 12721 case 183: 12722 return 178; /* wsr.epc7 */ 12723 case 192: 12724 return 205; /* wsr.depc */ 12725 case 194: 12726 return 184; /* wsr.eps2 */ 12727 case 195: 12728 return 187; /* wsr.eps3 */ 12729 case 196: 12730 return 190; /* wsr.eps4 */ 12731 case 197: 12732 return 193; /* wsr.eps5 */ 12733 case 198: 12734 return 196; /* wsr.eps6 */ 12735 case 199: 12736 return 199; /* wsr.eps7 */ 12737 case 209: 12738 return 145; /* wsr.excsave1 */ 12739 case 210: 12740 return 151; /* wsr.excsave2 */ 12741 case 211: 12742 return 157; /* wsr.excsave3 */ 12743 case 212: 12744 return 163; /* wsr.excsave4 */ 12745 case 213: 12746 return 169; /* wsr.excsave5 */ 12747 case 214: 12748 return 175; /* wsr.excsave6 */ 12749 case 215: 12750 return 181; /* wsr.excsave7 */ 12751 case 224: 12752 return 419; /* wsr.cpenable */ 12753 case 226: 12754 return 313; /* wsr.intset */ 12755 case 227: 12756 return 314; /* wsr.intclear */ 12757 case 228: 12758 return 316; /* wsr.intenable */ 12759 case 230: 12760 return 139; /* wsr.ps */ 12761 case 231: 12762 return 218; /* wsr.vecbase */ 12763 case 232: 12764 return 208; /* wsr.exccause */ 12765 case 233: 12766 return 342; /* wsr.debugcause */ 12767 case 234: 12768 return 357; /* wsr.ccount */ 12769 case 236: 12770 return 345; /* wsr.icount */ 12771 case 237: 12772 return 348; /* wsr.icountlevel */ 12773 case 238: 12774 return 202; /* wsr.excvaddr */ 12775 case 240: 12776 return 360; /* wsr.ccompare0 */ 12777 case 241: 12778 return 363; /* wsr.ccompare1 */ 12779 case 242: 12780 return 366; /* wsr.ccompare2 */ 12781 case 244: 12782 return 211; /* wsr.misc0 */ 12783 case 245: 12784 return 214; /* wsr.misc1 */ 12785 } 12786 break; 12787 case 2: 12788 return 428; /* sext */ 12789 case 3: 12790 return 421; /* clamps */ 12791 case 4: 12792 return 422; /* min */ 12793 case 5: 12794 return 423; /* max */ 12795 case 6: 12796 return 424; /* minu */ 12797 case 7: 12798 return 425; /* maxu */ 12799 case 8: 12800 return 91; /* moveqz */ 12801 case 9: 12802 return 92; /* movnez */ 12803 case 10: 12804 return 93; /* movltz */ 12805 case 11: 12806 return 94; /* movgez */ 12807 case 14: 12808 switch (Field_st_Slot_inst_get (insn)) 12809 { 12810 case 230: 12811 return 440; /* rur.expstate */ 12812 case 231: 12813 return 37; /* rur.threadptr */ 12814 } 12815 break; 12816 case 15: 12817 switch (Field_sr_Slot_inst_get (insn)) 12818 { 12819 case 230: 12820 return 441; /* wur.expstate */ 12821 case 231: 12822 return 38; /* wur.threadptr */ 12823 } 12824 break; 12825 } 12826 break; 12827 case 4: 12828 case 5: 12829 return 78; /* extui */ 12830 case 9: 12831 switch (Field_op2_Slot_inst_get (insn)) 12832 { 12833 case 0: 12834 return 18; /* l32e */ 12835 case 4: 12836 return 19; /* s32e */ 12837 } 12838 break; 12839 } 12840 switch (Field_r_Slot_inst_get (insn)) 12841 { 12842 case 0: 12843 if (Field_s_Slot_inst_get (insn) == 0 && 12844 Field_op2_Slot_inst_get (insn) == 0 && 12845 Field_op1_Slot_inst_get (insn) == 14) 12846 return 442; /* read_impwire */ 12847 break; 12848 case 1: 12849 if (Field_s3to1_Slot_inst_get (insn) == 0 && 12850 Field_op2_Slot_inst_get (insn) == 0 && 12851 Field_op1_Slot_inst_get (insn) == 14) 12852 return 443; /* setb_expstate */ 12853 if (Field_s3to1_Slot_inst_get (insn) == 1 && 12854 Field_op2_Slot_inst_get (insn) == 0 && 12855 Field_op1_Slot_inst_get (insn) == 14) 12856 return 444; /* clrb_expstate */ 12857 break; 12858 case 2: 12859 if (Field_op2_Slot_inst_get (insn) == 0 && 12860 Field_op1_Slot_inst_get (insn) == 14) 12861 return 445; /* wrmsk_expstate */ 12862 break; 12863 } 12864 break; 12865 case 1: 12866 return 85; /* l32r */ 12867 case 2: 12868 switch (Field_r_Slot_inst_get (insn)) 12869 { 12870 case 0: 12871 return 86; /* l8ui */ 12872 case 1: 12873 return 82; /* l16ui */ 12874 case 2: 12875 return 84; /* l32i */ 12876 case 4: 12877 return 101; /* s8i */ 12878 case 5: 12879 return 99; /* s16i */ 12880 case 6: 12881 return 100; /* s32i */ 12882 case 7: 12883 switch (Field_t_Slot_inst_get (insn)) 12884 { 12885 case 0: 12886 return 384; /* dpfr */ 12887 case 1: 12888 return 385; /* dpfw */ 12889 case 2: 12890 return 386; /* dpfro */ 12891 case 3: 12892 return 387; /* dpfwo */ 12893 case 4: 12894 return 378; /* dhwb */ 12895 case 5: 12896 return 379; /* dhwbi */ 12897 case 6: 12898 return 382; /* dhi */ 12899 case 7: 12900 return 383; /* dii */ 12901 case 8: 12902 switch (Field_op1_Slot_inst_get (insn)) 12903 { 12904 case 0: 12905 return 388; /* dpfl */ 12906 case 2: 12907 return 389; /* dhu */ 12908 case 3: 12909 return 390; /* diu */ 12910 case 4: 12911 return 380; /* diwb */ 12912 case 5: 12913 return 381; /* diwbi */ 12914 } 12915 break; 12916 case 12: 12917 return 368; /* ipf */ 12918 case 13: 12919 switch (Field_op1_Slot_inst_get (insn)) 12920 { 12921 case 0: 12922 return 370; /* ipfl */ 12923 case 2: 12924 return 371; /* ihu */ 12925 case 3: 12926 return 372; /* iiu */ 12927 } 12928 break; 12929 case 14: 12930 return 369; /* ihi */ 12931 case 15: 12932 return 373; /* iii */ 12933 } 12934 break; 12935 case 9: 12936 return 83; /* l16si */ 12937 case 10: 12938 return 90; /* movi */ 12939 case 11: 12940 return 429; /* l32ai */ 12941 case 12: 12942 return 39; /* addi */ 12943 case 13: 12944 return 40; /* addmi */ 12945 case 14: 12946 return 431; /* s32c1i */ 12947 case 15: 12948 return 430; /* s32ri */ 12949 } 12950 break; 12951 case 4: 12952 switch (Field_op2_Slot_inst_get (insn)) 12953 { 12954 case 0: 12955 switch (Field_op1_Slot_inst_get (insn)) 12956 { 12957 case 8: 12958 if (Field_t3_Slot_inst_get (insn) == 0 && 12959 Field_tlo_Slot_inst_get (insn) == 0 && 12960 Field_r3_Slot_inst_get (insn) == 0) 12961 return 281; /* mula.dd.ll.ldinc */ 12962 break; 12963 case 9: 12964 if (Field_t3_Slot_inst_get (insn) == 0 && 12965 Field_tlo_Slot_inst_get (insn) == 0 && 12966 Field_r3_Slot_inst_get (insn) == 0) 12967 return 283; /* mula.dd.hl.ldinc */ 12968 break; 12969 case 10: 12970 if (Field_t3_Slot_inst_get (insn) == 0 && 12971 Field_tlo_Slot_inst_get (insn) == 0 && 12972 Field_r3_Slot_inst_get (insn) == 0) 12973 return 285; /* mula.dd.lh.ldinc */ 12974 break; 12975 case 11: 12976 if (Field_t3_Slot_inst_get (insn) == 0 && 12977 Field_tlo_Slot_inst_get (insn) == 0 && 12978 Field_r3_Slot_inst_get (insn) == 0) 12979 return 287; /* mula.dd.hh.ldinc */ 12980 break; 12981 } 12982 break; 12983 case 1: 12984 switch (Field_op1_Slot_inst_get (insn)) 12985 { 12986 case 8: 12987 if (Field_t3_Slot_inst_get (insn) == 0 && 12988 Field_tlo_Slot_inst_get (insn) == 0 && 12989 Field_r3_Slot_inst_get (insn) == 0) 12990 return 280; /* mula.dd.ll.lddec */ 12991 break; 12992 case 9: 12993 if (Field_t3_Slot_inst_get (insn) == 0 && 12994 Field_tlo_Slot_inst_get (insn) == 0 && 12995 Field_r3_Slot_inst_get (insn) == 0) 12996 return 282; /* mula.dd.hl.lddec */ 12997 break; 12998 case 10: 12999 if (Field_t3_Slot_inst_get (insn) == 0 && 13000 Field_tlo_Slot_inst_get (insn) == 0 && 13001 Field_r3_Slot_inst_get (insn) == 0) 13002 return 284; /* mula.dd.lh.lddec */ 13003 break; 13004 case 11: 13005 if (Field_t3_Slot_inst_get (insn) == 0 && 13006 Field_tlo_Slot_inst_get (insn) == 0 && 13007 Field_r3_Slot_inst_get (insn) == 0) 13008 return 286; /* mula.dd.hh.lddec */ 13009 break; 13010 } 13011 break; 13012 case 2: 13013 switch (Field_op1_Slot_inst_get (insn)) 13014 { 13015 case 4: 13016 if (Field_s_Slot_inst_get (insn) == 0 && 13017 Field_w_Slot_inst_get (insn) == 0 && 13018 Field_r3_Slot_inst_get (insn) == 0 && 13019 Field_t3_Slot_inst_get (insn) == 0 && 13020 Field_tlo_Slot_inst_get (insn) == 0) 13021 return 236; /* mul.dd.ll */ 13022 break; 13023 case 5: 13024 if (Field_s_Slot_inst_get (insn) == 0 && 13025 Field_w_Slot_inst_get (insn) == 0 && 13026 Field_r3_Slot_inst_get (insn) == 0 && 13027 Field_t3_Slot_inst_get (insn) == 0 && 13028 Field_tlo_Slot_inst_get (insn) == 0) 13029 return 237; /* mul.dd.hl */ 13030 break; 13031 case 6: 13032 if (Field_s_Slot_inst_get (insn) == 0 && 13033 Field_w_Slot_inst_get (insn) == 0 && 13034 Field_r3_Slot_inst_get (insn) == 0 && 13035 Field_t3_Slot_inst_get (insn) == 0 && 13036 Field_tlo_Slot_inst_get (insn) == 0) 13037 return 238; /* mul.dd.lh */ 13038 break; 13039 case 7: 13040 if (Field_s_Slot_inst_get (insn) == 0 && 13041 Field_w_Slot_inst_get (insn) == 0 && 13042 Field_r3_Slot_inst_get (insn) == 0 && 13043 Field_t3_Slot_inst_get (insn) == 0 && 13044 Field_tlo_Slot_inst_get (insn) == 0) 13045 return 239; /* mul.dd.hh */ 13046 break; 13047 case 8: 13048 if (Field_s_Slot_inst_get (insn) == 0 && 13049 Field_w_Slot_inst_get (insn) == 0 && 13050 Field_r3_Slot_inst_get (insn) == 0 && 13051 Field_t3_Slot_inst_get (insn) == 0 && 13052 Field_tlo_Slot_inst_get (insn) == 0) 13053 return 264; /* mula.dd.ll */ 13054 break; 13055 case 9: 13056 if (Field_s_Slot_inst_get (insn) == 0 && 13057 Field_w_Slot_inst_get (insn) == 0 && 13058 Field_r3_Slot_inst_get (insn) == 0 && 13059 Field_t3_Slot_inst_get (insn) == 0 && 13060 Field_tlo_Slot_inst_get (insn) == 0) 13061 return 265; /* mula.dd.hl */ 13062 break; 13063 case 10: 13064 if (Field_s_Slot_inst_get (insn) == 0 && 13065 Field_w_Slot_inst_get (insn) == 0 && 13066 Field_r3_Slot_inst_get (insn) == 0 && 13067 Field_t3_Slot_inst_get (insn) == 0 && 13068 Field_tlo_Slot_inst_get (insn) == 0) 13069 return 266; /* mula.dd.lh */ 13070 break; 13071 case 11: 13072 if (Field_s_Slot_inst_get (insn) == 0 && 13073 Field_w_Slot_inst_get (insn) == 0 && 13074 Field_r3_Slot_inst_get (insn) == 0 && 13075 Field_t3_Slot_inst_get (insn) == 0 && 13076 Field_tlo_Slot_inst_get (insn) == 0) 13077 return 267; /* mula.dd.hh */ 13078 break; 13079 case 12: 13080 if (Field_s_Slot_inst_get (insn) == 0 && 13081 Field_w_Slot_inst_get (insn) == 0 && 13082 Field_r3_Slot_inst_get (insn) == 0 && 13083 Field_t3_Slot_inst_get (insn) == 0 && 13084 Field_tlo_Slot_inst_get (insn) == 0) 13085 return 268; /* muls.dd.ll */ 13086 break; 13087 case 13: 13088 if (Field_s_Slot_inst_get (insn) == 0 && 13089 Field_w_Slot_inst_get (insn) == 0 && 13090 Field_r3_Slot_inst_get (insn) == 0 && 13091 Field_t3_Slot_inst_get (insn) == 0 && 13092 Field_tlo_Slot_inst_get (insn) == 0) 13093 return 269; /* muls.dd.hl */ 13094 break; 13095 case 14: 13096 if (Field_s_Slot_inst_get (insn) == 0 && 13097 Field_w_Slot_inst_get (insn) == 0 && 13098 Field_r3_Slot_inst_get (insn) == 0 && 13099 Field_t3_Slot_inst_get (insn) == 0 && 13100 Field_tlo_Slot_inst_get (insn) == 0) 13101 return 270; /* muls.dd.lh */ 13102 break; 13103 case 15: 13104 if (Field_s_Slot_inst_get (insn) == 0 && 13105 Field_w_Slot_inst_get (insn) == 0 && 13106 Field_r3_Slot_inst_get (insn) == 0 && 13107 Field_t3_Slot_inst_get (insn) == 0 && 13108 Field_tlo_Slot_inst_get (insn) == 0) 13109 return 271; /* muls.dd.hh */ 13110 break; 13111 } 13112 break; 13113 case 3: 13114 switch (Field_op1_Slot_inst_get (insn)) 13115 { 13116 case 4: 13117 if (Field_r_Slot_inst_get (insn) == 0 && 13118 Field_t3_Slot_inst_get (insn) == 0 && 13119 Field_tlo_Slot_inst_get (insn) == 0) 13120 return 228; /* mul.ad.ll */ 13121 break; 13122 case 5: 13123 if (Field_r_Slot_inst_get (insn) == 0 && 13124 Field_t3_Slot_inst_get (insn) == 0 && 13125 Field_tlo_Slot_inst_get (insn) == 0) 13126 return 229; /* mul.ad.hl */ 13127 break; 13128 case 6: 13129 if (Field_r_Slot_inst_get (insn) == 0 && 13130 Field_t3_Slot_inst_get (insn) == 0 && 13131 Field_tlo_Slot_inst_get (insn) == 0) 13132 return 230; /* mul.ad.lh */ 13133 break; 13134 case 7: 13135 if (Field_r_Slot_inst_get (insn) == 0 && 13136 Field_t3_Slot_inst_get (insn) == 0 && 13137 Field_tlo_Slot_inst_get (insn) == 0) 13138 return 231; /* mul.ad.hh */ 13139 break; 13140 case 8: 13141 if (Field_r_Slot_inst_get (insn) == 0 && 13142 Field_t3_Slot_inst_get (insn) == 0 && 13143 Field_tlo_Slot_inst_get (insn) == 0) 13144 return 248; /* mula.ad.ll */ 13145 break; 13146 case 9: 13147 if (Field_r_Slot_inst_get (insn) == 0 && 13148 Field_t3_Slot_inst_get (insn) == 0 && 13149 Field_tlo_Slot_inst_get (insn) == 0) 13150 return 249; /* mula.ad.hl */ 13151 break; 13152 case 10: 13153 if (Field_r_Slot_inst_get (insn) == 0 && 13154 Field_t3_Slot_inst_get (insn) == 0 && 13155 Field_tlo_Slot_inst_get (insn) == 0) 13156 return 250; /* mula.ad.lh */ 13157 break; 13158 case 11: 13159 if (Field_r_Slot_inst_get (insn) == 0 && 13160 Field_t3_Slot_inst_get (insn) == 0 && 13161 Field_tlo_Slot_inst_get (insn) == 0) 13162 return 251; /* mula.ad.hh */ 13163 break; 13164 case 12: 13165 if (Field_r_Slot_inst_get (insn) == 0 && 13166 Field_t3_Slot_inst_get (insn) == 0 && 13167 Field_tlo_Slot_inst_get (insn) == 0) 13168 return 252; /* muls.ad.ll */ 13169 break; 13170 case 13: 13171 if (Field_r_Slot_inst_get (insn) == 0 && 13172 Field_t3_Slot_inst_get (insn) == 0 && 13173 Field_tlo_Slot_inst_get (insn) == 0) 13174 return 253; /* muls.ad.hl */ 13175 break; 13176 case 14: 13177 if (Field_r_Slot_inst_get (insn) == 0 && 13178 Field_t3_Slot_inst_get (insn) == 0 && 13179 Field_tlo_Slot_inst_get (insn) == 0) 13180 return 254; /* muls.ad.lh */ 13181 break; 13182 case 15: 13183 if (Field_r_Slot_inst_get (insn) == 0 && 13184 Field_t3_Slot_inst_get (insn) == 0 && 13185 Field_tlo_Slot_inst_get (insn) == 0) 13186 return 255; /* muls.ad.hh */ 13187 break; 13188 } 13189 break; 13190 case 4: 13191 switch (Field_op1_Slot_inst_get (insn)) 13192 { 13193 case 8: 13194 if (Field_r3_Slot_inst_get (insn) == 0) 13195 return 273; /* mula.da.ll.ldinc */ 13196 break; 13197 case 9: 13198 if (Field_r3_Slot_inst_get (insn) == 0) 13199 return 275; /* mula.da.hl.ldinc */ 13200 break; 13201 case 10: 13202 if (Field_r3_Slot_inst_get (insn) == 0) 13203 return 277; /* mula.da.lh.ldinc */ 13204 break; 13205 case 11: 13206 if (Field_r3_Slot_inst_get (insn) == 0) 13207 return 279; /* mula.da.hh.ldinc */ 13208 break; 13209 } 13210 break; 13211 case 5: 13212 switch (Field_op1_Slot_inst_get (insn)) 13213 { 13214 case 8: 13215 if (Field_r3_Slot_inst_get (insn) == 0) 13216 return 272; /* mula.da.ll.lddec */ 13217 break; 13218 case 9: 13219 if (Field_r3_Slot_inst_get (insn) == 0) 13220 return 274; /* mula.da.hl.lddec */ 13221 break; 13222 case 10: 13223 if (Field_r3_Slot_inst_get (insn) == 0) 13224 return 276; /* mula.da.lh.lddec */ 13225 break; 13226 case 11: 13227 if (Field_r3_Slot_inst_get (insn) == 0) 13228 return 278; /* mula.da.hh.lddec */ 13229 break; 13230 } 13231 break; 13232 case 6: 13233 switch (Field_op1_Slot_inst_get (insn)) 13234 { 13235 case 4: 13236 if (Field_s_Slot_inst_get (insn) == 0 && 13237 Field_w_Slot_inst_get (insn) == 0 && 13238 Field_r3_Slot_inst_get (insn) == 0) 13239 return 232; /* mul.da.ll */ 13240 break; 13241 case 5: 13242 if (Field_s_Slot_inst_get (insn) == 0 && 13243 Field_w_Slot_inst_get (insn) == 0 && 13244 Field_r3_Slot_inst_get (insn) == 0) 13245 return 233; /* mul.da.hl */ 13246 break; 13247 case 6: 13248 if (Field_s_Slot_inst_get (insn) == 0 && 13249 Field_w_Slot_inst_get (insn) == 0 && 13250 Field_r3_Slot_inst_get (insn) == 0) 13251 return 234; /* mul.da.lh */ 13252 break; 13253 case 7: 13254 if (Field_s_Slot_inst_get (insn) == 0 && 13255 Field_w_Slot_inst_get (insn) == 0 && 13256 Field_r3_Slot_inst_get (insn) == 0) 13257 return 235; /* mul.da.hh */ 13258 break; 13259 case 8: 13260 if (Field_s_Slot_inst_get (insn) == 0 && 13261 Field_w_Slot_inst_get (insn) == 0 && 13262 Field_r3_Slot_inst_get (insn) == 0) 13263 return 256; /* mula.da.ll */ 13264 break; 13265 case 9: 13266 if (Field_s_Slot_inst_get (insn) == 0 && 13267 Field_w_Slot_inst_get (insn) == 0 && 13268 Field_r3_Slot_inst_get (insn) == 0) 13269 return 257; /* mula.da.hl */ 13270 break; 13271 case 10: 13272 if (Field_s_Slot_inst_get (insn) == 0 && 13273 Field_w_Slot_inst_get (insn) == 0 && 13274 Field_r3_Slot_inst_get (insn) == 0) 13275 return 258; /* mula.da.lh */ 13276 break; 13277 case 11: 13278 if (Field_s_Slot_inst_get (insn) == 0 && 13279 Field_w_Slot_inst_get (insn) == 0 && 13280 Field_r3_Slot_inst_get (insn) == 0) 13281 return 259; /* mula.da.hh */ 13282 break; 13283 case 12: 13284 if (Field_s_Slot_inst_get (insn) == 0 && 13285 Field_w_Slot_inst_get (insn) == 0 && 13286 Field_r3_Slot_inst_get (insn) == 0) 13287 return 260; /* muls.da.ll */ 13288 break; 13289 case 13: 13290 if (Field_s_Slot_inst_get (insn) == 0 && 13291 Field_w_Slot_inst_get (insn) == 0 && 13292 Field_r3_Slot_inst_get (insn) == 0) 13293 return 261; /* muls.da.hl */ 13294 break; 13295 case 14: 13296 if (Field_s_Slot_inst_get (insn) == 0 && 13297 Field_w_Slot_inst_get (insn) == 0 && 13298 Field_r3_Slot_inst_get (insn) == 0) 13299 return 262; /* muls.da.lh */ 13300 break; 13301 case 15: 13302 if (Field_s_Slot_inst_get (insn) == 0 && 13303 Field_w_Slot_inst_get (insn) == 0 && 13304 Field_r3_Slot_inst_get (insn) == 0) 13305 return 263; /* muls.da.hh */ 13306 break; 13307 } 13308 break; 13309 case 7: 13310 switch (Field_op1_Slot_inst_get (insn)) 13311 { 13312 case 0: 13313 if (Field_r_Slot_inst_get (insn) == 0) 13314 return 224; /* umul.aa.ll */ 13315 break; 13316 case 1: 13317 if (Field_r_Slot_inst_get (insn) == 0) 13318 return 225; /* umul.aa.hl */ 13319 break; 13320 case 2: 13321 if (Field_r_Slot_inst_get (insn) == 0) 13322 return 226; /* umul.aa.lh */ 13323 break; 13324 case 3: 13325 if (Field_r_Slot_inst_get (insn) == 0) 13326 return 227; /* umul.aa.hh */ 13327 break; 13328 case 4: 13329 if (Field_r_Slot_inst_get (insn) == 0) 13330 return 220; /* mul.aa.ll */ 13331 break; 13332 case 5: 13333 if (Field_r_Slot_inst_get (insn) == 0) 13334 return 221; /* mul.aa.hl */ 13335 break; 13336 case 6: 13337 if (Field_r_Slot_inst_get (insn) == 0) 13338 return 222; /* mul.aa.lh */ 13339 break; 13340 case 7: 13341 if (Field_r_Slot_inst_get (insn) == 0) 13342 return 223; /* mul.aa.hh */ 13343 break; 13344 case 8: 13345 if (Field_r_Slot_inst_get (insn) == 0) 13346 return 240; /* mula.aa.ll */ 13347 break; 13348 case 9: 13349 if (Field_r_Slot_inst_get (insn) == 0) 13350 return 241; /* mula.aa.hl */ 13351 break; 13352 case 10: 13353 if (Field_r_Slot_inst_get (insn) == 0) 13354 return 242; /* mula.aa.lh */ 13355 break; 13356 case 11: 13357 if (Field_r_Slot_inst_get (insn) == 0) 13358 return 243; /* mula.aa.hh */ 13359 break; 13360 case 12: 13361 if (Field_r_Slot_inst_get (insn) == 0) 13362 return 244; /* muls.aa.ll */ 13363 break; 13364 case 13: 13365 if (Field_r_Slot_inst_get (insn) == 0) 13366 return 245; /* muls.aa.hl */ 13367 break; 13368 case 14: 13369 if (Field_r_Slot_inst_get (insn) == 0) 13370 return 246; /* muls.aa.lh */ 13371 break; 13372 case 15: 13373 if (Field_r_Slot_inst_get (insn) == 0) 13374 return 247; /* muls.aa.hh */ 13375 break; 13376 } 13377 break; 13378 case 8: 13379 if (Field_op1_Slot_inst_get (insn) == 0 && 13380 Field_t_Slot_inst_get (insn) == 0 && 13381 Field_rhi_Slot_inst_get (insn) == 0) 13382 return 289; /* ldinc */ 13383 break; 13384 case 9: 13385 if (Field_op1_Slot_inst_get (insn) == 0 && 13386 Field_t_Slot_inst_get (insn) == 0 && 13387 Field_rhi_Slot_inst_get (insn) == 0) 13388 return 288; /* lddec */ 13389 break; 13390 } 13391 break; 13392 case 5: 13393 switch (Field_n_Slot_inst_get (insn)) 13394 { 13395 case 0: 13396 return 76; /* call0 */ 13397 case 1: 13398 return 7; /* call4 */ 13399 case 2: 13400 return 6; /* call8 */ 13401 case 3: 13402 return 5; /* call12 */ 13403 } 13404 break; 13405 case 6: 13406 switch (Field_n_Slot_inst_get (insn)) 13407 { 13408 case 0: 13409 return 80; /* j */ 13410 case 1: 13411 switch (Field_m_Slot_inst_get (insn)) 13412 { 13413 case 0: 13414 return 72; /* beqz */ 13415 case 1: 13416 return 73; /* bnez */ 13417 case 2: 13418 return 75; /* bltz */ 13419 case 3: 13420 return 74; /* bgez */ 13421 } 13422 break; 13423 case 2: 13424 switch (Field_m_Slot_inst_get (insn)) 13425 { 13426 case 0: 13427 return 52; /* beqi */ 13428 case 1: 13429 return 53; /* bnei */ 13430 case 2: 13431 return 55; /* blti */ 13432 case 3: 13433 return 54; /* bgei */ 13434 } 13435 break; 13436 case 3: 13437 switch (Field_m_Slot_inst_get (insn)) 13438 { 13439 case 0: 13440 return 11; /* entry */ 13441 case 1: 13442 switch (Field_r_Slot_inst_get (insn)) 13443 { 13444 case 8: 13445 return 87; /* loop */ 13446 case 9: 13447 return 88; /* loopnez */ 13448 case 10: 13449 return 89; /* loopgtz */ 13450 } 13451 break; 13452 case 2: 13453 return 59; /* bltui */ 13454 case 3: 13455 return 58; /* bgeui */ 13456 } 13457 break; 13458 } 13459 break; 13460 case 7: 13461 switch (Field_r_Slot_inst_get (insn)) 13462 { 13463 case 0: 13464 return 67; /* bnone */ 13465 case 1: 13466 return 60; /* beq */ 13467 case 2: 13468 return 63; /* blt */ 13469 case 3: 13470 return 65; /* bltu */ 13471 case 4: 13472 return 68; /* ball */ 13473 case 5: 13474 return 70; /* bbc */ 13475 case 6: 13476 case 7: 13477 return 56; /* bbci */ 13478 case 8: 13479 return 66; /* bany */ 13480 case 9: 13481 return 61; /* bne */ 13482 case 10: 13483 return 62; /* bge */ 13484 case 11: 13485 return 64; /* bgeu */ 13486 case 12: 13487 return 69; /* bnall */ 13488 case 13: 13489 return 71; /* bbs */ 13490 case 14: 13491 case 15: 13492 return 57; /* bbsi */ 13493 } 13494 break; 13495 } 13496 return XTENSA_UNDEFINED; 13497} 13498 13499static int 13500Slot_inst16b_decode (const xtensa_insnbuf insn) 13501{ 13502 switch (Field_op0_Slot_inst16b_get (insn)) 13503 { 13504 case 12: 13505 switch (Field_i_Slot_inst16b_get (insn)) 13506 { 13507 case 0: 13508 return 33; /* movi.n */ 13509 case 1: 13510 switch (Field_z_Slot_inst16b_get (insn)) 13511 { 13512 case 0: 13513 return 28; /* beqz.n */ 13514 case 1: 13515 return 29; /* bnez.n */ 13516 } 13517 break; 13518 } 13519 break; 13520 case 13: 13521 switch (Field_r_Slot_inst16b_get (insn)) 13522 { 13523 case 0: 13524 return 32; /* mov.n */ 13525 case 15: 13526 switch (Field_t_Slot_inst16b_get (insn)) 13527 { 13528 case 0: 13529 return 35; /* ret.n */ 13530 case 1: 13531 return 15; /* retw.n */ 13532 case 2: 13533 return 319; /* break.n */ 13534 case 3: 13535 if (Field_s_Slot_inst16b_get (insn) == 0) 13536 return 34; /* nop.n */ 13537 break; 13538 case 6: 13539 if (Field_s_Slot_inst16b_get (insn) == 0) 13540 return 30; /* ill.n */ 13541 break; 13542 } 13543 break; 13544 } 13545 break; 13546 } 13547 return XTENSA_UNDEFINED; 13548} 13549 13550static int 13551Slot_inst16a_decode (const xtensa_insnbuf insn) 13552{ 13553 switch (Field_op0_Slot_inst16a_get (insn)) 13554 { 13555 case 8: 13556 return 31; /* l32i.n */ 13557 case 9: 13558 return 36; /* s32i.n */ 13559 case 10: 13560 return 26; /* add.n */ 13561 case 11: 13562 return 27; /* addi.n */ 13563 } 13564 return XTENSA_UNDEFINED; 13565} 13566 13567 13568/* Instruction slots. */ 13569 13570static void 13571Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, 13572 xtensa_insnbuf slotbuf) 13573{ 13574 slotbuf[0] = (insn[0] & 0xffffff); 13575} 13576 13577static void 13578Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, 13579 const xtensa_insnbuf slotbuf) 13580{ 13581 insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); 13582} 13583 13584static void 13585Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, 13586 xtensa_insnbuf slotbuf) 13587{ 13588 slotbuf[0] = (insn[0] & 0xffff); 13589} 13590 13591static void 13592Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, 13593 const xtensa_insnbuf slotbuf) 13594{ 13595 insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); 13596} 13597 13598static void 13599Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, 13600 xtensa_insnbuf slotbuf) 13601{ 13602 slotbuf[0] = (insn[0] & 0xffff); 13603} 13604 13605static void 13606Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, 13607 const xtensa_insnbuf slotbuf) 13608{ 13609 insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); 13610} 13611 13612static xtensa_get_field_fn 13613Slot_inst_get_field_fns[] = { 13614 Field_t_Slot_inst_get, 13615 Field_bbi4_Slot_inst_get, 13616 Field_bbi_Slot_inst_get, 13617 Field_imm12_Slot_inst_get, 13618 Field_imm8_Slot_inst_get, 13619 Field_s_Slot_inst_get, 13620 Field_imm12b_Slot_inst_get, 13621 Field_imm16_Slot_inst_get, 13622 Field_m_Slot_inst_get, 13623 Field_n_Slot_inst_get, 13624 Field_offset_Slot_inst_get, 13625 Field_op0_Slot_inst_get, 13626 Field_op1_Slot_inst_get, 13627 Field_op2_Slot_inst_get, 13628 Field_r_Slot_inst_get, 13629 Field_sa4_Slot_inst_get, 13630 Field_sae4_Slot_inst_get, 13631 Field_sae_Slot_inst_get, 13632 Field_sal_Slot_inst_get, 13633 Field_sargt_Slot_inst_get, 13634 Field_sas4_Slot_inst_get, 13635 Field_sas_Slot_inst_get, 13636 Field_sr_Slot_inst_get, 13637 Field_st_Slot_inst_get, 13638 Field_thi3_Slot_inst_get, 13639 Field_imm4_Slot_inst_get, 13640 Field_mn_Slot_inst_get, 13641 0, 13642 0, 13643 0, 13644 0, 13645 0, 13646 0, 13647 0, 13648 0, 13649 Field_r3_Slot_inst_get, 13650 Field_rbit2_Slot_inst_get, 13651 Field_rhi_Slot_inst_get, 13652 Field_t3_Slot_inst_get, 13653 Field_tbit2_Slot_inst_get, 13654 Field_tlo_Slot_inst_get, 13655 Field_w_Slot_inst_get, 13656 Field_y_Slot_inst_get, 13657 Field_x_Slot_inst_get, 13658 Field_xt_wbr15_imm_Slot_inst_get, 13659 Field_xt_wbr18_imm_Slot_inst_get, 13660 Field_bitindex_Slot_inst_get, 13661 Field_s3to1_Slot_inst_get, 13662 Implicit_Field_ar0_get, 13663 Implicit_Field_ar4_get, 13664 Implicit_Field_ar8_get, 13665 Implicit_Field_ar12_get, 13666 Implicit_Field_mr0_get, 13667 Implicit_Field_mr1_get, 13668 Implicit_Field_mr2_get, 13669 Implicit_Field_mr3_get 13670}; 13671 13672static xtensa_set_field_fn 13673Slot_inst_set_field_fns[] = { 13674 Field_t_Slot_inst_set, 13675 Field_bbi4_Slot_inst_set, 13676 Field_bbi_Slot_inst_set, 13677 Field_imm12_Slot_inst_set, 13678 Field_imm8_Slot_inst_set, 13679 Field_s_Slot_inst_set, 13680 Field_imm12b_Slot_inst_set, 13681 Field_imm16_Slot_inst_set, 13682 Field_m_Slot_inst_set, 13683 Field_n_Slot_inst_set, 13684 Field_offset_Slot_inst_set, 13685 Field_op0_Slot_inst_set, 13686 Field_op1_Slot_inst_set, 13687 Field_op2_Slot_inst_set, 13688 Field_r_Slot_inst_set, 13689 Field_sa4_Slot_inst_set, 13690 Field_sae4_Slot_inst_set, 13691 Field_sae_Slot_inst_set, 13692 Field_sal_Slot_inst_set, 13693 Field_sargt_Slot_inst_set, 13694 Field_sas4_Slot_inst_set, 13695 Field_sas_Slot_inst_set, 13696 Field_sr_Slot_inst_set, 13697 Field_st_Slot_inst_set, 13698 Field_thi3_Slot_inst_set, 13699 Field_imm4_Slot_inst_set, 13700 Field_mn_Slot_inst_set, 13701 0, 13702 0, 13703 0, 13704 0, 13705 0, 13706 0, 13707 0, 13708 0, 13709 Field_r3_Slot_inst_set, 13710 Field_rbit2_Slot_inst_set, 13711 Field_rhi_Slot_inst_set, 13712 Field_t3_Slot_inst_set, 13713 Field_tbit2_Slot_inst_set, 13714 Field_tlo_Slot_inst_set, 13715 Field_w_Slot_inst_set, 13716 Field_y_Slot_inst_set, 13717 Field_x_Slot_inst_set, 13718 Field_xt_wbr15_imm_Slot_inst_set, 13719 Field_xt_wbr18_imm_Slot_inst_set, 13720 Field_bitindex_Slot_inst_set, 13721 Field_s3to1_Slot_inst_set, 13722 Implicit_Field_set, 13723 Implicit_Field_set, 13724 Implicit_Field_set, 13725 Implicit_Field_set, 13726 Implicit_Field_set, 13727 Implicit_Field_set, 13728 Implicit_Field_set, 13729 Implicit_Field_set 13730}; 13731 13732static xtensa_get_field_fn 13733Slot_inst16a_get_field_fns[] = { 13734 Field_t_Slot_inst16a_get, 13735 0, 13736 0, 13737 0, 13738 0, 13739 Field_s_Slot_inst16a_get, 13740 0, 13741 0, 13742 0, 13743 0, 13744 0, 13745 Field_op0_Slot_inst16a_get, 13746 0, 13747 0, 13748 Field_r_Slot_inst16a_get, 13749 0, 13750 0, 13751 0, 13752 0, 13753 0, 13754 0, 13755 0, 13756 Field_sr_Slot_inst16a_get, 13757 Field_st_Slot_inst16a_get, 13758 0, 13759 Field_imm4_Slot_inst16a_get, 13760 0, 13761 Field_i_Slot_inst16a_get, 13762 Field_imm6lo_Slot_inst16a_get, 13763 Field_imm6hi_Slot_inst16a_get, 13764 Field_imm7lo_Slot_inst16a_get, 13765 Field_imm7hi_Slot_inst16a_get, 13766 Field_z_Slot_inst16a_get, 13767 Field_imm6_Slot_inst16a_get, 13768 Field_imm7_Slot_inst16a_get, 13769 0, 13770 0, 13771 0, 13772 0, 13773 0, 13774 0, 13775 0, 13776 0, 13777 0, 13778 0, 13779 0, 13780 Field_bitindex_Slot_inst16a_get, 13781 Field_s3to1_Slot_inst16a_get, 13782 Implicit_Field_ar0_get, 13783 Implicit_Field_ar4_get, 13784 Implicit_Field_ar8_get, 13785 Implicit_Field_ar12_get, 13786 Implicit_Field_mr0_get, 13787 Implicit_Field_mr1_get, 13788 Implicit_Field_mr2_get, 13789 Implicit_Field_mr3_get 13790}; 13791 13792static xtensa_set_field_fn 13793Slot_inst16a_set_field_fns[] = { 13794 Field_t_Slot_inst16a_set, 13795 0, 13796 0, 13797 0, 13798 0, 13799 Field_s_Slot_inst16a_set, 13800 0, 13801 0, 13802 0, 13803 0, 13804 0, 13805 Field_op0_Slot_inst16a_set, 13806 0, 13807 0, 13808 Field_r_Slot_inst16a_set, 13809 0, 13810 0, 13811 0, 13812 0, 13813 0, 13814 0, 13815 0, 13816 Field_sr_Slot_inst16a_set, 13817 Field_st_Slot_inst16a_set, 13818 0, 13819 Field_imm4_Slot_inst16a_set, 13820 0, 13821 Field_i_Slot_inst16a_set, 13822 Field_imm6lo_Slot_inst16a_set, 13823 Field_imm6hi_Slot_inst16a_set, 13824 Field_imm7lo_Slot_inst16a_set, 13825 Field_imm7hi_Slot_inst16a_set, 13826 Field_z_Slot_inst16a_set, 13827 Field_imm6_Slot_inst16a_set, 13828 Field_imm7_Slot_inst16a_set, 13829 0, 13830 0, 13831 0, 13832 0, 13833 0, 13834 0, 13835 0, 13836 0, 13837 0, 13838 0, 13839 0, 13840 Field_bitindex_Slot_inst16a_set, 13841 Field_s3to1_Slot_inst16a_set, 13842 Implicit_Field_set, 13843 Implicit_Field_set, 13844 Implicit_Field_set, 13845 Implicit_Field_set, 13846 Implicit_Field_set, 13847 Implicit_Field_set, 13848 Implicit_Field_set, 13849 Implicit_Field_set 13850}; 13851 13852static xtensa_get_field_fn 13853Slot_inst16b_get_field_fns[] = { 13854 Field_t_Slot_inst16b_get, 13855 0, 13856 0, 13857 0, 13858 0, 13859 Field_s_Slot_inst16b_get, 13860 0, 13861 0, 13862 0, 13863 0, 13864 0, 13865 Field_op0_Slot_inst16b_get, 13866 0, 13867 0, 13868 Field_r_Slot_inst16b_get, 13869 0, 13870 0, 13871 0, 13872 0, 13873 0, 13874 0, 13875 0, 13876 Field_sr_Slot_inst16b_get, 13877 Field_st_Slot_inst16b_get, 13878 0, 13879 Field_imm4_Slot_inst16b_get, 13880 0, 13881 Field_i_Slot_inst16b_get, 13882 Field_imm6lo_Slot_inst16b_get, 13883 Field_imm6hi_Slot_inst16b_get, 13884 Field_imm7lo_Slot_inst16b_get, 13885 Field_imm7hi_Slot_inst16b_get, 13886 Field_z_Slot_inst16b_get, 13887 Field_imm6_Slot_inst16b_get, 13888 Field_imm7_Slot_inst16b_get, 13889 0, 13890 0, 13891 0, 13892 0, 13893 0, 13894 0, 13895 0, 13896 0, 13897 0, 13898 0, 13899 0, 13900 Field_bitindex_Slot_inst16b_get, 13901 Field_s3to1_Slot_inst16b_get, 13902 Implicit_Field_ar0_get, 13903 Implicit_Field_ar4_get, 13904 Implicit_Field_ar8_get, 13905 Implicit_Field_ar12_get, 13906 Implicit_Field_mr0_get, 13907 Implicit_Field_mr1_get, 13908 Implicit_Field_mr2_get, 13909 Implicit_Field_mr3_get 13910}; 13911 13912static xtensa_set_field_fn 13913Slot_inst16b_set_field_fns[] = { 13914 Field_t_Slot_inst16b_set, 13915 0, 13916 0, 13917 0, 13918 0, 13919 Field_s_Slot_inst16b_set, 13920 0, 13921 0, 13922 0, 13923 0, 13924 0, 13925 Field_op0_Slot_inst16b_set, 13926 0, 13927 0, 13928 Field_r_Slot_inst16b_set, 13929 0, 13930 0, 13931 0, 13932 0, 13933 0, 13934 0, 13935 0, 13936 Field_sr_Slot_inst16b_set, 13937 Field_st_Slot_inst16b_set, 13938 0, 13939 Field_imm4_Slot_inst16b_set, 13940 0, 13941 Field_i_Slot_inst16b_set, 13942 Field_imm6lo_Slot_inst16b_set, 13943 Field_imm6hi_Slot_inst16b_set, 13944 Field_imm7lo_Slot_inst16b_set, 13945 Field_imm7hi_Slot_inst16b_set, 13946 Field_z_Slot_inst16b_set, 13947 Field_imm6_Slot_inst16b_set, 13948 Field_imm7_Slot_inst16b_set, 13949 0, 13950 0, 13951 0, 13952 0, 13953 0, 13954 0, 13955 0, 13956 0, 13957 0, 13958 0, 13959 0, 13960 Field_bitindex_Slot_inst16b_set, 13961 Field_s3to1_Slot_inst16b_set, 13962 Implicit_Field_set, 13963 Implicit_Field_set, 13964 Implicit_Field_set, 13965 Implicit_Field_set, 13966 Implicit_Field_set, 13967 Implicit_Field_set, 13968 Implicit_Field_set, 13969 Implicit_Field_set 13970}; 13971 13972static xtensa_slot_internal slots[] = { 13973 { "Inst", "x24", 0, 13974 Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, 13975 Slot_inst_get_field_fns, Slot_inst_set_field_fns, 13976 Slot_inst_decode, "nop" }, 13977 { "Inst16a", "x16a", 0, 13978 Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, 13979 Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, 13980 Slot_inst16a_decode, "" }, 13981 { "Inst16b", "x16b", 0, 13982 Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, 13983 Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, 13984 Slot_inst16b_decode, "nop.n" } 13985}; 13986 13987 13988/* Instruction formats. */ 13989 13990static void 13991Format_x24_encode (xtensa_insnbuf insn) 13992{ 13993 insn[0] = 0; 13994} 13995 13996static void 13997Format_x16a_encode (xtensa_insnbuf insn) 13998{ 13999 insn[0] = 0x8; 14000} 14001 14002static void 14003Format_x16b_encode (xtensa_insnbuf insn) 14004{ 14005 insn[0] = 0xc; 14006} 14007 14008static int Format_x24_slots[] = { 0 }; 14009 14010static int Format_x16a_slots[] = { 1 }; 14011 14012static int Format_x16b_slots[] = { 2 }; 14013 14014static xtensa_format_internal formats[] = { 14015 { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, 14016 { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, 14017 { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots } 14018}; 14019 14020 14021static int 14022format_decoder (const xtensa_insnbuf insn) 14023{ 14024 if ((insn[0] & 0x8) == 0) 14025 return 0; /* x24 */ 14026 if ((insn[0] & 0xc) == 0x8) 14027 return 1; /* x16a */ 14028 if ((insn[0] & 0xe) == 0xc) 14029 return 2; /* x16b */ 14030 return -1; 14031} 14032 14033static int length_table[16] = { 14034 3, 14035 3, 14036 3, 14037 3, 14038 3, 14039 3, 14040 3, 14041 3, 14042 2, 14043 2, 14044 2, 14045 2, 14046 2, 14047 2, 14048 -1, 14049 -1 14050}; 14051 14052static int 14053length_decoder (const unsigned char *insn) 14054{ 14055 int op0 = insn[0] & 0xf; 14056 return length_table[op0]; 14057} 14058 14059 14060/* Top-level ISA structure. */ 14061 14062xtensa_isa_internal xtensa_modules = { 14063 0 /* little-endian */, 14064 3 /* insn_size */, 0, 14065 3, formats, format_decoder, length_decoder, 14066 3, slots, 14067 56 /* num_fields */, 14068 93, operands, 14069 320, iclasses, 14070 446, opcodes, 0, 14071 2, regfiles, 14072 NUM_STATES, states, 0, 14073 NUM_SYSREGS, sysregs, 0, 14074 { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, 14075 1, interfaces, 0, 14076 0, funcUnits, 0 14077}; 14078