1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *  cht-bsw-rt5645.c - ASoc Machine driver for Intel Cherryview-based platforms
4  *                     Cherrytrail and Braswell, with RT5645 codec.
5  *
6  *  Copyright (C) 2015 Intel Corp
7  *  Author: Fang, Yang A <yang.a.fang@intel.com>
8  *	        N,Harshapriya <harshapriya.n@intel.com>
9  *  This file is modified from cht_bsw_rt5672.c
10  *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
11  *
12  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
13  */
14 
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/acpi.h>
18 #include <linux/clk.h>
19 #include <linux/dmi.h>
20 #include <linux/slab.h>
21 #include <sound/pcm.h>
22 #include <sound/pcm_params.h>
23 #include <sound/soc.h>
24 #include <sound/jack.h>
25 #include <sound/soc-acpi.h>
26 #include "../../codecs/rt5645.h"
27 #include "../atom/sst-atom-controls.h"
28 #include "../common/soc-intel-quirks.h"
29 
30 #define CHT_PLAT_CLK_3_HZ	19200000
31 #define CHT_CODEC_DAI1	"rt5645-aif1"
32 #define CHT_CODEC_DAI2	"rt5645-aif2"
33 
34 struct cht_acpi_card {
35 	char *codec_id;
36 	int codec_type;
37 	struct snd_soc_card *soc_card;
38 };
39 
40 struct cht_mc_private {
41 	struct snd_soc_jack jack;
42 	struct cht_acpi_card *acpi_card;
43 	char codec_name[SND_ACPI_I2C_ID_LEN];
44 	struct clk *mclk;
45 };
46 
47 #define CHT_RT5645_MAP(quirk)	((quirk) & GENMASK(7, 0))
48 #define CHT_RT5645_SSP2_AIF2     BIT(16) /* default is using AIF1  */
49 #define CHT_RT5645_SSP0_AIF1     BIT(17)
50 #define CHT_RT5645_SSP0_AIF2     BIT(18)
51 #define CHT_RT5645_PMC_PLT_CLK_0 BIT(19)
52 
53 static unsigned long cht_rt5645_quirk = 0;
54 
log_quirks(struct device * dev)55 static void log_quirks(struct device *dev)
56 {
57 	if (cht_rt5645_quirk & CHT_RT5645_SSP2_AIF2)
58 		dev_info(dev, "quirk SSP2_AIF2 enabled");
59 	if (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF1)
60 		dev_info(dev, "quirk SSP0_AIF1 enabled");
61 	if (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2)
62 		dev_info(dev, "quirk SSP0_AIF2 enabled");
63 	if (cht_rt5645_quirk & CHT_RT5645_PMC_PLT_CLK_0)
64 		dev_info(dev, "quirk PMC_PLT_CLK_0 enabled");
65 }
66 
platform_clock_control(struct snd_soc_dapm_widget * w,struct snd_kcontrol * k,int event)67 static int platform_clock_control(struct snd_soc_dapm_widget *w,
68 		struct snd_kcontrol *k, int  event)
69 {
70 	struct snd_soc_dapm_context *dapm = w->dapm;
71 	struct snd_soc_card *card = dapm->card;
72 	struct snd_soc_dai *codec_dai;
73 	struct cht_mc_private *ctx = snd_soc_card_get_drvdata(card);
74 	int ret;
75 
76 	codec_dai = snd_soc_card_get_codec_dai(card, CHT_CODEC_DAI1);
77 	if (!codec_dai)
78 		codec_dai = snd_soc_card_get_codec_dai(card, CHT_CODEC_DAI2);
79 
80 	if (!codec_dai) {
81 		dev_err(card->dev, "Codec dai not found; Unable to set platform clock\n");
82 		return -EIO;
83 	}
84 
85 	if (SND_SOC_DAPM_EVENT_ON(event)) {
86 		ret = clk_prepare_enable(ctx->mclk);
87 		if (ret < 0) {
88 			dev_err(card->dev,
89 				"could not configure MCLK state");
90 			return ret;
91 		}
92 	} else {
93 		/* Set codec sysclk source to its internal clock because codec PLL will
94 		 * be off when idle and MCLK will also be off when codec is
95 		 * runtime suspended. Codec needs clock for jack detection and button
96 		 * press. MCLK is turned off with clock framework or ACPI.
97 		 */
98 		ret = snd_soc_dai_set_sysclk(codec_dai, RT5645_SCLK_S_RCCLK,
99 					48000 * 512, SND_SOC_CLOCK_IN);
100 		if (ret < 0) {
101 			dev_err(card->dev, "can't set codec sysclk: %d\n", ret);
102 			return ret;
103 		}
104 
105 		clk_disable_unprepare(ctx->mclk);
106 	}
107 
108 	return 0;
109 }
110 
111 static const struct snd_soc_dapm_widget cht_dapm_widgets[] = {
112 	SND_SOC_DAPM_HP("Headphone", NULL),
113 	SND_SOC_DAPM_MIC("Headset Mic", NULL),
114 	SND_SOC_DAPM_MIC("Int Mic", NULL),
115 	SND_SOC_DAPM_MIC("Int Analog Mic", NULL),
116 	SND_SOC_DAPM_SPK("Ext Spk", NULL),
117 	SND_SOC_DAPM_SUPPLY("Platform Clock", SND_SOC_NOPM, 0, 0,
118 			platform_clock_control, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
119 };
120 
121 static const struct snd_soc_dapm_route cht_rt5645_audio_map[] = {
122 	{"IN1P", NULL, "Headset Mic"},
123 	{"IN1N", NULL, "Headset Mic"},
124 	{"DMIC L1", NULL, "Int Mic"},
125 	{"DMIC R1", NULL, "Int Mic"},
126 	{"IN2P", NULL, "Int Analog Mic"},
127 	{"IN2N", NULL, "Int Analog Mic"},
128 	{"Headphone", NULL, "HPOL"},
129 	{"Headphone", NULL, "HPOR"},
130 	{"Ext Spk", NULL, "SPOL"},
131 	{"Ext Spk", NULL, "SPOR"},
132 	{"Headphone", NULL, "Platform Clock"},
133 	{"Headset Mic", NULL, "Platform Clock"},
134 	{"Int Mic", NULL, "Platform Clock"},
135 	{"Int Analog Mic", NULL, "Platform Clock"},
136 	{"Int Analog Mic", NULL, "micbias1"},
137 	{"Int Analog Mic", NULL, "micbias2"},
138 	{"Ext Spk", NULL, "Platform Clock"},
139 };
140 
141 static const struct snd_soc_dapm_route cht_rt5650_audio_map[] = {
142 	{"IN1P", NULL, "Headset Mic"},
143 	{"IN1N", NULL, "Headset Mic"},
144 	{"DMIC L2", NULL, "Int Mic"},
145 	{"DMIC R2", NULL, "Int Mic"},
146 	{"Headphone", NULL, "HPOL"},
147 	{"Headphone", NULL, "HPOR"},
148 	{"Ext Spk", NULL, "SPOL"},
149 	{"Ext Spk", NULL, "SPOR"},
150 	{"Headphone", NULL, "Platform Clock"},
151 	{"Headset Mic", NULL, "Platform Clock"},
152 	{"Int Mic", NULL, "Platform Clock"},
153 	{"Ext Spk", NULL, "Platform Clock"},
154 };
155 
156 static const struct snd_soc_dapm_route cht_rt5645_ssp2_aif1_map[] = {
157 	{"AIF1 Playback", NULL, "ssp2 Tx"},
158 	{"ssp2 Tx", NULL, "codec_out0"},
159 	{"ssp2 Tx", NULL, "codec_out1"},
160 	{"codec_in0", NULL, "ssp2 Rx" },
161 	{"codec_in1", NULL, "ssp2 Rx" },
162 	{"ssp2 Rx", NULL, "AIF1 Capture"},
163 };
164 
165 static const struct snd_soc_dapm_route cht_rt5645_ssp2_aif2_map[] = {
166 	{"AIF2 Playback", NULL, "ssp2 Tx"},
167 	{"ssp2 Tx", NULL, "codec_out0"},
168 	{"ssp2 Tx", NULL, "codec_out1"},
169 	{"codec_in0", NULL, "ssp2 Rx" },
170 	{"codec_in1", NULL, "ssp2 Rx" },
171 	{"ssp2 Rx", NULL, "AIF2 Capture"},
172 };
173 
174 static const struct snd_soc_dapm_route cht_rt5645_ssp0_aif1_map[] = {
175 	{"AIF1 Playback", NULL, "ssp0 Tx"},
176 	{"ssp0 Tx", NULL, "modem_out"},
177 	{"modem_in", NULL, "ssp0 Rx" },
178 	{"ssp0 Rx", NULL, "AIF1 Capture"},
179 };
180 
181 static const struct snd_soc_dapm_route cht_rt5645_ssp0_aif2_map[] = {
182 	{"AIF2 Playback", NULL, "ssp0 Tx"},
183 	{"ssp0 Tx", NULL, "modem_out"},
184 	{"modem_in", NULL, "ssp0 Rx" },
185 	{"ssp0 Rx", NULL, "AIF2 Capture"},
186 };
187 
188 static const struct snd_kcontrol_new cht_mc_controls[] = {
189 	SOC_DAPM_PIN_SWITCH("Headphone"),
190 	SOC_DAPM_PIN_SWITCH("Headset Mic"),
191 	SOC_DAPM_PIN_SWITCH("Int Mic"),
192 	SOC_DAPM_PIN_SWITCH("Int Analog Mic"),
193 	SOC_DAPM_PIN_SWITCH("Ext Spk"),
194 };
195 
196 static struct snd_soc_jack_pin cht_bsw_jack_pins[] = {
197 	{
198 		.pin	= "Headphone",
199 		.mask	= SND_JACK_HEADPHONE,
200 	},
201 	{
202 		.pin	= "Headset Mic",
203 		.mask	= SND_JACK_MICROPHONE,
204 	},
205 };
206 
cht_aif1_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params)207 static int cht_aif1_hw_params(struct snd_pcm_substream *substream,
208 			     struct snd_pcm_hw_params *params)
209 {
210 	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
211 	struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
212 	int ret;
213 
214 	/* set codec PLL source to the 19.2MHz platform clock (MCLK) */
215 	ret = snd_soc_dai_set_pll(codec_dai, 0, RT5645_PLL1_S_MCLK,
216 				  CHT_PLAT_CLK_3_HZ, params_rate(params) * 512);
217 	if (ret < 0) {
218 		dev_err(rtd->dev, "can't set codec pll: %d\n", ret);
219 		return ret;
220 	}
221 
222 	ret = snd_soc_dai_set_sysclk(codec_dai, RT5645_SCLK_S_PLL1,
223 				params_rate(params) * 512, SND_SOC_CLOCK_IN);
224 	if (ret < 0) {
225 		dev_err(rtd->dev, "can't set codec sysclk: %d\n", ret);
226 		return ret;
227 	}
228 
229 	return 0;
230 }
231 
cht_rt5645_quirk_cb(const struct dmi_system_id * id)232 static int cht_rt5645_quirk_cb(const struct dmi_system_id *id)
233 {
234 	cht_rt5645_quirk = (unsigned long)id->driver_data;
235 	return 1;
236 }
237 
238 static const struct dmi_system_id cht_rt5645_quirk_table[] = {
239 	{
240 		/* Strago family Chromebooks */
241 		.callback = cht_rt5645_quirk_cb,
242 		.matches = {
243 			DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"),
244 		},
245 		.driver_data = (void *)CHT_RT5645_PMC_PLT_CLK_0,
246 	},
247 	{
248 	},
249 };
250 
cht_codec_init(struct snd_soc_pcm_runtime * runtime)251 static int cht_codec_init(struct snd_soc_pcm_runtime *runtime)
252 {
253 	struct snd_soc_card *card = runtime->card;
254 	struct cht_mc_private *ctx = snd_soc_card_get_drvdata(runtime->card);
255 	struct snd_soc_component *component = asoc_rtd_to_codec(runtime, 0)->component;
256 	int jack_type;
257 	int ret;
258 
259 	if ((cht_rt5645_quirk & CHT_RT5645_SSP2_AIF2) ||
260 	    (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2)) {
261 		/* Select clk_i2s2_asrc as ASRC clock source */
262 		rt5645_sel_asrc_clk_src(component,
263 					RT5645_DA_STEREO_FILTER |
264 					RT5645_DA_MONO_L_FILTER |
265 					RT5645_DA_MONO_R_FILTER |
266 					RT5645_AD_STEREO_FILTER,
267 					RT5645_CLK_SEL_I2S2_ASRC);
268 	} else {
269 		/* Select clk_i2s1_asrc as ASRC clock source */
270 		rt5645_sel_asrc_clk_src(component,
271 					RT5645_DA_STEREO_FILTER |
272 					RT5645_DA_MONO_L_FILTER |
273 					RT5645_DA_MONO_R_FILTER |
274 					RT5645_AD_STEREO_FILTER,
275 					RT5645_CLK_SEL_I2S1_ASRC);
276 	}
277 
278 	if (cht_rt5645_quirk & CHT_RT5645_SSP2_AIF2) {
279 		ret = snd_soc_dapm_add_routes(&card->dapm,
280 					cht_rt5645_ssp2_aif2_map,
281 					ARRAY_SIZE(cht_rt5645_ssp2_aif2_map));
282 	} else if (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF1) {
283 		ret = snd_soc_dapm_add_routes(&card->dapm,
284 					cht_rt5645_ssp0_aif1_map,
285 					ARRAY_SIZE(cht_rt5645_ssp0_aif1_map));
286 	} else if (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2) {
287 		ret = snd_soc_dapm_add_routes(&card->dapm,
288 					cht_rt5645_ssp0_aif2_map,
289 					ARRAY_SIZE(cht_rt5645_ssp0_aif2_map));
290 	} else {
291 		ret = snd_soc_dapm_add_routes(&card->dapm,
292 					cht_rt5645_ssp2_aif1_map,
293 					ARRAY_SIZE(cht_rt5645_ssp2_aif1_map));
294 	}
295 	if (ret)
296 		return ret;
297 
298 	if (ctx->acpi_card->codec_type == CODEC_TYPE_RT5650)
299 		jack_type = SND_JACK_HEADPHONE | SND_JACK_MICROPHONE |
300 					SND_JACK_BTN_0 | SND_JACK_BTN_1 |
301 					SND_JACK_BTN_2 | SND_JACK_BTN_3;
302 	else
303 		jack_type = SND_JACK_HEADPHONE | SND_JACK_MICROPHONE;
304 
305 	ret = snd_soc_card_jack_new_pins(runtime->card, "Headset", jack_type,
306 					 &ctx->jack, cht_bsw_jack_pins,
307 					 ARRAY_SIZE(cht_bsw_jack_pins));
308 	if (ret) {
309 		dev_err(runtime->dev, "Headset jack creation failed %d\n", ret);
310 		return ret;
311 	}
312 
313 	rt5645_set_jack_detect(component, &ctx->jack, &ctx->jack, &ctx->jack);
314 
315 
316 	/*
317 	 * The firmware might enable the clock at
318 	 * boot (this information may or may not
319 	 * be reflected in the enable clock register).
320 	 * To change the rate we must disable the clock
321 	 * first to cover these cases. Due to common
322 	 * clock framework restrictions that do not allow
323 	 * to disable a clock that has not been enabled,
324 	 * we need to enable the clock first.
325 	 */
326 	ret = clk_prepare_enable(ctx->mclk);
327 	if (!ret)
328 		clk_disable_unprepare(ctx->mclk);
329 
330 	ret = clk_set_rate(ctx->mclk, CHT_PLAT_CLK_3_HZ);
331 
332 	if (ret)
333 		dev_err(runtime->dev, "unable to set MCLK rate\n");
334 
335 	return ret;
336 }
337 
cht_codec_fixup(struct snd_soc_pcm_runtime * rtd,struct snd_pcm_hw_params * params)338 static int cht_codec_fixup(struct snd_soc_pcm_runtime *rtd,
339 			    struct snd_pcm_hw_params *params)
340 {
341 	int ret;
342 	struct snd_interval *rate = hw_param_interval(params,
343 			SNDRV_PCM_HW_PARAM_RATE);
344 	struct snd_interval *channels = hw_param_interval(params,
345 						SNDRV_PCM_HW_PARAM_CHANNELS);
346 
347 	/* The DSP will convert the FE rate to 48k, stereo, 24bits */
348 	rate->min = rate->max = 48000;
349 	channels->min = channels->max = 2;
350 
351 	if ((cht_rt5645_quirk & CHT_RT5645_SSP0_AIF1) ||
352 		(cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2)) {
353 
354 		/* set SSP0 to 16-bit */
355 		params_set_format(params, SNDRV_PCM_FORMAT_S16_LE);
356 
357 		/*
358 		 * Default mode for SSP configuration is TDM 4 slot, override config
359 		 * with explicit setting to I2S 2ch 16-bit. The word length is set with
360 		 * dai_set_tdm_slot() since there is no other API exposed
361 		 */
362 		ret = snd_soc_dai_set_fmt(asoc_rtd_to_cpu(rtd, 0),
363 					SND_SOC_DAIFMT_I2S     |
364 					SND_SOC_DAIFMT_NB_NF   |
365 					SND_SOC_DAIFMT_BP_FP
366 			);
367 		if (ret < 0) {
368 			dev_err(rtd->dev, "can't set format to I2S, err %d\n", ret);
369 			return ret;
370 		}
371 
372 		ret = snd_soc_dai_set_fmt(asoc_rtd_to_codec(rtd, 0),
373 					SND_SOC_DAIFMT_I2S     |
374 					SND_SOC_DAIFMT_NB_NF   |
375 					SND_SOC_DAIFMT_BC_FC
376 			);
377 		if (ret < 0) {
378 			dev_err(rtd->dev, "can't set format to I2S, err %d\n", ret);
379 			return ret;
380 		}
381 
382 		ret = snd_soc_dai_set_tdm_slot(asoc_rtd_to_cpu(rtd, 0), 0x3, 0x3, 2, 16);
383 		if (ret < 0) {
384 			dev_err(rtd->dev, "can't set I2S config, err %d\n", ret);
385 			return ret;
386 		}
387 
388 	} else {
389 
390 		/* set SSP2 to 24-bit */
391 		params_set_format(params, SNDRV_PCM_FORMAT_S24_LE);
392 
393 		/*
394 		 * Default mode for SSP configuration is TDM 4 slot
395 		 */
396 		ret = snd_soc_dai_set_fmt(asoc_rtd_to_codec(rtd, 0),
397 					SND_SOC_DAIFMT_DSP_B |
398 					SND_SOC_DAIFMT_IB_NF |
399 					SND_SOC_DAIFMT_BC_FC);
400 		if (ret < 0) {
401 			dev_err(rtd->dev, "can't set format to TDM %d\n", ret);
402 			return ret;
403 		}
404 
405 		/* TDM 4 slots 24 bit, set Rx & Tx bitmask to 4 active slots */
406 		ret = snd_soc_dai_set_tdm_slot(asoc_rtd_to_codec(rtd, 0), 0xF, 0xF, 4, 24);
407 		if (ret < 0) {
408 			dev_err(rtd->dev, "can't set codec TDM slot %d\n", ret);
409 			return ret;
410 		}
411 	}
412 	return 0;
413 }
414 
cht_aif1_startup(struct snd_pcm_substream * substream)415 static int cht_aif1_startup(struct snd_pcm_substream *substream)
416 {
417 	return snd_pcm_hw_constraint_single(substream->runtime,
418 			SNDRV_PCM_HW_PARAM_RATE, 48000);
419 }
420 
421 static const struct snd_soc_ops cht_aif1_ops = {
422 	.startup = cht_aif1_startup,
423 };
424 
425 static const struct snd_soc_ops cht_be_ssp2_ops = {
426 	.hw_params = cht_aif1_hw_params,
427 };
428 
429 SND_SOC_DAILINK_DEF(dummy,
430 	DAILINK_COMP_ARRAY(COMP_DUMMY()));
431 
432 SND_SOC_DAILINK_DEF(media,
433 	DAILINK_COMP_ARRAY(COMP_CPU("media-cpu-dai")));
434 
435 SND_SOC_DAILINK_DEF(deepbuffer,
436 	DAILINK_COMP_ARRAY(COMP_CPU("deepbuffer-cpu-dai")));
437 
438 SND_SOC_DAILINK_DEF(ssp2_port,
439 	DAILINK_COMP_ARRAY(COMP_CPU("ssp2-port")));
440 SND_SOC_DAILINK_DEF(ssp2_codec,
441 	DAILINK_COMP_ARRAY(COMP_CODEC("i2c-10EC5645:00", "rt5645-aif1")));
442 
443 SND_SOC_DAILINK_DEF(platform,
444 	DAILINK_COMP_ARRAY(COMP_PLATFORM("sst-mfld-platform")));
445 
446 static struct snd_soc_dai_link cht_dailink[] = {
447 	[MERR_DPCM_AUDIO] = {
448 		.name = "Audio Port",
449 		.stream_name = "Audio",
450 		.nonatomic = true,
451 		.dynamic = 1,
452 		.dpcm_playback = 1,
453 		.dpcm_capture = 1,
454 		.ops = &cht_aif1_ops,
455 		SND_SOC_DAILINK_REG(media, dummy, platform),
456 	},
457 	[MERR_DPCM_DEEP_BUFFER] = {
458 		.name = "Deep-Buffer Audio Port",
459 		.stream_name = "Deep-Buffer Audio",
460 		.nonatomic = true,
461 		.dynamic = 1,
462 		.dpcm_playback = 1,
463 		.ops = &cht_aif1_ops,
464 		SND_SOC_DAILINK_REG(deepbuffer, dummy, platform),
465 	},
466 	/* CODEC<->CODEC link */
467 	/* back ends */
468 	{
469 		.name = "SSP2-Codec",
470 		.id = 0,
471 		.no_pcm = 1,
472 		.init = cht_codec_init,
473 		.be_hw_params_fixup = cht_codec_fixup,
474 		.dpcm_playback = 1,
475 		.dpcm_capture = 1,
476 		.ops = &cht_be_ssp2_ops,
477 		SND_SOC_DAILINK_REG(ssp2_port, ssp2_codec, platform),
478 	},
479 };
480 
481 /* use space before codec name to simplify card ID, and simplify driver name */
482 #define SOF_CARD_RT5645_NAME "bytcht rt5645" /* card name 'sof-bytcht rt5645' */
483 #define SOF_CARD_RT5650_NAME "bytcht rt5650" /* card name 'sof-bytcht rt5650' */
484 #define SOF_DRIVER_NAME "SOF"
485 
486 #define CARD_RT5645_NAME "chtrt5645"
487 #define CARD_RT5650_NAME "chtrt5650"
488 #define DRIVER_NAME NULL /* card name will be used for driver name */
489 
490 /* SoC card */
491 static struct snd_soc_card snd_soc_card_chtrt5645 = {
492 	.owner = THIS_MODULE,
493 	.dai_link = cht_dailink,
494 	.num_links = ARRAY_SIZE(cht_dailink),
495 	.dapm_widgets = cht_dapm_widgets,
496 	.num_dapm_widgets = ARRAY_SIZE(cht_dapm_widgets),
497 	.dapm_routes = cht_rt5645_audio_map,
498 	.num_dapm_routes = ARRAY_SIZE(cht_rt5645_audio_map),
499 	.controls = cht_mc_controls,
500 	.num_controls = ARRAY_SIZE(cht_mc_controls),
501 };
502 
503 static struct snd_soc_card snd_soc_card_chtrt5650 = {
504 	.owner = THIS_MODULE,
505 	.dai_link = cht_dailink,
506 	.num_links = ARRAY_SIZE(cht_dailink),
507 	.dapm_widgets = cht_dapm_widgets,
508 	.num_dapm_widgets = ARRAY_SIZE(cht_dapm_widgets),
509 	.dapm_routes = cht_rt5650_audio_map,
510 	.num_dapm_routes = ARRAY_SIZE(cht_rt5650_audio_map),
511 	.controls = cht_mc_controls,
512 	.num_controls = ARRAY_SIZE(cht_mc_controls),
513 };
514 
515 static struct cht_acpi_card snd_soc_cards[] = {
516 	{"10EC5640", CODEC_TYPE_RT5645, &snd_soc_card_chtrt5645},
517 	{"10EC5645", CODEC_TYPE_RT5645, &snd_soc_card_chtrt5645},
518 	{"10EC5648", CODEC_TYPE_RT5645, &snd_soc_card_chtrt5645},
519 	{"10EC3270", CODEC_TYPE_RT5645, &snd_soc_card_chtrt5645},
520 	{"10EC5650", CODEC_TYPE_RT5650, &snd_soc_card_chtrt5650},
521 };
522 
523 static char cht_rt5645_codec_name[SND_ACPI_I2C_ID_LEN];
524 
525 struct acpi_chan_package {   /* ACPICA seems to require 64 bit integers */
526 	u64 aif_value;       /* 1: AIF1, 2: AIF2 */
527 	u64 mclock_value;    /* usually 25MHz (0x17d7940), ignored */
528 };
529 
snd_cht_mc_probe(struct platform_device * pdev)530 static int snd_cht_mc_probe(struct platform_device *pdev)
531 {
532 	struct snd_soc_card *card = snd_soc_cards[0].soc_card;
533 	struct snd_soc_acpi_mach *mach;
534 	const char *platform_name;
535 	struct cht_mc_private *drv;
536 	struct acpi_device *adev;
537 	bool sof_parent;
538 	bool found = false;
539 	bool is_bytcr = false;
540 	int dai_index = 0;
541 	int ret_val = 0;
542 	int i;
543 	const char *mclk_name;
544 
545 	drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
546 	if (!drv)
547 		return -ENOMEM;
548 
549 	mach = pdev->dev.platform_data;
550 
551 	for (i = 0; i < ARRAY_SIZE(snd_soc_cards); i++) {
552 		if (acpi_dev_found(snd_soc_cards[i].codec_id) &&
553 			(!strncmp(snd_soc_cards[i].codec_id, mach->id, 8))) {
554 			dev_dbg(&pdev->dev,
555 				"found codec %s\n", snd_soc_cards[i].codec_id);
556 			card = snd_soc_cards[i].soc_card;
557 			drv->acpi_card = &snd_soc_cards[i];
558 			found = true;
559 			break;
560 		}
561 	}
562 
563 	if (!found) {
564 		dev_err(&pdev->dev, "No matching HID found in supported list\n");
565 		return -ENODEV;
566 	}
567 
568 	card->dev = &pdev->dev;
569 	sprintf(drv->codec_name, "i2c-%s:00", drv->acpi_card->codec_id);
570 
571 	/* set correct codec name */
572 	for (i = 0; i < ARRAY_SIZE(cht_dailink); i++)
573 		if (!strcmp(card->dai_link[i].codecs->name,
574 			    "i2c-10EC5645:00")) {
575 			card->dai_link[i].codecs->name = drv->codec_name;
576 			dai_index = i;
577 		}
578 
579 	/* fixup codec name based on HID */
580 	adev = acpi_dev_get_first_match_dev(mach->id, NULL, -1);
581 	if (adev) {
582 		snprintf(cht_rt5645_codec_name, sizeof(cht_rt5645_codec_name),
583 			 "i2c-%s", acpi_dev_name(adev));
584 		cht_dailink[dai_index].codecs->name = cht_rt5645_codec_name;
585 	}
586 	acpi_dev_put(adev);
587 
588 	/*
589 	 * swap SSP0 if bytcr is detected
590 	 * (will be overridden if DMI quirk is detected)
591 	 */
592 	if (soc_intel_is_byt()) {
593 		if (mach->mach_params.acpi_ipc_irq_index == 0)
594 			is_bytcr = true;
595 	}
596 
597 	if (is_bytcr) {
598 		/*
599 		 * Baytrail CR platforms may have CHAN package in BIOS, try
600 		 * to find relevant routing quirk based as done on Windows
601 		 * platforms. We have to read the information directly from the
602 		 * BIOS, at this stage the card is not created and the links
603 		 * with the codec driver/pdata are non-existent
604 		 */
605 
606 		struct acpi_chan_package chan_package = { 0 };
607 
608 		/* format specified: 2 64-bit integers */
609 		struct acpi_buffer format = {sizeof("NN"), "NN"};
610 		struct acpi_buffer state = {0, NULL};
611 		struct snd_soc_acpi_package_context pkg_ctx;
612 		bool pkg_found = false;
613 
614 		state.length = sizeof(chan_package);
615 		state.pointer = &chan_package;
616 
617 		pkg_ctx.name = "CHAN";
618 		pkg_ctx.length = 2;
619 		pkg_ctx.format = &format;
620 		pkg_ctx.state = &state;
621 		pkg_ctx.data_valid = false;
622 
623 		pkg_found = snd_soc_acpi_find_package_from_hid(mach->id,
624 							       &pkg_ctx);
625 		if (pkg_found) {
626 			if (chan_package.aif_value == 1) {
627 				dev_info(&pdev->dev, "BIOS Routing: AIF1 connected\n");
628 				cht_rt5645_quirk |= CHT_RT5645_SSP0_AIF1;
629 			} else  if (chan_package.aif_value == 2) {
630 				dev_info(&pdev->dev, "BIOS Routing: AIF2 connected\n");
631 				cht_rt5645_quirk |= CHT_RT5645_SSP0_AIF2;
632 			} else {
633 				dev_info(&pdev->dev, "BIOS Routing isn't valid, ignored\n");
634 				pkg_found = false;
635 			}
636 		}
637 
638 		if (!pkg_found) {
639 			/* no BIOS indications, assume SSP0-AIF2 connection */
640 			cht_rt5645_quirk |= CHT_RT5645_SSP0_AIF2;
641 		}
642 	}
643 
644 	/* check quirks before creating card */
645 	dmi_check_system(cht_rt5645_quirk_table);
646 	log_quirks(&pdev->dev);
647 
648 	if ((cht_rt5645_quirk & CHT_RT5645_SSP2_AIF2) ||
649 	    (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2))
650 		cht_dailink[dai_index].codecs->dai_name = "rt5645-aif2";
651 
652 	if ((cht_rt5645_quirk & CHT_RT5645_SSP0_AIF1) ||
653 	    (cht_rt5645_quirk & CHT_RT5645_SSP0_AIF2))
654 		cht_dailink[dai_index].cpus->dai_name = "ssp0-port";
655 
656 	/* override platform name, if required */
657 	platform_name = mach->mach_params.platform;
658 
659 	ret_val = snd_soc_fixup_dai_links_platform_name(card,
660 							platform_name);
661 	if (ret_val)
662 		return ret_val;
663 
664 	if (cht_rt5645_quirk & CHT_RT5645_PMC_PLT_CLK_0)
665 		mclk_name = "pmc_plt_clk_0";
666 	else
667 		mclk_name = "pmc_plt_clk_3";
668 
669 	drv->mclk = devm_clk_get(&pdev->dev, mclk_name);
670 	if (IS_ERR(drv->mclk)) {
671 		dev_err(&pdev->dev, "Failed to get MCLK from %s: %ld\n",
672 			mclk_name, PTR_ERR(drv->mclk));
673 		return PTR_ERR(drv->mclk);
674 	}
675 
676 	snd_soc_card_set_drvdata(card, drv);
677 
678 	sof_parent = snd_soc_acpi_sof_parent(&pdev->dev);
679 
680 	/* set card and driver name */
681 	if (sof_parent) {
682 		snd_soc_card_chtrt5645.name = SOF_CARD_RT5645_NAME;
683 		snd_soc_card_chtrt5645.driver_name = SOF_DRIVER_NAME;
684 		snd_soc_card_chtrt5650.name = SOF_CARD_RT5650_NAME;
685 		snd_soc_card_chtrt5650.driver_name = SOF_DRIVER_NAME;
686 	} else {
687 		snd_soc_card_chtrt5645.name = CARD_RT5645_NAME;
688 		snd_soc_card_chtrt5645.driver_name = DRIVER_NAME;
689 		snd_soc_card_chtrt5650.name = CARD_RT5650_NAME;
690 		snd_soc_card_chtrt5650.driver_name = DRIVER_NAME;
691 	}
692 
693 	/* set pm ops */
694 	if (sof_parent)
695 		pdev->dev.driver->pm = &snd_soc_pm_ops;
696 
697 	ret_val = devm_snd_soc_register_card(&pdev->dev, card);
698 	if (ret_val) {
699 		dev_err(&pdev->dev,
700 			"snd_soc_register_card failed %d\n", ret_val);
701 		return ret_val;
702 	}
703 	platform_set_drvdata(pdev, card);
704 	return ret_val;
705 }
706 
707 static struct platform_driver snd_cht_mc_driver = {
708 	.driver = {
709 		.name = "cht-bsw-rt5645",
710 	},
711 	.probe = snd_cht_mc_probe,
712 };
713 
714 module_platform_driver(snd_cht_mc_driver)
715 
716 MODULE_DESCRIPTION("ASoC Intel(R) Braswell Machine driver");
717 MODULE_AUTHOR("Fang, Yang A,N,Harshapriya");
718 MODULE_LICENSE("GPL v2");
719 MODULE_ALIAS("platform:cht-bsw-rt5645");
720