1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright 2016 Maxime Ripard 4 * 5 * Maxime Ripard <maxime.ripard@free-electrons.com> 6 */ 7 8 #ifndef _CCU_SUN50I_A64_H_ 9 #define _CCU_SUN50I_A64_H_ 10 11 #include <dt-bindings/clock/sun50i-a64-ccu.h> 12 #include <dt-bindings/reset/sun50i-a64-ccu.h> 13 14 #define CLK_OSC_12M 0 15 #define CLK_PLL_CPUX 1 16 #define CLK_PLL_AUDIO_BASE 2 17 #define CLK_PLL_AUDIO 3 18 #define CLK_PLL_AUDIO_2X 4 19 #define CLK_PLL_AUDIO_4X 5 20 #define CLK_PLL_AUDIO_8X 6 21 22 /* PLL_VIDEO0 exported for HDMI PHY */ 23 24 #define CLK_PLL_VE 9 25 #define CLK_PLL_DDR0 10 26 27 /* PLL_PERIPH0 exported for PRCM */ 28 29 #define CLK_PLL_PERIPH0_2X 12 30 #define CLK_PLL_PERIPH1 13 31 #define CLK_PLL_PERIPH1_2X 14 32 #define CLK_PLL_VIDEO1 15 33 #define CLK_PLL_GPU 16 34 #define CLK_PLL_HSIC 18 35 #define CLK_PLL_DE 19 36 #define CLK_PLL_DDR1 20 37 #define CLK_AXI 22 38 #define CLK_APB 23 39 #define CLK_AHB1 24 40 #define CLK_APB1 25 41 #define CLK_APB2 26 42 #define CLK_AHB2 27 43 44 /* All the bus gates are exported */ 45 46 /* The first bunch of module clocks are exported */ 47 48 #define CLK_USB_OHCI0_12M 90 49 50 #define CLK_USB_OHCI1_12M 92 51 52 /* All the DRAM gates are exported */ 53 54 /* And the DSI and GPU module clock is exported */ 55 56 #define CLK_NUMBER (CLK_GPU + 1) 57 58 #endif /* _CCU_SUN50I_A64_H_ */ 59