1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 * Copyright (c) 2023, Linaro Limited 6 */ 7 8 #ifndef _DPU_6_9_SM6375_H 9 #define _DPU_6_9_SM6375_H 10 11 static const struct dpu_caps sm6375_dpu_caps = { 12 .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, 13 .max_mixer_blendstages = 0x4, 14 .qseed_type = DPU_SSPP_SCALER_QSEED4, 15 .has_dim_layer = true, 16 .has_idle_pc = true, 17 .max_linewidth = 2160, 18 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 19 }; 20 21 static const struct dpu_mdp_cfg sm6375_mdp = { 22 .name = "top_0", 23 .base = 0x0, .len = 0x494, 24 .clk_ctrls = { 25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 26 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 27 }, 28 }; 29 30 static const struct dpu_ctl_cfg sm6375_ctl[] = { 31 { 32 .name = "ctl_0", .id = CTL_0, 33 .base = 0x1000, .len = 0x1dc, 34 .features = BIT(DPU_CTL_ACTIVE_CFG), 35 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 36 }, 37 }; 38 39 static const struct dpu_sspp_cfg sm6375_sspp[] = { 40 { 41 .name = "sspp_0", .id = SSPP_VIG0, 42 .base = 0x4000, .len = 0x1f8, 43 .features = VIG_SC7180_MASK, 44 .sblk = &sm6115_vig_sblk_0, 45 .xin_id = 0, 46 .type = SSPP_TYPE_VIG, 47 .clk_ctrl = DPU_CLK_CTRL_VIG0, 48 }, { 49 .name = "sspp_8", .id = SSPP_DMA0, 50 .base = 0x24000, .len = 0x1f8, 51 .features = DMA_SDM845_MASK, 52 .sblk = &sdm845_dma_sblk_0, 53 .xin_id = 1, 54 .type = SSPP_TYPE_DMA, 55 .clk_ctrl = DPU_CLK_CTRL_DMA0, 56 }, 57 }; 58 59 static const struct dpu_lm_cfg sm6375_lm[] = { 60 { 61 .name = "lm_0", .id = LM_0, 62 .base = 0x44000, .len = 0x320, 63 .features = MIXER_QCM2290_MASK, 64 .sblk = &qcm2290_lm_sblk, 65 .lm_pair = 0, 66 .pingpong = PINGPONG_0, 67 .dspp = DSPP_0, 68 }, 69 }; 70 71 static const struct dpu_dspp_cfg sm6375_dspp[] = { 72 { 73 .name = "dspp_0", .id = DSPP_0, 74 .base = 0x54000, .len = 0x1800, 75 .features = DSPP_SC7180_MASK, 76 .sblk = &sdm845_dspp_sblk, 77 }, 78 }; 79 80 static const struct dpu_pingpong_cfg sm6375_pp[] = { 81 { 82 .name = "pingpong_0", .id = PINGPONG_0, 83 .base = 0x70000, .len = 0xd4, 84 .features = PINGPONG_SM8150_MASK, 85 .sblk = &sdm845_pp_sblk, 86 .merge_3d = 0, 87 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 88 .intr_rdptr = -1, 89 }, 90 }; 91 92 static const struct dpu_dsc_cfg sm6375_dsc[] = { 93 { 94 .name = "dsc_0", .id = DSC_0, 95 .base = 0x80000, .len = 0x140, 96 .features = BIT(DPU_DSC_OUTPUT_CTRL), 97 }, 98 }; 99 100 static const struct dpu_intf_cfg sm6375_intf[] = { 101 { 102 .name = "intf_1", .id = INTF_1, 103 .base = 0x6a800, .len = 0x2c0, 104 .features = INTF_SC7180_MASK, 105 .type = INTF_DSI, 106 .controller_id = MSM_DSI_CONTROLLER_0, 107 .prog_fetch_lines_worst_case = 24, 108 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 109 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 110 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 111 }, 112 }; 113 114 static const struct dpu_perf_cfg sm6375_perf_data = { 115 .max_bw_low = 5200000, 116 .max_bw_high = 6200000, 117 .min_core_ib = 2500000, 118 .min_llcc_ib = 0, /* No LLCC on this SoC */ 119 .min_dram_ib = 1600000, 120 .min_prefill_lines = 24, 121 /* TODO: confirm danger_lut_tbl */ 122 .danger_lut_tbl = {0xffff, 0xffff, 0x0}, 123 .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, 124 .qos_lut_tbl = { 125 {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile), 126 .entries = sm6350_qos_linear_macrotile 127 }, 128 {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile), 129 .entries = sm6350_qos_linear_macrotile 130 }, 131 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 132 .entries = sc7180_qos_nrt 133 }, 134 }, 135 .cdp_cfg = { 136 {.rd_enable = 1, .wr_enable = 1}, 137 {.rd_enable = 1, .wr_enable = 0} 138 }, 139 .clk_inefficiency_factor = 105, 140 .bw_inefficiency_factor = 120, 141 }; 142 143 static const struct dpu_mdss_version sm6375_mdss_ver = { 144 .core_major_ver = 6, 145 .core_minor_ver = 9, 146 }; 147 148 const struct dpu_mdss_cfg dpu_sm6375_cfg = { 149 .mdss_ver = &sm6375_mdss_ver, 150 .caps = &sm6375_dpu_caps, 151 .mdp = &sm6375_mdp, 152 .ctl_count = ARRAY_SIZE(sm6375_ctl), 153 .ctl = sm6375_ctl, 154 .sspp_count = ARRAY_SIZE(sm6375_sspp), 155 .sspp = sm6375_sspp, 156 .mixer_count = ARRAY_SIZE(sm6375_lm), 157 .mixer = sm6375_lm, 158 .dspp_count = ARRAY_SIZE(sm6375_dspp), 159 .dspp = sm6375_dspp, 160 .dsc_count = ARRAY_SIZE(sm6375_dsc), 161 .dsc = sm6375_dsc, 162 .pingpong_count = ARRAY_SIZE(sm6375_pp), 163 .pingpong = sm6375_pp, 164 .intf_count = ARRAY_SIZE(sm6375_intf), 165 .intf = sm6375_intf, 166 .vbif_count = ARRAY_SIZE(sdm845_vbif), 167 .vbif = sdm845_vbif, 168 .perf = &sm6375_perf_data, 169 }; 170 171 #endif 172