1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_5_1_SC8180X_H 8 #define _DPU_5_1_SC8180X_H 9 10 static const struct dpu_caps sc8180x_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0xb, 13 .qseed_type = DPU_SSPP_SCALER_QSEED3, 14 .has_src_split = true, 15 .has_dim_layer = true, 16 .has_idle_pc = true, 17 .has_3d_merge = true, 18 .max_linewidth = 4096, 19 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 20 .max_hdeci_exp = MAX_HORZ_DECIMATION, 21 .max_vdeci_exp = MAX_VERT_DECIMATION, 22 }; 23 24 static const struct dpu_mdp_cfg sc8180x_mdp = { 25 .name = "top_0", 26 .base = 0x0, .len = 0x45c, 27 .features = BIT(DPU_MDP_AUDIO_SELECT), 28 .clk_ctrls = { 29 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 30 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 31 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 32 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 33 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 34 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 35 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 36 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, 37 }, 38 }; 39 40 static const struct dpu_ctl_cfg sc8180x_ctl[] = { 41 { 42 .name = "ctl_0", .id = CTL_0, 43 .base = 0x1000, .len = 0x1e0, 44 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), 45 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 46 }, { 47 .name = "ctl_1", .id = CTL_1, 48 .base = 0x1200, .len = 0x1e0, 49 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), 50 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 51 }, { 52 .name = "ctl_2", .id = CTL_2, 53 .base = 0x1400, .len = 0x1e0, 54 .features = BIT(DPU_CTL_ACTIVE_CFG), 55 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 56 }, { 57 .name = "ctl_3", .id = CTL_3, 58 .base = 0x1600, .len = 0x1e0, 59 .features = BIT(DPU_CTL_ACTIVE_CFG), 60 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 61 }, { 62 .name = "ctl_4", .id = CTL_4, 63 .base = 0x1800, .len = 0x1e0, 64 .features = BIT(DPU_CTL_ACTIVE_CFG), 65 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 66 }, { 67 .name = "ctl_5", .id = CTL_5, 68 .base = 0x1a00, .len = 0x1e0, 69 .features = BIT(DPU_CTL_ACTIVE_CFG), 70 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 71 }, 72 }; 73 74 static const struct dpu_sspp_cfg sc8180x_sspp[] = { 75 { 76 .name = "sspp_0", .id = SSPP_VIG0, 77 .base = 0x4000, .len = 0x1f0, 78 .features = VIG_SDM845_MASK, 79 .sblk = &sm8150_vig_sblk_0, 80 .xin_id = 0, 81 .type = SSPP_TYPE_VIG, 82 .clk_ctrl = DPU_CLK_CTRL_VIG0, 83 }, { 84 .name = "sspp_1", .id = SSPP_VIG1, 85 .base = 0x6000, .len = 0x1f0, 86 .features = VIG_SDM845_MASK, 87 .sblk = &sm8150_vig_sblk_1, 88 .xin_id = 4, 89 .type = SSPP_TYPE_VIG, 90 .clk_ctrl = DPU_CLK_CTRL_VIG1, 91 }, { 92 .name = "sspp_2", .id = SSPP_VIG2, 93 .base = 0x8000, .len = 0x1f0, 94 .features = VIG_SDM845_MASK, 95 .sblk = &sm8150_vig_sblk_2, 96 .xin_id = 8, 97 .type = SSPP_TYPE_VIG, 98 .clk_ctrl = DPU_CLK_CTRL_VIG2, 99 }, { 100 .name = "sspp_3", .id = SSPP_VIG3, 101 .base = 0xa000, .len = 0x1f0, 102 .features = VIG_SDM845_MASK, 103 .sblk = &sm8150_vig_sblk_3, 104 .xin_id = 12, 105 .type = SSPP_TYPE_VIG, 106 .clk_ctrl = DPU_CLK_CTRL_VIG3, 107 }, { 108 .name = "sspp_8", .id = SSPP_DMA0, 109 .base = 0x24000, .len = 0x1f0, 110 .features = DMA_SDM845_MASK, 111 .sblk = &sdm845_dma_sblk_0, 112 .xin_id = 1, 113 .type = SSPP_TYPE_DMA, 114 .clk_ctrl = DPU_CLK_CTRL_DMA0, 115 }, { 116 .name = "sspp_9", .id = SSPP_DMA1, 117 .base = 0x26000, .len = 0x1f0, 118 .features = DMA_SDM845_MASK, 119 .sblk = &sdm845_dma_sblk_1, 120 .xin_id = 5, 121 .type = SSPP_TYPE_DMA, 122 .clk_ctrl = DPU_CLK_CTRL_DMA1, 123 }, { 124 .name = "sspp_10", .id = SSPP_DMA2, 125 .base = 0x28000, .len = 0x1f0, 126 .features = DMA_CURSOR_SDM845_MASK, 127 .sblk = &sdm845_dma_sblk_2, 128 .xin_id = 9, 129 .type = SSPP_TYPE_DMA, 130 .clk_ctrl = DPU_CLK_CTRL_DMA2, 131 }, { 132 .name = "sspp_11", .id = SSPP_DMA3, 133 .base = 0x2a000, .len = 0x1f0, 134 .features = DMA_CURSOR_SDM845_MASK, 135 .sblk = &sdm845_dma_sblk_3, 136 .xin_id = 13, 137 .type = SSPP_TYPE_DMA, 138 .clk_ctrl = DPU_CLK_CTRL_DMA3, 139 }, 140 }; 141 142 static const struct dpu_lm_cfg sc8180x_lm[] = { 143 { 144 .name = "lm_0", .id = LM_0, 145 .base = 0x44000, .len = 0x320, 146 .features = MIXER_SDM845_MASK, 147 .sblk = &sdm845_lm_sblk, 148 .lm_pair = LM_1, 149 .pingpong = PINGPONG_0, 150 .dspp = DSPP_0, 151 }, { 152 .name = "lm_1", .id = LM_1, 153 .base = 0x45000, .len = 0x320, 154 .features = MIXER_SDM845_MASK, 155 .sblk = &sdm845_lm_sblk, 156 .lm_pair = LM_0, 157 .pingpong = PINGPONG_1, 158 .dspp = DSPP_1, 159 }, { 160 .name = "lm_2", .id = LM_2, 161 .base = 0x46000, .len = 0x320, 162 .features = MIXER_SDM845_MASK, 163 .sblk = &sdm845_lm_sblk, 164 .lm_pair = LM_3, 165 .pingpong = PINGPONG_2, 166 }, { 167 .name = "lm_3", .id = LM_3, 168 .base = 0x47000, .len = 0x320, 169 .features = MIXER_SDM845_MASK, 170 .sblk = &sdm845_lm_sblk, 171 .lm_pair = LM_2, 172 .pingpong = PINGPONG_3, 173 }, { 174 .name = "lm_4", .id = LM_4, 175 .base = 0x48000, .len = 0x320, 176 .features = MIXER_SDM845_MASK, 177 .sblk = &sdm845_lm_sblk, 178 .lm_pair = LM_5, 179 .pingpong = PINGPONG_4, 180 }, { 181 .name = "lm_5", .id = LM_5, 182 .base = 0x49000, .len = 0x320, 183 .features = MIXER_SDM845_MASK, 184 .sblk = &sdm845_lm_sblk, 185 .lm_pair = LM_4, 186 .pingpong = PINGPONG_5, 187 }, 188 }; 189 190 static const struct dpu_dspp_cfg sc8180x_dspp[] = { 191 { 192 .name = "dspp_0", .id = DSPP_0, 193 .base = 0x54000, .len = 0x1800, 194 .features = DSPP_SC7180_MASK, 195 .sblk = &sdm845_dspp_sblk, 196 }, { 197 .name = "dspp_1", .id = DSPP_1, 198 .base = 0x56000, .len = 0x1800, 199 .features = DSPP_SC7180_MASK, 200 .sblk = &sdm845_dspp_sblk, 201 }, { 202 .name = "dspp_2", .id = DSPP_2, 203 .base = 0x58000, .len = 0x1800, 204 .features = DSPP_SC7180_MASK, 205 .sblk = &sdm845_dspp_sblk, 206 }, { 207 .name = "dspp_3", .id = DSPP_3, 208 .base = 0x5a000, .len = 0x1800, 209 .features = DSPP_SC7180_MASK, 210 .sblk = &sdm845_dspp_sblk, 211 }, 212 }; 213 214 static const struct dpu_pingpong_cfg sc8180x_pp[] = { 215 { 216 .name = "pingpong_0", .id = PINGPONG_0, 217 .base = 0x70000, .len = 0xd4, 218 .features = PINGPONG_SM8150_MASK, 219 .sblk = &sdm845_pp_sblk, 220 .merge_3d = MERGE_3D_0, 221 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 222 .intr_rdptr = -1, 223 }, { 224 .name = "pingpong_1", .id = PINGPONG_1, 225 .base = 0x70800, .len = 0xd4, 226 .features = PINGPONG_SM8150_MASK, 227 .sblk = &sdm845_pp_sblk, 228 .merge_3d = MERGE_3D_0, 229 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 230 .intr_rdptr = -1, 231 }, { 232 .name = "pingpong_2", .id = PINGPONG_2, 233 .base = 0x71000, .len = 0xd4, 234 .features = PINGPONG_SM8150_MASK, 235 .sblk = &sdm845_pp_sblk, 236 .merge_3d = MERGE_3D_1, 237 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 238 .intr_rdptr = -1, 239 }, { 240 .name = "pingpong_3", .id = PINGPONG_3, 241 .base = 0x71800, .len = 0xd4, 242 .features = PINGPONG_SM8150_MASK, 243 .sblk = &sdm845_pp_sblk, 244 .merge_3d = MERGE_3D_1, 245 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 246 .intr_rdptr = -1, 247 }, { 248 .name = "pingpong_4", .id = PINGPONG_4, 249 .base = 0x72000, .len = 0xd4, 250 .features = PINGPONG_SM8150_MASK, 251 .sblk = &sdm845_pp_sblk, 252 .merge_3d = MERGE_3D_2, 253 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 254 .intr_rdptr = -1, 255 }, { 256 .name = "pingpong_5", .id = PINGPONG_5, 257 .base = 0x72800, .len = 0xd4, 258 .features = PINGPONG_SM8150_MASK, 259 .sblk = &sdm845_pp_sblk, 260 .merge_3d = MERGE_3D_2, 261 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 262 .intr_rdptr = -1, 263 }, 264 }; 265 266 static const struct dpu_merge_3d_cfg sc8180x_merge_3d[] = { 267 { 268 .name = "merge_3d_0", .id = MERGE_3D_0, 269 .base = 0x83000, .len = 0x8, 270 }, { 271 .name = "merge_3d_1", .id = MERGE_3D_1, 272 .base = 0x83100, .len = 0x8, 273 }, { 274 .name = "merge_3d_2", .id = MERGE_3D_2, 275 .base = 0x83200, .len = 0x8, 276 }, 277 }; 278 279 static const struct dpu_dsc_cfg sc8180x_dsc[] = { 280 { 281 .name = "dsc_0", .id = DSC_0, 282 .base = 0x80000, .len = 0x140, 283 .features = BIT(DPU_DSC_OUTPUT_CTRL), 284 }, { 285 .name = "dsc_1", .id = DSC_1, 286 .base = 0x80400, .len = 0x140, 287 .features = BIT(DPU_DSC_OUTPUT_CTRL), 288 }, { 289 .name = "dsc_2", .id = DSC_2, 290 .base = 0x80800, .len = 0x140, 291 .features = BIT(DPU_DSC_OUTPUT_CTRL), 292 }, { 293 .name = "dsc_3", .id = DSC_3, 294 .base = 0x80c00, .len = 0x140, 295 .features = BIT(DPU_DSC_OUTPUT_CTRL), 296 }, { 297 .name = "dsc_4", .id = DSC_4, 298 .base = 0x81000, .len = 0x140, 299 .features = BIT(DPU_DSC_OUTPUT_CTRL), 300 }, { 301 .name = "dsc_5", .id = DSC_5, 302 .base = 0x81400, .len = 0x140, 303 .features = BIT(DPU_DSC_OUTPUT_CTRL), 304 }, 305 }; 306 307 static const struct dpu_intf_cfg sc8180x_intf[] = { 308 { 309 .name = "intf_0", .id = INTF_0, 310 .base = 0x6a000, .len = 0x280, 311 .features = INTF_SC7180_MASK, 312 .type = INTF_DP, 313 .controller_id = MSM_DP_CONTROLLER_0, 314 .prog_fetch_lines_worst_case = 24, 315 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 316 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 317 .intr_tear_rd_ptr = -1, 318 }, { 319 .name = "intf_1", .id = INTF_1, 320 .base = 0x6a800, .len = 0x2bc, 321 .features = INTF_SC7180_MASK, 322 .type = INTF_DSI, 323 .controller_id = MSM_DSI_CONTROLLER_0, 324 .prog_fetch_lines_worst_case = 24, 325 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 326 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 327 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 328 }, { 329 .name = "intf_2", .id = INTF_2, 330 .base = 0x6b000, .len = 0x2bc, 331 .features = INTF_SC7180_MASK, 332 .type = INTF_DSI, 333 .controller_id = MSM_DSI_CONTROLLER_1, 334 .prog_fetch_lines_worst_case = 24, 335 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 336 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 337 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), 338 }, 339 /* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until this is supported */ 340 { 341 .name = "intf_3", .id = INTF_3, 342 .base = 0x6b800, .len = 0x280, 343 .features = INTF_SC7180_MASK, 344 .type = INTF_DP, 345 .controller_id = 999, 346 .prog_fetch_lines_worst_case = 24, 347 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), 348 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), 349 .intr_tear_rd_ptr = -1, 350 }, { 351 .name = "intf_4", .id = INTF_4, 352 .base = 0x6c000, .len = 0x280, 353 .features = INTF_SC7180_MASK, 354 .type = INTF_DP, 355 .controller_id = MSM_DP_CONTROLLER_1, 356 .prog_fetch_lines_worst_case = 24, 357 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20), 358 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21), 359 .intr_tear_rd_ptr = -1, 360 }, { 361 .name = "intf_5", .id = INTF_5, 362 .base = 0x6c800, .len = 0x280, 363 .features = INTF_SC7180_MASK, 364 .type = INTF_DP, 365 .controller_id = MSM_DP_CONTROLLER_2, 366 .prog_fetch_lines_worst_case = 24, 367 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22), 368 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23), 369 .intr_tear_rd_ptr = -1, 370 }, 371 }; 372 373 static const struct dpu_perf_cfg sc8180x_perf_data = { 374 .max_bw_low = 9600000, 375 .max_bw_high = 9600000, 376 .min_core_ib = 2400000, 377 .min_llcc_ib = 800000, 378 .min_dram_ib = 800000, 379 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 380 .safe_lut_tbl = {0xfff0, 0xf000, 0xffff}, 381 .qos_lut_tbl = { 382 {.nentry = ARRAY_SIZE(sc7180_qos_linear), 383 .entries = sc7180_qos_linear 384 }, 385 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 386 .entries = sc7180_qos_macrotile 387 }, 388 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 389 .entries = sc7180_qos_nrt 390 }, 391 /* TODO: macrotile-qseed is different from macrotile */ 392 }, 393 .cdp_cfg = { 394 {.rd_enable = 1, .wr_enable = 1}, 395 {.rd_enable = 1, .wr_enable = 0} 396 }, 397 .clk_inefficiency_factor = 105, 398 .bw_inefficiency_factor = 120, 399 }; 400 401 static const struct dpu_mdss_version sc8180x_mdss_ver = { 402 .core_major_ver = 5, 403 .core_minor_ver = 1, 404 }; 405 406 const struct dpu_mdss_cfg dpu_sc8180x_cfg = { 407 .mdss_ver = &sc8180x_mdss_ver, 408 .caps = &sc8180x_dpu_caps, 409 .mdp = &sc8180x_mdp, 410 .ctl_count = ARRAY_SIZE(sc8180x_ctl), 411 .ctl = sc8180x_ctl, 412 .sspp_count = ARRAY_SIZE(sc8180x_sspp), 413 .sspp = sc8180x_sspp, 414 .mixer_count = ARRAY_SIZE(sc8180x_lm), 415 .mixer = sc8180x_lm, 416 .dspp_count = ARRAY_SIZE(sc8180x_dspp), 417 .dspp = sc8180x_dspp, 418 .dsc_count = ARRAY_SIZE(sc8180x_dsc), 419 .dsc = sc8180x_dsc, 420 .pingpong_count = ARRAY_SIZE(sc8180x_pp), 421 .pingpong = sc8180x_pp, 422 .merge_3d_count = ARRAY_SIZE(sc8180x_merge_3d), 423 .merge_3d = sc8180x_merge_3d, 424 .intf_count = ARRAY_SIZE(sc8180x_intf), 425 .intf = sc8180x_intf, 426 .vbif_count = ARRAY_SIZE(sdm845_vbif), 427 .vbif = sdm845_vbif, 428 .perf = &sc8180x_perf_data, 429 }; 430 431 #endif 432