xref: /openbmc/u-boot/board/tbs/tbs2910/tbs2910.cfg (revision e8f80a5a)
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2017 Soeren Moch <smoch@web.de>
4 */
5
6#define __ASSEMBLY__
7#include "asm/arch/crm_regs.h"
8#include "asm/arch/iomux.h"
9#include "asm/arch/mx6-ddr.h"
10
11/* image version 2 for imx6 */
12IMAGE_VERSION 2
13BOOT_FROM sd
14
15/* set the default clock gates to save power */
16DATA 4, CCM_CCGR0, 0x00C03F3F
17DATA 4, CCM_CCGR1, 0x0030FC03
18DATA 4, CCM_CCGR2, 0x0FFFC000
19DATA 4, CCM_CCGR3, 0x3FF00000
20DATA 4, CCM_CCGR4, 0x00FFF300
21DATA 4, CCM_CCGR5, 0x0F0000C3
22DATA 4, CCM_CCGR6, 0x000003FF
23/* set CKO1 (used as AUDIO_MCLK) to ahb_clk_root/8 = 16.5 MHz */
24DATA 4, CCM_CCOSR, 0x000000fb
25
26/* enable AXI cache for VDOA/VPU/IPU */
27DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
28/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
29DATA 4, MX6_IOMUXC_GPR6, 0x77177717
30DATA 4, MX6_IOMUXC_GPR7, 0x77177717
31
32
33/*
34 * DDR3/DDR3L settings
35 * use default 40 Ohm pad drive strength, no odt
36 * 4x256Mx16 DDR3L-1066 7-7-7
37 */
38
39/* disable dq pullup */
40DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
41/* disable dqs pullup */
42DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
43DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
44DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
45DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
46DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
47DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
48DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
49DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
50/* set ddr input mode for dq signals */
51DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
52/* set ddr input mode for dqs signals */
53DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
54/* set pad calibration type to DDR3 */
55DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
56/* ZQ calibration */
57DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
58/* dqs write delay */
59DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001f001f
60DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001f001f
61DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001f001f
62DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001f001f
63/* dqs read delay */
64DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
65DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
66DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
67DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
68DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
69DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
70DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
71DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
72/* dqs read gating control */
73DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43000300
74DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03000300
75DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43000300
76DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03000300
77/* start delay line calibration */
78DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
79/* tRFC=0x89+1,tXS=0x8e+1,tXP=3+1,tXPDLL=0xc+1,tFAW=0x17+1,tCL=0x4+3 */
80DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7974
81/* tRCD=6+1,tRP=6+1,tRC=0x1a+1,tRAS=0x13+1,tRPA=tRP+1,tWR=7+1,tMRD=0xb+1,tCWL=4+2 */
82DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64
83/* tDLLK=0x1ff+1,tRTP=3+1,tWTR=3+1,tRRD=3+1 */
84DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
85/* RTW_SAME=2,WTR_DIFF=3,WTW_DIFF=3,RTW_DIFF=2,RTR_DIFF=2 */
86DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
87/* tXPR=0x8e+1,SDE2RST=0x10-2,RST2CKE=0x23-2 */
88DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023
89/* ODT timing */
90DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
91/* read odt settings, 120 Ohm */
92DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117
93DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117
94/* cs0, 15-bit row, 10-bit column, BL 8, 64-bit bus */
95DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
96/* interleaved bank access (row/bank/col), 5 cycles additional read delay */
97DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
98/* 2GiByte RAM at cs0 */
99DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
100/* load mode registers of external ddr chips */
101DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030
102DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
103DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
104DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
105/* externel chip ZQ calibration */
106DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
107/* configure and start refreshes, 8 refresh commands at 32 kHz */
108DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
109/* tCKE=2+1,tCKSRX=6,tCKSE=6, active power down after 256 cycles (setting 5) */
110DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
111/* set automatic self refresh */
112DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
113/* controller configuration finished */
114DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
115