xref: /openbmc/qemu/hw/arm/bcm2838.c (revision 7785e8ea)
1 /*
2  * BCM2838 SoC emulation
3  *
4  * Copyright (C) 2022 Ovchinnikov Vitalii <vitalii.ovchinnikov@auriga.com>
5  *
6  * SPDX-License-Identifier: GPL-2.0-or-later
7  */
8 
9 #include "qemu/osdep.h"
10 #include "qapi/error.h"
11 #include "qemu/module.h"
12 #include "hw/arm/raspi_platform.h"
13 #include "hw/sysbus.h"
14 #include "hw/arm/bcm2838.h"
15 #include "trace.h"
16 
17 #define GIC400_MAINTENANCE_IRQ      9
18 #define GIC400_TIMER_NS_EL2_IRQ     10
19 #define GIC400_TIMER_VIRT_IRQ       11
20 #define GIC400_LEGACY_FIQ           12
21 #define GIC400_TIMER_S_EL1_IRQ      13
22 #define GIC400_TIMER_NS_EL1_IRQ     14
23 #define GIC400_LEGACY_IRQ           15
24 
25 /* Number of external interrupt lines to configure the GIC with */
26 #define GIC_NUM_IRQS                192
27 
28 #define PPI(cpu, irq) (GIC_NUM_IRQS + (cpu) * GIC_INTERNAL + GIC_NR_SGIS + irq)
29 
30 #define GIC_BASE_OFS                0x0000
31 #define GIC_DIST_OFS                0x1000
32 #define GIC_CPU_OFS                 0x2000
33 #define GIC_VIFACE_THIS_OFS         0x4000
34 #define GIC_VIFACE_OTHER_OFS(cpu)  (0x5000 + (cpu) * 0x200)
35 #define GIC_VCPU_OFS                0x6000
36 
37 #define VIRTUAL_PMU_IRQ 7
38 
bcm2838_gic_set_irq(void * opaque,int irq,int level)39 static void bcm2838_gic_set_irq(void *opaque, int irq, int level)
40 {
41     BCM2838State *s = (BCM2838State *)opaque;
42 
43     trace_bcm2838_gic_set_irq(irq, level);
44     qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
45 }
46 
bcm2838_init(Object * obj)47 static void bcm2838_init(Object *obj)
48 {
49     BCM2838State *s = BCM2838(obj);
50 
51     object_initialize_child(obj, "peripherals", &s->peripherals,
52                             TYPE_BCM2838_PERIPHERALS);
53     object_property_add_alias(obj, "board-rev", OBJECT(&s->peripherals),
54                               "board-rev");
55     object_property_add_alias(obj, "vcram-size", OBJECT(&s->peripherals),
56                               "vcram-size");
57     object_property_add_alias(obj, "vcram-base", OBJECT(&s->peripherals),
58                               "vcram-base");
59     object_property_add_alias(obj, "command-line", OBJECT(&s->peripherals),
60                               "command-line");
61 
62     object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);
63 }
64 
bcm2838_realize(DeviceState * dev,Error ** errp)65 static void bcm2838_realize(DeviceState *dev, Error **errp)
66 {
67     BCM2838State *s = BCM2838(dev);
68     BCM283XBaseState *s_base = BCM283X_BASE(dev);
69     BCM283XBaseClass *bc_base = BCM283X_BASE_GET_CLASS(dev);
70     BCM2838PeripheralState *ps = BCM2838_PERIPHERALS(&s->peripherals);
71     BCMSocPeripheralBaseState *ps_base =
72         BCM_SOC_PERIPHERALS_BASE(&s->peripherals);
73 
74     DeviceState *gicdev = NULL;
75 
76     if (!bcm283x_common_realize(dev, ps_base, errp)) {
77         return;
78     }
79     sysbus_mmio_map_overlap(SYS_BUS_DEVICE(ps), 1, BCM2838_PERI_LOW_BASE, 1);
80 
81     /* bcm2836 interrupt controller (and mailboxes, etc.) */
82     if (!sysbus_realize(SYS_BUS_DEVICE(&s_base->control), errp)) {
83         return;
84     }
85     sysbus_mmio_map(SYS_BUS_DEVICE(&s_base->control), 0, bc_base->ctrl_base);
86 
87     /* Create cores */
88     for (int n = 0; n < bc_base->core_count; n++) {
89 
90         object_property_set_int(OBJECT(&s_base->cpu[n].core), "mp-affinity",
91                                 (bc_base->clusterid << 8) | n, &error_abort);
92 
93         /* set periphbase/CBAR value for CPU-local registers */
94         object_property_set_int(OBJECT(&s_base->cpu[n].core), "reset-cbar",
95                                 bc_base->peri_base, &error_abort);
96 
97         /* start powered off if not enabled */
98         object_property_set_bool(OBJECT(&s_base->cpu[n].core),
99                                  "start-powered-off",
100                                  n >= s_base->enabled_cpus, &error_abort);
101 
102         if (!qdev_realize(DEVICE(&s_base->cpu[n].core), NULL, errp)) {
103             return;
104         }
105     }
106 
107     if (!object_property_set_uint(OBJECT(&s->gic), "revision", 2, errp)) {
108         return;
109     }
110 
111     if (!object_property_set_uint(OBJECT(&s->gic), "num-cpu", BCM283X_NCPUS,
112                                   errp)) {
113         return;
114     }
115 
116     if (!object_property_set_uint(OBJECT(&s->gic), "num-irq",
117                                   GIC_NUM_IRQS + GIC_INTERNAL, errp)) {
118         return;
119     }
120 
121     if (!object_property_set_bool(OBJECT(&s->gic),
122                                   "has-virtualization-extensions", true,
123                                   errp)) {
124         return;
125     }
126 
127     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) {
128         return;
129     }
130 
131     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0,
132                     bc_base->ctrl_base + BCM2838_GIC_BASE + GIC_DIST_OFS);
133     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1,
134                     bc_base->ctrl_base + BCM2838_GIC_BASE + GIC_CPU_OFS);
135     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2,
136                     bc_base->ctrl_base + BCM2838_GIC_BASE + GIC_VIFACE_THIS_OFS);
137     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3,
138                     bc_base->ctrl_base + BCM2838_GIC_BASE + GIC_VCPU_OFS);
139 
140     for (int n = 0; n < BCM283X_NCPUS; n++) {
141         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 4 + n,
142                         bc_base->ctrl_base + BCM2838_GIC_BASE
143                             + GIC_VIFACE_OTHER_OFS(n));
144     }
145 
146     gicdev = DEVICE(&s->gic);
147 
148     for (int n = 0; n < BCM283X_NCPUS; n++) {
149         DeviceState *cpudev = DEVICE(&s_base->cpu[n]);
150 
151         /* Connect the GICv2 outputs to the CPU */
152         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), n,
153                            qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
154         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), n + BCM283X_NCPUS,
155                            qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
156         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), n + 2 * BCM283X_NCPUS,
157                            qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
158         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), n + 3 * BCM283X_NCPUS,
159                            qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
160 
161         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), n + 4 * BCM283X_NCPUS,
162                            qdev_get_gpio_in(gicdev,
163                                             PPI(n, GIC400_MAINTENANCE_IRQ)));
164 
165         /* Connect timers from the CPU to the interrupt controller */
166         qdev_connect_gpio_out(cpudev, GTIMER_PHYS,
167                     qdev_get_gpio_in(gicdev, PPI(n, GIC400_TIMER_NS_EL1_IRQ)));
168         qdev_connect_gpio_out(cpudev, GTIMER_VIRT,
169                     qdev_get_gpio_in(gicdev, PPI(n, GIC400_TIMER_VIRT_IRQ)));
170         qdev_connect_gpio_out(cpudev, GTIMER_HYP,
171                     qdev_get_gpio_in(gicdev, PPI(n, GIC400_TIMER_NS_EL2_IRQ)));
172         qdev_connect_gpio_out(cpudev, GTIMER_SEC,
173                     qdev_get_gpio_in(gicdev, PPI(n, GIC400_TIMER_S_EL1_IRQ)));
174         /* PMU interrupt */
175         qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
176                     qdev_get_gpio_in(gicdev, PPI(n, VIRTUAL_PMU_IRQ)));
177     }
178 
179     /* Connect UART0 to the interrupt controller */
180     sysbus_connect_irq(SYS_BUS_DEVICE(&ps_base->uart0), 0,
181                        qdev_get_gpio_in(gicdev, GIC_SPI_INTERRUPT_UART0));
182 
183     /* Connect AUX / UART1 to the interrupt controller */
184     sysbus_connect_irq(SYS_BUS_DEVICE(&ps_base->aux), 0,
185                        qdev_get_gpio_in(gicdev, GIC_SPI_INTERRUPT_AUX_UART1));
186 
187     /* Connect VC mailbox to the interrupt controller */
188     sysbus_connect_irq(SYS_BUS_DEVICE(&ps_base->mboxes), 0,
189                        qdev_get_gpio_in(gicdev, GIC_SPI_INTERRUPT_MBOX));
190 
191     /* Connect SD host to the interrupt controller */
192     sysbus_connect_irq(SYS_BUS_DEVICE(&ps_base->sdhost), 0,
193                        qdev_get_gpio_in(gicdev, GIC_SPI_INTERRUPT_SDHOST));
194 
195     /* According to DTS, EMMC and EMMC2 share one irq */
196     DeviceState *mmc_irq_orgate = DEVICE(&ps->mmc_irq_orgate);
197 
198     /* Connect EMMC and EMMC2 to the interrupt controller */
199     qdev_connect_gpio_out(mmc_irq_orgate, 0,
200                           qdev_get_gpio_in(gicdev, GIC_SPI_INTERRUPT_EMMC_EMMC2));
201 
202     /* Connect USB OTG and MPHI to the interrupt controller */
203     sysbus_connect_irq(SYS_BUS_DEVICE(&ps_base->mphi), 0,
204                        qdev_get_gpio_in(gicdev, GIC_SPI_INTERRUPT_MPHI));
205     sysbus_connect_irq(SYS_BUS_DEVICE(&ps_base->dwc2), 0,
206                        qdev_get_gpio_in(gicdev, GIC_SPI_INTERRUPT_DWC2));
207 
208     /* Connect DMA 0-6 to the interrupt controller */
209     for (int n = GIC_SPI_INTERRUPT_DMA_0; n <= GIC_SPI_INTERRUPT_DMA_6; n++) {
210         sysbus_connect_irq(SYS_BUS_DEVICE(&ps_base->dma),
211                            n - GIC_SPI_INTERRUPT_DMA_0,
212                            qdev_get_gpio_in(gicdev, n));
213     }
214 
215     /* According to DTS, DMA 7 and 8 share one irq */
216     DeviceState *dma_7_8_irq_orgate = DEVICE(&ps->dma_7_8_irq_orgate);
217 
218     /* Connect DMA 7-8 to the interrupt controller */
219     qdev_connect_gpio_out(dma_7_8_irq_orgate, 0,
220                           qdev_get_gpio_in(gicdev, GIC_SPI_INTERRUPT_DMA_7_8));
221 
222     /* According to DTS, DMA 9 and 10 share one irq */
223     DeviceState *dma_9_10_irq_orgate = DEVICE(&ps->dma_9_10_irq_orgate);
224 
225     /* Connect DMA 9-10 to the interrupt controller */
226     qdev_connect_gpio_out(dma_9_10_irq_orgate, 0,
227                           qdev_get_gpio_in(gicdev, GIC_SPI_INTERRUPT_DMA_9_10));
228 
229     /* Pass through inbound GPIO lines to the GIC */
230     qdev_init_gpio_in(dev, bcm2838_gic_set_irq, GIC_NUM_IRQS);
231 
232     /* Pass through outbound IRQ lines from the GIC */
233     qdev_pass_gpios(DEVICE(&s->gic), DEVICE(&s->peripherals), NULL);
234 }
235 
bcm2838_class_init(ObjectClass * oc,void * data)236 static void bcm2838_class_init(ObjectClass *oc, void *data)
237 {
238     DeviceClass *dc = DEVICE_CLASS(oc);
239     BCM283XBaseClass *bc_base = BCM283X_BASE_CLASS(oc);
240 
241     bc_base->cpu_type = ARM_CPU_TYPE_NAME("cortex-a72");
242     bc_base->core_count = BCM283X_NCPUS;
243     bc_base->peri_base = 0xfe000000;
244     bc_base->ctrl_base = 0xff800000;
245     bc_base->clusterid = 0x0;
246     dc->realize = bcm2838_realize;
247 }
248 
249 static const TypeInfo bcm2838_type = {
250     .name           = TYPE_BCM2838,
251     .parent         = TYPE_BCM283X_BASE,
252     .instance_size  = sizeof(BCM2838State),
253     .instance_init  = bcm2838_init,
254     .class_size     = sizeof(BCM283XBaseClass),
255     .class_init     = bcm2838_class_init,
256 };
257 
bcm2838_register_types(void)258 static void bcm2838_register_types(void)
259 {
260     type_register_static(&bcm2838_type);
261 }
262 
263 type_init(bcm2838_register_types);
264