1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
4  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
5  *
6  * Vineetg: March 2009 (Supporting 2 levels of Interrupts)
7  *  Stack switching code can no longer reliably rely on the fact that
8  *  if we are NOT in user mode, stack is switched to kernel mode.
9  *  e.g. L2 IRQ interrupted a L1 ISR which had not yet completed
10  *  it's prologue including stack switching from user mode
11  *
12  * Vineetg: Aug 28th 2008: Bug #94984
13  *  -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap
14  *   Normally CPU does this automatically, however when doing FAKE rtie,
15  *   we also need to explicitly do this. The problem in macros
16  *   FAKE_RET_FROM_EXCPN and FAKE_RET_FROM_EXCPN_LOCK_IRQ was that this bit
17  *   was being "CLEARED" rather then "SET". Actually "SET" clears ZOL context
18  *
19  * Vineetg: May 5th 2008
20  *  -Modified CALLEE_REG save/restore macros to handle the fact that
21  *      r25 contains the kernel current task ptr
22  *  - Defined Stack Switching Macro to be reused in all intr/excp hdlrs
23  *  - Shaved off 11 instructions from RESTORE_ALL_INT1 by using the
24  *      address Write back load ld.ab instead of separate ld/add instn
25  *
26  * Amit Bhor, Sameer Dhavale: Codito Technologies 2004
27  */
28 
29 #ifndef __ASM_ARC_ENTRY_COMPACT_H
30 #define __ASM_ARC_ENTRY_COMPACT_H
31 
32 #include <asm/asm-offsets.h>
33 #include <asm/irqflags-compact.h>
34 #include <asm/thread_info.h>	/* For THREAD_SIZE */
35 
36 /*--------------------------------------------------------------
37  * Switch to Kernel Mode stack if SP points to User Mode stack
38  *
39  * Entry   : r9 contains pre-IRQ/exception/trap status32
40  * Exit    : SP set to K mode stack
41  *           SP at the time of entry (K/U) saved @ pt_regs->sp
42  * Clobbers: r9
43  *-------------------------------------------------------------*/
44 
45 .macro SWITCH_TO_KERNEL_STK
46 
47 	/* User Mode when this happened ? Yes: Proceed to switch stack */
48 	bbit1   r9, STATUS_U_BIT, 88f
49 
50 	/* OK we were already in kernel mode when this event happened, thus can
51 	 * assume SP is kernel mode SP. _NO_ need to do any stack switching
52 	 */
53 
54 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
55 	/* However....
56 	 * If Level 2 Interrupts enabled, we may end up with a corner case:
57 	 * 1. User Task executing
58 	 * 2. L1 IRQ taken, ISR starts (CPU auto-switched to KERNEL mode)
59 	 * 3. But before it could switch SP from USER to KERNEL stack
60 	 *      a L2 IRQ "Interrupts" L1
61 	 * Thay way although L2 IRQ happened in Kernel mode, stack is still
62 	 * not switched.
63 	 * To handle this, we may need to switch stack even if in kernel mode
64 	 * provided SP has values in range of USER mode stack ( < 0x7000_0000 )
65 	 */
66 	brlo sp, VMALLOC_START, 88f
67 
68 	/* TODO: vineetg:
69 	 * We need to be a bit more cautious here. What if a kernel bug in
70 	 * L1 ISR, caused SP to go whaco (some small value which looks like
71 	 * USER stk) and then we take L2 ISR.
72 	 * Above brlo alone would treat it as a valid L1-L2 scenario
73 	 * instead of shouting around
74 	 * The only feasible way is to make sure this L2 happened in
75 	 * L1 prelogue ONLY i.e. ilink2 is less than a pre-set marker in
76 	 * L1 ISR before it switches stack
77 	 */
78 
79 #endif
80 
81     /*------Intr/Ecxp happened in kernel mode, SP already setup ------ */
82 	/* save it nevertheless @ pt_regs->sp for uniformity */
83 
84 	b.d	66f
85 	st	sp, [sp, PT_sp - SZ_PT_REGS]
86 
87 88: /*------Intr/Ecxp happened in user mode, "switch" stack ------ */
88 
89 	GET_CURR_TASK_ON_CPU   r9
90 
91 	/* With current tsk in r9, get it's kernel mode stack base */
92 	GET_TSK_STACK_BASE  r9, r9
93 
94 	/* save U mode SP @ pt_regs->sp */
95 	st	sp, [r9, PT_sp - SZ_PT_REGS]
96 
97 	/* final SP switch */
98 	mov	sp, r9
99 66:
100 .endm
101 
102 /*------------------------------------------------------------
103  * "FAKE" a rtie to return from CPU Exception context
104  * This is to re-enable Exceptions within exception
105  * Look at EV_ProtV to see how this is actually used
106  *-------------------------------------------------------------*/
107 
108 .macro FAKE_RET_FROM_EXCPN
109 
110 	lr	r9, [status32]
111 	bclr	r9, r9, STATUS_AE_BIT
112 	or	r9, r9, (STATUS_E1_MASK|STATUS_E2_MASK)
113 	sr	r9, [erstatus]
114 	mov	r9, 55f
115 	sr	r9, [eret]
116 	rtie
117 55:
118 .endm
119 
120 /*--------------------------------------------------------------
121  * For early Exception/ISR Prologue, a core reg is temporarily needed to
122  * code the rest of prolog (stack switching). This is done by stashing
123  * it to memory (non-SMP case) or SCRATCH0 Aux Reg (SMP).
124  *
125  * Before saving the full regfile - this reg is restored back, only
126  * to be saved again on kernel mode stack, as part of pt_regs.
127  *-------------------------------------------------------------*/
128 .macro PROLOG_FREEUP_REG	reg, mem
129 	st  \reg, [\mem]
130 .endm
131 
132 .macro PROLOG_RESTORE_REG	reg, mem
133 	ld  \reg, [\mem]
134 .endm
135 
136 /*--------------------------------------------------------------
137  * Exception Entry prologue
138  * -Switches stack to K mode (if not already)
139  * -Saves the register file
140  *
141  * After this it is safe to call the "C" handlers
142  *-------------------------------------------------------------*/
143 .macro EXCEPTION_PROLOGUE_KEEP_AE
144 
145 	/* Need at least 1 reg to code the early exception prologue */
146 	PROLOG_FREEUP_REG r9, @ex_saved_reg1
147 
148 	/* U/K mode at time of exception (stack not switched if already K) */
149 	lr  r9, [erstatus]
150 
151 	/* ARC700 doesn't provide auto-stack switching */
152 	SWITCH_TO_KERNEL_STK
153 
154 	st.a	r0, [sp, -8]    /* orig_r0 needed for syscall (skip ECR slot) */
155 	sub	sp, sp, 4	/* skip pt_regs->sp, already saved above */
156 
157 	/* Restore r9 used to code the early prologue */
158 	PROLOG_RESTORE_REG  r9, @ex_saved_reg1
159 
160 	/* now we are ready to save the regfile */
161 	SAVE_R0_TO_R12
162 	PUSH	gp
163 	PUSH	fp
164 	PUSH	blink
165 	PUSHAX	eret
166 	PUSHAX	erstatus
167 	PUSH	lp_count
168 	PUSHAX	lp_end
169 	PUSHAX	lp_start
170 	PUSHAX	erbta
171 
172 	lr	r10, [ecr]
173 	st      r10, [sp, PT_event]
174 
175 #ifdef CONFIG_ARC_CURR_IN_REG
176 	/* gp already saved on stack: now load with "current" */
177 	GET_CURR_TASK_ON_CPU   gp
178 #endif
179 	; OUTPUT: r10 has ECR expected by EV_Trap
180 .endm
181 
182 .macro EXCEPTION_PROLOGUE
183 
184 	EXCEPTION_PROLOGUE_KEEP_AE	; return ECR in r10
185 
186 	lr  r0, [efa]
187 	mov r1, sp
188 
189 	FAKE_RET_FROM_EXCPN		; clobbers r9
190 .endm
191 
192 /*--------------------------------------------------------------
193  * Restore all registers used by system call or Exceptions
194  * SP should always be pointing to the next free stack element
195  * when entering this macro.
196  *
197  * NOTE:
198  *
199  * It is recommended that lp_count/ilink1/ilink2 not be used as a dest reg
200  * for memory load operations. If used in that way interrupts are deffered
201  * by hardware and that is not good.
202  *-------------------------------------------------------------*/
203 .macro EXCEPTION_EPILOGUE
204 
205 	POPAX	erbta
206 	POPAX	lp_start
207 	POPAX	lp_end
208 
209 	POP	r9
210 	mov	lp_count, r9	;LD to lp_count is not allowed
211 
212 	POPAX	erstatus
213 	POPAX	eret
214 	POP	blink
215 	POP	fp
216 	POP	gp
217 	RESTORE_R12_TO_R0
218 
219 	ld  sp, [sp] /* restore original sp */
220 	/* orig_r0, ECR skipped automatically */
221 .endm
222 
223 /* Dummy ECR values for Interrupts */
224 #define event_IRQ1		0x0031abcd
225 #define event_IRQ2		0x0032abcd
226 
227 .macro INTERRUPT_PROLOGUE  LVL
228 
229 	/* free up r9 as scratchpad */
230 	PROLOG_FREEUP_REG r9, @int\LVL\()_saved_reg
231 
232 	/* Which mode (user/kernel) was the system in when intr occurred */
233 	lr  r9, [status32_l\LVL\()]
234 
235 	SWITCH_TO_KERNEL_STK
236 
237 
238 	PUSH	0x003\LVL\()abcd    /* Dummy ECR */
239 	sub	sp, sp, 8	    /* skip orig_r0 (not needed)
240 				       skip pt_regs->sp, already saved above */
241 
242 	/* Restore r9 used to code the early prologue */
243 	PROLOG_RESTORE_REG  r9, @int\LVL\()_saved_reg
244 
245 	SAVE_R0_TO_R12
246 	PUSH	gp
247 	PUSH	fp
248 	PUSH	blink
249 	PUSH	ilink\LVL\()
250 	PUSHAX	status32_l\LVL\()
251 	PUSH	lp_count
252 	PUSHAX	lp_end
253 	PUSHAX	lp_start
254 	PUSHAX	bta_l\LVL\()
255 
256 #ifdef CONFIG_ARC_CURR_IN_REG
257 	/* gp already saved on stack: now load with "current" */
258 	GET_CURR_TASK_ON_CPU   gp
259 #endif
260 .endm
261 
262 /*--------------------------------------------------------------
263  * Restore all registers used by interrupt handlers.
264  *
265  * NOTE:
266  *
267  * It is recommended that lp_count/ilink1/ilink2 not be used as a dest reg
268  * for memory load operations. If used in that way interrupts are deffered
269  * by hardware and that is not good.
270  *-------------------------------------------------------------*/
271 .macro INTERRUPT_EPILOGUE  LVL
272 
273 	POPAX	bta_l\LVL\()
274 	POPAX	lp_start
275 	POPAX	lp_end
276 
277 	POP	r9
278 	mov	lp_count, r9	;LD to lp_count is not allowed
279 
280 	POPAX	status32_l\LVL\()
281 	POP	ilink\LVL\()
282 	POP	blink
283 	POP	fp
284 	POP	gp
285 	RESTORE_R12_TO_R0
286 
287 	ld  sp, [sp] /* restore original sp; orig_r0, ECR skipped implicitly */
288 .endm
289 
290 /* Get thread_info of "current" tsk */
291 .macro GET_CURR_THR_INFO_FROM_SP  reg
292 	bic \reg, sp, (THREAD_SIZE - 1)
293 .endm
294 
295 /* Get CPU-ID of this core */
296 .macro  GET_CPU_ID  reg
297 	lr  \reg, [identity]
298 	lsr \reg, \reg, 8
299 	bmsk \reg, \reg, 7
300 .endm
301 
302 #endif  /* __ASM_ARC_ENTRY_COMPACT_H */
303