xref: /openbmc/linux/arch/arm/boot/dts/axis/artpec6.dtsi (revision 724ba675)
1/*
2 * Device Tree Source for the Axis ARTPEC-6 SoC
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 *  a) This file is free software; you can redistribute it and/or
10 *     modify it under the terms of the GNU General Public License as
11 *     published by the Free Software Foundation; either version 2 of the
12 *     License, or (at your option) any later version.
13 *
14 *     This file is distributed in the hope that it will be useful,
15 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 *     GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 *  b) Permission is hereby granted, free of charge, to any person
22 *     obtaining a copy of this software and associated documentation
23 *     files (the "Software"), to deal in the Software without
24 *     restriction, including without limitation the rights to use,
25 *     copy, modify, merge, publish, distribute, sublicense, and/or
26 *     sell copies of the Software, and to permit persons to whom the
27 *     Software is furnished to do so, subject to the following
28 *     conditions:
29 *
30 *     The above copyright notice and this permission notice shall be
31 *     included in all copies or substantial portions of the Software.
32 *
33 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 *     OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include <dt-bindings/interrupt-controller/arm-gic.h>
44#include <dt-bindings/dma/nbpfaxi.h>
45#include <dt-bindings/clock/axis,artpec6-clkctrl.h>
46
47/ {
48	#address-cells = <1>;
49	#size-cells = <1>;
50	compatible = "axis,artpec6";
51	interrupt-parent = <&intc>;
52
53	cpus {
54		#address-cells = <1>;
55		#size-cells = <0>;
56
57		cpu0: cpu@0 {
58			device_type = "cpu";
59			compatible = "arm,cortex-a9";
60			reg = <0>;
61			next-level-cache = <&pl310>;
62		};
63
64		cpu1: cpu@1 {
65			device_type = "cpu";
66			compatible = "arm,cortex-a9";
67			reg = <1>;
68			next-level-cache = <&pl310>;
69		};
70	};
71
72	syscon: syscon@f8000000 {
73		compatible = "axis,artpec6-syscon", "syscon";
74		reg = <0xf8000000 0x48>;
75	};
76
77	psci {
78		compatible = "arm,psci-0.2", "arm,psci";
79		method = "smc";
80		psci_version = <0x84000000>;
81		cpu_on = <0x84000003>;
82		system_reset = <0x84000009>;
83	};
84
85	scu@faf00000 {
86		compatible = "arm,cortex-a9-scu";
87		reg = <0xfaf00000 0x58>;
88	};
89
90	/* Main external clock driving CPU and peripherals */
91	ext_clk: ext_clk {
92		#clock-cells = <0>;
93		compatible = "fixed-clock";
94		clock-frequency = <50000000>;
95	};
96
97	eth_phy_ref_clk: eth_phy_ref_clk {
98		#clock-cells = <0>;
99		compatible = "fixed-clock";
100		clock-frequency = <125000000>;
101	};
102
103	clkctrl: clkctrl@f8000000 {
104		#clock-cells = <1>;
105		compatible = "axis,artpec6-clkctrl";
106		reg = <0xf8000000 0x48>;
107		clocks = <&ext_clk>;
108		clock-names = "sys_refclk";
109	};
110
111	gtimer@faf00200 {
112		compatible = "arm,cortex-a9-global-timer";
113		reg = <0xfaf00200 0x20>;
114		interrupts = <GIC_PPI 11 0xf01>;
115		clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>;
116	};
117
118	timer@faf00600 {
119		compatible = "arm,cortex-a9-twd-timer";
120		reg = <0xfaf00600 0x20>;
121		interrupts = <GIC_PPI 13 0xf04>;
122		clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>;
123		status = "disabled";
124	};
125
126	intc: interrupt-controller@faf01000 {
127		interrupt-controller;
128		compatible = "arm,cortex-a9-gic";
129		#interrupt-cells = <3>;
130		reg = < 0xfaf01000 0x1000 >, < 0xfaf00100 0x0100 >;
131	};
132
133	pl310: cache-controller@faf10000 {
134		compatible = "arm,pl310-cache";
135		cache-unified;
136		cache-level = <2>;
137		reg = <0xfaf10000 0x1000>;
138		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
139		arm,data-latency = <1 1 1>;
140		arm,tag-latency = <1 1 1>;
141		arm,filter-ranges = <0x0 0x80000000>;
142		arm,double-linefill = <1>;
143		arm,double-linefill-incr = <0>;
144		arm,double-linefill-wrap = <0>;
145		prefetch-data = <1>;
146		prefetch-instr = <1>;
147		arm,prefetch-offset = <0>;
148		arm,prefetch-drop = <1>;
149	};
150
151	pmu {
152		compatible = "arm,cortex-a9-pmu";
153		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
154			<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
155		interrupt-affinity = <&cpu0>, <&cpu1>;
156	};
157
158	/*
159	 * Both pci nodes cannot be enabled at the same time,
160	 * leave the unwanted node as disabled.
161	 */
162	pcie: pcie@f8050000 {
163		compatible = "axis,artpec6-pcie", "snps,dw-pcie";
164		reg = <0xf8050000 0x2000
165		       0xf8040000 0x1000
166		       0xc0000000 0x2000>;
167		reg-names = "dbi", "phy", "config";
168		#address-cells = <3>;
169		#size-cells = <2>;
170		device_type = "pci";
171			  /* downstream I/O */
172		ranges = <0x81000000 0 0 0xc0002000 0 0x00010000
173			  /* non-prefetchable memory */
174			  0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
175		num-lanes = <2>;
176		bus-range = <0x00 0xff>;
177		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
178		interrupt-names = "msi";
179		#interrupt-cells = <1>;
180		interrupt-map-mask = <0 0 0 0x7>;
181		interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
182				<0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
183				<0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
184				<0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
185		axis,syscon-pcie = <&syscon>;
186		status = "disabled";
187	};
188
189	pcie_ep: pcie_ep@f8050000 {
190		compatible = "axis,artpec6-pcie-ep", "snps,dw-pcie";
191		reg = <0xf8050000 0x2000
192		       0xf8051000 0x2000
193		       0xf8040000 0x1000
194		       0xc0000000 0x20000000>;
195		reg-names = "dbi", "dbi2", "phy", "addr_space";
196		num-ib-windows = <6>;
197		num-ob-windows = <2>;
198		num-lanes = <2>;
199		axis,syscon-pcie = <&syscon>;
200		status = "disabled";
201	};
202
203	pinctrl: pinctrl@f801d000 {
204		compatible = "axis,artpec6-pinctrl";
205		reg = <0xf801d000 0x400>;
206
207		pinctrl_uart0: uart0grp {
208			function = "uart0";
209			groups = "uart0grp2";
210			bias-pull-up;
211		};
212		pinctrl_uart1: uart1grp {
213			function = "uart1";
214			groups = "uart1grp0";
215			bias-pull-up;
216		};
217		pinctrl_uart2: uart2grp {
218			function = "uart2";
219			groups = "uart2grp1";
220			bias-pull-up;
221		};
222		pinctrl_uart3: uart3grp {
223			function = "uart3";
224			groups = "uart3grp0";
225			bias-pull-up;
226		};
227	};
228
229	amba@0 {
230		compatible = "simple-bus";
231		#address-cells = <0x1>;
232		#size-cells = <0x1>;
233		ranges;
234		dma-ranges;
235
236		crypto@f4264000 {
237			compatible = "axis,artpec6-crypto";
238			reg = <0xf4264000 0x4000>;
239			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
240		};
241
242		dma0: dma@f8019000 {
243			compatible = "renesas,nbpfaxi64dmac8b16";
244			reg = <0xf8019000 0x400>;
245			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* error */
246				     <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
247				     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
248				     <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
249				     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
250				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
251				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
252				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
253				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
254			interrupt-names = "error",
255					  "ch0", "ch1", "ch2", "ch3",
256					  "ch4", "ch5", "ch6", "ch7",
257					  "ch8", "ch9", "ch10", "ch12",
258					  "ch12", "ch13", "ch14", "ch15";
259			clocks = <&clkctrl ARTPEC6_CLK_DMA_ACLK>;
260			#dma-cells = <2>;
261			dma-channels = <8>;
262			dma-requests = <8>;
263		};
264		dma1: dma@f8019400 {
265			compatible = "renesas,nbpfaxi64dmac8b16";
266			reg = <0xf8019400 0x400>;
267			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* error */
268				     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
269				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
270				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
271				     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
272				     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
273				     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
274				     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
275				     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
276			interrupt-names = "error",
277					  "ch0", "ch1", "ch2", "ch3",
278					  "ch4", "ch5", "ch6", "ch7",
279					  "ch8", "ch9", "ch10", "ch12",
280					  "ch12", "ch13", "ch14", "ch15";
281			clocks = <&clkctrl ARTPEC6_CLK_DMA_ACLK>;
282			#dma-cells = <2>;
283			dma-channels = <8>;
284			dma-requests = <8>;
285		};
286
287		ethernet: ethernet@f8010000 {
288			clock-names = "stmmaceth", "ptp_ref";
289			clocks = <&clkctrl ARTPEC6_CLK_ETH_ACLK>,
290				<&clkctrl ARTPEC6_CLK_PTP_REF>;
291			compatible = "snps,dwmac-4.10a", "snps,dwmac";
292			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
293				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
294			interrupt-names = "macirq", "eth_lpi";
295			reg = <0xf8010000 0x4000>;
296
297			snps,axi-config = <&stmmac_axi_setup>;
298			snps,mtl-rx-config = <&mtl_rx_setup>;
299			snps,mtl-tx-config = <&mtl_tx_setup>;
300
301			snps,txpbl = <8>;
302			snps,rxpbl = <2>;
303			snps,aal;
304			snps,tso;
305
306			status = "disabled";
307
308			stmmac_axi_setup: stmmac-axi-config {
309				snps,wr_osr_lmt = <1>;
310				snps,rd_osr_lmt = <15>;
311				/* If FB is disabled, the AXI master chooses
312				 * a burst length of any value less than the
313				 * maximum enabled burst length
314				 * (all lesser burst length enables are redundant).
315				 */
316				snps,blen = <0 0 0 0 16 0 0>;
317			};
318
319			mtl_rx_setup: rx-queues-config {
320				snps,rx-queues-to-use = <1>;
321				queue0 {};
322			};
323
324			mtl_tx_setup: tx-queues-config {
325				snps,tx-queues-to-use = <2>;
326				queue0 {};
327				queue1 {};
328			};
329		};
330
331		uart0: serial@f8036000 {
332			compatible = "arm,pl011", "arm,primecell";
333			reg = <0xf8036000 0x1000>;
334			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
335			clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
336				<&clkctrl ARTPEC6_CLK_UART_PCLK>;
337			clock-names = "uart_clk", "apb_pclk";
338			pinctrl-names = "default";
339			pinctrl-0 = <&pinctrl_uart0>;
340			dmas = <&dma0 4 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>,
341			       <&dma0 5 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>;
342			dma-names = "rx", "tx";
343			status = "disabled";
344		};
345		uart1: serial@f8037000 {
346			compatible = "arm,pl011", "arm,primecell";
347			reg = <0xf8037000 0x1000>;
348			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
349			clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
350				<&clkctrl ARTPEC6_CLK_UART_PCLK>;
351			clock-names = "uart_clk", "apb_pclk";
352			pinctrl-names = "default";
353			pinctrl-0 = <&pinctrl_uart1>;
354			dmas = <&dma0 6 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>,
355			       <&dma0 7 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>;
356			dma-names = "rx", "tx";
357			status = "disabled";
358		};
359		uart2: serial@f8038000 {
360			compatible = "arm,pl011", "arm,primecell";
361			reg = <0xf8038000 0x1000>;
362			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
363			clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
364				<&clkctrl ARTPEC6_CLK_UART_PCLK>;
365			clock-names = "uart_clk", "apb_pclk";
366			pinctrl-names = "default";
367			pinctrl-0 = <&pinctrl_uart2>;
368			dmas = <&dma1 0 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>,
369			       <&dma1 1 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>;
370			dma-names = "rx", "tx";
371			status = "disabled";
372		};
373		uart3: serial@f8039000 {
374			compatible = "arm,pl011", "arm,primecell";
375			reg = <0xf8039000 0x1000>;
376			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
377			clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
378				<&clkctrl ARTPEC6_CLK_UART_PCLK>;
379			clock-names = "uart_clk", "apb_pclk";
380			pinctrl-names = "default";
381			pinctrl-0 = <&pinctrl_uart3>;
382			dmas = <&dma1 2 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>,
383			       <&dma1 3 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>;
384			dma-names = "rx", "tx";
385			status = "disabled";
386		};
387	};
388};
389