xref: /openbmc/u-boot/arch/x86/dts/dfi-bt700.dtsi (revision 2ae23a28)
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
5 */
6
7#include <asm/arch-baytrail/fsp/fsp_configs.h>
8#include <dt-bindings/gpio/x86-gpio.h>
9#include <dt-bindings/interrupt-router/intel-irq.h>
10
11#include "skeleton.dtsi"
12#include "reset.dtsi"
13#include "rtc.dtsi"
14#include "tsc_timer.dtsi"
15
16/ {
17	config {
18		silent_console = <0>;
19	};
20
21	pch_pinctrl {
22		compatible = "intel,x86-pinctrl";
23		reg = <0 0>;
24
25		/* Add UART1 PAD configuration (SIO HS-UART) */
26		uart1_txd@0 {
27			pad-offset = <0x10>;
28			mode-func = <1>;
29		};
30
31		uart1_rxd@0 {
32			pad-offset = <0x20>;
33			mode-func = <1>;
34		};
35
36		/*
37		 * As of today, the latest version FSP (gold4) for BayTrail
38		 * misses the PAD configuration of the SD controller's Card
39		 * Detect signal. The default PAD value for the CD pin sets
40		 * the pin to work in GPIO mode, which causes card detect
41		 * status cannot be reflected by the Present State register
42		 * in the SD controller (bit 16 & bit 18 are always zero).
43		 *
44		 * Configure this pin to function 1 (SD controller).
45		 */
46		sdmmc3_cd@0 {
47			pad-offset = <0x3a0>;
48			mode-func = <1>;
49		};
50
51		xhci_hub_reset: usb_ulpi_stp@0 {
52			gpio-offset = <0xa0 10>;
53			pad-offset = <0x23b0>;
54			mode-func = <0>;
55			mode-gpio;
56			output-value = <1>;
57			direction = <PIN_OUTPUT>;
58		};
59	};
60
61	chosen {
62		stdout-path = "/serial";
63	};
64
65	cpus {
66		#address-cells = <1>;
67		#size-cells = <0>;
68
69		cpu@0 {
70			device_type = "cpu";
71			compatible = "intel,baytrail-cpu";
72			reg = <0>;
73			intel,apic-id = <0>;
74		};
75
76		cpu@1 {
77			device_type = "cpu";
78			compatible = "intel,baytrail-cpu";
79			reg = <1>;
80			intel,apic-id = <2>;
81		};
82
83		cpu@2 {
84			device_type = "cpu";
85			compatible = "intel,baytrail-cpu";
86			reg = <2>;
87			intel,apic-id = <4>;
88		};
89
90		cpu@3 {
91			device_type = "cpu";
92			compatible = "intel,baytrail-cpu";
93			reg = <3>;
94			intel,apic-id = <6>;
95		};
96	};
97
98	pci {
99		compatible = "intel,pci-baytrail", "pci-x86";
100		#address-cells = <3>;
101		#size-cells = <2>;
102		u-boot,dm-pre-reloc;
103		ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
104			  0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
105			  0x01000000 0x0 0x2000 0x2000 0 0xe000>;
106
107		pciuart0: uart@1e,3 {
108			compatible = "pci8086,0f0a.00",
109					"pci8086,0f0a",
110					"pciclass,070002",
111					"pciclass,0700",
112					"ns16550";
113			u-boot,dm-pre-reloc;
114			reg = <0x0200f310 0x0 0x0 0x0 0x0>;
115			reg-shift = <2>;
116			clock-frequency = <58982400>;
117			current-speed = <115200>;
118		};
119
120		pch@1f,0 {
121			reg = <0x0000f800 0 0 0 0>;
122			compatible = "pci8086,0f1c", "intel,pch9";
123			#address-cells = <1>;
124			#size-cells = <1>;
125
126			irq-router {
127				compatible = "intel,irq-router";
128				intel,pirq-config = "ibase";
129				intel,ibase-offset = <0x50>;
130				intel,actl-addr = <0>;
131				intel,pirq-link = <8 8>;
132				intel,pirq-mask = <0xdee0>;
133				intel,pirq-routing = <
134					/* BayTrail PCI devices */
135					PCI_BDF(0, 2, 0) INTA PIRQA
136					PCI_BDF(0, 3, 0) INTA PIRQA
137					PCI_BDF(0, 16, 0) INTA PIRQA
138					PCI_BDF(0, 17, 0) INTA PIRQA
139					PCI_BDF(0, 18, 0) INTA PIRQA
140					PCI_BDF(0, 19, 0) INTA PIRQA
141					PCI_BDF(0, 20, 0) INTA PIRQA
142					PCI_BDF(0, 21, 0) INTA PIRQA
143					PCI_BDF(0, 22, 0) INTA PIRQA
144					PCI_BDF(0, 23, 0) INTA PIRQA
145					PCI_BDF(0, 24, 0) INTA PIRQA
146					PCI_BDF(0, 24, 1) INTC PIRQC
147					PCI_BDF(0, 24, 2) INTD PIRQD
148					PCI_BDF(0, 24, 3) INTB PIRQB
149					PCI_BDF(0, 24, 4) INTA PIRQA
150					PCI_BDF(0, 24, 5) INTC PIRQC
151					PCI_BDF(0, 24, 6) INTD PIRQD
152					PCI_BDF(0, 24, 7) INTB PIRQB
153					PCI_BDF(0, 26, 0) INTA PIRQA
154					PCI_BDF(0, 27, 0) INTA PIRQA
155					PCI_BDF(0, 28, 0) INTA PIRQA
156					PCI_BDF(0, 28, 1) INTB PIRQB
157					PCI_BDF(0, 28, 2) INTC PIRQC
158					PCI_BDF(0, 28, 3) INTD PIRQD
159					PCI_BDF(0, 29, 0) INTA PIRQA
160					PCI_BDF(0, 30, 0) INTA PIRQA
161					PCI_BDF(0, 30, 1) INTD PIRQD
162					PCI_BDF(0, 30, 2) INTB PIRQB
163					PCI_BDF(0, 30, 3) INTC PIRQC
164					PCI_BDF(0, 30, 4) INTD PIRQD
165					PCI_BDF(0, 30, 5) INTB PIRQB
166					PCI_BDF(0, 31, 3) INTB PIRQB
167
168					/*
169					 * PCIe root ports downstream
170					 * interrupts
171					 */
172					PCI_BDF(1, 0, 0) INTA PIRQA
173					PCI_BDF(1, 0, 0) INTB PIRQB
174					PCI_BDF(1, 0, 0) INTC PIRQC
175					PCI_BDF(1, 0, 0) INTD PIRQD
176					PCI_BDF(2, 0, 0) INTA PIRQB
177					PCI_BDF(2, 0, 0) INTB PIRQC
178					PCI_BDF(2, 0, 0) INTC PIRQD
179					PCI_BDF(2, 0, 0) INTD PIRQA
180					PCI_BDF(3, 0, 0) INTA PIRQC
181					PCI_BDF(3, 0, 0) INTB PIRQD
182					PCI_BDF(3, 0, 0) INTC PIRQA
183					PCI_BDF(3, 0, 0) INTD PIRQB
184					PCI_BDF(4, 0, 0) INTA PIRQD
185					PCI_BDF(4, 0, 0) INTB PIRQA
186					PCI_BDF(4, 0, 0) INTC PIRQB
187					PCI_BDF(4, 0, 0) INTD PIRQC
188				>;
189			};
190
191			spi: spi {
192				#address-cells = <1>;
193				#size-cells = <0>;
194				compatible = "intel,ich9-spi";
195				spi-flash@0 {
196					#address-cells = <1>;
197					#size-cells = <1>;
198					reg = <0>;
199					compatible = "stmicro,n25q064a",
200						"spi-flash";
201					memory-map = <0xff800000 0x00800000>;
202					rw-mrc-cache {
203						label = "rw-mrc-cache";
204						reg = <0x006f0000 0x00010000>;
205					};
206				};
207			};
208
209			gpioa {
210				compatible = "intel,ich6-gpio";
211				u-boot,dm-pre-reloc;
212				reg = <0 0x20>;
213				bank-name = "A";
214				use-lvl-write-cache;
215			};
216
217			gpiob {
218				compatible = "intel,ich6-gpio";
219				u-boot,dm-pre-reloc;
220				reg = <0x20 0x20>;
221				bank-name = "B";
222				use-lvl-write-cache;
223			};
224
225			gpioc {
226				compatible = "intel,ich6-gpio";
227				u-boot,dm-pre-reloc;
228				reg = <0x40 0x20>;
229				bank-name = "C";
230				use-lvl-write-cache;
231			};
232
233			gpiod {
234				compatible = "intel,ich6-gpio";
235				u-boot,dm-pre-reloc;
236				reg = <0x60 0x20>;
237				bank-name = "D";
238				use-lvl-write-cache;
239			};
240
241			gpioe {
242				compatible = "intel,ich6-gpio";
243				u-boot,dm-pre-reloc;
244				reg = <0x80 0x20>;
245				bank-name = "E";
246				use-lvl-write-cache;
247			};
248
249			gpiof {
250				compatible = "intel,ich6-gpio";
251				u-boot,dm-pre-reloc;
252				reg = <0xA0 0x20>;
253				bank-name = "F";
254				use-lvl-write-cache;
255			};
256		};
257	};
258
259	fsp {
260		compatible = "intel,baytrail-fsp";
261		fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
262		fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
263		fsp,mrc-init-spd-addr1 = <0xa0>;
264		fsp,mrc-init-spd-addr2 = <0xa2>;
265		fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>;
266		fsp,enable-sdio;
267		fsp,enable-sdcard;
268		fsp,enable-hsuart0;
269		fsp,enable-hsuart1;
270		fsp,enable-spi;
271		fsp,enable-sata;
272		fsp,sata-mode = <SATA_MODE_AHCI>;
273#ifdef CONFIG_USB_XHCI_HCD
274		fsp,enable-xhci;
275#endif
276		fsp,lpe-mode = <LPE_MODE_PCI>;
277		fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
278		fsp,enable-dma0;
279		fsp,enable-dma1;
280		fsp,enable-i2c0;
281		fsp,enable-i2c1;
282		fsp,enable-i2c2;
283		fsp,enable-i2c3;
284		fsp,enable-i2c4;
285		fsp,enable-i2c5;
286		fsp,enable-i2c6;
287		fsp,enable-pwm0;
288		fsp,enable-pwm1;
289		fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
290		fsp,aperture-size = <APERTURE_SIZE_256MB>;
291		fsp,gtt-size = <GTT_SIZE_2MB>;
292		fsp,scc-mode = <SCC_MODE_PCI>;
293		fsp,os-selection = <OS_SELECTION_LINUX>;
294		fsp,emmc45-ddr50-enabled;
295		fsp,emmc45-retune-timer-value = <8>;
296		fsp,enable-igd;
297		fsp,enable-memory-down;
298		fsp,memory-down-params {
299			compatible = "intel,baytrail-fsp-mdp";
300			fsp,dram-speed = <DRAM_SPEED_1333MTS>;
301			fsp,dram-type = <DRAM_TYPE_DDR3L>;
302			fsp,dimm-0-enable;
303			fsp,dimm-width = <DIMM_WIDTH_X16>;
304			fsp,dimm-density = <DIMM_DENSITY_8GBIT>;
305			fsp,dimm-bus-width = <DIMM_BUS_WIDTH_64BITS>;
306			fsp,dimm-sides = <DIMM_SIDES_1RANKS>;
307
308			/* These following values might need a re-visit */
309			fsp,dimm-tcl = <8>;
310			fsp,dimm-trpt-rcd = <8>;
311			fsp,dimm-twr = <8>;
312			fsp,dimm-twtr = <4>;
313			fsp,dimm-trrd = <6>;
314			fsp,dimm-trtp = <4>;
315			fsp,dimm-tfaw = <22>;
316		};
317	};
318
319	microcode {
320		update@0 {
321#include "microcode/m0130673325.dtsi"
322		};
323		update@1 {
324#include "microcode/m0130679907.dtsi"
325		};
326	};
327};
328