xref: /openbmc/linux/arch/mips/include/asm/mips-boards/generic.h (revision e5451c8f8330e03ad3cfa16048b4daf961af434f)
1  /*
2   * This file is subject to the terms and conditions of the GNU General Public
3   * License.  See the file "COPYING" in the main directory of this archive
4   * for more details.
5   *
6   * Defines of the MIPS boards specific address-MAP, registers, etc.
7   *
8   * Copyright (C) 2000,2012 MIPS Technologies, Inc.
9   * All rights reserved.
10   * Authors: Carsten Langgaard <carstenl@mips.com>
11   *          Steven J. Hill <sjhill@mips.com>
12   */
13  #ifndef __ASM_MIPS_BOARDS_GENERIC_H
14  #define __ASM_MIPS_BOARDS_GENERIC_H
15  
16  #include <asm/addrspace.h>
17  #include <asm/byteorder.h>
18  #include <asm/mips-boards/bonito64.h>
19  
20  /*
21   * Display register base.
22   */
23  #define ASCII_DISPLAY_WORD_BASE	   0x1f000410
24  #define ASCII_DISPLAY_POS_BASE	   0x1f000418
25  
26  /*
27   * Revision register.
28   */
29  #define MIPS_REVISION_REG		   0x1fc00010
30  #define MIPS_REVISION_CORID_QED_RM5261	   0
31  #define MIPS_REVISION_CORID_CORE_LV	   1
32  #define MIPS_REVISION_CORID_BONITO64	   2
33  #define MIPS_REVISION_CORID_CORE_20K	   3
34  #define MIPS_REVISION_CORID_CORE_FPGA	   4
35  #define MIPS_REVISION_CORID_CORE_MSC	   5
36  #define MIPS_REVISION_CORID_CORE_EMUL	   6
37  #define MIPS_REVISION_CORID_CORE_FPGA2	   7
38  #define MIPS_REVISION_CORID_CORE_FPGAR2	   8
39  #define MIPS_REVISION_CORID_CORE_FPGA3	   9
40  #define MIPS_REVISION_CORID_CORE_24K	   10
41  #define MIPS_REVISION_CORID_CORE_FPGA4	   11
42  #define MIPS_REVISION_CORID_CORE_FPGA5	   12
43  
44  /**** Artificial corid defines ****/
45  /*
46   *  CoreEMUL with   Bonito   System Controller is treated like a Core20K
47   *  CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC
48   */
49  #define MIPS_REVISION_CORID_CORE_EMUL_BON  -1
50  #define MIPS_REVISION_CORID_CORE_EMUL_MSC  -2
51  
52  #define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f)
53  
54  #define MIPS_REVISION_SCON_OTHER	   0
55  #define MIPS_REVISION_SCON_SOCITSC	   1
56  #define MIPS_REVISION_SCON_SOCITSCP	   2
57  
58  /* Artificial SCON defines for MIPS_REVISION_SCON_OTHER */
59  #define MIPS_REVISION_SCON_UNKNOWN	   -1
60  #define MIPS_REVISION_SCON_GT64120	   -2
61  #define MIPS_REVISION_SCON_BONITO	   -3
62  #define MIPS_REVISION_SCON_BRTL		   -4
63  #define MIPS_REVISION_SCON_SOCIT	   -5
64  #define MIPS_REVISION_SCON_ROCIT	   -6
65  
66  #define MIPS_REVISION_SCONID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff)
67  
68  extern int mips_revision_sconid;
69  
70  #ifdef CONFIG_PCI
71  extern void mips_pcibios_init(void);
72  #else
73  #define mips_pcibios_init() do { } while (0)
74  #endif
75  
76  extern void mips_scroll_message(void);
77  extern void mips_display_message(const char *str);
78  
79  #endif	/* __ASM_MIPS_BOARDS_GENERIC_H */
80