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Searched refs:stage (Results 251 – 275 of 446) sorted by relevance

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/openbmc/u-boot/board/LaCie/net2big_v2/
H A Dkwbimage.cfg109 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
/openbmc/u-boot/board/LaCie/netspace_v2/
H A Dkwbimage-is2.cfg109 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
/openbmc/u-boot/board/cloudengines/pogo_e02/
H A Dkwbimage.cfg113 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
/openbmc/u-boot/board/Marvell/openrd/
H A Dkwbimage.cfg109 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
/openbmc/u-boot/board/raidsonic/ib62x0/
H A Dkwbimage.cfg110 # bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
/openbmc/u-boot/board/iomega/iconnect/
H A Dkwbimage.cfg109 # bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
/openbmc/u-boot/doc/
H A DREADME.m68k28 Because of this, a new port was created which no longer needs a first stage
H A DREADME.omap381 is typically used to write 2nd stage bootloader (known as 'x-loader') which is
H A DREADME.ramboot-ppc85xx18 - In very early stage of platform bringup where other boot options are not
/openbmc/linux/Documentation/ABI/
H A DREADME53 the "testing" stage, so that kernel developers can work
/openbmc/openbmc/meta-openembedded/meta-oe/dynamic-layers/meta-python/recipes-connectivity/lirc/
H A Dlirc_0.10.2.bb60 # during the configure stage, e.g ../recipe-sysroot-native/usr/bin/python3-native/python3.
/openbmc/qemu/.gitlab-ci.d/
H A Dwindows.yml14 stage: build
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-bus-fcoe30 The FCoE Controller now has a three stage creation process.
/openbmc/phosphor-ipmi-flash/
H A DREADME.md112 This supports three methods of providing the image to stage. You can send the
131 The image flashing mechanism itself is the initramfs stage during reboot. It
/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_plane.c831 pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos; in dpu_plane_atomic_check()
832 if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) { in dpu_plane_atomic_check()
1283 drm_printf(p, "\tstage=%d\n", pstate->stage); in dpu_plane_atomic_print_state()
/openbmc/linux/drivers/infiniband/hw/mlx5/
H A Dmlx5_ib.h963 .stage[_stage] = {.init = _init, .cleanup = _cleanup}
966 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX]; member
1448 int stage);
/openbmc/linux/Documentation/networking/device_drivers/ethernet/microsoft/
H A Dnetvsc.rst103 stage when packets arrive at a NIC card. The goal is to increase performance
/openbmc/linux/arch/x86/kvm/
H A Dkvm_emulate.h212 enum x86_intercept_stage stage);
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Ddm.c2420 static u8 stage; in rtl8821ae_dm_refresh_basic_rate_mask() local
2433 if (cur_stage != stage) { in rtl8821ae_dm_refresh_basic_rate_mask()
2438 } else if (cur_stage == 3 && (stage == 1 || stage == 2)) { in rtl8821ae_dm_refresh_basic_rate_mask()
2443 stage = cur_stage; in rtl8821ae_dm_refresh_basic_rate_mask()
/openbmc/u-boot/dts/
H A DKconfig105 bool "Prior stage bootloader DTB for DT control"
109 location passed to U-Boot by the prior stage bootloader.
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/
H A Dphy.c32 u8 channel, u8 *stage,
1796 u8 channel, u8 *stage, u8 *step, in _rtl92ee_phy_sw_chnl_step_by_step() argument
1838 switch (*stage) { in _rtl92ee_phy_sw_chnl_step_by_step()
1850 *stage); in _rtl92ee_phy_sw_chnl_step_by_step()
1855 if ((*stage) == 2) in _rtl92ee_phy_sw_chnl_step_by_step()
1857 (*stage)++; in _rtl92ee_phy_sw_chnl_step_by_step()
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dcs35l33.txt62 stage enters LDO operation. Starts as a default value of 50mV for a value
/openbmc/u-boot/doc/imx/habv4/guides/
H A Dmx6_mx7_spl_secure_boot.txt37 binary (u-boot-ivt.img) so it can be used by HAB API in a post ROM stage.
/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage-memphis.cfg124 # bit8 : 1 , add a sample stage
/openbmc/qemu/docs/devel/
H A Dci-definitions.rst.inc76 A gate restricts the move of code from one stage to another on a

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