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/openbmc/linux/drivers/media/dvb-frontends/
H A Dtua6100.c64 u8 reg1[] = { 0x01, 0x00, 0x00, 0x00 }; in tua6100_set_params() local
67 struct i2c_msg msg1 = { .addr = priv->i2c_address, .flags = 0, .buf = reg1, .len = 4 }; in tua6100_set_params()
82 reg1[1] = 0x2c; in tua6100_set_params()
84 reg1[1] = 0x0c; in tua6100_set_params()
87 reg1[1] |= 0x40; in tua6100_set_params()
89 reg1[1] |= 0x80; in tua6100_set_params()
107 reg1[1] |= (div >> 9) & 0x03; in tua6100_set_params()
108 reg1[2] = div >> 1; in tua6100_set_params()
109 reg1[3] = (div << 7); in tua6100_set_params()
113 reg1[3] |= (prediv - (div*_P_VAL)) & 0x7f; in tua6100_set_params()
/openbmc/linux/arch/arm/lib/
H A Dcopy_to_user.S40 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
41 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
44 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
45 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
64 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
65 str1w \ptr, \reg1, \abort
83 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
84 USERL(\abort, stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8})
H A Dmemcpy.S21 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
22 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
25 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
26 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
37 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
38 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
/openbmc/qemu/target/s390x/
H A Dioinst.c60 void ioinst_handle_xsch(S390CPU *cpu, uint64_t reg1, uintptr_t ra) in ioinst_handle_xsch() argument
78 void ioinst_handle_csch(S390CPU *cpu, uint64_t reg1, uintptr_t ra) in ioinst_handle_csch() argument
96 void ioinst_handle_hsch(S390CPU *cpu, uint64_t reg1, uintptr_t ra) in ioinst_handle_hsch() argument
735 if (SCHM_REG1_RES(reg1)) { in ioinst_handle_schm()
740 mbk = SCHM_REG1_MBK(reg1); in ioinst_handle_schm()
741 update = SCHM_REG1_UPD(reg1); in ioinst_handle_schm()
742 dct = SCHM_REG1_DCT(reg1); in ioinst_handle_schm()
781 if (RCHP_REG1_RES(reg1)) { in ioinst_handle_rchp()
786 cssid = RCHP_REG1_CSSID(reg1); in ioinst_handle_rchp()
787 chpid = RCHP_REG1_CHPID(reg1); in ioinst_handle_rchp()
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H A Ds390x-internal.h359 void ioinst_handle_xsch(S390CPU *cpu, uint64_t reg1, uintptr_t ra);
360 void ioinst_handle_csch(S390CPU *cpu, uint64_t reg1, uintptr_t ra);
361 void ioinst_handle_hsch(S390CPU *cpu, uint64_t reg1, uintptr_t ra);
362 void ioinst_handle_msch(S390CPU *cpu, uint64_t reg1, uint32_t ipb,
364 void ioinst_handle_ssch(S390CPU *cpu, uint64_t reg1, uint32_t ipb,
367 void ioinst_handle_stsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb,
369 int ioinst_handle_tsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb, uintptr_t ra);
371 void ioinst_handle_schm(S390CPU *cpu, uint64_t reg1, uint64_t reg2,
373 void ioinst_handle_rsch(S390CPU *cpu, uint64_t reg1, uintptr_t ra);
374 void ioinst_handle_rchp(S390CPU *cpu, uint64_t reg1, uintptr_t ra);
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/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_pmdemand.c387 u32 reg1, reg2; in intel_pmdemand_init_pmdemand_params() local
406 REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
408 REG_FIELD_GET(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
410 REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
412 REG_FIELD_GET(XELPDP_PMDEMAND_PIPES_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
414 REG_FIELD_GET(XELPDP_PMDEMAND_DBUFS_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
416 REG_FIELD_GET(XELPDP_PMDEMAND_PHYS_MASK, reg1); in intel_pmdemand_init_pmdemand_params()
471 u32 *reg1, u32 *reg2, bool serialized) in intel_pmdemand_update_params() argument
524 u32 reg1, mod_reg1; in intel_pmdemand_program_params() local
533 mod_reg1 = reg1; in intel_pmdemand_program_params()
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dnv04.c49 nv04_clk_pll_prog(struct nvkm_clk *clk, u32 reg1, struct nvkm_pll_vals *pv) in nv04_clk_pll_prog() argument
57 if (reg1 > 0x405c) in nv04_clk_pll_prog()
58 setPLL_double_highregs(devinit, reg1, pv); in nv04_clk_pll_prog()
60 setPLL_double_lowregs(devinit, reg1, pv); in nv04_clk_pll_prog()
62 setPLL_single(devinit, reg1, pv); in nv04_clk_pll_prog()
/openbmc/qemu/pc-bios/s390-ccw/
H A Dcio.h377 register struct subchannel_id reg1 asm ("1") = schid; in stsch_err()
386 : "d" (reg1), "a" (addr) in stsch_err()
393 register struct subchannel_id reg1 asm ("1") = schid; in msch()
401 : "d" (reg1), "a" (addr), "m" (*addr) in msch()
408 register struct subchannel_id reg1 asm ("1") = schid; in msch_err()
417 : "d" (reg1), "a" (addr), "m" (*addr) in msch_err()
432 : "d" (reg1), "a" (addr) in tsch()
439 register struct subchannel_id reg1 asm("1") = schid; in ssch()
448 : "d" (reg1), "a" (addr), "m" (*addr) in ssch()
455 register struct subchannel_id reg1 asm("1") = schid; in csch()
[all …]
/openbmc/u-boot/post/lib_powerpc/
H A Dandi.c62 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_andi() local
70 ASM_STW(reg1, stk, 0), in cpu_post_test_andi()
72 ASM_11IX(test->cmd, reg1, reg0, test->op2), in cpu_post_test_andi()
73 ASM_STW(reg1, stk, 8), in cpu_post_test_andi()
74 ASM_LWZ(reg1, stk, 0), in cpu_post_test_andi()
H A Dthreei.c76 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_threei() local
84 ASM_STW(reg1, stk, 0), in cpu_post_test_threei()
86 ASM_11IX(test->cmd, reg1, reg0, test->op2), in cpu_post_test_threei()
87 ASM_STW(reg1, stk, 8), in cpu_post_test_threei()
88 ASM_LWZ(reg1, stk, 0), in cpu_post_test_threei()
/openbmc/linux/arch/s390/kvm/
H A Dpriv.c260 int reg1, reg2; in handle_iske() local
299 vcpu->run->s.regs.gprs[reg1] &= ~0xff; in handle_iske()
300 vcpu->run->s.regs.gprs[reg1] |= key; in handle_iske()
307 int reg1, reg2; in handle_rrbe() local
358 int reg1, reg2; in handle_sske() local
1041 int reg1, reg2; in handle_epsw() local
1071 int reg1, reg2; in handle_pfmf() local
1361 reg = reg1; in kvm_s390_handle_lctl()
1396 reg = reg1; in kvm_s390_handle_stctl()
1434 reg = reg1; in handle_lctlg()
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H A Dtrace.h287 TP_PROTO(VCPU_PROTO_COMMON, int g, int reg1, int reg3, u64 addr),
288 TP_ARGS(VCPU_ARGS_COMMON, g, reg1, reg3, addr),
293 __field(int, reg1)
301 __entry->reg1 = reg1;
308 __entry->reg1, __entry->reg3, __entry->addr)
312 TP_PROTO(VCPU_PROTO_COMMON, int g, int reg1, int reg3, u64 addr),
313 TP_ARGS(VCPU_ARGS_COMMON, g, reg1, reg3, addr),
318 __field(int, reg1)
326 __entry->reg1 = reg1;
333 __entry->reg1, __entry->reg3, __entry->addr)
/openbmc/linux/arch/parisc/net/
H A Dbpf_jit.h103 #define hppa_or(reg1, reg2, target) \ argument
105 #define hppa_or_cond(reg1, reg2, cond, f, target) \ argument
106 hppa_t6_insn(0x02, reg2, reg1, cond, f, 0x09, target)
107 #define hppa_and(reg1, reg2, target) \ argument
109 #define hppa_and_cond(reg1, reg2, cond, f, target) \ argument
110 hppa_t6_insn(0x02, reg2, reg1, cond, f, 0x08, target)
111 #define hppa_xor(reg1, reg2, target) \ argument
113 #define hppa_add(reg1, reg2, target) \ argument
115 #define hppa_addc(reg1, reg2, target) \ argument
117 #define hppa_sub(reg1, reg2, target) \ argument
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/openbmc/linux/drivers/mcb/
H A Dmcb-parse.c47 __le32 reg1; in chameleon_parse_gdd() local
54 reg1 = readl(&gdd->reg1); in chameleon_parse_gdd()
59 mdev->id = GDD_DEV(reg1); in chameleon_parse_gdd()
60 mdev->rev = GDD_REV(reg1); in chameleon_parse_gdd()
61 mdev->var = GDD_VAR(reg1); in chameleon_parse_gdd()
93 mdev->irq.start = GDD_IRQ(reg1); in chameleon_parse_gdd()
94 mdev->irq.end = GDD_IRQ(reg1); in chameleon_parse_gdd()
/openbmc/linux/arch/x86/events/intel/
H A Duncore_snbep.c944 reg1->alloc = 0; in snbep_cbox_put_constraint()
1130 reg1->alloc = 0; in snbep_pcu_put_constraint()
1142 reg1->config = event->attr.config1 & (0xff << (reg1->idx * 8)); in snbep_pcu_hw_config()
1195 reg1->idx = 0; in snbep_qpi_hw_config()
2604 reg1->idx = 0; in hswep_ubox_hw_config()
2858 reg1->config = event->attr.config1 & (0xff << reg1->idx); in hswep_pcu_hw_config()
4637 reg1->idx = 0; in snr_cha_hw_config()
4649 wrmsrl(reg1->reg, reg1->config); in snr_cha_enable_event()
4842 reg1->config = event->attr.config1 & (0xff << reg1->idx); in snr_pcu_hw_config()
5300 reg1->idx = 0; in icx_cha_hw_config()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn302/
H A Dirq_service_dcn302.c195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
196 .enable_reg = SRI(reg1, block, reg_num),\
197 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
199 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
200 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
213 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
214 .enable_reg = SRI_DMUB(reg1),\
216 reg1 ## __ ## mask1 ## _MASK,\
218 reg1 ## __ ## mask1 ## _MASK,\
219 ~reg1 ## __ ## mask1 ## _MASK \
/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn21/
H A Dirq_service_dcn21.c215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
216 .enable_reg = SRI(reg1, block, reg_num),\
218 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
220 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
221 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
229 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
230 .enable_reg = SRI_DMUB(reg1),\
232 reg1 ## __ ## mask1 ## _MASK,\
234 reg1 ## __ ## mask1 ## _MASK,\
235 ~reg1 ## __ ## mask1 ## _MASK \
/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn314/
H A Dirq_service_dcn314.c210 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
211 .enable_reg = SRI(reg1, block, reg_num),\
213 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
215 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
216 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
224 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
225 .enable_reg = SRI_DMUB(reg1),\
227 reg1 ## __ ## mask1 ## _MASK,\
229 reg1 ## __ ## mask1 ## _MASK,\
230 ~reg1 ## __ ## mask1 ## _MASK \
/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn315/
H A Dirq_service_dcn315.c215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
216 .enable_reg = SRI(reg1, block, reg_num),\
218 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
220 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
221 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
229 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
230 .enable_reg = SRI_DMUB(reg1),\
232 reg1 ## __ ## mask1 ## _MASK,\
234 reg1 ## __ ## mask1 ## _MASK,\
235 ~reg1 ## __ ## mask1 ## _MASK \
/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn31/
H A Dirq_service_dcn31.c208 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
209 .enable_reg = SRI(reg1, block, reg_num),\
211 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
213 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
214 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
222 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
223 .enable_reg = SRI_DMUB(reg1),\
225 reg1 ## __ ## mask1 ## _MASK,\
227 reg1 ## __ ## mask1 ## _MASK,\
228 ~reg1 ## __ ## mask1 ## _MASK \
/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn32/
H A Dirq_service_dcn32.c209 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
210 .enable_reg = SRI(reg1, block, reg_num),\
212 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
214 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
215 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
223 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
224 .enable_reg = SRI_DMUB(reg1),\
226 reg1 ## __ ## mask1 ## _MASK,\
228 reg1 ## __ ## mask1 ## _MASK,\
229 ~reg1 ## __ ## mask1 ## _MASK \
/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn30/
H A Dirq_service_dcn30.c220 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
221 .enable_reg = SRI(reg1, block, reg_num),\
223 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
225 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
226 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
234 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
235 .enable_reg = SRI_DMUB(reg1),\
237 reg1 ## __ ## mask1 ## _MASK,\
239 reg1 ## __ ## mask1 ## _MASK,\
240 ~reg1 ## __ ## mask1 ## _MASK \
/openbmc/linux/arch/arm64/lib/
H A Dcopy_to_user.S46 .macro ldp1 reg1, reg2, ptr, val
47 ldp \reg1, \reg2, [\ptr], \val
50 .macro stp1 reg1, reg2, ptr, val
51 user_stp 9997f, \reg1, \reg2, \ptr, \val
H A Dcopy_from_user.S47 .macro ldp1 reg1, reg2, ptr, val
48 user_ldp 9997f, \reg1, \reg2, \ptr, \val
51 .macro stp1 reg1, reg2, ptr, val
52 stp \reg1, \reg2, [\ptr], \val
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dnv04.c185 new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580) in new_ramdac580() argument
187 bool head_a = (reg1 == 0x680508); in new_ramdac580()
198 setPLL_double_highregs(struct nvkm_devinit *init, u32 reg1, in setPLL_double_highregs() argument
204 uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70); in setPLL_double_highregs()
205 uint32_t oldpll1 = nvkm_rd32(device, reg1); in setPLL_double_highregs()
212 int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1); in setPLL_double_highregs()
220 if (chip_version > 0x40 && reg1 >= 0x680508) { /* !nv40 */ in setPLL_double_highregs()
222 ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580); in setPLL_double_highregs()
246 switch (reg1) { in setPLL_double_highregs()
267 nvkm_wr32(device, reg1, pll1); in setPLL_double_highregs()

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