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Searched refs:rate (Results 301 – 325 of 3152) sorted by relevance

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/openbmc/linux/sound/soc/codecs/
H A Dcs42xx8.c49 u32 rate[2]; member
267 u32 rate[2]; in cs42xx8_hw_params() local
275 rate[tx] = params_rate(params); in cs42xx8_hw_params()
276 rate[!tx] = cs42xx8->rate[!tx]; in cs42xx8_hw_params()
278 ratio[tx] = rate[tx] > 0 ? cs42xx8->sysclk / rate[tx] : 0; in cs42xx8_hw_params()
279 ratio[!tx] = rate[!tx] > 0 ? cs42xx8->sysclk / rate[!tx] : 0; in cs42xx8_hw_params()
286 if (rate[i] < 50000) { in cs42xx8_hw_params()
288 } else if (rate[i] > 50000 && rate[i] < 100000) { in cs42xx8_hw_params()
290 } else if (rate[i] > 100000 && rate[i] < 200000) { in cs42xx8_hw_params()
336 cs42xx8->rate[tx] = params_rate(params); in cs42xx8_hw_params()
[all …]
H A Dtlv320aic32x4-clk.c143 u64 rate; in clk_aic32x4_pll_calc_rate() local
148 rate = (u64) parent_rate * settings->r * in clk_aic32x4_pll_calc_rate()
151 return (unsigned long) DIV_ROUND_UP_ULL(rate, settings->p * 10000); in clk_aic32x4_pll_calc_rate()
155 unsigned long rate, unsigned long parent_rate) in clk_aic32x4_pll_calc_muldiv() argument
168 multiplier = (u64) rate * settings->p * 10000; in clk_aic32x4_pll_calc_muldiv()
217 req->rate = clk_aic32x4_pll_calc_rate(&settings, req->best_parent_rate); in clk_aic32x4_pll_determine_rate()
223 unsigned long rate, in clk_aic32x4_pll_set_rate() argument
230 ret = clk_aic32x4_pll_calc_muldiv(&settings, rate, parent_rate); in clk_aic32x4_pll_set_rate()
323 divisor = DIV_ROUND_UP(parent_rate, rate); in clk_aic32x4_div_set_rate()
336 divisor = DIV_ROUND_UP(req->best_parent_rate, req->rate); in clk_aic32x4_div_determine_rate()
[all …]
H A Dssm4567.c203 unsigned int rate = params_rate(params); in ssm4567_hw_params() local
206 if (rate >= 8000 && rate <= 12000) in ssm4567_hw_params()
208 else if (rate >= 16000 && rate <= 24000) in ssm4567_hw_params()
210 else if (rate >= 32000 && rate <= 48000) in ssm4567_hw_params()
212 else if (rate >= 64000 && rate <= 96000) in ssm4567_hw_params()
214 else if (rate >= 128000 && rate <= 192000) in ssm4567_hw_params()
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32h7-pinctrl.dtsi53 slew-rate = <0>;
68 slew-rate = <2>;
80 slew-rate = <3>;
93 slew-rate = <3>;
99 slew-rate = <3>;
121 slew-rate = <3>;
148 slew-rate = <3>;
161 slew-rate = <3>;
167 slew-rate = <3>;
192 slew-rate = <2>;
[all …]
/openbmc/linux/drivers/clk/mxs/
H A Dclk-ref.c60 static long clk_ref_round_rate(struct clk_hw *hw, unsigned long rate, in clk_ref_round_rate() argument
67 tmp = tmp * 18 + rate / 2; in clk_ref_round_rate()
68 do_div(tmp, rate); in clk_ref_round_rate()
83 static int clk_ref_set_rate(struct clk_hw *hw, unsigned long rate, in clk_ref_set_rate() argument
92 tmp = tmp * 18 + rate / 2; in clk_ref_set_rate()
93 do_div(tmp, rate); in clk_ref_set_rate()
H A Dclk-ssp.c21 void mxs_ssp_set_clk_rate(struct mxs_ssp *ssp, unsigned int rate) in mxs_ssp_set_clk_rate() argument
30 clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide); in mxs_ssp_set_clk_rate()
38 "%s: cannot set clock to %d\n", __func__, rate); in mxs_ssp_set_clk_rate()
54 __func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate); in mxs_ssp_set_clk_rate()
/openbmc/linux/drivers/clk/sunxi-ng/
H A Dccu_frac.c57 unsigned long rate) in ccu_frac_helper_has_rate() argument
62 return (cf->rates[0] == rate) || (cf->rates[1] == rate); in ccu_frac_helper_has_rate()
90 unsigned long rate, u32 lock) in ccu_frac_helper_set_rate() argument
98 if (cf->rates[0] == rate) in ccu_frac_helper_set_rate()
100 else if (cf->rates[1] == rate) in ccu_frac_helper_set_rate()
/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zc1751-xm015-dc1.dts142 slew-rate = <SLEW_RATE_SLOW>;
155 slew-rate = <SLEW_RATE_SLOW>;
168 slew-rate = <SLEW_RATE_SLOW>;
198 slew-rate = <SLEW_RATE_FAST>;
206 slew-rate = <SLEW_RATE_SLOW>;
218 slew-rate = <SLEW_RATE_SLOW>;
243 slew-rate = <SLEW_RATE_SLOW>;
257 slew-rate = <SLEW_RATE_SLOW>;
271 slew-rate = <SLEW_RATE_SLOW>;
284 slew-rate = <SLEW_RATE_SLOW>;
[all …]
/openbmc/linux/tools/testing/selftests/alsa/
H A Dtest-pcmtest-driver.c25 unsigned int rate; member
80 return rate * channels * snd_pcm_format_physical_width(format) / 8; in get_sec_buf_len()
99 snd_pcm_hw_params_set_rate_near(*handle, hwparams, &params->rate, 0); in setup_handle()
141 self->params.rate = 8000; in FIXTURE_SETUP()
147 self->params.sec_buf_len = get_sec_buf_len(self->params.rate, self->params.channels, in FIXTURE_SETUP()
184 params->rate * params->channels * params->time); in TEST_F()
192 write_res = snd_pcm_writei(handle, samples, params->rate * params->time); in TEST_F()
223 params->rate * params->channels * params->time); in TEST_F()
224 read_res = snd_pcm_readi(handle, samples, params->rate * params->time); in TEST_F()
259 read_res = snd_pcm_readn(handle, (void **)chan_samples, params.rate * params.time); in TEST_F()
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/openbmc/linux/drivers/devfreq/
H A Drk3399_dmc.c49 unsigned long rate, target_rate; member
74 unsigned long old_clk_rate = dmcfreq->rate; in rk3399_dmcfreq_target()
92 if (dmcfreq->rate == target_rate) in rk3399_dmcfreq_target()
196 if (dmcfreq->rate != target_rate) { in rk3399_dmcfreq_target()
198 target_rate, dmcfreq->rate); in rk3399_dmcfreq_target()
208 dmcfreq->rate = target_rate; in rk3399_dmcfreq_target()
229 stat->current_frequency = dmcfreq->rate; in rk3399_dmcfreq_get_dev_status()
240 *freq = dmcfreq->rate; in rk3399_dmcfreq_get_cur_freq()
420 data->rate = clk_get_rate(data->dmc_clk); in rk3399_dmcfreq_probe()
428 data->rate = dev_pm_opp_get_freq(opp); in rk3399_dmcfreq_probe()
[all …]
H A Dimx8m-ddrc.c27 unsigned long rate; member
80 unsigned long rate) in imx8m_ddrc_find_freq() argument
89 rate = DIV_ROUND_CLOSEST(rate, 250000); in imx8m_ddrc_find_freq()
92 if (freq->rate == rate || in imx8m_ddrc_find_freq()
93 freq->rate + 1 == rate || in imx8m_ddrc_find_freq()
94 freq->rate - 1 == rate) in imx8m_ddrc_find_freq()
306 freq->rate = res.a0; in imx8m_ddrc_init_freq_info()
/openbmc/linux/drivers/clk/renesas/
H A Drcar-gen4-cpg.c93 mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate); in cpg_pll_clk_determine_rate()
96 req->rate = prate * mult; in cpg_pll_clk_determine_rate()
100 static int cpg_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate, in cpg_pll_clk_set_rate() argument
107 mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * 2); in cpg_pll_clk_set_rate()
214 unsigned long rate, prate; in cpg_z_clk_determine_rate() local
216 rate = min(req->rate, req->max_rate); in cpg_z_clk_determine_rate()
217 if (rate <= zclk->max_rate) { in cpg_z_clk_determine_rate()
222 prate = rate; in cpg_z_clk_determine_rate()
233 mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate); in cpg_z_clk_determine_rate()
236 req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32); in cpg_z_clk_determine_rate()
[all …]
/openbmc/linux/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7780.c24 clk->rate *= pfc_divisors[__raw_readl(FRQCR) & 0x0003]; in master_clk_init()
34 return clk->parent->rate / pfc_divisors[idx]; in module_clk_recalc()
44 return clk->parent->rate / bfc_divisors[idx]; in bus_clk_recalc()
54 return clk->parent->rate / ifc_divisors[idx]; in cpu_clk_recalc()
77 return clk->parent->rate / cfc_divisors[idx]; in shyway_clk_recalc()
/openbmc/linux/arch/arm/mach-footbridge/
H A Ddc21285-timer.c110 unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16); in footbridge_timer_init() local
112 clocksource_register_hz(&cksrc_dc21285, rate); in footbridge_timer_init()
119 clockevents_config_and_register(ce, rate, 0x4, 0xffffff); in footbridge_timer_init()
129 unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16); in footbridge_sched_clock() local
135 sched_clock_register(footbridge_read_sched_clock, 24, rate); in footbridge_sched_clock()
/openbmc/linux/drivers/clk/sprd/
H A Dpll.c86 static u32 pll_get_ibias(u64 rate, const u64 *table) in pll_get_ibias() argument
92 if (rate <= table[i + 1]) in pll_get_ibias()
103 unsigned long rate, nint, kint = 0; in _sprd_pll_recalc_rate() local
125 rate = refin * pinternal_val(pll, cfg, PLL_N) * CLK_PLL_10M; in _sprd_pll_recalc_rate()
135 rate = DIV_ROUND_CLOSEST_ULL(refin * kint * k1, in _sprd_pll_recalc_rate()
141 return rate; in _sprd_pll_recalc_rate()
148 unsigned long rate, in _sprd_pll_set_rate() argument
156 u64 tmp, refin, fvco = rate; in _sprd_pll_set_rate()
240 unsigned long rate, in sprd_pll_set_rate() argument
245 return _sprd_pll_set_rate(pll, rate, parent_rate); in sprd_pll_set_rate()
[all …]
/openbmc/linux/drivers/staging/rtl8712/
H A Dieee80211.c61 uint r8712_is_cckrates_included(u8 *rate) in r8712_is_cckrates_included() argument
65 while (rate[i] != 0) { in r8712_is_cckrates_included()
66 if ((((rate[i]) & 0x7f) == 2) || (((rate[i]) & 0x7f) == 4) || in r8712_is_cckrates_included()
67 (((rate[i]) & 0x7f) == 11) || (((rate[i]) & 0x7f) == 22)) in r8712_is_cckrates_included()
74 uint r8712_is_cckratesonly_included(u8 *rate) in r8712_is_cckratesonly_included() argument
78 while (rate[i] != 0) { in r8712_is_cckratesonly_included()
79 if ((((rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) && in r8712_is_cckratesonly_included()
80 (((rate[i]) & 0x7f) != 11) && (((rate[i]) & 0x7f) != 22)) in r8712_is_cckratesonly_included()
/openbmc/u-boot/drivers/clk/altera/
H A Dclk-arria10.c121 ulong rate = 0, reg, numer, denom; in socfpga_a10_clk_get_rate() local
128 rate = clk_get_rate(upclk); in socfpga_a10_clk_get_rate()
136 rate /= denom + 1; in socfpga_a10_clk_get_rate()
137 rate *= numer + 1; in socfpga_a10_clk_get_rate()
144 rate /= denom + 1; in socfpga_a10_clk_get_rate()
145 rate *= numer + 1; in socfpga_a10_clk_get_rate()
147 rate /= plat->fix_div; in socfpga_a10_clk_get_rate()
152 rate /= reg + 1; in socfpga_a10_clk_get_rate()
160 rate /= reg + 1; in socfpga_a10_clk_get_rate()
162 rate /= 1 << reg; in socfpga_a10_clk_get_rate()
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/openbmc/linux/drivers/i3c/master/mipi-i3c-hci/
H A Dcmd_v2.c95 unsigned int rate) in hci_cmd_v2_prep_private_xfer() argument
108 CMD_U0_XFER_RATE(rate) | in hci_cmd_v2_prep_private_xfer()
142 CMD_U0_XFER_RATE(rate) | in hci_cmd_v2_prep_private_xfer()
155 unsigned int rate = get_i3c_rate_idx(hci); in hci_cmd_v2_prep_ccc() local
161 hci_cmd_v2_prep_private_xfer(hci, xfer, ccc_addr, mode, rate); in hci_cmd_v2_prep_ccc()
172 CMD_U0_XFER_RATE(rate) | in hci_cmd_v2_prep_ccc()
204 CMD_U0_XFER_RATE(rate) | in hci_cmd_v2_prep_ccc()
222 unsigned int rate = get_i3c_rate_idx(hci); in hci_cmd_v2_prep_i3c_xfer() local
225 hci_cmd_v2_prep_private_xfer(hci, xfer, addr, mode, rate); in hci_cmd_v2_prep_i3c_xfer()
233 unsigned int rate = get_i2c_rate_idx(hci); in hci_cmd_v2_prep_i2c_xfer() local
[all …]
/openbmc/linux/drivers/clk/spear/
H A Dclk-vco-pll.c69 unsigned long rate = prate; in pll_calc_rate() local
73 rate = (((2 * rate / 10000) * rtbl[index].m) / (mode * rtbl[index].n)); in pll_calc_rate()
76 *pll_rate = (rate / (1 << rtbl[index].p)) * 10000; in pll_calc_rate()
78 return rate * 10000; in pll_calc_rate()
85 unsigned long prev_rate, vco_prev_rate, rate = 0; in clk_pll_round_rate_index() local
95 prev_rate = rate; in clk_pll_round_rate_index()
98 &rate); in clk_pll_round_rate_index()
99 if (drate < rate) { in clk_pll_round_rate_index()
102 rate = prev_rate; in clk_pll_round_rate_index()
110 return rate; in clk_pll_round_rate_index()
/openbmc/linux/arch/sh/kernel/cpu/sh3/
H A Dclock-sh7710.c26 clk->rate *= md_table[__raw_readw(FRQCR) & 0x0007]; in master_clk_init()
36 return clk->parent->rate / md_table[idx]; in module_clk_recalc()
46 return clk->parent->rate / md_table[idx]; in bus_clk_recalc()
56 return clk->parent->rate / md_table[idx]; in cpu_clk_recalc()
/openbmc/linux/drivers/clk/mvebu/
H A Dcommon.c113 unsigned long rate; in mvebu_coreclk_setup() local
137 rate = desc->get_tclk_freq(base); in mvebu_coreclk_setup()
139 rate); in mvebu_coreclk_setup()
145 rate = desc->get_cpu_freq(base); in mvebu_coreclk_setup()
149 rate = desc->fix_sscg_deviation(rate); in mvebu_coreclk_setup()
152 rate); in mvebu_coreclk_setup()
173 rate = desc->get_refclk_freq(base); in mvebu_coreclk_setup()
175 clk_register_fixed_rate(NULL, name, NULL, 0, rate); in mvebu_coreclk_setup()
/openbmc/linux/sound/pci/echoaudio/
H A Dgina24_dsp.c164 static int set_sample_rate(struct echoaudio *chip, u32 rate) in set_sample_rate() argument
168 if (snd_BUG_ON(rate >= 50000 && in set_sample_rate()
177 chip->comm_page->sample_rate = cpu_to_le32(rate); in set_sample_rate()
178 chip->sample_rate = rate; in set_sample_rate()
187 switch (rate) { in set_sample_rate()
221 "set_sample_rate: %d invalid!\n", rate); in set_sample_rate()
227 chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP */ in set_sample_rate()
228 chip->sample_rate = rate; in set_sample_rate()
229 dev_dbg(chip->card->dev, "set_sample_rate: %d clock %d\n", rate, clock); in set_sample_rate()
/openbmc/linux/sound/firewire/motu/
H A Dmotu-protocol-v2.c34 static int get_clock_rate(u32 data, unsigned int *rate) in get_clock_rate() argument
40 *rate = snd_motu_clock_rates[index]; in get_clock_rate()
46 unsigned int *rate) in snd_motu_protocol_v2_get_clock_rate() argument
56 return get_clock_rate(be32_to_cpu(reg), rate); in snd_motu_protocol_v2_get_clock_rate()
60 unsigned int rate) in snd_motu_protocol_v2_set_clock_rate() argument
68 if (snd_motu_clock_rates[i] == rate) in snd_motu_protocol_v2_set_clock_rate()
172 unsigned int rate; in switch_fetching_mode_spartan() local
180 err = get_clock_rate(*data, &rate); in switch_fetching_mode_spartan()
184 if (src == SND_MOTU_CLOCK_SOURCE_SPH && rate > 48000) in switch_fetching_mode_spartan()
/openbmc/linux/drivers/clk/hisilicon/
H A Dclk-hi6220-stub.c119 u32 rate = 0; in hi6220_stub_clk_recalc_rate() local
124 rate = hi6220_acpu_get_freq(stub_clk); in hi6220_stub_clk_recalc_rate()
127 rate *= 1000; in hi6220_stub_clk_recalc_rate()
136 return rate; in hi6220_stub_clk_recalc_rate()
139 static int hi6220_stub_clk_set_rate(struct clk_hw *hw, unsigned long rate, in hi6220_stub_clk_set_rate() argument
143 unsigned long new_rate = rate / 1000; /* kHz */ in hi6220_stub_clk_set_rate()
164 static long hi6220_stub_clk_round_rate(struct clk_hw *hw, unsigned long rate, in hi6220_stub_clk_round_rate() argument
168 unsigned long new_rate = rate / 1000; /* kHz */ in hi6220_stub_clk_round_rate()
/openbmc/linux/Documentation/scheduler/
H A Dsched-debug.rst14 high then the rate the kernel samples for NUMA hinting faults may be
28 In combination, the "scan delay" and "scan size" determine the scan rate.
29 When "scan delay" decreases, the scan rate increases. The scan delay and
30 hence the scan rate of every task is adaptive and depends on historical
33 the higher the "scan size", the higher the scan rate.
37 rate, the more quickly a tasks memory is migrated to a local node if the
44 rate for each task.
51 rate for each task.

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