/openbmc/qemu/hw/m68k/ |
H A D | q800-glue.c | 89 qemu_set_irq(s->irqs[GLUE_IRQ_NUBUS_9], level); in GLUE_set_irq() 102 qemu_set_irq(s->irqs[GLUE_IRQ_ASC], !level); in GLUE_set_irq()
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/openbmc/qemu/hw/ssi/ |
H A D | omap_spi.c | 59 qemu_set_irq(s->irq, s->irqst & s->irqen); in omap_mcspi_interrupt_update() 64 qemu_set_irq(ch->txdrq, in omap_mcspi_dmarequest_update() 69 qemu_set_irq(ch->rxdrq, in omap_mcspi_dmarequest_update()
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H A D | mss-spi.c | 137 qemu_set_irq(s->irq, irq); in spi_update_irq() 206 qemu_set_irq(s->cs_line, 0); in assert_cs() 211 qemu_set_irq(s->cs_line, 1); in deassert_cs()
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H A D | imx_spi.c | 119 qemu_set_irq(s->irq, level); in imx_spi_update_irq() 268 qemu_set_irq(s->cs_lines[i], 1); in imx_spi_soft_reset() 408 qemu_set_irq(s->cs_lines[i], in imx_spi_write()
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/openbmc/qemu/hw/misc/ |
H A D | armsse-mhu.c | 60 qemu_set_irq(s->cpu0irq, s->cpu0intr != 0); in armsse_mhu_update() 61 qemu_set_irq(s->cpu1irq, s->cpu1intr != 0); in armsse_mhu_update()
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H A D | nrf51_rng.c | 26 qemu_set_irq(s->irq, irq); in update_irq() 155 qemu_set_irq(s->eep_valrdy, 1); in nrf51_rng_timer_expire()
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/openbmc/qemu/target/rx/ |
H A D | helper.c | 70 qemu_set_irq(env->ack, env->ack_irq); in rx_cpu_do_interrupt() 80 qemu_set_irq(env->ack, env->ack_irq); in rx_cpu_do_interrupt()
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/openbmc/qemu/hw/sd/ |
H A D | pxa2xx_mmci.c | 173 qemu_set_irq(s->rx_dma, !!(s->intreq & INT_RXFIFO_REQ)); in pxa2xx_mmci_int_update() 174 qemu_set_irq(s->tx_dma, !!(s->intreq & INT_TXFIFO_REQ)); in pxa2xx_mmci_int_update() 177 qemu_set_irq(s->irq, !!(s->intreq & ~mask)); in pxa2xx_mmci_int_update() 494 qemu_set_irq(s->inserted, inserted); in pxa2xx_mmci_set_inserted() 501 qemu_set_irq(s->readonly, readonly); in pxa2xx_mmci_set_readonly()
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H A D | omap_mmc.c | 73 qemu_set_irq(s->irq, !!(s->status & s->mask)); in omap_mmc_interrupts_update() 312 qemu_set_irq(host->coverswitch, host->cdet_state); in omap_mmc_reset() 589 qemu_set_irq(host->coverswitch, level); in omap_mmc_cover_cb() 656 qemu_set_irq(cover, s->cdet_state); in omap_mmc_handlers()
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/openbmc/qemu/hw/timer/ |
H A D | hpet.c | 624 qemu_set_irq(s->pit_enabled, 0); in hpet_ram_write() 629 qemu_set_irq(s->pit_enabled, 1); in hpet_ram_write() 630 qemu_set_irq(s->irqs[RTC_ISA_IRQ], s->rtc_irq_level); in hpet_ram_write() 700 qemu_set_irq(s->pit_enabled, 1); in hpet_reset() 717 qemu_set_irq(s->irqs[0], level); in hpet_handle_legacy_irq() 722 qemu_set_irq(s->irqs[RTC_ISA_IRQ], level); in hpet_handle_legacy_irq()
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H A D | bcm2835_systmr.c | 37 qemu_set_irq(tmr->irq, 1); in bcm2835_systmr_timer_expire() 86 qemu_set_irq(s->tmr[index].irq, 0); in bcm2835_systmr_write()
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H A D | altera_timer.c | 145 qemu_set_irq(t->irq, timer_irq_state(t)); in timer_write() 175 qemu_set_irq(t->irq, timer_irq_state(t)); in timer_hit()
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/openbmc/qemu/hw/gpio/ |
H A D | mpc8xxx.c | 64 qemu_set_irq(s->irq, !!(s->ier & s->imr)); in mpc8xxx_gpio_update() 109 qemu_set_irq(s->out[i], (new_data & mask) != 0); in mpc8xxx_write_data()
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H A D | omap_gpio.c | 133 qemu_set_irq(s->handler[ln], (value >> ln) & 1); in omap_gpio_write() 145 qemu_set_irq(s->handler[ln], (value >> ln) & 1); in omap_gpio_write() 231 qemu_set_irq(s->irq[line], s->ints[line] & s->mask[line]); in omap2_gpio_module_int_update() 254 qemu_set_irq(s->handler[ln], (s->outputs >> ln) & 1); in omap2_gpio_module_out_update() 445 qemu_set_irq(s->handler[ln], (value >> ln) & 1); in omap2_gpio_module_write()
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/openbmc/qemu/hw/xtensa/ |
H A D | mx_pic.c | 145 qemu_set_irq(mx->cpu[cpu].irq[i], irq & mask); in xtensa_mx_pic_update_cpu() 241 qemu_set_irq(mx->cpu[cpu].runstall, v & (1u << cpu)); in xtensa_mx_pic_ext_reg_write() 347 qemu_set_irq(mx->cpu[i].runstall, i > 0); in xtensa_mx_pic_reset()
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/openbmc/qemu/hw/arm/ |
H A D | strongarm.c | 118 qemu_set_irq(s->fiq, s->pending & s->enabled & s->is_fiq); in strongarm_pic_update() 119 qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq); in strongarm_pic_update() 274 qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL); in strongarm_rtc_int_update() 275 qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ); in strongarm_rtc_int_update() 505 qemu_set_irq(s->irqs[i], s->status & (1 << i)); in strongarm_gpio_irq_update() 508 qemu_set_irq(s->irqX, (s->status & ~0x7ff)); in strongarm_gpio_irq_update() 542 qemu_set_irq(s->handler[bit], (level >> bit) & 1); in strongarm_gpio_handler_update() 755 qemu_set_irq(s->handler[bit], (level >> bit) & 1); in strongarm_ppc_handler_update() 995 qemu_set_irq(s->irq, utsr0); in strongarm_uart_update_int_status() 1392 qemu_set_irq(s->irq, level); in strongarm_ssp_int_update()
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H A D | versatilepb.c | 68 qemu_set_irq(s->parent[s->irq], flags != 0); in vpb_sic_update() 80 qemu_set_irq(s->parent[i], (s->level & mask) != 0); in vpb_sic_update_pic() 92 qemu_set_irq(s->parent[irq], level); in vpb_sic_set_irq()
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H A D | integratorcp.c | 362 qemu_set_irq(s->parent_irq, flags != 0); in icp_pic_update() 364 qemu_set_irq(s->parent_fiq, flags != 0); in icp_pic_update() 526 qemu_set_irq(s->mmc_irq, !!(s->intreg_state & ICP_INTREG_CARDIN)); in icp_control_write() 561 qemu_set_irq(s->mmc_irq, 1); in icp_control_mmc_cardin()
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/openbmc/qemu/hw/intc/ |
H A D | allwinner-a10-pic.c | 45 qemu_set_irq(s->parent_irq, !!irq); in aw_a10_pic_update() 46 qemu_set_irq(s->parent_fiq, !!fiq); in aw_a10_pic_update()
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H A D | bcm2835_ic.c | 50 qemu_set_irq(s->fiq, set); in bcm2835_ic_update() 54 qemu_set_irq(s->irq, set); in bcm2835_ic_update()
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H A D | sifive_plic.c | 127 qemu_set_irq(plic->m_external_irqs[hartid - plic->hartid_base], level); in sifive_plic_update() 130 qemu_set_irq(plic->s_external_irqs[hartid - plic->hartid_base], level); in sifive_plic_update() 280 qemu_set_irq(s->m_external_irqs[i], 0); in sifive_plic_reset() 281 qemu_set_irq(s->s_external_irqs[i], 0); in sifive_plic_reset()
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/openbmc/qemu/hw/char/ |
H A D | stm32f2xx_usart.c | 61 qemu_set_irq(s->irq, 1); in stm32f2xx_update_irq() 63 qemu_set_irq(s->irq, 0); in stm32f2xx_update_irq()
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/openbmc/qemu/hw/net/fsl_etsec/ |
H A D | etsec.c | 73 qemu_set_irq(etsec->tx_irq, tx); in etsec_update_irq() 74 qemu_set_irq(etsec->rx_irq, rx); in etsec_update_irq() 75 qemu_set_irq(etsec->err_irq, err); in etsec_update_irq()
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/openbmc/qemu/hw/mips/ |
H A D | mips_int.c | 77 qemu_set_irq(env->irq[irq], level); in cpu_mips_soft_irq()
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/openbmc/qemu/hw/rtc/ |
H A D | m48t59.c | 94 qemu_set_irq(NVRAM->IRQ, 1); in alarm_cb() 131 qemu_set_irq(NVRAM->IRQ, 0); in alarm_cb() 169 qemu_set_irq(NVRAM->IRQ, 1); in watchdog_cb() 170 qemu_set_irq(NVRAM->IRQ, 0); in watchdog_cb()
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