Searched refs:ptes (Results 26 – 37 of 37) sorted by relevance
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378 *(vuip)MCPCIA_T0_BASE(mid) = virt_to_phys(hose->sg_isa->ptes) >> 8; in mcpcia_startup_hose()382 *(vuip)MCPCIA_T1_BASE(mid) = virt_to_phys(hose->sg_pci->ptes) >> 8; in mcpcia_startup_hose()
361 *(vuip)APECS_IOC_TB2R = virt_to_phys(hose->sg_isa->ptes) >> 1; in apecs_init_arch()
123 pci->pci_window[0].tbase.csr = virt_to_phys(hose->sg_isa->ptes); in wildfire_init_hose()135 pci->pci_window[3].tbase.csr = virt_to_phys(hose->sg_pci->ptes); in wildfire_init_hose()
286 *(vulp)LCA_IOC_T_BASE0 = virt_to_phys(hose->sg_isa->ptes); in lca_init_arch()
361 *(vulp)T2_TBASE2 = virt_to_phys(hose->sg_isa->ptes) >> 1; in t2_sg_map_window2()
268 uint32_t *ptes; in psb_mmu_alloc_pt() local284 ptes = (uint32_t *) v; in psb_mmu_alloc_pt()286 *ptes++ = pd->invalid_pte; in psb_mmu_alloc_pt()
222 Userfaultfd write-protect mode currently behave differently on none ptes225 For anonymous memory, ``ioctl(UFFDIO_WRITEPROTECT)`` will ignore none ptes227 like shmem and hugetlbfs, none ptes will be write protected just like a233 If the application wants to be able to write protect none ptes on anonymous236 and set the feature bit in advance to make sure none ptes will also be
13 knowledge fall back to breaking huge pmd mapping into table of ptes and,
139 with real ptes. Doing so will enable access for user space processes not
87 swp_entry's refcnt += # of ptes.
313 fbdev defio stuff. These should all work on plain ptes, they don't actually314 require a struct page. uff. These should all work on plain ptes, they don't
263 depends on !CPU_BIG_ENDIAN # revisit driver if we can enable big-endian ptes