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Searched refs:p0_mpwldectrl0 (Results 26 – 31 of 31) sorted by relevance

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/openbmc/u-boot/board/phytec/pcm058/
H A Dpcm058.c448 .p0_mpwldectrl0 = 0x00140014,
/openbmc/u-boot/arch/arm/mach-imx/mx6/
H A Dddr.c1102 mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0; in mx6_lpddr2_cfg()
1386 mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0; in mx6_ddr3_cfg()
1532 calib->p0_mpwldectrl0 = readl(&mmdc0->mpwldectrl0); in mmdc_read_calibration()
/openbmc/u-boot/board/freescale/mx6sxsabresd/
H A Dmx6sxsabresd.c473 .p0_mpwldectrl0 = 0x00290025,
/openbmc/u-boot/arch/arm/include/asm/arch-mx6/
H A Dmx6-ddr.h424 u32 p0_mpwldectrl0; member
/openbmc/u-boot/board/el/el6x/
H A Del6x.c532 .p0_mpwldectrl0 = 0x001F001F,
/openbmc/u-boot/board/phytec/pfla02/
H A Dpfla02.c471 .p0_mpwldectrl0 = 0x00110011,

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