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Searched refs:ccm (Results 76 – 100 of 196) sorted by relevance

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/openbmc/u-boot/board/dhelectronics/dh_imx6/
H A Ddh_imx6_spl.c277 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
279 writel(0x00C03F3F, &ccm->CCGR0); in ccgr_init()
280 writel(0x0030FC03, &ccm->CCGR1); in ccgr_init()
281 writel(0x0FFFC000, &ccm->CCGR2); in ccgr_init()
282 writel(0x3FF00000, &ccm->CCGR3); in ccgr_init()
283 writel(0x00FFF300, &ccm->CCGR4); in ccgr_init()
284 writel(0x0F0000C3, &ccm->CCGR5); in ccgr_init()
285 writel(0x000003FF, &ccm->CCGR6); in ccgr_init()
/openbmc/u-boot/board/freescale/mx6ul_14x14_evk/
H A Dmx6ul_14x14_evk.c699 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
701 writel(0xFFFFFFFF, &ccm->CCGR0); in ccgr_init()
702 writel(0xFFFFFFFF, &ccm->CCGR1); in ccgr_init()
703 writel(0xFFFFFFFF, &ccm->CCGR2); in ccgr_init()
704 writel(0xFFFFFFFF, &ccm->CCGR3); in ccgr_init()
705 writel(0xFFFFFFFF, &ccm->CCGR4); in ccgr_init()
706 writel(0xFFFFFFFF, &ccm->CCGR5); in ccgr_init()
707 writel(0xFFFFFFFF, &ccm->CCGR6); in ccgr_init()
708 writel(0xFFFFFFFF, &ccm->CCGR7); in ccgr_init()
/openbmc/u-boot/board/el/el6x/
H A Del6x.c562 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
564 writel(0x00C03F3F, &ccm->CCGR0); in ccgr_init()
565 writel(0x0030FC03, &ccm->CCGR1); in ccgr_init()
566 writel(0x0FFFC000, &ccm->CCGR2); in ccgr_init()
567 writel(0x3FF00000, &ccm->CCGR3); in ccgr_init()
568 writel(0x00FFF300, &ccm->CCGR4); in ccgr_init()
569 writel(0x0F0000C3, &ccm->CCGR5); in ccgr_init()
570 writel(0x000003FF, &ccm->CCGR6); in ccgr_init()
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dvf610-clock.txt4 - compatible: Should be "fsl,vf610-ccm"
27 clks: ccm@4006b000 {
28 compatible = "fsl,vf610-ccm";
H A Dimx21-clock.yaml19 const: fsl,imx21-ccm
39 compatible = "fsl,imx21-ccm";
H A Dimx1-clock.yaml19 const: fsl,imx1-ccm
40 compatible = "fsl,imx1-ccm";
H A Dimx27-clock.yaml19 const: fsl,imx27-ccm
42 compatible = "fsl,imx27-ccm";
H A Dimx6sl-clock.yaml14 const: fsl,imx6sl-ccm
44 compatible = "fsl,imx6sl-ccm";
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dmp.c254 volatile ccsr_local_t *ccm; in plat_mp_up() local
262 ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); in plat_mp_up()
268 out_be32(&ccm->bstrl, bootpg); in plat_mp_up()
274 out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | brsize); in plat_mp_up()
278 in_be32(&ccm->bstrar); in plat_mp_up()
324 clrbits_be32(&ccm->bstrar, LAW_EN); in plat_mp_up()
/openbmc/u-boot/board/freescale/m54418twr/
H A Dm54418twr.c39 ccm_t *ccm = (ccm_t *)MMAP_CCM; in dram_init() local
54 clrbits_be16(&ccm->misccr2, CCM_MISCCR2_FBHALF); in dram_init()
55 setbits_be16(&ccm->misccr2, CCM_MISCCR2_DDR2CLK); in dram_init()
/openbmc/qemu/hw/arm/
H A Dfsl-imx25.c43 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX25_CCM); in fsl_imx25_init()
99 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) { in fsl_imx25_realize()
102 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX25_CCM_ADDR); in fsl_imx25_realize()
140 s->gpt[i].ccm = IMX_CCM(&s->ccm); in fsl_imx25_realize()
161 s->epit[i].ccm = IMX_CCM(&s->ccm); in fsl_imx25_realize()
H A Dfsl-imx6.c52 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX6_CCM); in fsl_imx6_init()
158 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) { in fsl_imx6_realize()
161 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6_CCM_ADDR); in fsl_imx6_realize()
193 s->gpt.ccm = IMX_CCM(&s->ccm); in fsl_imx6_realize()
214 s->epit[i].ccm = IMX_CCM(&s->ccm); in fsl_imx6_realize()
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun6i.c31 struct sunxi_ccm_reg * const ccm = in mctl_sys_init() local
37 clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK, in mctl_sys_init()
40 mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); in mctl_sys_init()
42 writel(MDFS_CLK_DEFAULT, &ccm->mdfs_clk_cfg); in mctl_sys_init()
45 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()
48 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
297 struct sunxi_ccm_reg * const ccm = in mctl_port_cfg() local
301 setbits_le32(&ccm->axi_gate, 1 << AXI_GATE_OFFSET_DRAM); in mctl_port_cfg()
H A Ddram_sun8i_a23.c60 struct sunxi_ccm_reg * const ccm = in mctl_sys_init() local
68 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()
71 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
92 struct sunxi_ccm_reg * const ccm = in mctl_init() local
224 setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); in mctl_init()
H A Ddram_sun9i.c200 struct sunxi_ccm_reg * const ccm = in mctl_sys_init() local
273 clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()
275 clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
280 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()
282 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
292 writel((3 << 12) | (1 << 16), &ccm->dram_clk_cfg); in mctl_sys_init()
296 } while (readl(&ccm->dram_clk_cfg) & (1 << 16)); in mctl_sys_init()
297 setbits_le32(&ccm->dram_clk_cfg, (1 << 31)); in mctl_sys_init()
/openbmc/u-boot/board/phytec/pfla02/
H A Dpfla02.c541 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
543 writel(0x00C03F3F, &ccm->CCGR0); in ccgr_init()
544 writel(0x0030FC03, &ccm->CCGR1); in ccgr_init()
545 writel(0x0FFFC000, &ccm->CCGR2); in ccgr_init()
546 writel(0x3FF00000, &ccm->CCGR3); in ccgr_init()
547 writel(0x00FFF300, &ccm->CCGR4); in ccgr_init()
548 writel(0x0F0000C3, &ccm->CCGR5); in ccgr_init()
549 writel(0x000003FF, &ccm->CCGR6); in ccgr_init()
/openbmc/u-boot/drivers/mmc/
H A Dsunxi_mmc.c66 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; in mmc_resource_init() local
74 priv->mclkreg = &ccm->sd0_clk_cfg; in mmc_resource_init()
78 priv->mclkreg = &ccm->sd1_clk_cfg; in mmc_resource_init()
82 priv->mclkreg = &ccm->sd2_clk_cfg; in mmc_resource_init()
87 priv->mclkreg = &ccm->sd3_clk_cfg; in mmc_resource_init()
519 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; in sunxi_mmc_init() local
547 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no)); in sunxi_mmc_init()
551 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no)); in sunxi_mmc_init()
559 setbits_le32(&ccm->sd_gate_reset, 1 << sdc_no); in sunxi_mmc_init()
561 setbits_le32(&ccm->sd_gate_reset, 1 << (RESET_SHIFT + sdc_no)); in sunxi_mmc_init()
/openbmc/u-boot/drivers/video/sunxi/
H A Dlcdc.c211 void lcdc_pll_set(struct sunxi_ccm_reg *ccm, int tcon, int dotclock, in lcdc_pll_set() argument
314 &ccm->lcd0_ch0_clk_cfg); in lcdc_pll_set()
317 &ccm->lcd0_clk_cfg); in lcdc_pll_set()
325 CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg); in lcdc_pll_set()
327 setbits_le32(&ccm->lcd0_ch1_clk_cfg, in lcdc_pll_set()
H A Dsunxi_de2.c35 struct sunxi_ccm_reg * const ccm = in sunxi_de2_composer_init() local
50 clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK, in sunxi_de2_composer_init()
54 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE); in sunxi_de2_composer_init()
55 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE); in sunxi_de2_composer_init()
58 setbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_GATE); in sunxi_de2_composer_init()
/openbmc/u-boot/board/ge/bx50v3/
H A Dbx50v3.c413 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in enable_videopll() local
416 setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); in enable_videopll()
429 clrsetbits_le32(&ccm->analog_pll_video, in enable_videopll()
435 writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); in enable_videopll()
436 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); in enable_videopll()
438 clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); in enable_videopll()
441 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) in enable_videopll()
447 clrsetbits_le32(&ccm->analog_pll_video, in enable_videopll()
/openbmc/u-boot/board/toradex/colibri_imx6/
H A Dcolibri_imx6.c1027 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
1029 writel(0x00C03F3F, &ccm->CCGR0); in ccgr_init()
1030 writel(0x0030FC03, &ccm->CCGR1); in ccgr_init()
1031 writel(0x0FFFFFF3, &ccm->CCGR2); in ccgr_init()
1032 writel(0x3FF0300F, &ccm->CCGR3); in ccgr_init()
1033 writel(0x00FFF300, &ccm->CCGR4); in ccgr_init()
1034 writel(0x0F0000F3, &ccm->CCGR5); in ccgr_init()
1035 writel(0x000003FF, &ccm->CCGR6); in ccgr_init()
1046 writel(0x000000FB, &ccm->ccosr); in ccgr_init()
/openbmc/u-boot/board/freescale/mx6sabreauto/
H A Dmx6sabreauto.c680 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
682 writel(0x00C03F3F, &ccm->CCGR0); in ccgr_init()
683 writel(0x0030FC03, &ccm->CCGR1); in ccgr_init()
684 writel(0x0FFFC000, &ccm->CCGR2); in ccgr_init()
685 writel(0x3FF00000, &ccm->CCGR3); in ccgr_init()
686 writel(0x00FFF300, &ccm->CCGR4); in ccgr_init()
687 writel(0x0F0000C3, &ccm->CCGR5); in ccgr_init()
688 writel(0x000003FF, &ccm->CCGR6); in ccgr_init()
/openbmc/u-boot/board/freescale/mx6sabresd/
H A Dmx6sabresd.c689 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
691 writel(0x00C03F3F, &ccm->CCGR0); in ccgr_init()
692 writel(0x0030FC03, &ccm->CCGR1); in ccgr_init()
693 writel(0x0FFFC000, &ccm->CCGR2); in ccgr_init()
694 writel(0x3FF00000, &ccm->CCGR3); in ccgr_init()
695 writel(0x00FFF300, &ccm->CCGR4); in ccgr_init()
696 writel(0x0F0000C3, &ccm->CCGR5); in ccgr_init()
697 writel(0x000003FF, &ccm->CCGR6); in ccgr_init()
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx31.c128 void __iomem *ccm; in mx31_clocks_init_dt() local
140 ccm = of_iomap(np, 0); in mx31_clocks_init_dt()
141 if (!ccm) in mx31_clocks_init_dt()
144 _mx31_clocks_init(ccm, fref); in mx31_clocks_init_dt()
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dsunxi_nand_spl.c538 struct sunxi_ccm_reg *const ccm = in nand_deselect() local
541 clrbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); in nand_deselect()
543 clrbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA)); in nand_deselect()
545 clrbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA)); in nand_deselect()
547 clrbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); in nand_deselect()

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