/openbmc/linux/drivers/clk/sprd/ |
H A D | gate.h | 41 .reg = _reg, \ 50 SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \ 56 SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \ 66 #define SPRD_GATE_CLK(_struct, _name, _parent, _reg, \ argument 68 SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, 0, \ 75 SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \ 100 SPRD_SC_GATE_CLK_HW_OPS(_struct, _name, _parent, _reg, \ 104 #define SPRD_GATE_CLK_HW(_struct, _name, _parent, _reg, \ argument 119 _reg, _sc_offset, \ argument 131 _reg, _sc_offset, \ [all …]
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H A D | composite.h | 21 #define SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \ argument 29 .reg = _reg, \ 35 #define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \ argument 37 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \ 41 #define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \ argument 43 SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, NULL, \ 46 #define SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, _table, \ argument 49 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \ 53 #define SPRD_COMP_CLK_DATA(_struct, _name, _parent, _reg, _mshift, \ argument 55 SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, NULL, \
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H A D | pll.h | 64 #define SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, \ argument 79 .reg = _reg, \ 85 #define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \ argument 88 SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \ 92 #define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg, \ argument 95 SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \ 99 #define SPRD_PLL_WITH_ITABLE_1K(_struct, _name, _parent, _reg, \ argument 101 SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \ 105 #define SPRD_PLL_FW_NAME(_struct, _name, _parent, _reg, _regs_num, \ argument 108 SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \ [all …]
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H A D | mux.h | 40 _reg, _shift, _width, _flags, _fn) \ argument 45 .reg = _reg, \ 52 _reg, _shift, _width, _flags) \ argument 54 _reg, _shift, _width, _flags, \ 57 #define SPRD_MUX_CLK(_struct, _name, _parents, _reg, \ argument 60 _reg, _shift, _width, _flags) 63 _reg, _shift, _width, _flags) \ argument 65 _reg, _shift, _width, _flags, \ 68 #define SPRD_MUX_CLK_DATA(_struct, _name, _parents, _reg, \ argument 71 _reg, _shift, _width, _flags)
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H A D | div.h | 38 #define SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \ argument 44 .reg = _reg, \ 50 #define SPRD_DIV_CLK(_struct, _name, _parent, _reg, \ argument 52 SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \ 55 #define SPRD_DIV_CLK_HW(_struct, _name, _parent, _reg, \ argument 57 SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
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/openbmc/linux/drivers/net/ethernet/amd/xgbe/ |
H A D | xgbe-common.h | 1507 _reg##_##_field##_INDEX, \ 1508 _reg##_##_field##_WIDTH) 1517 _reg##_##_field##_INDEX, \ 1532 _reg##_##_field##_INDEX, \ 1533 _reg##_##_field##_WIDTH) 1558 _reg##_##_field##_WIDTH) 1616 _reg##_##_field##_WIDTH) 1636 _reg##_##_field##_WIDTH) 1659 _reg##_##_field##_WIDTH) 1692 _reg##_##_field##_WIDTH) [all …]
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/openbmc/linux/drivers/clk/sunxi-ng/ |
H A D | ccu_div.h | 95 .reg = _reg, \ 118 .reg = _reg, \ 129 _reg, \ argument 138 .reg = _reg, \ 148 _reg, \ argument 157 .reg = _reg, \ 171 _reg, _mshift, _mwidth, \ 202 .reg = _reg, \ 224 .reg = _reg, \ 249 .reg = _reg, \ [all …]
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H A D | ccu_gate.h | 19 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument 23 .reg = _reg, \ 31 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ argument 35 .reg = _reg, \ 43 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ argument 47 .reg = _reg, \ 63 .reg = _reg, \ 71 #define SUNXI_CCU_GATE_HWS_WITH_PREDIV(_struct, _name, _parent, _reg, \ argument 76 .reg = _reg, \ 90 .reg = _reg, \ [all …]
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H A D | ccu_mux.h | 50 _reg, _shift, _width, _gate, \ argument 56 .reg = _reg, \ 66 _table, _reg, _shift, \ argument 69 _table, _reg, _shift, \ 74 _reg, _shift, _width, _gate, \ argument 77 _table, _reg, _shift, \ 83 _reg, _shift, _width, _gate, \ 89 _reg, _shift, _width, 0, _flags) 97 .reg = _reg, \ 105 #define SUNXI_CCU_MUX_DATA(_struct, _name, _parents, _reg, \ argument [all …]
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H A D | ccu_mp.h | 34 #define SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(_struct, _name, _parents, _reg, \ argument 46 .reg = _reg, \ 55 #define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument 66 .reg = _reg, \ 74 #define SUNXI_CCU_MP_WITH_MUX(_struct, _name, _parents, _reg, \ argument 79 SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ 96 .reg = _reg, \ 104 #define SUNXI_CCU_MP_DATA_WITH_MUX(_struct, _name, _parents, _reg, \ argument 109 SUNXI_CCU_MP_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ 126 .reg = _reg, \ [all …]
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H A D | ccu_nm.h | 52 .reg = _reg, \ 76 .reg = _reg, \ 86 _reg, _min_rate, \ argument 102 .reg = _reg, \ 112 _parent, _reg, \ argument 132 .reg = _reg, \ 142 _parent, _reg, \ argument 151 _parent, _reg, \ 162 _parent, _reg, \ argument 171 _parent, _reg, \ [all …]
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/openbmc/linux/drivers/regulator/ |
H A D | mc13xxx.h | 66 .reg = prefix ## _reg, \ 67 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \ 73 #define MC13xxx_FIXED_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \ argument 84 .reg = prefix ## _reg, \ 85 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \ 88 #define MC13xxx_GPO_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \ argument 99 .reg = prefix ## _reg, \ 100 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \ 103 #define MC13xxx_DEFINE_SW(_name, _node, _reg, _vsel_reg, _voltages, ops) \ argument 104 MC13xxx_DEFINE(SW, _name, _node, _reg, _vsel_reg, _voltages, ops) [all …]
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/openbmc/linux/drivers/clk/pistachio/ |
H A D | clk.h | 19 #define GATE(_id, _name, _pname, _reg, _shift) \ argument 22 .reg = _reg, \ 39 #define MUX(_id, _name, _pnames, _reg, _shift) \ argument 42 .reg = _reg, \ 59 #define DIV(_id, _name, _pname, _reg, _width) \ argument 62 .reg = _reg, \ 72 .reg = _reg, \ 119 #define PLL(_id, _name, _pname, _type, _reg, _rates) \ argument 122 .reg_base = _reg, \ 130 #define PLL_FIXED(_id, _name, _pname, _type, _reg) \ argument [all …]
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/openbmc/linux/arch/mips/include/asm/mach-pic32/ |
H A D | pic32.h | 14 #define PIC32_CLR(_reg) ((_reg) + 0x04) argument 15 #define PIC32_SET(_reg) ((_reg) + 0x08) argument 16 #define PIC32_INV(_reg) ((_reg) + 0x0C) argument
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/openbmc/linux/drivers/clk/mediatek/ |
H A D | clk-mtk.h | 112 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ argument 116 .mux_reg = _reg, \ 119 .gate_reg = _reg, \ 132 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ argument 134 MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, \ 142 MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ 145 #define MUX(_id, _name, _parents, _reg, _shift, _width) \ argument 146 MUX_FLAGS(_id, _name, _parents, _reg, \ 152 .mux_reg = _reg, \ 196 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument [all …]
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/openbmc/linux/drivers/clk/actions/ |
H A D | owl-pll.h | 41 #define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ argument 44 .reg = _reg, \ 55 #define OWL_PLL(_struct, _name, _parent, _reg, _bfreq, _bit_idx, \ argument 58 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ 70 #define OWL_PLL_NO_PARENT(_struct, _name, _reg, _bfreq, _bit_idx, \ argument 73 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ 84 #define OWL_PLL_NO_PARENT_DELAY(_struct, _name, _reg, _bfreq, _bit_idx, \ argument 88 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
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H A D | owl-gate.h | 27 #define OWL_GATE_HW(_reg, _bit_idx, _gate_flags) \ argument 29 .reg = _reg, \ 34 #define OWL_GATE(_struct, _name, _parent, _reg, \ argument 37 .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \ 47 #define OWL_GATE_NO_PARENT(_struct, _name, _reg, \ argument 50 .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \
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/openbmc/linux/drivers/clk/x86/ |
H A D | clk-cgu.h | 118 _reg, _type) \ argument 125 .reg = _reg, \ 157 .reg = _reg, \ 203 #define LGM_MUX(_id, _name, _pdata, _f, _reg, \ argument 212 .mux_off = _reg, \ 231 .div_off = _reg, \ 241 #define LGM_GATE(_id, _name, _pname, _f, _reg, \ argument 253 .gate_off = _reg, \ 259 #define LGM_FIXED(_id, _name, _pname, _f, _reg, \ argument 271 .div_off = _reg, \ [all …]
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/openbmc/linux/drivers/clk/meson/ |
H A D | clk-regmap.h | 117 #define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \ argument 120 .offset = (_reg), \ 132 #define MESON_PCLK(_name, _reg, _bit, _pname) \ argument 133 __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname) 135 #define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ argument 136 __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname)
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H A D | axg-audio.c | 28 .offset = (_reg), \ 42 .offset = (_reg), \ 58 .offset = (_reg), \ 74 .offset = (_reg), \ 89 .reg_off = (_reg), \ 94 .reg_off = (_reg), \ 112 .reg_off = (_reg), \ 117 .reg_off = (_reg), \ 122 .reg_off = (_reg), \ 139 .reg_off = (_reg), \ [all …]
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/openbmc/u-boot/include/linux/ |
H A D | bitfield.h | 51 #define __BF_FIELD_CHECK(_mask, _reg, _val, _pfx) \ argument 59 BUILD_BUG_ON_MSG((_mask) > (typeof(_reg))~0ull, \ 100 #define FIELD_GET(_mask, _reg) \ argument 102 __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \ 103 (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
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/openbmc/linux/arch/mips/include/asm/ |
H A D | kvm_host.h | 439 return cop0->reg[(_reg)][(sel)]; \ 444 cop0->reg[(_reg)][(sel)] = val; \ 452 cop0->reg[(_reg)][(sel)] |= val; \ 457 cop0->reg[(_reg)][(sel)] &= ~val; \ 464 cop0->reg[(_reg)][(sel)] &= ~_mask; \ 465 cop0->reg[(_reg)][(sel)] |= val & _mask; \ 525 #define __BUILD_KVM_SAVE_VZ(name, _reg, sel) \ argument 528 write_gc0_##name(cop0->reg[(_reg)][(sel)]); \ 606 __BUILD_KVM_RW_VZ(name, type, _reg, sel) \ 608 __BUILD_KVM_SAVE_VZ(name, _reg, sel) [all …]
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/openbmc/linux/drivers/media/tuners/ |
H A D | mc44s803_priv.h | 179 #define MC44S803_REG_SM(_val, _reg) \ argument 180 (((_val) << _reg##_S) & (_reg)) 183 #define MC44S803_REG_MS(_val, _reg) \ argument 184 (((_val) & (_reg)) >> _reg##_S)
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/openbmc/linux/tools/testing/selftests/powerpc/mm/ |
H A D | large_vm_gpr_corruption.c | 54 #define CHECK_REG(_reg) \ argument 55 if (_reg != _reg##_orig) { \ 56 printf(str(_reg) " corrupted! Expected 0x%lx != 0x%lx\n", _reg##_orig, \ 57 _reg); \
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/openbmc/u-boot/drivers/clk/mediatek/ |
H A D | clk-mtk.h | 113 #define MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, \ argument 116 .mux_reg = _reg, \ 119 .gate_reg = _reg, \ 126 #define MUX_GATE(_id, _parents, _reg, _shift, _width, _gate) \ argument 127 MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, 0) 129 #define MUX(_id, _parents, _reg, _shift, _width) { \ argument 131 .mux_reg = _reg, \
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