| /openbmc/linux/drivers/phy/st/ |
| H A D | Kconfig | 10 Enable this to support the miphy transceiver (for SATA/PCIE/USB3)
34 and USB3 controllers on STMicroelectronics STiH407 SoC families.
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | qcom,sa8775p-gcc.yaml | 32 - description: Primary USB3 PHY wrapper pipe clock
33 - description: Secondary USB3 PHY wrapper pipe clock
|
| H A D | qcom,gcc-sm8350.yaml | 34 - description: USB3 phy wrapper pipe clock source (Optional clock)
35 - description: USB3 phy sec pipe clock source (Optional clock)
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| /openbmc/u-boot/board/theobroma-systems/puma_rk3399/ |
| H A D | README | 17 * USB3.0 dual role port
18 * 2x USB3.0 host, 1x USB2.0 host via onboard USB3.0 hub
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| /openbmc/linux/drivers/usb/mtu3/ |
| H A D | Kconfig | 3 # For MTK USB3.0 IP
6 tristate "MediaTek USB3 Dual Role controller"
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| /openbmc/linux/Documentation/devicetree/bindings/phy/ |
| H A D | phy-miphy28lp.txt | 5 for SATA, PCIe or USB3.
10 which contain the SATA, PCIe or USB3 mode setting bits.
27 registers used as glue-logic to setup the device for SATA/PCIe or USB3
|
| H A D | phy-mvebu-comphy.txt | 21 * Lane 0 (USB3/GbE)
22 * Lane 2 (SATA/USB3)
|
| H A D | socionext,uniphier-usb3ss-phy.yaml | 7 title: Socionext UniPhier USB3 Super-Speed (SS) PHY
11 USB3 controller implemented on Socionext UniPhier SoCs.
|
| H A D | socionext,uniphier-usb3hs-phy.yaml | 7 title: Socionext UniPhier USB3 High-Speed (HS) PHY
11 USB3 controller implemented on Socionext UniPhier SoCs.
|
| H A D | keystone-usb-phy.txt | 10 gate on the Keystone SOC for both the USB2 and USB3 PHY. Otherwise it is just
|
| H A D | allwinner,sun50i-h6-usb3-phy.yaml | 8 title: Allwinner H6 USB3 PHY
|
| H A D | amlogic,g12a-usb3-pcie-phy.yaml | 8 title: Amlogic G12A USB3 + PCIE Combo PHY
|
| /openbmc/linux/Documentation/devicetree/bindings/usb/ |
| H A D | rockchip,rk3399-dwc3.yaml | 34 USB3 aclk peri
36 USB3 aclk
|
| H A D | mediatek,mtu3.yaml | 8 title: MediaTek USB3 DRD Controller
89 - description: USB3/SS(P) PHY
91 - description: USB3/SS(P) PHY
93 - description: USB3/SS(P) PHY
95 - description: USB3/SS(P) PHY
|
| H A D | snps,dwc3.yaml | 7 title: Synopsys DesignWare USB3 Controller
61 PHY is suspended. suspend clocks a small part of the USB3 core when
84 - description: USB3/SS PHY
117 description: Determines if platform is USB3 LPM capable
184 The value driven to the PHY is controlled by the LTSSM during USB3
193 description: When set core will disable USB3 suspend phy
|
| H A D | usb-xhci.yaml | 21 description: Determines if platform is USB3 LPM capable
|
| /openbmc/linux/drivers/phy/mediatek/ |
| H A D | Kconfig | 49 USB3.1 GEN2 controllers on MediaTek chips. The driver supports
50 multiple USB2.0, USB3.1 GEN2 ports.
|
| /openbmc/linux/arch/arm/boot/dts/marvell/ |
| H A D | armada-388-clearfog.dts | 66 * 5-USB3 overcurrent
67 * 6-USB3 power
|
| /openbmc/linux/arch/arm/boot/dts/ti/omap/ |
| H A D | am5718.dtsi | 20 * USB3
|
| H A D | am5728.dtsi | 21 * USB3, USB4
|
| H A D | am5748.dtsi | 21 * USB3, USB4
|
| /openbmc/u-boot/arch/arm/mach-tegra/tegra186/ |
| H A D | Kconfig | 16 micro-B port, Ethernet, USB3 host port, SATA, PCIe, and two GPIO
|
| /openbmc/linux/drivers/phy/qualcomm/ |
| H A D | Kconfig | 69 with USB3 and DisplayPort controllers on Qualcomm chips.
103 with USB3 controllers on Qualcomm chips.
111 PHY transceivers working only in USB3 mode on Qualcomm chips. This
210 Qualcomm USB3.0 DWC3 controller on ipq806x SoC. This driver supports
|
| /openbmc/linux/drivers/phy/amlogic/ |
| H A D | Kconfig | 64 tristate "Meson G12A USB3+PCIE Combo PHY driver"
70 Enable this to support the Meson USB3 + PCIE Combo PHY found
|
| /openbmc/u-boot/arch/arm/mach-mvebu/serdes/a38x/ |
| H A D | high_speed_env_spec.c | 1171 serdes_seq_db[USB3_POWER_UP_SEQ].data_arr_idx = USB3; in hws_serdes_seq_db_init()
1203 serdes_seq_db[USB3_ELECTRICAL_CONFIG_SEQ].data_arr_idx = USB3; in hws_serdes_seq_db_init()
1210 serdes_seq_db[USB3_TX_CONFIG_SEQ1].data_arr_idx = USB3; in hws_serdes_seq_db_init()
1217 serdes_seq_db[USB3_TX_CONFIG_SEQ2].data_arr_idx = USB3; in hws_serdes_seq_db_init()
1224 serdes_seq_db[USB3_TX_CONFIG_SEQ3].data_arr_idx = USB3; in hws_serdes_seq_db_init()
1579 if (serdes_type == USB3) { in serdes_pex_usb3_pipe_delay_w_a()
1793 (serdes_num, USB3)); in serdes_power_up_ctrl()
|