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Searched refs:TLB (Results 126 – 150 of 161) sorted by relevance

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/openbmc/qemu/docs/devel/
H A Dstyle.rst369 performance-critical built-per-target core code such as the TLB code.
449 SoftMMU TLB code.
/openbmc/qemu/target/hexagon/imported/
H A Dcompare.idef580 "Detect if a VA/ASID matches a TLB entry",
/openbmc/qemu/target/ppc/
H A Dinsn32.decode960 ## TLB Management Instructions
/openbmc/linux/arch/arm/mm/
H A Dproc-v7.S297 mov r10, #(1 << 0) @ Cache/TLB ops broadcasting
/openbmc/qemu/tcg/ppc/
H A Dtcg-target.c.inc2287 * For system-mode, perform the TLB load and compare.
2347 * Load the (low part) TLB comparator into TMP2.
2371 * Load the TLB addend for use on the fast path.
2399 * which will then force a mismatch of the TLB compare.
2426 /* Load the high part TLB comparator into TMP2. */
/openbmc/linux/Documentation/virt/kvm/
H A Dapi.rst2063 TLB, prior to calling KVM_RUN on the associated vcpu.
2066 consists of a number of bits, equal to the total number of TLB entries as
2070 Each bit corresponds to one TLB entry, ordered the same as in the shared TLB
4265 to be able to use the global TLB and SLB invalidation instructions;
4287 (TLB invalidate entry) instruction.
6837 Configures the virtual CPU's TLB array, establishing a shared memory area
6849 the guest's TLB. If userspace makes any changes, it must call KVM_DIRTY_TLB
6858 - The array consists of all entries in the first TLB, followed by all
6859 entries in the second TLB.
8020 enables Direct TLB flush for its guests meaning that TLB flush
[all …]
/openbmc/linux/tools/arch/x86/kcpuid/
H A Dcpuid.csv84 # cache and TLB descriptor info
/openbmc/linux/arch/loongarch/
H A DKconfig477 We use generic TLB-based ioremap() by default since it has page
/openbmc/linux/Documentation/arch/sparc/oradax/
H A Doracle-dax.rst202 no I/O TLB or any scatter/gather mechanism. All buffers, whether input
H A Ddax-hv-api.txt237 …addresses used in the CCB must have translation entries present in either the TLB or a configured …
1121 must be present in either the TLB or an active TSB to be processed. The translation context for vir…
1230 CCBs, could not be translated by the virtual machine using either the TLB
/openbmc/linux/arch/
H A DKconfig483 irqs disabled over activate_mm. Architectures that do IPI based TLB
494 # final exit(2) TLB flush, for example.
/openbmc/linux/Documentation/arch/ia64/
H A Derr_inject.rst702 case 2: // TLB
/openbmc/linux/arch/mips/
H A DKconfig1303 Fast TLB refill support, etc.
1524 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
2040 overhead as well as slower TLB fault handling.
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-target.c.inc892 * For system-mode, perform the TLB load and compare.
953 /* Compare masked address with the TLB entry. */
/openbmc/qemu/target/arm/tcg/
H A Dcpu64.c1121 t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ in aarch64_max_tcg_initfn()
/openbmc/qemu/tcg/mips/
H A Dtcg-target.c.inc1202 * For system-mode, perform the TLB load and compare.
1243 /* Extract the TLB index from the address into TMP3. */
/openbmc/linux/Documentation/driver-api/
H A Dvfio.rst77 reducing the overhead both to the platform (reduced TLB thrashing,
/openbmc/linux/Documentation/filesystems/
H A Dproc.rst817 RES, CAL, TLB
818 rescheduling, call and TLB flush interrupts are
1125 CommitLimit = ([total RAM pages] - [total huge TLB pages]) *
/openbmc/linux/Documentation/powerpc/
H A Dultravisor.rst498 the TLB cache for the partition is flushed.
/openbmc/qemu/target/arm/
H A Dcpu.h2244 FIELD(ID_AA64ISAR0, TLB, 56, 4)
/openbmc/linux/arch/arm64/tools/
H A Dsysreg1197 UnsignedEnum 59:56 TLB
/openbmc/qemu/tcg/aarch64/
H A Dtcg-target.c.inc1644 * For system-mode, perform the TLB load and compare.
1686 /* Extract the TLB index from the address into X0. */
/openbmc/qemu/tcg/sparc64/
H A Dtcg-target.c.inc1041 * For system-mode, perform the TLB load and compare.
/openbmc/linux/Documentation/core-api/
H A Ddma-api-howto.rst23 The virtual memory system (TLB, page tables, etc.) translates virtual
/openbmc/linux/Documentation/RCU/
H A DRTFP.txt34 In 1987, Rashid et al. described lazy TLB-flush [RichardRashid87a].
321 Describes lazy TLB flush, where one waits for each CPU to pass

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